| commit | f72df8dbe2211cf2b70e54f8e9408b889fa56974 | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Wed Apr 09 13:29:03 2014 +0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Tue May 20 15:52:38 2014 +0200 |
| tree | fc8900ccbbd5ab19e78a79ea7edd426d4ede33f0 | |
| parent | 97fd4d5c81af7976b4ec9971a93bf3c361066c65 [diff] |
drm/i915/chv: Don't do group access reads from TX lanes either Like PCS, TX group reads return 0xffffffff. So we need to target each lane separately if we want to use RMW cycles to update the registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>