tree 151538a3a33026ae516606240a13404d1f1e7037
parent f920bb6f5fe21047e669381fe4dd346f6a9d3562
author Zhang Wei <wei.zhang@freescale.com> 1205891100 -0700
committer Dan Williams <dan.j.williams@intel.com> 1205884859 -0700

fsldma: Fix the DMA halt when using DMA_INTERRUPT async_tx transfer.

The DMA_INTERRUPT async_tx is a NULL transfer, thus the BCR(count register)
is 0. When the transfer started with a byte count of zero, the DMA
controller will triger a PE(programming error) event and halt, not a normal
interrupt. I add special codes for PE event and DMA_INTERRUPT
async_tx testing.

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>