tree bc37051ba47599b871a0f438070821f8c4bbf0ea
parent d75d9e73cd59127a4d926a2bf5e9cdcc90f033d6
author Paul Walmsley <paul@pwsan.com> 1242170829 -0600
committer paul <paul@twilight.(none)> 1242170829 -0600

OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change

Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode.  This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.

Signed-off-by: Paul Walmsley <paul@pwsan.com>