| commit | fb1cecd40690e61e122d7249e7499c8d799feffb | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Jun 02 14:31:39 2015 +0200 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Fri Feb 19 14:52:22 2016 +0900 |
| tree | c0d99812dd543d4c8647a662bf619c1d570c3ccb | |
| parent | c86a4b621994dbe9361185362c4be6887f04b1a4 [diff] |
ARM: dts: r8a7790: Add L2 cache-controller nodes Add device nodes for the L2 caches, and link the CPU nodes to them. The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways). The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>