drm/msm/sde: stage border fill after ctl start timeout
In some error cases ctl start irq is delayed more than ctl start
timeout period and it is received after programming the
next commit CTL registers but before next flush. Due to this
only new CTL register configuration takes effect but not the pipe
configuration. This is leading to smmu fault. Staging border-fill
in these cases after ctl start timeout will help prevent illegal
iova 0x0 (non-configured pipe) transactions onto the bus.
Change-Id: I85418df3a922a8468f31adc285fac217e8f2eee4
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 2c7f758..f8e3f23 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -757,6 +757,25 @@
return true;
}
+static int _sde_crtc_get_ctlstart_timeout(struct drm_crtc *crtc)
+{
+ struct drm_encoder *encoder;
+ int rc = 0;
+
+ if (!crtc || !crtc->dev)
+ return 0;
+
+ list_for_each_entry(encoder,
+ &crtc->dev->mode_config.encoder_list, head) {
+ if (encoder->crtc != crtc)
+ continue;
+
+ if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_CMD)
+ rc += sde_encoder_get_ctlstart_timeout_state(encoder);
+ }
+
+ return rc;
+}
static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
struct sde_plane_state *pstate, struct sde_format *format)
@@ -3184,7 +3203,13 @@
if (unlikely(!sde_crtc->num_mixers))
return;
- _sde_crtc_blend_setup(crtc, old_state, true);
+ if (_sde_crtc_get_ctlstart_timeout(crtc)) {
+ _sde_crtc_blend_setup(crtc, old_state, false);
+ SDE_ERROR("border fill only commit after ctlstart timeout\n");
+ } else {
+ _sde_crtc_blend_setup(crtc, old_state, true);
+ }
+
_sde_crtc_dest_scaler_setup(crtc);
/* cancel the idle notify delayed work */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 34777b30..0237b99 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -3229,6 +3229,24 @@
return 0;
}
+int sde_encoder_get_ctlstart_timeout_state(struct drm_encoder *drm_enc)
+{
+ struct sde_encoder_virt *sde_enc = NULL;
+ int i, count = 0;
+
+ if (!drm_enc)
+ return 0;
+
+ sde_enc = to_sde_encoder_virt(drm_enc);
+
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ count += atomic_read(&sde_enc->phys_encs[i]->ctlstart_timeout);
+ atomic_set(&sde_enc->phys_encs[i]->ctlstart_timeout, 0);
+ }
+
+ return count;
+}
+
/**
* _sde_encoder_trigger_flush - trigger flush for a physical encoder
* drm_enc: Pointer to drm encoder structure
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index a4cf467..62b0c9b 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -266,4 +266,11 @@
*/
void sde_encoder_control_idle_pc(struct drm_encoder *enc, bool enable);
+/**
+ * sde_encoder_get_ctlstart_timeout_state - checks if ctl start timeout happened
+ * @drm_enc: Pointer to drm encoder structure
+ * @Return: non zero value if ctl start timeout occurred
+ */
+int sde_encoder_get_ctlstart_timeout_state(struct drm_encoder *enc);
+
#endif /* __SDE_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
index 163a36d..ab16156 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -267,6 +267,7 @@
* @pending_retire_fence_cnt: Atomic counter tracking the pending retire
* fences that have to be signalled.
* @pending_kickoff_wq: Wait queue for blocking until kickoff completes
+ * @ctlstart_timeout: Indicates if ctl start timeout occurred
* @irq: IRQ tracking structures
* @cont_splash_single_flush Variable to check if single flush is enabled.
* @cont_splash_settings Variable to store continuous splash settings.
@@ -301,6 +302,7 @@
atomic_t pending_kickoff_cnt;
atomic_t pending_retire_fence_cnt;
wait_queue_head_t pending_kickoff_wq;
+ atomic_t ctlstart_timeout;
struct sde_encoder_irq irq[INTR_IDX_MAX];
u32 cont_splash_single_flush;
bool cont_splash_settings;
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
index 4409408..d6e8fd3 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -193,6 +193,7 @@
phys_enc,
SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE);
atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
+ atomic_set(&phys_enc->ctlstart_timeout, 0);
}
/* notify all synchronous clients first, then asynchronous clients */
@@ -292,6 +293,7 @@
ctl = phys_enc->hw_ctl;
atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
+ atomic_set(&phys_enc->ctlstart_timeout, 0);
time_diff_us = ktime_us_delta(ktime_get(), cmd_enc->rd_ptr_timestamp);
@@ -1054,6 +1056,7 @@
SDE_ERROR("invalid encoder\n");
return;
}
+ atomic_set(&phys_enc->ctlstart_timeout, 0);
SDE_DEBUG_CMDENC(cmd_enc, "pp %d state %d\n",
phys_enc->hw_pp->idx - PINGPONG_0,
phys_enc->enable_state);
@@ -1176,6 +1179,9 @@
"ctl start interrupt wait failed\n");
else
ret = 0;
+
+ if (sde_encoder_phys_cmd_is_master(phys_enc))
+ atomic_inc_return(&phys_enc->ctlstart_timeout);
}
return ret;
@@ -1476,6 +1482,7 @@
atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
atomic_set(&cmd_enc->pending_rd_ptr_cnt, 0);
atomic_set(&cmd_enc->pending_vblank_cnt, 0);
+ atomic_set(&phys_enc->ctlstart_timeout, 0);
init_waitqueue_head(&phys_enc->pending_kickoff_wq);
init_waitqueue_head(&cmd_enc->pending_vblank_wq);
atomic_set(&cmd_enc->autorefresh.kickoff_cnt, 0);