| commit | fd2963b071c1346572285a274a6ae8f26a970c4d | [log] [tgz] |
|---|---|---|
| author | Rhyland Klein <rklein@nvidia.com> | Thu Jan 14 14:24:37 2016 -0500 |
| committer | Thierry Reding <treding@nvidia.com> | Tue Feb 02 15:49:26 2016 +0100 |
| tree | bdc7652551379221c049a13f595ec97db81adff6 | |
| parent | f59b0168d3f3257f9bf0734563290acc3c9d972b [diff] |
clk: tegra: Fix typos around clearing PLLE bits during enable While enabling PLLE on both Tegra114 and Tegra210, we should be clearing PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting them. This patch fixes both places where we incorrectly set instead of cleared those bits. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>