tree 761c1bc2325eaed041a9fbe3a1fe18d9f6c9b988
parent b73d7e4381311bea024bf7cedcba3dcf20f63aab
author eric miao <eric.miao@marvell.com> 1202975303 +0800
committer David Woodhouse <dwmw2@infradead.org> 1208888847 +0100

[MTD] [NAND] support for pxa3xx

This is preliminary since:

1. It supports only _one_ chip select at the moment. As there is no
   existing platforms available using two chip selects of the NAND
   controller, it shall really not include code for supporting the
   2nd chip select for now, as such code cannot be verified.

2. It resorts to the default and simpliest memory based badblock
   table

3. Only limited types of nand flash are currently supported. Most
   PXA3xx processors come with on-chip NAND flash dies, so there
   isn't much flexibility for other types of NAND.

4. The NAND controller should be configured to detect the device's
   ID, thus making it difficult to use nand_scan_ident() to assist
   the detection process (though it's not impossible)

TODO: fix all the above limitations of cuz :-)

Signed-off-by: eric miao <eric.miao@marvell.com>
Cc: Sergey Podstavin <spodstavin@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>