Merge "clk: qcom: debugcc-sdm845: Changes to the debug mux structure"
diff --git a/drivers/clk/qcom/debugcc-sdm845.c b/drivers/clk/qcom/debugcc-sdm845.c
index 44c5b81..9ffa555 100644
--- a/drivers/clk/qcom/debugcc-sdm845.c
+++ b/drivers/clk/qcom/debugcc-sdm845.c
@@ -104,14 +104,6 @@
"disp_cc_mdss_rot_clk",
"disp_cc_mdss_rscc_ahb_clk",
"disp_cc_mdss_rscc_vsync_clk",
- "disp_cc_mdss_spdm_debug_clk",
- "disp_cc_mdss_spdm_dp_crypto_clk",
- "disp_cc_mdss_spdm_dp_pixel1_clk",
- "disp_cc_mdss_spdm_dp_pixel_clk",
- "disp_cc_mdss_spdm_mdp_clk",
- "disp_cc_mdss_spdm_pclk0_clk",
- "disp_cc_mdss_spdm_pclk1_clk",
- "disp_cc_mdss_spdm_rot_clk",
"disp_cc_mdss_vsync_clk",
"measure_only_snoc_clk",
"measure_only_cnoc_clk",
@@ -254,13 +246,13 @@
"gpu_cc_cxo_aon_clk",
"gpu_cc_cxo_clk",
"gpu_cc_gx_cxo_clk",
+ "gpu_cc_gx_gfx3d_clk",
"gpu_cc_gx_gmu_clk",
"gpu_cc_gx_qdss_tsctr_clk",
"gpu_cc_gx_vsense_clk",
"gpu_cc_rbcpr_ahb_clk",
"gpu_cc_rbcpr_clk",
"gpu_cc_sleep_clk",
- "gpu_cc_spdm_gx_gfx3d_div_clk",
"video_cc_apb_clk",
"video_cc_at_clk",
"video_cc_qdss_trig_clk",
@@ -433,22 +425,6 @@
0x17, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
{ "disp_cc_mdss_rscc_vsync_clk", 0x47, 4, DISP_CC,
0x18, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_debug_clk", 0x47, 4, DISP_CC,
- 0x20, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_dp_crypto_clk", 0x47, 4, DISP_CC,
- 0x1D, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_dp_pixel1_clk", 0x47, 4, DISP_CC,
- 0x1F, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_dp_pixel_clk", 0x47, 4, DISP_CC,
- 0x1E, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_mdp_clk", 0x47, 4, DISP_CC,
- 0x1B, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_pclk0_clk", 0x47, 4, DISP_CC,
- 0x19, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_pclk1_clk", 0x47, 4, DISP_CC,
- 0x1A, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
- { "disp_cc_mdss_spdm_rot_clk", 0x47, 4, DISP_CC,
- 0x1C, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
{ "disp_cc_mdss_vsync_clk", 0x47, 4, DISP_CC,
0x6, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
{ "measure_only_snoc_clk", 0x7, 4, GCC,
@@ -733,6 +709,8 @@
0xA, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
{ "gpu_cc_gx_cxo_clk", 0x144, 4, GPU_CC,
0xF, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
+ { "gpu_cc_gx_gfx3d_clk", 0x144, 4, GPU_CC,
+ 0xC, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
{ "gpu_cc_gx_gmu_clk", 0x144, 4, GPU_CC,
0x10, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
{ "gpu_cc_gx_qdss_tsctr_clk", 0x144, 4, GPU_CC,
@@ -745,8 +723,6 @@
0x1C, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
{ "gpu_cc_sleep_clk", 0x144, 4, GPU_CC,
0x17, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
- { "gpu_cc_spdm_gx_gfx3d_div_clk", 0x144, 4, GPU_CC,
- 0x1E, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
{ "video_cc_apb_clk", 0x48, 4, VIDEO_CC,
0x8, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
{ "video_cc_at_clk", 0x48, 4, VIDEO_CC,