clk: msm: Update test_cntrl register for sdm439/429
GPLL3_TEST_CTL_U register value on sdm439/429 requires
to be updated as per pll specification, so update the same.
Change-Id: I874f87bfc635d5733400caab6189f81cb5b6b33f
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
diff --git a/drivers/clk/msm/clock-gcc-8952.c b/drivers/clk/msm/clock-gcc-8952.c
index d471138..47619f5 100644
--- a/drivers/clk/msm/clock-gcc-8952.c
+++ b/drivers/clk/msm/clock-gcc-8952.c
@@ -4505,6 +4505,7 @@
vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_439;
vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_439;
+ gpll3_clk_src.test_ctl_hi_val = 0x400000;
gpll3_clk_src.vco_tbl = p_vco;
gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco);
gpll3_clk_src.c.fmax[VDD_DIG_LOW] = 800000000;