tree dbef1b618769de768343efa0fe61817cb318a41a
parent d065ab7189f368bbe9505865d63a0ebc470c409e
author Laxman Dewangan <ldewangan@nvidia.com> 1351580724 +0530
committer Stephen Warren <swarren@nvidia.com> 1352140583 -0700

ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt

Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30
board dt files.
Set the parent clock of slink controller to PLLP and configure
clock to 100MHz.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>