Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 28 | #include <linux/cpufreq.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "intel_drv.h" |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 31 | #include "../../../platform/x86/intel_ips.h" |
| 32 | #include <linux/module.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 33 | |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 34 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
| 35 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
| 36 | * during in-memory transfers and, therefore, reduce the power packet. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 37 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 38 | * The benefits of FBC are mostly visible with solid backgrounds and |
| 39 | * variation-less patterns. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 40 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 41 | * FBC-related functionality can be enabled by the means of the |
| 42 | * i915.i915_enable_fbc parameter |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 43 | */ |
| 44 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 45 | static void i8xx_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 46 | { |
| 47 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 48 | u32 fbc_ctl; |
| 49 | |
| 50 | /* Disable compression */ |
| 51 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 52 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 53 | return; |
| 54 | |
| 55 | fbc_ctl &= ~FBC_CTL_EN; |
| 56 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 57 | |
| 58 | /* Wait for compressing bit to clear */ |
| 59 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
| 60 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 61 | return; |
| 62 | } |
| 63 | |
| 64 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 65 | } |
| 66 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 67 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 68 | { |
| 69 | struct drm_device *dev = crtc->dev; |
| 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 71 | struct drm_framebuffer *fb = crtc->fb; |
| 72 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 73 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 74 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 75 | int cfb_pitch; |
| 76 | int plane, i; |
| 77 | u32 fbc_ctl, fbc_ctl2; |
| 78 | |
| 79 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
| 80 | if (fb->pitches[0] < cfb_pitch) |
| 81 | cfb_pitch = fb->pitches[0]; |
| 82 | |
| 83 | /* FBC_CTL wants 64B units */ |
| 84 | cfb_pitch = (cfb_pitch / 64) - 1; |
| 85 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
| 86 | |
| 87 | /* Clear old tags */ |
| 88 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 89 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 90 | |
| 91 | /* Set it up... */ |
| 92 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
| 93 | fbc_ctl2 |= plane; |
| 94 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 95 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 96 | |
| 97 | /* enable it... */ |
| 98 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
| 99 | if (IS_I945GM(dev)) |
| 100 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
| 101 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
| 102 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
| 103 | fbc_ctl |= obj->fence_reg; |
| 104 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 105 | |
| 106 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
| 107 | cfb_pitch, crtc->y, intel_crtc->plane); |
| 108 | } |
| 109 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 110 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 111 | { |
| 112 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 113 | |
| 114 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 115 | } |
| 116 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 117 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 118 | { |
| 119 | struct drm_device *dev = crtc->dev; |
| 120 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 121 | struct drm_framebuffer *fb = crtc->fb; |
| 122 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 123 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 125 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
| 126 | unsigned long stall_watermark = 200; |
| 127 | u32 dpfc_ctl; |
| 128 | |
| 129 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
| 130 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
| 131 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 132 | |
| 133 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 134 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 135 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 136 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 137 | |
| 138 | /* enable it... */ |
| 139 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
| 140 | |
| 141 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
| 142 | } |
| 143 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 144 | static void g4x_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 145 | { |
| 146 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 147 | u32 dpfc_ctl; |
| 148 | |
| 149 | /* Disable compression */ |
| 150 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 151 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 152 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 153 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 154 | |
| 155 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 156 | } |
| 157 | } |
| 158 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 159 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 160 | { |
| 161 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 162 | |
| 163 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 164 | } |
| 165 | |
| 166 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
| 167 | { |
| 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 169 | u32 blt_ecoskpd; |
| 170 | |
| 171 | /* Make sure blitter notifies FBC of writes */ |
| 172 | gen6_gt_force_wake_get(dev_priv); |
| 173 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
| 174 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
| 175 | GEN6_BLITTER_LOCK_SHIFT; |
| 176 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 177 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
| 178 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 179 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
| 180 | GEN6_BLITTER_LOCK_SHIFT); |
| 181 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 182 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
| 183 | gen6_gt_force_wake_put(dev_priv); |
| 184 | } |
| 185 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 186 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 187 | { |
| 188 | struct drm_device *dev = crtc->dev; |
| 189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 190 | struct drm_framebuffer *fb = crtc->fb; |
| 191 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 192 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 193 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 194 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
| 195 | unsigned long stall_watermark = 200; |
| 196 | u32 dpfc_ctl; |
| 197 | |
| 198 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 199 | dpfc_ctl &= DPFC_RESERVED; |
| 200 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
| 201 | /* Set persistent mode for front-buffer rendering, ala X. */ |
| 202 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
| 203 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
| 204 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 205 | |
| 206 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 207 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 208 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 209 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
| 210 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
| 211 | /* enable it... */ |
| 212 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 213 | |
| 214 | if (IS_GEN6(dev)) { |
| 215 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 216 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 217 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 218 | sandybridge_blit_fbc_update(dev); |
| 219 | } |
| 220 | |
| 221 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
| 222 | } |
| 223 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 224 | static void ironlake_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 225 | { |
| 226 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 227 | u32 dpfc_ctl; |
| 228 | |
| 229 | /* Disable compression */ |
| 230 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 231 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 232 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 233 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 234 | |
| 235 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 236 | } |
| 237 | } |
| 238 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 239 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 240 | { |
| 241 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 242 | |
| 243 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 244 | } |
| 245 | |
| 246 | bool intel_fbc_enabled(struct drm_device *dev) |
| 247 | { |
| 248 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 249 | |
| 250 | if (!dev_priv->display.fbc_enabled) |
| 251 | return false; |
| 252 | |
| 253 | return dev_priv->display.fbc_enabled(dev); |
| 254 | } |
| 255 | |
| 256 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 257 | { |
| 258 | struct intel_fbc_work *work = |
| 259 | container_of(to_delayed_work(__work), |
| 260 | struct intel_fbc_work, work); |
| 261 | struct drm_device *dev = work->crtc->dev; |
| 262 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 263 | |
| 264 | mutex_lock(&dev->struct_mutex); |
| 265 | if (work == dev_priv->fbc_work) { |
| 266 | /* Double check that we haven't switched fb without cancelling |
| 267 | * the prior work. |
| 268 | */ |
| 269 | if (work->crtc->fb == work->fb) { |
| 270 | dev_priv->display.enable_fbc(work->crtc, |
| 271 | work->interval); |
| 272 | |
| 273 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
| 274 | dev_priv->cfb_fb = work->crtc->fb->base.id; |
| 275 | dev_priv->cfb_y = work->crtc->y; |
| 276 | } |
| 277 | |
| 278 | dev_priv->fbc_work = NULL; |
| 279 | } |
| 280 | mutex_unlock(&dev->struct_mutex); |
| 281 | |
| 282 | kfree(work); |
| 283 | } |
| 284 | |
| 285 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
| 286 | { |
| 287 | if (dev_priv->fbc_work == NULL) |
| 288 | return; |
| 289 | |
| 290 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
| 291 | |
| 292 | /* Synchronisation is provided by struct_mutex and checking of |
| 293 | * dev_priv->fbc_work, so we can perform the cancellation |
| 294 | * entirely asynchronously. |
| 295 | */ |
| 296 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
| 297 | /* tasklet was killed before being run, clean up */ |
| 298 | kfree(dev_priv->fbc_work); |
| 299 | |
| 300 | /* Mark the work as no longer wanted so that if it does |
| 301 | * wake-up (because the work was already running and waiting |
| 302 | * for our mutex), it will discover that is no longer |
| 303 | * necessary to run. |
| 304 | */ |
| 305 | dev_priv->fbc_work = NULL; |
| 306 | } |
| 307 | |
| 308 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 309 | { |
| 310 | struct intel_fbc_work *work; |
| 311 | struct drm_device *dev = crtc->dev; |
| 312 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 313 | |
| 314 | if (!dev_priv->display.enable_fbc) |
| 315 | return; |
| 316 | |
| 317 | intel_cancel_fbc_work(dev_priv); |
| 318 | |
| 319 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 320 | if (work == NULL) { |
| 321 | dev_priv->display.enable_fbc(crtc, interval); |
| 322 | return; |
| 323 | } |
| 324 | |
| 325 | work->crtc = crtc; |
| 326 | work->fb = crtc->fb; |
| 327 | work->interval = interval; |
| 328 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
| 329 | |
| 330 | dev_priv->fbc_work = work; |
| 331 | |
| 332 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); |
| 333 | |
| 334 | /* Delay the actual enabling to let pageflipping cease and the |
| 335 | * display to settle before starting the compression. Note that |
| 336 | * this delay also serves a second purpose: it allows for a |
| 337 | * vblank to pass after disabling the FBC before we attempt |
| 338 | * to modify the control registers. |
| 339 | * |
| 340 | * A more complicated solution would involve tracking vblanks |
| 341 | * following the termination of the page-flipping sequence |
| 342 | * and indeed performing the enable as a co-routine and not |
| 343 | * waiting synchronously upon the vblank. |
| 344 | */ |
| 345 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
| 346 | } |
| 347 | |
| 348 | void intel_disable_fbc(struct drm_device *dev) |
| 349 | { |
| 350 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 351 | |
| 352 | intel_cancel_fbc_work(dev_priv); |
| 353 | |
| 354 | if (!dev_priv->display.disable_fbc) |
| 355 | return; |
| 356 | |
| 357 | dev_priv->display.disable_fbc(dev); |
| 358 | dev_priv->cfb_plane = -1; |
| 359 | } |
| 360 | |
| 361 | /** |
| 362 | * intel_update_fbc - enable/disable FBC as needed |
| 363 | * @dev: the drm_device |
| 364 | * |
| 365 | * Set up the framebuffer compression hardware at mode set time. We |
| 366 | * enable it if possible: |
| 367 | * - plane A only (on pre-965) |
| 368 | * - no pixel mulitply/line duplication |
| 369 | * - no alpha buffer discard |
| 370 | * - no dual wide |
| 371 | * - framebuffer <= 2048 in width, 1536 in height |
| 372 | * |
| 373 | * We can't assume that any compression will take place (worst case), |
| 374 | * so the compressed buffer has to be the same size as the uncompressed |
| 375 | * one. It also must reside (along with the line length buffer) in |
| 376 | * stolen memory. |
| 377 | * |
| 378 | * We need to enable/disable FBC on a global basis. |
| 379 | */ |
| 380 | void intel_update_fbc(struct drm_device *dev) |
| 381 | { |
| 382 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 383 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
| 384 | struct intel_crtc *intel_crtc; |
| 385 | struct drm_framebuffer *fb; |
| 386 | struct intel_framebuffer *intel_fb; |
| 387 | struct drm_i915_gem_object *obj; |
| 388 | int enable_fbc; |
| 389 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 390 | if (!i915_powersave) |
| 391 | return; |
| 392 | |
| 393 | if (!I915_HAS_FBC(dev)) |
| 394 | return; |
| 395 | |
| 396 | /* |
| 397 | * If FBC is already on, we just have to verify that we can |
| 398 | * keep it that way... |
| 399 | * Need to disable if: |
| 400 | * - more than one pipe is active |
| 401 | * - changing FBC params (stride, fence, mode) |
| 402 | * - new fb is too large to fit in compressed buffer |
| 403 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 404 | */ |
| 405 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | 93314b5 | 2012-06-13 17:36:55 +0100 | [diff] [blame] | 406 | if (tmp_crtc->enabled && |
| 407 | !to_intel_crtc(tmp_crtc)->primary_disabled && |
| 408 | tmp_crtc->fb) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 409 | if (crtc) { |
| 410 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
| 411 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
| 412 | goto out_disable; |
| 413 | } |
| 414 | crtc = tmp_crtc; |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | if (!crtc || crtc->fb == NULL) { |
| 419 | DRM_DEBUG_KMS("no output, disabling\n"); |
| 420 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
| 421 | goto out_disable; |
| 422 | } |
| 423 | |
| 424 | intel_crtc = to_intel_crtc(crtc); |
| 425 | fb = crtc->fb; |
| 426 | intel_fb = to_intel_framebuffer(fb); |
| 427 | obj = intel_fb->obj; |
| 428 | |
| 429 | enable_fbc = i915_enable_fbc; |
| 430 | if (enable_fbc < 0) { |
| 431 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
| 432 | enable_fbc = 1; |
| 433 | if (INTEL_INFO(dev)->gen <= 6) |
| 434 | enable_fbc = 0; |
| 435 | } |
| 436 | if (!enable_fbc) { |
| 437 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
| 438 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
| 439 | goto out_disable; |
| 440 | } |
| 441 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
| 442 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
| 443 | "compression\n"); |
| 444 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
| 445 | goto out_disable; |
| 446 | } |
| 447 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
| 448 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
| 449 | DRM_DEBUG_KMS("mode incompatible with compression, " |
| 450 | "disabling\n"); |
| 451 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
| 452 | goto out_disable; |
| 453 | } |
| 454 | if ((crtc->mode.hdisplay > 2048) || |
| 455 | (crtc->mode.vdisplay > 1536)) { |
| 456 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
| 457 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
| 458 | goto out_disable; |
| 459 | } |
| 460 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
| 461 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
| 462 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
| 463 | goto out_disable; |
| 464 | } |
| 465 | |
| 466 | /* The use of a CPU fence is mandatory in order to detect writes |
| 467 | * by the CPU to the scanout and trigger updates to the FBC. |
| 468 | */ |
| 469 | if (obj->tiling_mode != I915_TILING_X || |
| 470 | obj->fence_reg == I915_FENCE_REG_NONE) { |
| 471 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
| 472 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
| 473 | goto out_disable; |
| 474 | } |
| 475 | |
| 476 | /* If the kernel debugger is active, always disable compression */ |
| 477 | if (in_dbg_master()) |
| 478 | goto out_disable; |
| 479 | |
| 480 | /* If the scanout has not changed, don't modify the FBC settings. |
| 481 | * Note that we make the fundamental assumption that the fb->obj |
| 482 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 483 | * without first being decoupled from the scanout and FBC disabled. |
| 484 | */ |
| 485 | if (dev_priv->cfb_plane == intel_crtc->plane && |
| 486 | dev_priv->cfb_fb == fb->base.id && |
| 487 | dev_priv->cfb_y == crtc->y) |
| 488 | return; |
| 489 | |
| 490 | if (intel_fbc_enabled(dev)) { |
| 491 | /* We update FBC along two paths, after changing fb/crtc |
| 492 | * configuration (modeswitching) and after page-flipping |
| 493 | * finishes. For the latter, we know that not only did |
| 494 | * we disable the FBC at the start of the page-flip |
| 495 | * sequence, but also more than one vblank has passed. |
| 496 | * |
| 497 | * For the former case of modeswitching, it is possible |
| 498 | * to switch between two FBC valid configurations |
| 499 | * instantaneously so we do need to disable the FBC |
| 500 | * before we can modify its control registers. We also |
| 501 | * have to wait for the next vblank for that to take |
| 502 | * effect. However, since we delay enabling FBC we can |
| 503 | * assume that a vblank has passed since disabling and |
| 504 | * that we can safely alter the registers in the deferred |
| 505 | * callback. |
| 506 | * |
| 507 | * In the scenario that we go from a valid to invalid |
| 508 | * and then back to valid FBC configuration we have |
| 509 | * no strict enforcement that a vblank occurred since |
| 510 | * disabling the FBC. However, along all current pipe |
| 511 | * disabling paths we do need to wait for a vblank at |
| 512 | * some point. And we wait before enabling FBC anyway. |
| 513 | */ |
| 514 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
| 515 | intel_disable_fbc(dev); |
| 516 | } |
| 517 | |
| 518 | intel_enable_fbc(crtc, 500); |
| 519 | return; |
| 520 | |
| 521 | out_disable: |
| 522 | /* Multiple disables should be harmless */ |
| 523 | if (intel_fbc_enabled(dev)) { |
| 524 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
| 525 | intel_disable_fbc(dev); |
| 526 | } |
| 527 | } |
| 528 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 529 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
| 530 | { |
| 531 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 532 | u32 tmp; |
| 533 | |
| 534 | tmp = I915_READ(CLKCFG); |
| 535 | |
| 536 | switch (tmp & CLKCFG_FSB_MASK) { |
| 537 | case CLKCFG_FSB_533: |
| 538 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 539 | break; |
| 540 | case CLKCFG_FSB_800: |
| 541 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 542 | break; |
| 543 | case CLKCFG_FSB_667: |
| 544 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 545 | break; |
| 546 | case CLKCFG_FSB_400: |
| 547 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 548 | break; |
| 549 | } |
| 550 | |
| 551 | switch (tmp & CLKCFG_MEM_MASK) { |
| 552 | case CLKCFG_MEM_533: |
| 553 | dev_priv->mem_freq = 533; |
| 554 | break; |
| 555 | case CLKCFG_MEM_667: |
| 556 | dev_priv->mem_freq = 667; |
| 557 | break; |
| 558 | case CLKCFG_MEM_800: |
| 559 | dev_priv->mem_freq = 800; |
| 560 | break; |
| 561 | } |
| 562 | |
| 563 | /* detect pineview DDR3 setting */ |
| 564 | tmp = I915_READ(CSHRDDR3CTL); |
| 565 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
| 566 | } |
| 567 | |
| 568 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 569 | { |
| 570 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 571 | u16 ddrpll, csipll; |
| 572 | |
| 573 | ddrpll = I915_READ16(DDRMPLL1); |
| 574 | csipll = I915_READ16(CSIPLL0); |
| 575 | |
| 576 | switch (ddrpll & 0xff) { |
| 577 | case 0xc: |
| 578 | dev_priv->mem_freq = 800; |
| 579 | break; |
| 580 | case 0x10: |
| 581 | dev_priv->mem_freq = 1066; |
| 582 | break; |
| 583 | case 0x14: |
| 584 | dev_priv->mem_freq = 1333; |
| 585 | break; |
| 586 | case 0x18: |
| 587 | dev_priv->mem_freq = 1600; |
| 588 | break; |
| 589 | default: |
| 590 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 591 | ddrpll & 0xff); |
| 592 | dev_priv->mem_freq = 0; |
| 593 | break; |
| 594 | } |
| 595 | |
| 596 | dev_priv->r_t = dev_priv->mem_freq; |
| 597 | |
| 598 | switch (csipll & 0x3ff) { |
| 599 | case 0x00c: |
| 600 | dev_priv->fsb_freq = 3200; |
| 601 | break; |
| 602 | case 0x00e: |
| 603 | dev_priv->fsb_freq = 3733; |
| 604 | break; |
| 605 | case 0x010: |
| 606 | dev_priv->fsb_freq = 4266; |
| 607 | break; |
| 608 | case 0x012: |
| 609 | dev_priv->fsb_freq = 4800; |
| 610 | break; |
| 611 | case 0x014: |
| 612 | dev_priv->fsb_freq = 5333; |
| 613 | break; |
| 614 | case 0x016: |
| 615 | dev_priv->fsb_freq = 5866; |
| 616 | break; |
| 617 | case 0x018: |
| 618 | dev_priv->fsb_freq = 6400; |
| 619 | break; |
| 620 | default: |
| 621 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 622 | csipll & 0x3ff); |
| 623 | dev_priv->fsb_freq = 0; |
| 624 | break; |
| 625 | } |
| 626 | |
| 627 | if (dev_priv->fsb_freq == 3200) { |
| 628 | dev_priv->c_m = 0; |
| 629 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
| 630 | dev_priv->c_m = 1; |
| 631 | } else { |
| 632 | dev_priv->c_m = 2; |
| 633 | } |
| 634 | } |
| 635 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 636 | static const struct cxsr_latency cxsr_latency_table[] = { |
| 637 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 638 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 639 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 640 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 641 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
| 642 | |
| 643 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 644 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 645 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 646 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 647 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
| 648 | |
| 649 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 650 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 651 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 652 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 653 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
| 654 | |
| 655 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 656 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 657 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 658 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 659 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
| 660 | |
| 661 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 662 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 663 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 664 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 665 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
| 666 | |
| 667 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 668 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 669 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 670 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 671 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
| 672 | }; |
| 673 | |
Daniel Vetter | 63c6227 | 2012-04-21 23:17:55 +0200 | [diff] [blame] | 674 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 675 | int is_ddr3, |
| 676 | int fsb, |
| 677 | int mem) |
| 678 | { |
| 679 | const struct cxsr_latency *latency; |
| 680 | int i; |
| 681 | |
| 682 | if (fsb == 0 || mem == 0) |
| 683 | return NULL; |
| 684 | |
| 685 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 686 | latency = &cxsr_latency_table[i]; |
| 687 | if (is_desktop == latency->is_desktop && |
| 688 | is_ddr3 == latency->is_ddr3 && |
| 689 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 690 | return latency; |
| 691 | } |
| 692 | |
| 693 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 694 | |
| 695 | return NULL; |
| 696 | } |
| 697 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 698 | static void pineview_disable_cxsr(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 699 | { |
| 700 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 701 | |
| 702 | /* deactivate cxsr */ |
| 703 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
| 704 | } |
| 705 | |
| 706 | /* |
| 707 | * Latency for FIFO fetches is dependent on several factors: |
| 708 | * - memory configuration (speed, channels) |
| 709 | * - chipset |
| 710 | * - current MCH state |
| 711 | * It can be fairly high in some situations, so here we assume a fairly |
| 712 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 713 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 714 | * and power consumption (set it too low to save power and we might see |
| 715 | * FIFO underruns and display "flicker"). |
| 716 | * |
| 717 | * A value of 5us seems to be a good balance; safe for very low end |
| 718 | * platforms but not overly aggressive on lower latency configs. |
| 719 | */ |
| 720 | static const int latency_ns = 5000; |
| 721 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 722 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 723 | { |
| 724 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 725 | uint32_t dsparb = I915_READ(DSPARB); |
| 726 | int size; |
| 727 | |
| 728 | size = dsparb & 0x7f; |
| 729 | if (plane) |
| 730 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
| 731 | |
| 732 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 733 | plane ? "B" : "A", size); |
| 734 | |
| 735 | return size; |
| 736 | } |
| 737 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 738 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 739 | { |
| 740 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 741 | uint32_t dsparb = I915_READ(DSPARB); |
| 742 | int size; |
| 743 | |
| 744 | size = dsparb & 0x1ff; |
| 745 | if (plane) |
| 746 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
| 747 | size >>= 1; /* Convert to cachelines */ |
| 748 | |
| 749 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 750 | plane ? "B" : "A", size); |
| 751 | |
| 752 | return size; |
| 753 | } |
| 754 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 755 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 756 | { |
| 757 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 758 | uint32_t dsparb = I915_READ(DSPARB); |
| 759 | int size; |
| 760 | |
| 761 | size = dsparb & 0x7f; |
| 762 | size >>= 2; /* Convert to cachelines */ |
| 763 | |
| 764 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 765 | plane ? "B" : "A", |
| 766 | size); |
| 767 | |
| 768 | return size; |
| 769 | } |
| 770 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 771 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 772 | { |
| 773 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 774 | uint32_t dsparb = I915_READ(DSPARB); |
| 775 | int size; |
| 776 | |
| 777 | size = dsparb & 0x7f; |
| 778 | size >>= 1; /* Convert to cachelines */ |
| 779 | |
| 780 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 781 | plane ? "B" : "A", size); |
| 782 | |
| 783 | return size; |
| 784 | } |
| 785 | |
| 786 | /* Pineview has different values for various configs */ |
| 787 | static const struct intel_watermark_params pineview_display_wm = { |
| 788 | PINEVIEW_DISPLAY_FIFO, |
| 789 | PINEVIEW_MAX_WM, |
| 790 | PINEVIEW_DFT_WM, |
| 791 | PINEVIEW_GUARD_WM, |
| 792 | PINEVIEW_FIFO_LINE_SIZE |
| 793 | }; |
| 794 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
| 795 | PINEVIEW_DISPLAY_FIFO, |
| 796 | PINEVIEW_MAX_WM, |
| 797 | PINEVIEW_DFT_HPLLOFF_WM, |
| 798 | PINEVIEW_GUARD_WM, |
| 799 | PINEVIEW_FIFO_LINE_SIZE |
| 800 | }; |
| 801 | static const struct intel_watermark_params pineview_cursor_wm = { |
| 802 | PINEVIEW_CURSOR_FIFO, |
| 803 | PINEVIEW_CURSOR_MAX_WM, |
| 804 | PINEVIEW_CURSOR_DFT_WM, |
| 805 | PINEVIEW_CURSOR_GUARD_WM, |
| 806 | PINEVIEW_FIFO_LINE_SIZE, |
| 807 | }; |
| 808 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
| 809 | PINEVIEW_CURSOR_FIFO, |
| 810 | PINEVIEW_CURSOR_MAX_WM, |
| 811 | PINEVIEW_CURSOR_DFT_WM, |
| 812 | PINEVIEW_CURSOR_GUARD_WM, |
| 813 | PINEVIEW_FIFO_LINE_SIZE |
| 814 | }; |
| 815 | static const struct intel_watermark_params g4x_wm_info = { |
| 816 | G4X_FIFO_SIZE, |
| 817 | G4X_MAX_WM, |
| 818 | G4X_MAX_WM, |
| 819 | 2, |
| 820 | G4X_FIFO_LINE_SIZE, |
| 821 | }; |
| 822 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
| 823 | I965_CURSOR_FIFO, |
| 824 | I965_CURSOR_MAX_WM, |
| 825 | I965_CURSOR_DFT_WM, |
| 826 | 2, |
| 827 | G4X_FIFO_LINE_SIZE, |
| 828 | }; |
| 829 | static const struct intel_watermark_params valleyview_wm_info = { |
| 830 | VALLEYVIEW_FIFO_SIZE, |
| 831 | VALLEYVIEW_MAX_WM, |
| 832 | VALLEYVIEW_MAX_WM, |
| 833 | 2, |
| 834 | G4X_FIFO_LINE_SIZE, |
| 835 | }; |
| 836 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
| 837 | I965_CURSOR_FIFO, |
| 838 | VALLEYVIEW_CURSOR_MAX_WM, |
| 839 | I965_CURSOR_DFT_WM, |
| 840 | 2, |
| 841 | G4X_FIFO_LINE_SIZE, |
| 842 | }; |
| 843 | static const struct intel_watermark_params i965_cursor_wm_info = { |
| 844 | I965_CURSOR_FIFO, |
| 845 | I965_CURSOR_MAX_WM, |
| 846 | I965_CURSOR_DFT_WM, |
| 847 | 2, |
| 848 | I915_FIFO_LINE_SIZE, |
| 849 | }; |
| 850 | static const struct intel_watermark_params i945_wm_info = { |
| 851 | I945_FIFO_SIZE, |
| 852 | I915_MAX_WM, |
| 853 | 1, |
| 854 | 2, |
| 855 | I915_FIFO_LINE_SIZE |
| 856 | }; |
| 857 | static const struct intel_watermark_params i915_wm_info = { |
| 858 | I915_FIFO_SIZE, |
| 859 | I915_MAX_WM, |
| 860 | 1, |
| 861 | 2, |
| 862 | I915_FIFO_LINE_SIZE |
| 863 | }; |
| 864 | static const struct intel_watermark_params i855_wm_info = { |
| 865 | I855GM_FIFO_SIZE, |
| 866 | I915_MAX_WM, |
| 867 | 1, |
| 868 | 2, |
| 869 | I830_FIFO_LINE_SIZE |
| 870 | }; |
| 871 | static const struct intel_watermark_params i830_wm_info = { |
| 872 | I830_FIFO_SIZE, |
| 873 | I915_MAX_WM, |
| 874 | 1, |
| 875 | 2, |
| 876 | I830_FIFO_LINE_SIZE |
| 877 | }; |
| 878 | |
| 879 | static const struct intel_watermark_params ironlake_display_wm_info = { |
| 880 | ILK_DISPLAY_FIFO, |
| 881 | ILK_DISPLAY_MAXWM, |
| 882 | ILK_DISPLAY_DFTWM, |
| 883 | 2, |
| 884 | ILK_FIFO_LINE_SIZE |
| 885 | }; |
| 886 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
| 887 | ILK_CURSOR_FIFO, |
| 888 | ILK_CURSOR_MAXWM, |
| 889 | ILK_CURSOR_DFTWM, |
| 890 | 2, |
| 891 | ILK_FIFO_LINE_SIZE |
| 892 | }; |
| 893 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
| 894 | ILK_DISPLAY_SR_FIFO, |
| 895 | ILK_DISPLAY_MAX_SRWM, |
| 896 | ILK_DISPLAY_DFT_SRWM, |
| 897 | 2, |
| 898 | ILK_FIFO_LINE_SIZE |
| 899 | }; |
| 900 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
| 901 | ILK_CURSOR_SR_FIFO, |
| 902 | ILK_CURSOR_MAX_SRWM, |
| 903 | ILK_CURSOR_DFT_SRWM, |
| 904 | 2, |
| 905 | ILK_FIFO_LINE_SIZE |
| 906 | }; |
| 907 | |
| 908 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
| 909 | SNB_DISPLAY_FIFO, |
| 910 | SNB_DISPLAY_MAXWM, |
| 911 | SNB_DISPLAY_DFTWM, |
| 912 | 2, |
| 913 | SNB_FIFO_LINE_SIZE |
| 914 | }; |
| 915 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
| 916 | SNB_CURSOR_FIFO, |
| 917 | SNB_CURSOR_MAXWM, |
| 918 | SNB_CURSOR_DFTWM, |
| 919 | 2, |
| 920 | SNB_FIFO_LINE_SIZE |
| 921 | }; |
| 922 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
| 923 | SNB_DISPLAY_SR_FIFO, |
| 924 | SNB_DISPLAY_MAX_SRWM, |
| 925 | SNB_DISPLAY_DFT_SRWM, |
| 926 | 2, |
| 927 | SNB_FIFO_LINE_SIZE |
| 928 | }; |
| 929 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
| 930 | SNB_CURSOR_SR_FIFO, |
| 931 | SNB_CURSOR_MAX_SRWM, |
| 932 | SNB_CURSOR_DFT_SRWM, |
| 933 | 2, |
| 934 | SNB_FIFO_LINE_SIZE |
| 935 | }; |
| 936 | |
| 937 | |
| 938 | /** |
| 939 | * intel_calculate_wm - calculate watermark level |
| 940 | * @clock_in_khz: pixel clock |
| 941 | * @wm: chip FIFO params |
| 942 | * @pixel_size: display pixel size |
| 943 | * @latency_ns: memory latency for the platform |
| 944 | * |
| 945 | * Calculate the watermark level (the level at which the display plane will |
| 946 | * start fetching from memory again). Each chip has a different display |
| 947 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 948 | * in the correct intel_watermark_params structure. |
| 949 | * |
| 950 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 951 | * on the pixel size. When it reaches the watermark level, it'll start |
| 952 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 953 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 954 | * will occur, and a display engine hang could result. |
| 955 | */ |
| 956 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 957 | const struct intel_watermark_params *wm, |
| 958 | int fifo_size, |
| 959 | int pixel_size, |
| 960 | unsigned long latency_ns) |
| 961 | { |
| 962 | long entries_required, wm_size; |
| 963 | |
| 964 | /* |
| 965 | * Note: we need to make sure we don't overflow for various clock & |
| 966 | * latency values. |
| 967 | * clocks go from a few thousand to several hundred thousand. |
| 968 | * latency is usually a few thousand |
| 969 | */ |
| 970 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 971 | 1000; |
| 972 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
| 973 | |
| 974 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
| 975 | |
| 976 | wm_size = fifo_size - (entries_required + wm->guard_size); |
| 977 | |
| 978 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
| 979 | |
| 980 | /* Don't promote wm_size to unsigned... */ |
| 981 | if (wm_size > (long)wm->max_wm) |
| 982 | wm_size = wm->max_wm; |
| 983 | if (wm_size <= 0) |
| 984 | wm_size = wm->default_wm; |
| 985 | return wm_size; |
| 986 | } |
| 987 | |
| 988 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 989 | { |
| 990 | struct drm_crtc *crtc, *enabled = NULL; |
| 991 | |
| 992 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 993 | if (crtc->enabled && crtc->fb) { |
| 994 | if (enabled) |
| 995 | return NULL; |
| 996 | enabled = crtc; |
| 997 | } |
| 998 | } |
| 999 | |
| 1000 | return enabled; |
| 1001 | } |
| 1002 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1003 | static void pineview_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1004 | { |
| 1005 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1006 | struct drm_crtc *crtc; |
| 1007 | const struct cxsr_latency *latency; |
| 1008 | u32 reg; |
| 1009 | unsigned long wm; |
| 1010 | |
| 1011 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 1012 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 1013 | if (!latency) { |
| 1014 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 1015 | pineview_disable_cxsr(dev); |
| 1016 | return; |
| 1017 | } |
| 1018 | |
| 1019 | crtc = single_enabled_crtc(dev); |
| 1020 | if (crtc) { |
| 1021 | int clock = crtc->mode.clock; |
| 1022 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1023 | |
| 1024 | /* Display SR */ |
| 1025 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 1026 | pineview_display_wm.fifo_size, |
| 1027 | pixel_size, latency->display_sr); |
| 1028 | reg = I915_READ(DSPFW1); |
| 1029 | reg &= ~DSPFW_SR_MASK; |
| 1030 | reg |= wm << DSPFW_SR_SHIFT; |
| 1031 | I915_WRITE(DSPFW1, reg); |
| 1032 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 1033 | |
| 1034 | /* cursor SR */ |
| 1035 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 1036 | pineview_display_wm.fifo_size, |
| 1037 | pixel_size, latency->cursor_sr); |
| 1038 | reg = I915_READ(DSPFW3); |
| 1039 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 1040 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 1041 | I915_WRITE(DSPFW3, reg); |
| 1042 | |
| 1043 | /* Display HPLL off SR */ |
| 1044 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 1045 | pineview_display_hplloff_wm.fifo_size, |
| 1046 | pixel_size, latency->display_hpll_disable); |
| 1047 | reg = I915_READ(DSPFW3); |
| 1048 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 1049 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 1050 | I915_WRITE(DSPFW3, reg); |
| 1051 | |
| 1052 | /* cursor HPLL off SR */ |
| 1053 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 1054 | pineview_display_hplloff_wm.fifo_size, |
| 1055 | pixel_size, latency->cursor_hpll_disable); |
| 1056 | reg = I915_READ(DSPFW3); |
| 1057 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 1058 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 1059 | I915_WRITE(DSPFW3, reg); |
| 1060 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 1061 | |
| 1062 | /* activate cxsr */ |
| 1063 | I915_WRITE(DSPFW3, |
| 1064 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
| 1065 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
| 1066 | } else { |
| 1067 | pineview_disable_cxsr(dev); |
| 1068 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 1073 | int plane, |
| 1074 | const struct intel_watermark_params *display, |
| 1075 | int display_latency_ns, |
| 1076 | const struct intel_watermark_params *cursor, |
| 1077 | int cursor_latency_ns, |
| 1078 | int *plane_wm, |
| 1079 | int *cursor_wm) |
| 1080 | { |
| 1081 | struct drm_crtc *crtc; |
| 1082 | int htotal, hdisplay, clock, pixel_size; |
| 1083 | int line_time_us, line_count; |
| 1084 | int entries, tlb_miss; |
| 1085 | |
| 1086 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1087 | if (crtc->fb == NULL || !crtc->enabled) { |
| 1088 | *cursor_wm = cursor->guard_size; |
| 1089 | *plane_wm = display->guard_size; |
| 1090 | return false; |
| 1091 | } |
| 1092 | |
| 1093 | htotal = crtc->mode.htotal; |
| 1094 | hdisplay = crtc->mode.hdisplay; |
| 1095 | clock = crtc->mode.clock; |
| 1096 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1097 | |
| 1098 | /* Use the small buffer method to calculate plane watermark */ |
| 1099 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 1100 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 1101 | if (tlb_miss > 0) |
| 1102 | entries += tlb_miss; |
| 1103 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 1104 | *plane_wm = entries + display->guard_size; |
| 1105 | if (*plane_wm > (int)display->max_wm) |
| 1106 | *plane_wm = display->max_wm; |
| 1107 | |
| 1108 | /* Use the large buffer method to calculate cursor watermark */ |
| 1109 | line_time_us = ((htotal * 1000) / clock); |
| 1110 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
| 1111 | entries = line_count * 64 * pixel_size; |
| 1112 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 1113 | if (tlb_miss > 0) |
| 1114 | entries += tlb_miss; |
| 1115 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1116 | *cursor_wm = entries + cursor->guard_size; |
| 1117 | if (*cursor_wm > (int)cursor->max_wm) |
| 1118 | *cursor_wm = (int)cursor->max_wm; |
| 1119 | |
| 1120 | return true; |
| 1121 | } |
| 1122 | |
| 1123 | /* |
| 1124 | * Check the wm result. |
| 1125 | * |
| 1126 | * If any calculated watermark values is larger than the maximum value that |
| 1127 | * can be programmed into the associated watermark register, that watermark |
| 1128 | * must be disabled. |
| 1129 | */ |
| 1130 | static bool g4x_check_srwm(struct drm_device *dev, |
| 1131 | int display_wm, int cursor_wm, |
| 1132 | const struct intel_watermark_params *display, |
| 1133 | const struct intel_watermark_params *cursor) |
| 1134 | { |
| 1135 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 1136 | display_wm, cursor_wm); |
| 1137 | |
| 1138 | if (display_wm > display->max_wm) { |
| 1139 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
| 1140 | display_wm, display->max_wm); |
| 1141 | return false; |
| 1142 | } |
| 1143 | |
| 1144 | if (cursor_wm > cursor->max_wm) { |
| 1145 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
| 1146 | cursor_wm, cursor->max_wm); |
| 1147 | return false; |
| 1148 | } |
| 1149 | |
| 1150 | if (!(display_wm || cursor_wm)) { |
| 1151 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 1152 | return false; |
| 1153 | } |
| 1154 | |
| 1155 | return true; |
| 1156 | } |
| 1157 | |
| 1158 | static bool g4x_compute_srwm(struct drm_device *dev, |
| 1159 | int plane, |
| 1160 | int latency_ns, |
| 1161 | const struct intel_watermark_params *display, |
| 1162 | const struct intel_watermark_params *cursor, |
| 1163 | int *display_wm, int *cursor_wm) |
| 1164 | { |
| 1165 | struct drm_crtc *crtc; |
| 1166 | int hdisplay, htotal, pixel_size, clock; |
| 1167 | unsigned long line_time_us; |
| 1168 | int line_count, line_size; |
| 1169 | int small, large; |
| 1170 | int entries; |
| 1171 | |
| 1172 | if (!latency_ns) { |
| 1173 | *display_wm = *cursor_wm = 0; |
| 1174 | return false; |
| 1175 | } |
| 1176 | |
| 1177 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1178 | hdisplay = crtc->mode.hdisplay; |
| 1179 | htotal = crtc->mode.htotal; |
| 1180 | clock = crtc->mode.clock; |
| 1181 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1182 | |
| 1183 | line_time_us = (htotal * 1000) / clock; |
| 1184 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1185 | line_size = hdisplay * pixel_size; |
| 1186 | |
| 1187 | /* Use the minimum of the small and large buffer method for primary */ |
| 1188 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1189 | large = line_count * line_size; |
| 1190 | |
| 1191 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1192 | *display_wm = entries + display->guard_size; |
| 1193 | |
| 1194 | /* calculate the self-refresh watermark for display cursor */ |
| 1195 | entries = line_count * pixel_size * 64; |
| 1196 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1197 | *cursor_wm = entries + cursor->guard_size; |
| 1198 | |
| 1199 | return g4x_check_srwm(dev, |
| 1200 | *display_wm, *cursor_wm, |
| 1201 | display, cursor); |
| 1202 | } |
| 1203 | |
| 1204 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
| 1205 | int plane, |
| 1206 | int *plane_prec_mult, |
| 1207 | int *plane_dl, |
| 1208 | int *cursor_prec_mult, |
| 1209 | int *cursor_dl) |
| 1210 | { |
| 1211 | struct drm_crtc *crtc; |
| 1212 | int clock, pixel_size; |
| 1213 | int entries; |
| 1214 | |
| 1215 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1216 | if (crtc->fb == NULL || !crtc->enabled) |
| 1217 | return false; |
| 1218 | |
| 1219 | clock = crtc->mode.clock; /* VESA DOT Clock */ |
| 1220 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
| 1221 | |
| 1222 | entries = (clock / 1000) * pixel_size; |
| 1223 | *plane_prec_mult = (entries > 256) ? |
| 1224 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
| 1225 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
| 1226 | pixel_size); |
| 1227 | |
| 1228 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
| 1229 | *cursor_prec_mult = (entries > 256) ? |
| 1230 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
| 1231 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
| 1232 | |
| 1233 | return true; |
| 1234 | } |
| 1235 | |
| 1236 | /* |
| 1237 | * Update drain latency registers of memory arbiter |
| 1238 | * |
| 1239 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
| 1240 | * to be programmed. Each plane has a drain latency multiplier and a drain |
| 1241 | * latency value. |
| 1242 | */ |
| 1243 | |
| 1244 | static void vlv_update_drain_latency(struct drm_device *dev) |
| 1245 | { |
| 1246 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1247 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
| 1248 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
| 1249 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
| 1250 | either 16 or 32 */ |
| 1251 | |
| 1252 | /* For plane A, Cursor A */ |
| 1253 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
| 1254 | &cursor_prec_mult, &cursora_dl)) { |
| 1255 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1256 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
| 1257 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1258 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
| 1259 | |
| 1260 | I915_WRITE(VLV_DDL1, cursora_prec | |
| 1261 | (cursora_dl << DDL_CURSORA_SHIFT) | |
| 1262 | planea_prec | planea_dl); |
| 1263 | } |
| 1264 | |
| 1265 | /* For plane B, Cursor B */ |
| 1266 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
| 1267 | &cursor_prec_mult, &cursorb_dl)) { |
| 1268 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1269 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
| 1270 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1271 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
| 1272 | |
| 1273 | I915_WRITE(VLV_DDL2, cursorb_prec | |
| 1274 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
| 1275 | planeb_prec | planeb_dl); |
| 1276 | } |
| 1277 | } |
| 1278 | |
| 1279 | #define single_plane_enabled(mask) is_power_of_2(mask) |
| 1280 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1281 | static void valleyview_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1282 | { |
| 1283 | static const int sr_latency_ns = 12000; |
| 1284 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1285 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1286 | int plane_sr, cursor_sr; |
| 1287 | unsigned int enabled = 0; |
| 1288 | |
| 1289 | vlv_update_drain_latency(dev); |
| 1290 | |
| 1291 | if (g4x_compute_wm0(dev, 0, |
| 1292 | &valleyview_wm_info, latency_ns, |
| 1293 | &valleyview_cursor_wm_info, latency_ns, |
| 1294 | &planea_wm, &cursora_wm)) |
| 1295 | enabled |= 1; |
| 1296 | |
| 1297 | if (g4x_compute_wm0(dev, 1, |
| 1298 | &valleyview_wm_info, latency_ns, |
| 1299 | &valleyview_cursor_wm_info, latency_ns, |
| 1300 | &planeb_wm, &cursorb_wm)) |
| 1301 | enabled |= 2; |
| 1302 | |
| 1303 | plane_sr = cursor_sr = 0; |
| 1304 | if (single_plane_enabled(enabled) && |
| 1305 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1306 | sr_latency_ns, |
| 1307 | &valleyview_wm_info, |
| 1308 | &valleyview_cursor_wm_info, |
| 1309 | &plane_sr, &cursor_sr)) |
| 1310 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
| 1311 | else |
| 1312 | I915_WRITE(FW_BLC_SELF_VLV, |
| 1313 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
| 1314 | |
| 1315 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 1316 | planea_wm, cursora_wm, |
| 1317 | planeb_wm, cursorb_wm, |
| 1318 | plane_sr, cursor_sr); |
| 1319 | |
| 1320 | I915_WRITE(DSPFW1, |
| 1321 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1322 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1323 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1324 | planea_wm); |
| 1325 | I915_WRITE(DSPFW2, |
| 1326 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
| 1327 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1328 | I915_WRITE(DSPFW3, |
| 1329 | (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT))); |
| 1330 | } |
| 1331 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1332 | static void g4x_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1333 | { |
| 1334 | static const int sr_latency_ns = 12000; |
| 1335 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1336 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1337 | int plane_sr, cursor_sr; |
| 1338 | unsigned int enabled = 0; |
| 1339 | |
| 1340 | if (g4x_compute_wm0(dev, 0, |
| 1341 | &g4x_wm_info, latency_ns, |
| 1342 | &g4x_cursor_wm_info, latency_ns, |
| 1343 | &planea_wm, &cursora_wm)) |
| 1344 | enabled |= 1; |
| 1345 | |
| 1346 | if (g4x_compute_wm0(dev, 1, |
| 1347 | &g4x_wm_info, latency_ns, |
| 1348 | &g4x_cursor_wm_info, latency_ns, |
| 1349 | &planeb_wm, &cursorb_wm)) |
| 1350 | enabled |= 2; |
| 1351 | |
| 1352 | plane_sr = cursor_sr = 0; |
| 1353 | if (single_plane_enabled(enabled) && |
| 1354 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1355 | sr_latency_ns, |
| 1356 | &g4x_wm_info, |
| 1357 | &g4x_cursor_wm_info, |
| 1358 | &plane_sr, &cursor_sr)) |
| 1359 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 1360 | else |
| 1361 | I915_WRITE(FW_BLC_SELF, |
| 1362 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
| 1363 | |
| 1364 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 1365 | planea_wm, cursora_wm, |
| 1366 | planeb_wm, cursorb_wm, |
| 1367 | plane_sr, cursor_sr); |
| 1368 | |
| 1369 | I915_WRITE(DSPFW1, |
| 1370 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1371 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1372 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1373 | planea_wm); |
| 1374 | I915_WRITE(DSPFW2, |
| 1375 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
| 1376 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1377 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 1378 | I915_WRITE(DSPFW3, |
| 1379 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | |
| 1380 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1381 | } |
| 1382 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1383 | static void i965_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1384 | { |
| 1385 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1386 | struct drm_crtc *crtc; |
| 1387 | int srwm = 1; |
| 1388 | int cursor_sr = 16; |
| 1389 | |
| 1390 | /* Calc sr entries for one plane configs */ |
| 1391 | crtc = single_enabled_crtc(dev); |
| 1392 | if (crtc) { |
| 1393 | /* self-refresh has much higher latency */ |
| 1394 | static const int sr_latency_ns = 12000; |
| 1395 | int clock = crtc->mode.clock; |
| 1396 | int htotal = crtc->mode.htotal; |
| 1397 | int hdisplay = crtc->mode.hdisplay; |
| 1398 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1399 | unsigned long line_time_us; |
| 1400 | int entries; |
| 1401 | |
| 1402 | line_time_us = ((htotal * 1000) / clock); |
| 1403 | |
| 1404 | /* Use ns/us then divide to preserve precision */ |
| 1405 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1406 | pixel_size * hdisplay; |
| 1407 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
| 1408 | srwm = I965_FIFO_SIZE - entries; |
| 1409 | if (srwm < 0) |
| 1410 | srwm = 1; |
| 1411 | srwm &= 0x1ff; |
| 1412 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 1413 | entries, srwm); |
| 1414 | |
| 1415 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1416 | pixel_size * 64; |
| 1417 | entries = DIV_ROUND_UP(entries, |
| 1418 | i965_cursor_wm_info.cacheline_size); |
| 1419 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 1420 | (entries + i965_cursor_wm_info.guard_size); |
| 1421 | |
| 1422 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 1423 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 1424 | |
| 1425 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 1426 | "cursor %d\n", srwm, cursor_sr); |
| 1427 | |
| 1428 | if (IS_CRESTLINE(dev)) |
| 1429 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 1430 | } else { |
| 1431 | /* Turn off self refresh if both pipes are enabled */ |
| 1432 | if (IS_CRESTLINE(dev)) |
| 1433 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 1434 | & ~FW_BLC_SELF_EN); |
| 1435 | } |
| 1436 | |
| 1437 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 1438 | srwm); |
| 1439 | |
| 1440 | /* 965 has limitations... */ |
| 1441 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
| 1442 | (8 << 16) | (8 << 8) | (8 << 0)); |
| 1443 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
| 1444 | /* update cursor SR watermark */ |
| 1445 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1446 | } |
| 1447 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1448 | static void i9xx_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1449 | { |
| 1450 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1451 | const struct intel_watermark_params *wm_info; |
| 1452 | uint32_t fwater_lo; |
| 1453 | uint32_t fwater_hi; |
| 1454 | int cwm, srwm = 1; |
| 1455 | int fifo_size; |
| 1456 | int planea_wm, planeb_wm; |
| 1457 | struct drm_crtc *crtc, *enabled = NULL; |
| 1458 | |
| 1459 | if (IS_I945GM(dev)) |
| 1460 | wm_info = &i945_wm_info; |
| 1461 | else if (!IS_GEN2(dev)) |
| 1462 | wm_info = &i915_wm_info; |
| 1463 | else |
| 1464 | wm_info = &i855_wm_info; |
| 1465 | |
| 1466 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 1467 | crtc = intel_get_crtc_for_plane(dev, 0); |
| 1468 | if (crtc->enabled && crtc->fb) { |
| 1469 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
| 1470 | wm_info, fifo_size, |
| 1471 | crtc->fb->bits_per_pixel / 8, |
| 1472 | latency_ns); |
| 1473 | enabled = crtc; |
| 1474 | } else |
| 1475 | planea_wm = fifo_size - wm_info->guard_size; |
| 1476 | |
| 1477 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 1478 | crtc = intel_get_crtc_for_plane(dev, 1); |
| 1479 | if (crtc->enabled && crtc->fb) { |
| 1480 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
| 1481 | wm_info, fifo_size, |
| 1482 | crtc->fb->bits_per_pixel / 8, |
| 1483 | latency_ns); |
| 1484 | if (enabled == NULL) |
| 1485 | enabled = crtc; |
| 1486 | else |
| 1487 | enabled = NULL; |
| 1488 | } else |
| 1489 | planeb_wm = fifo_size - wm_info->guard_size; |
| 1490 | |
| 1491 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 1492 | |
| 1493 | /* |
| 1494 | * Overlay gets an aggressive default since video jitter is bad. |
| 1495 | */ |
| 1496 | cwm = 2; |
| 1497 | |
| 1498 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
| 1499 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1500 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
| 1501 | else if (IS_I915GM(dev)) |
| 1502 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
| 1503 | |
| 1504 | /* Calc sr entries for one plane configs */ |
| 1505 | if (HAS_FW_BLC(dev) && enabled) { |
| 1506 | /* self-refresh has much higher latency */ |
| 1507 | static const int sr_latency_ns = 6000; |
| 1508 | int clock = enabled->mode.clock; |
| 1509 | int htotal = enabled->mode.htotal; |
| 1510 | int hdisplay = enabled->mode.hdisplay; |
| 1511 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
| 1512 | unsigned long line_time_us; |
| 1513 | int entries; |
| 1514 | |
| 1515 | line_time_us = (htotal * 1000) / clock; |
| 1516 | |
| 1517 | /* Use ns/us then divide to preserve precision */ |
| 1518 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1519 | pixel_size * hdisplay; |
| 1520 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 1521 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 1522 | srwm = wm_info->fifo_size - entries; |
| 1523 | if (srwm < 0) |
| 1524 | srwm = 1; |
| 1525 | |
| 1526 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1527 | I915_WRITE(FW_BLC_SELF, |
| 1528 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 1529 | else if (IS_I915GM(dev)) |
| 1530 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 1531 | } |
| 1532 | |
| 1533 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
| 1534 | planea_wm, planeb_wm, cwm, srwm); |
| 1535 | |
| 1536 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 1537 | fwater_hi = (cwm & 0x1f); |
| 1538 | |
| 1539 | /* Set request length to 8 cachelines per fetch */ |
| 1540 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 1541 | fwater_hi = fwater_hi | (1 << 8); |
| 1542 | |
| 1543 | I915_WRITE(FW_BLC, fwater_lo); |
| 1544 | I915_WRITE(FW_BLC2, fwater_hi); |
| 1545 | |
| 1546 | if (HAS_FW_BLC(dev)) { |
| 1547 | if (enabled) { |
| 1548 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1549 | I915_WRITE(FW_BLC_SELF, |
| 1550 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
| 1551 | else if (IS_I915GM(dev)) |
| 1552 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
| 1553 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
| 1554 | } else |
| 1555 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
| 1556 | } |
| 1557 | } |
| 1558 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1559 | static void i830_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1560 | { |
| 1561 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1562 | struct drm_crtc *crtc; |
| 1563 | uint32_t fwater_lo; |
| 1564 | int planea_wm; |
| 1565 | |
| 1566 | crtc = single_enabled_crtc(dev); |
| 1567 | if (crtc == NULL) |
| 1568 | return; |
| 1569 | |
| 1570 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
| 1571 | dev_priv->display.get_fifo_size(dev, 0), |
| 1572 | crtc->fb->bits_per_pixel / 8, |
| 1573 | latency_ns); |
| 1574 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
| 1575 | fwater_lo |= (3<<8) | planea_wm; |
| 1576 | |
| 1577 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
| 1578 | |
| 1579 | I915_WRITE(FW_BLC, fwater_lo); |
| 1580 | } |
| 1581 | |
| 1582 | #define ILK_LP0_PLANE_LATENCY 700 |
| 1583 | #define ILK_LP0_CURSOR_LATENCY 1300 |
| 1584 | |
| 1585 | /* |
| 1586 | * Check the wm result. |
| 1587 | * |
| 1588 | * If any calculated watermark values is larger than the maximum value that |
| 1589 | * can be programmed into the associated watermark register, that watermark |
| 1590 | * must be disabled. |
| 1591 | */ |
| 1592 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
| 1593 | int fbc_wm, int display_wm, int cursor_wm, |
| 1594 | const struct intel_watermark_params *display, |
| 1595 | const struct intel_watermark_params *cursor) |
| 1596 | { |
| 1597 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1598 | |
| 1599 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
| 1600 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
| 1601 | |
| 1602 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
| 1603 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
| 1604 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
| 1605 | |
| 1606 | /* fbc has it's own way to disable FBC WM */ |
| 1607 | I915_WRITE(DISP_ARB_CTL, |
| 1608 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
| 1609 | return false; |
| 1610 | } |
| 1611 | |
| 1612 | if (display_wm > display->max_wm) { |
| 1613 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
| 1614 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
| 1615 | return false; |
| 1616 | } |
| 1617 | |
| 1618 | if (cursor_wm > cursor->max_wm) { |
| 1619 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
| 1620 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
| 1621 | return false; |
| 1622 | } |
| 1623 | |
| 1624 | if (!(fbc_wm || display_wm || cursor_wm)) { |
| 1625 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
| 1626 | return false; |
| 1627 | } |
| 1628 | |
| 1629 | return true; |
| 1630 | } |
| 1631 | |
| 1632 | /* |
| 1633 | * Compute watermark values of WM[1-3], |
| 1634 | */ |
| 1635 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
| 1636 | int latency_ns, |
| 1637 | const struct intel_watermark_params *display, |
| 1638 | const struct intel_watermark_params *cursor, |
| 1639 | int *fbc_wm, int *display_wm, int *cursor_wm) |
| 1640 | { |
| 1641 | struct drm_crtc *crtc; |
| 1642 | unsigned long line_time_us; |
| 1643 | int hdisplay, htotal, pixel_size, clock; |
| 1644 | int line_count, line_size; |
| 1645 | int small, large; |
| 1646 | int entries; |
| 1647 | |
| 1648 | if (!latency_ns) { |
| 1649 | *fbc_wm = *display_wm = *cursor_wm = 0; |
| 1650 | return false; |
| 1651 | } |
| 1652 | |
| 1653 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1654 | hdisplay = crtc->mode.hdisplay; |
| 1655 | htotal = crtc->mode.htotal; |
| 1656 | clock = crtc->mode.clock; |
| 1657 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1658 | |
| 1659 | line_time_us = (htotal * 1000) / clock; |
| 1660 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1661 | line_size = hdisplay * pixel_size; |
| 1662 | |
| 1663 | /* Use the minimum of the small and large buffer method for primary */ |
| 1664 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1665 | large = line_count * line_size; |
| 1666 | |
| 1667 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1668 | *display_wm = entries + display->guard_size; |
| 1669 | |
| 1670 | /* |
| 1671 | * Spec says: |
| 1672 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
| 1673 | */ |
| 1674 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
| 1675 | |
| 1676 | /* calculate the self-refresh watermark for display cursor */ |
| 1677 | entries = line_count * pixel_size * 64; |
| 1678 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1679 | *cursor_wm = entries + cursor->guard_size; |
| 1680 | |
| 1681 | return ironlake_check_srwm(dev, level, |
| 1682 | *fbc_wm, *display_wm, *cursor_wm, |
| 1683 | display, cursor); |
| 1684 | } |
| 1685 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1686 | static void ironlake_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1687 | { |
| 1688 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1689 | int fbc_wm, plane_wm, cursor_wm; |
| 1690 | unsigned int enabled; |
| 1691 | |
| 1692 | enabled = 0; |
| 1693 | if (g4x_compute_wm0(dev, 0, |
| 1694 | &ironlake_display_wm_info, |
| 1695 | ILK_LP0_PLANE_LATENCY, |
| 1696 | &ironlake_cursor_wm_info, |
| 1697 | ILK_LP0_CURSOR_LATENCY, |
| 1698 | &plane_wm, &cursor_wm)) { |
| 1699 | I915_WRITE(WM0_PIPEA_ILK, |
| 1700 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 1701 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 1702 | " plane %d, " "cursor: %d\n", |
| 1703 | plane_wm, cursor_wm); |
| 1704 | enabled |= 1; |
| 1705 | } |
| 1706 | |
| 1707 | if (g4x_compute_wm0(dev, 1, |
| 1708 | &ironlake_display_wm_info, |
| 1709 | ILK_LP0_PLANE_LATENCY, |
| 1710 | &ironlake_cursor_wm_info, |
| 1711 | ILK_LP0_CURSOR_LATENCY, |
| 1712 | &plane_wm, &cursor_wm)) { |
| 1713 | I915_WRITE(WM0_PIPEB_ILK, |
| 1714 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 1715 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 1716 | " plane %d, cursor: %d\n", |
| 1717 | plane_wm, cursor_wm); |
| 1718 | enabled |= 2; |
| 1719 | } |
| 1720 | |
| 1721 | /* |
| 1722 | * Calculate and update the self-refresh watermark only when one |
| 1723 | * display plane is used. |
| 1724 | */ |
| 1725 | I915_WRITE(WM3_LP_ILK, 0); |
| 1726 | I915_WRITE(WM2_LP_ILK, 0); |
| 1727 | I915_WRITE(WM1_LP_ILK, 0); |
| 1728 | |
| 1729 | if (!single_plane_enabled(enabled)) |
| 1730 | return; |
| 1731 | enabled = ffs(enabled) - 1; |
| 1732 | |
| 1733 | /* WM1 */ |
| 1734 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 1735 | ILK_READ_WM1_LATENCY() * 500, |
| 1736 | &ironlake_display_srwm_info, |
| 1737 | &ironlake_cursor_srwm_info, |
| 1738 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1739 | return; |
| 1740 | |
| 1741 | I915_WRITE(WM1_LP_ILK, |
| 1742 | WM1_LP_SR_EN | |
| 1743 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1744 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1745 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1746 | cursor_wm); |
| 1747 | |
| 1748 | /* WM2 */ |
| 1749 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 1750 | ILK_READ_WM2_LATENCY() * 500, |
| 1751 | &ironlake_display_srwm_info, |
| 1752 | &ironlake_cursor_srwm_info, |
| 1753 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1754 | return; |
| 1755 | |
| 1756 | I915_WRITE(WM2_LP_ILK, |
| 1757 | WM2_LP_EN | |
| 1758 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1759 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1760 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1761 | cursor_wm); |
| 1762 | |
| 1763 | /* |
| 1764 | * WM3 is unsupported on ILK, probably because we don't have latency |
| 1765 | * data for that power state |
| 1766 | */ |
| 1767 | } |
| 1768 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1769 | static void sandybridge_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1770 | { |
| 1771 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1772 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
| 1773 | u32 val; |
| 1774 | int fbc_wm, plane_wm, cursor_wm; |
| 1775 | unsigned int enabled; |
| 1776 | |
| 1777 | enabled = 0; |
| 1778 | if (g4x_compute_wm0(dev, 0, |
| 1779 | &sandybridge_display_wm_info, latency, |
| 1780 | &sandybridge_cursor_wm_info, latency, |
| 1781 | &plane_wm, &cursor_wm)) { |
| 1782 | val = I915_READ(WM0_PIPEA_ILK); |
| 1783 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 1784 | I915_WRITE(WM0_PIPEA_ILK, val | |
| 1785 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 1786 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 1787 | " plane %d, " "cursor: %d\n", |
| 1788 | plane_wm, cursor_wm); |
| 1789 | enabled |= 1; |
| 1790 | } |
| 1791 | |
| 1792 | if (g4x_compute_wm0(dev, 1, |
| 1793 | &sandybridge_display_wm_info, latency, |
| 1794 | &sandybridge_cursor_wm_info, latency, |
| 1795 | &plane_wm, &cursor_wm)) { |
| 1796 | val = I915_READ(WM0_PIPEB_ILK); |
| 1797 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 1798 | I915_WRITE(WM0_PIPEB_ILK, val | |
| 1799 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 1800 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 1801 | " plane %d, cursor: %d\n", |
| 1802 | plane_wm, cursor_wm); |
| 1803 | enabled |= 2; |
| 1804 | } |
| 1805 | |
Eugeni Dodonov | 461bc9b | 2012-05-09 15:37:11 -0300 | [diff] [blame] | 1806 | if ((dev_priv->num_pipe == 3) && |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1807 | g4x_compute_wm0(dev, 2, |
| 1808 | &sandybridge_display_wm_info, latency, |
| 1809 | &sandybridge_cursor_wm_info, latency, |
| 1810 | &plane_wm, &cursor_wm)) { |
| 1811 | val = I915_READ(WM0_PIPEC_IVB); |
| 1812 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 1813 | I915_WRITE(WM0_PIPEC_IVB, val | |
| 1814 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 1815 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
| 1816 | " plane %d, cursor: %d\n", |
| 1817 | plane_wm, cursor_wm); |
| 1818 | enabled |= 3; |
| 1819 | } |
| 1820 | |
| 1821 | /* |
| 1822 | * Calculate and update the self-refresh watermark only when one |
| 1823 | * display plane is used. |
| 1824 | * |
| 1825 | * SNB support 3 levels of watermark. |
| 1826 | * |
| 1827 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
| 1828 | * and disabled in the descending order |
| 1829 | * |
| 1830 | */ |
| 1831 | I915_WRITE(WM3_LP_ILK, 0); |
| 1832 | I915_WRITE(WM2_LP_ILK, 0); |
| 1833 | I915_WRITE(WM1_LP_ILK, 0); |
| 1834 | |
| 1835 | if (!single_plane_enabled(enabled) || |
| 1836 | dev_priv->sprite_scaling_enabled) |
| 1837 | return; |
| 1838 | enabled = ffs(enabled) - 1; |
| 1839 | |
| 1840 | /* WM1 */ |
| 1841 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 1842 | SNB_READ_WM1_LATENCY() * 500, |
| 1843 | &sandybridge_display_srwm_info, |
| 1844 | &sandybridge_cursor_srwm_info, |
| 1845 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1846 | return; |
| 1847 | |
| 1848 | I915_WRITE(WM1_LP_ILK, |
| 1849 | WM1_LP_SR_EN | |
| 1850 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1851 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1852 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1853 | cursor_wm); |
| 1854 | |
| 1855 | /* WM2 */ |
| 1856 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 1857 | SNB_READ_WM2_LATENCY() * 500, |
| 1858 | &sandybridge_display_srwm_info, |
| 1859 | &sandybridge_cursor_srwm_info, |
| 1860 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1861 | return; |
| 1862 | |
| 1863 | I915_WRITE(WM2_LP_ILK, |
| 1864 | WM2_LP_EN | |
| 1865 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1866 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1867 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1868 | cursor_wm); |
| 1869 | |
| 1870 | /* WM3 */ |
| 1871 | if (!ironlake_compute_srwm(dev, 3, enabled, |
| 1872 | SNB_READ_WM3_LATENCY() * 500, |
| 1873 | &sandybridge_display_srwm_info, |
| 1874 | &sandybridge_cursor_srwm_info, |
| 1875 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1876 | return; |
| 1877 | |
| 1878 | I915_WRITE(WM3_LP_ILK, |
| 1879 | WM3_LP_EN | |
| 1880 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1881 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1882 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1883 | cursor_wm); |
| 1884 | } |
| 1885 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 1886 | static void |
| 1887 | haswell_update_linetime_wm(struct drm_device *dev, int pipe, |
| 1888 | struct drm_display_mode *mode) |
| 1889 | { |
| 1890 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1891 | u32 temp; |
| 1892 | |
| 1893 | temp = I915_READ(PIPE_WM_LINETIME(pipe)); |
| 1894 | temp &= ~PIPE_WM_LINETIME_MASK; |
| 1895 | |
| 1896 | /* The WM are computed with base on how long it takes to fill a single |
| 1897 | * row at the given clock rate, multiplied by 8. |
| 1898 | * */ |
| 1899 | temp |= PIPE_WM_LINETIME_TIME( |
| 1900 | ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); |
| 1901 | |
| 1902 | /* IPS watermarks are only used by pipe A, and are ignored by |
| 1903 | * pipes B and C. They are calculated similarly to the common |
| 1904 | * linetime values, except that we are using CD clock frequency |
| 1905 | * in MHz instead of pixel rate for the division. |
| 1906 | * |
| 1907 | * This is a placeholder for the IPS watermark calculation code. |
| 1908 | */ |
| 1909 | |
| 1910 | I915_WRITE(PIPE_WM_LINETIME(pipe), temp); |
| 1911 | } |
| 1912 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1913 | static bool |
| 1914 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
| 1915 | uint32_t sprite_width, int pixel_size, |
| 1916 | const struct intel_watermark_params *display, |
| 1917 | int display_latency_ns, int *sprite_wm) |
| 1918 | { |
| 1919 | struct drm_crtc *crtc; |
| 1920 | int clock; |
| 1921 | int entries, tlb_miss; |
| 1922 | |
| 1923 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1924 | if (crtc->fb == NULL || !crtc->enabled) { |
| 1925 | *sprite_wm = display->guard_size; |
| 1926 | return false; |
| 1927 | } |
| 1928 | |
| 1929 | clock = crtc->mode.clock; |
| 1930 | |
| 1931 | /* Use the small buffer method to calculate the sprite watermark */ |
| 1932 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 1933 | tlb_miss = display->fifo_size*display->cacheline_size - |
| 1934 | sprite_width * 8; |
| 1935 | if (tlb_miss > 0) |
| 1936 | entries += tlb_miss; |
| 1937 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 1938 | *sprite_wm = entries + display->guard_size; |
| 1939 | if (*sprite_wm > (int)display->max_wm) |
| 1940 | *sprite_wm = display->max_wm; |
| 1941 | |
| 1942 | return true; |
| 1943 | } |
| 1944 | |
| 1945 | static bool |
| 1946 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
| 1947 | uint32_t sprite_width, int pixel_size, |
| 1948 | const struct intel_watermark_params *display, |
| 1949 | int latency_ns, int *sprite_wm) |
| 1950 | { |
| 1951 | struct drm_crtc *crtc; |
| 1952 | unsigned long line_time_us; |
| 1953 | int clock; |
| 1954 | int line_count, line_size; |
| 1955 | int small, large; |
| 1956 | int entries; |
| 1957 | |
| 1958 | if (!latency_ns) { |
| 1959 | *sprite_wm = 0; |
| 1960 | return false; |
| 1961 | } |
| 1962 | |
| 1963 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1964 | clock = crtc->mode.clock; |
| 1965 | if (!clock) { |
| 1966 | *sprite_wm = 0; |
| 1967 | return false; |
| 1968 | } |
| 1969 | |
| 1970 | line_time_us = (sprite_width * 1000) / clock; |
| 1971 | if (!line_time_us) { |
| 1972 | *sprite_wm = 0; |
| 1973 | return false; |
| 1974 | } |
| 1975 | |
| 1976 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1977 | line_size = sprite_width * pixel_size; |
| 1978 | |
| 1979 | /* Use the minimum of the small and large buffer method for primary */ |
| 1980 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1981 | large = line_count * line_size; |
| 1982 | |
| 1983 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1984 | *sprite_wm = entries + display->guard_size; |
| 1985 | |
| 1986 | return *sprite_wm > 0x3ff ? false : true; |
| 1987 | } |
| 1988 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1989 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1990 | uint32_t sprite_width, int pixel_size) |
| 1991 | { |
| 1992 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1993 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
| 1994 | u32 val; |
| 1995 | int sprite_wm, reg; |
| 1996 | int ret; |
| 1997 | |
| 1998 | switch (pipe) { |
| 1999 | case 0: |
| 2000 | reg = WM0_PIPEA_ILK; |
| 2001 | break; |
| 2002 | case 1: |
| 2003 | reg = WM0_PIPEB_ILK; |
| 2004 | break; |
| 2005 | case 2: |
| 2006 | reg = WM0_PIPEC_IVB; |
| 2007 | break; |
| 2008 | default: |
| 2009 | return; /* bad pipe */ |
| 2010 | } |
| 2011 | |
| 2012 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
| 2013 | &sandybridge_display_wm_info, |
| 2014 | latency, &sprite_wm); |
| 2015 | if (!ret) { |
| 2016 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", |
| 2017 | pipe); |
| 2018 | return; |
| 2019 | } |
| 2020 | |
| 2021 | val = I915_READ(reg); |
| 2022 | val &= ~WM0_PIPE_SPRITE_MASK; |
| 2023 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
| 2024 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
| 2025 | |
| 2026 | |
| 2027 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 2028 | pixel_size, |
| 2029 | &sandybridge_display_srwm_info, |
| 2030 | SNB_READ_WM1_LATENCY() * 500, |
| 2031 | &sprite_wm); |
| 2032 | if (!ret) { |
| 2033 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", |
| 2034 | pipe); |
| 2035 | return; |
| 2036 | } |
| 2037 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
| 2038 | |
| 2039 | /* Only IVB has two more LP watermarks for sprite */ |
| 2040 | if (!IS_IVYBRIDGE(dev)) |
| 2041 | return; |
| 2042 | |
| 2043 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 2044 | pixel_size, |
| 2045 | &sandybridge_display_srwm_info, |
| 2046 | SNB_READ_WM2_LATENCY() * 500, |
| 2047 | &sprite_wm); |
| 2048 | if (!ret) { |
| 2049 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", |
| 2050 | pipe); |
| 2051 | return; |
| 2052 | } |
| 2053 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
| 2054 | |
| 2055 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 2056 | pixel_size, |
| 2057 | &sandybridge_display_srwm_info, |
| 2058 | SNB_READ_WM3_LATENCY() * 500, |
| 2059 | &sprite_wm); |
| 2060 | if (!ret) { |
| 2061 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", |
| 2062 | pipe); |
| 2063 | return; |
| 2064 | } |
| 2065 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
| 2066 | } |
| 2067 | |
| 2068 | /** |
| 2069 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 2070 | * |
| 2071 | * Calculate watermark values for the various WM regs based on current mode |
| 2072 | * and plane configuration. |
| 2073 | * |
| 2074 | * There are several cases to deal with here: |
| 2075 | * - normal (i.e. non-self-refresh) |
| 2076 | * - self-refresh (SR) mode |
| 2077 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 2078 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 2079 | * lines), so need to account for TLB latency |
| 2080 | * |
| 2081 | * The normal calculation is: |
| 2082 | * watermark = dotclock * bytes per pixel * latency |
| 2083 | * where latency is platform & configuration dependent (we assume pessimal |
| 2084 | * values here). |
| 2085 | * |
| 2086 | * The SR calculation is: |
| 2087 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 2088 | * bytes per pixel |
| 2089 | * where |
| 2090 | * line time = htotal / dotclock |
| 2091 | * surface width = hdisplay for normal plane and 64 for cursor |
| 2092 | * and latency is assumed to be high, as above. |
| 2093 | * |
| 2094 | * The final value programmed to the register should always be rounded up, |
| 2095 | * and include an extra 2 entries to account for clock crossings. |
| 2096 | * |
| 2097 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 2098 | * to set the non-SR watermarks to 8. |
| 2099 | */ |
| 2100 | void intel_update_watermarks(struct drm_device *dev) |
| 2101 | { |
| 2102 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2103 | |
| 2104 | if (dev_priv->display.update_wm) |
| 2105 | dev_priv->display.update_wm(dev); |
| 2106 | } |
| 2107 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2108 | void intel_update_linetime_watermarks(struct drm_device *dev, |
| 2109 | int pipe, struct drm_display_mode *mode) |
| 2110 | { |
| 2111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2112 | |
| 2113 | if (dev_priv->display.update_linetime_wm) |
| 2114 | dev_priv->display.update_linetime_wm(dev, pipe, mode); |
| 2115 | } |
| 2116 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2117 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
| 2118 | uint32_t sprite_width, int pixel_size) |
| 2119 | { |
| 2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2121 | |
| 2122 | if (dev_priv->display.update_sprite_wm) |
| 2123 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
| 2124 | pixel_size); |
| 2125 | } |
| 2126 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2127 | static struct drm_i915_gem_object * |
| 2128 | intel_alloc_context_page(struct drm_device *dev) |
| 2129 | { |
| 2130 | struct drm_i915_gem_object *ctx; |
| 2131 | int ret; |
| 2132 | |
| 2133 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2134 | |
| 2135 | ctx = i915_gem_alloc_object(dev, 4096); |
| 2136 | if (!ctx) { |
| 2137 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 2138 | return NULL; |
| 2139 | } |
| 2140 | |
| 2141 | ret = i915_gem_object_pin(ctx, 4096, true); |
| 2142 | if (ret) { |
| 2143 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 2144 | goto err_unref; |
| 2145 | } |
| 2146 | |
| 2147 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
| 2148 | if (ret) { |
| 2149 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 2150 | goto err_unpin; |
| 2151 | } |
| 2152 | |
| 2153 | return ctx; |
| 2154 | |
| 2155 | err_unpin: |
| 2156 | i915_gem_object_unpin(ctx); |
| 2157 | err_unref: |
| 2158 | drm_gem_object_unreference(&ctx->base); |
| 2159 | mutex_unlock(&dev->struct_mutex); |
| 2160 | return NULL; |
| 2161 | } |
| 2162 | |
| 2163 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 2164 | { |
| 2165 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2166 | u16 rgvswctl; |
| 2167 | |
| 2168 | rgvswctl = I915_READ16(MEMSWCTL); |
| 2169 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 2170 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 2171 | return false; /* still busy with another command */ |
| 2172 | } |
| 2173 | |
| 2174 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 2175 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 2176 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 2177 | POSTING_READ16(MEMSWCTL); |
| 2178 | |
| 2179 | rgvswctl |= MEMCTL_CMD_STS; |
| 2180 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 2181 | |
| 2182 | return true; |
| 2183 | } |
| 2184 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2185 | static void ironlake_enable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2186 | { |
| 2187 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2188 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
| 2189 | u8 fmax, fmin, fstart, vstart; |
| 2190 | |
| 2191 | /* Enable temp reporting */ |
| 2192 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 2193 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 2194 | |
| 2195 | /* 100ms RC evaluation intervals */ |
| 2196 | I915_WRITE(RCUPEI, 100000); |
| 2197 | I915_WRITE(RCDNEI, 100000); |
| 2198 | |
| 2199 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 2200 | I915_WRITE(RCBMAXAVG, 90000); |
| 2201 | I915_WRITE(RCBMINAVG, 80000); |
| 2202 | |
| 2203 | I915_WRITE(MEMIHYST, 1); |
| 2204 | |
| 2205 | /* Set up min, max, and cur for interrupt handling */ |
| 2206 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 2207 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 2208 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 2209 | MEMMODE_FSTART_SHIFT; |
| 2210 | |
| 2211 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 2212 | PXVFREQ_PX_SHIFT; |
| 2213 | |
| 2214 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
| 2215 | dev_priv->fstart = fstart; |
| 2216 | |
| 2217 | dev_priv->max_delay = fstart; |
| 2218 | dev_priv->min_delay = fmin; |
| 2219 | dev_priv->cur_delay = fstart; |
| 2220 | |
| 2221 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 2222 | fmax, fmin, fstart); |
| 2223 | |
| 2224 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 2225 | |
| 2226 | /* |
| 2227 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 2228 | */ |
| 2229 | |
| 2230 | I915_WRITE(VIDSTART, vstart); |
| 2231 | POSTING_READ(VIDSTART); |
| 2232 | |
| 2233 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 2234 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 2235 | |
| 2236 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
| 2237 | DRM_ERROR("stuck trying to change perf mode\n"); |
| 2238 | msleep(1); |
| 2239 | |
| 2240 | ironlake_set_drps(dev, fstart); |
| 2241 | |
| 2242 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
| 2243 | I915_READ(0x112e0); |
| 2244 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); |
| 2245 | dev_priv->last_count2 = I915_READ(0x112f4); |
| 2246 | getrawmonotonic(&dev_priv->last_time2); |
| 2247 | } |
| 2248 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2249 | static void ironlake_disable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2250 | { |
| 2251 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2252 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 2253 | |
| 2254 | /* Ack interrupts, disable EFC interrupt */ |
| 2255 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 2256 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 2257 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 2258 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 2259 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 2260 | |
| 2261 | /* Go back to the starting frequency */ |
| 2262 | ironlake_set_drps(dev, dev_priv->fstart); |
| 2263 | msleep(1); |
| 2264 | rgvswctl |= MEMCTL_CMD_STS; |
| 2265 | I915_WRITE(MEMSWCTL, rgvswctl); |
| 2266 | msleep(1); |
| 2267 | |
| 2268 | } |
| 2269 | |
Daniel Vetter | acbe947 | 2012-07-26 11:50:05 +0200 | [diff] [blame] | 2270 | /* There's a funny hw issue where the hw returns all 0 when reading from |
| 2271 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
| 2272 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
| 2273 | * all limits and the gpu stuck at whatever frequency it is at atm). |
| 2274 | */ |
Daniel Vetter | 65bccb5 | 2012-08-08 17:42:52 +0200 | [diff] [blame] | 2275 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2276 | { |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2277 | u32 limits; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2278 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2279 | limits = 0; |
Daniel Vetter | 65bccb5 | 2012-08-08 17:42:52 +0200 | [diff] [blame] | 2280 | if (*val >= dev_priv->max_delay) |
| 2281 | *val = dev_priv->max_delay; |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 2282 | limits |= dev_priv->max_delay << 24; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2283 | |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 2284 | /* Only set the down limit when we've reached the lowest level to avoid |
| 2285 | * getting more interrupts, otherwise leave this clear. This prevents a |
| 2286 | * race in the hw when coming out of rc6: There's a tiny window where |
| 2287 | * the hw runs at the minimal clock before selecting the desired |
| 2288 | * frequency, if the down threshold expires in that window we will not |
| 2289 | * receive a down interrupt. */ |
Daniel Vetter | 65bccb5 | 2012-08-08 17:42:52 +0200 | [diff] [blame] | 2290 | if (*val <= dev_priv->min_delay) { |
| 2291 | *val = dev_priv->min_delay; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2292 | limits |= dev_priv->min_delay << 16; |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 2293 | } |
| 2294 | |
| 2295 | return limits; |
| 2296 | } |
| 2297 | |
| 2298 | void gen6_set_rps(struct drm_device *dev, u8 val) |
| 2299 | { |
| 2300 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 65bccb5 | 2012-08-08 17:42:52 +0200 | [diff] [blame] | 2301 | u32 limits = gen6_rps_limits(dev_priv, &val); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2302 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame^] | 2303 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2304 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2305 | if (val == dev_priv->cur_delay) |
| 2306 | return; |
| 2307 | |
| 2308 | I915_WRITE(GEN6_RPNSWREQ, |
| 2309 | GEN6_FREQUENCY(val) | |
| 2310 | GEN6_OFFSET(0) | |
| 2311 | GEN6_AGGRESSIVE_TURBO); |
| 2312 | |
| 2313 | /* Make sure we continue to get interrupts |
| 2314 | * until we hit the minimum or maximum frequencies. |
| 2315 | */ |
| 2316 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); |
| 2317 | |
| 2318 | dev_priv->cur_delay = val; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2319 | } |
| 2320 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2321 | static void gen6_disable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2322 | { |
| 2323 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2324 | |
Eugeni Dodonov | 8850948 | 2012-07-02 11:51:08 -0300 | [diff] [blame] | 2325 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2326 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
| 2327 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
| 2328 | I915_WRITE(GEN6_PMIER, 0); |
| 2329 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 2330 | * item again unmasking PM interrupts because that is using a different |
| 2331 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
| 2332 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
| 2333 | |
| 2334 | spin_lock_irq(&dev_priv->rps_lock); |
| 2335 | dev_priv->pm_iir = 0; |
| 2336 | spin_unlock_irq(&dev_priv->rps_lock); |
| 2337 | |
| 2338 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
| 2339 | } |
| 2340 | |
| 2341 | int intel_enable_rc6(const struct drm_device *dev) |
| 2342 | { |
| 2343 | /* |
| 2344 | * Respect the kernel parameter if it is set |
| 2345 | */ |
| 2346 | if (i915_enable_rc6 >= 0) |
| 2347 | return i915_enable_rc6; |
| 2348 | |
| 2349 | /* |
| 2350 | * Disable RC6 on Ironlake |
| 2351 | */ |
| 2352 | if (INTEL_INFO(dev)->gen == 5) |
| 2353 | return 0; |
| 2354 | |
Eugeni Dodonov | 4a637c2 | 2012-07-02 11:51:07 -0300 | [diff] [blame] | 2355 | /* On Haswell, only RC6 is available. So let's enable it by default to |
| 2356 | * provide better testing and coverage since the beginning. |
| 2357 | */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2358 | if (IS_HASWELL(dev)) |
Eugeni Dodonov | 4a637c2 | 2012-07-02 11:51:07 -0300 | [diff] [blame] | 2359 | return INTEL_RC6_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2360 | |
| 2361 | /* |
| 2362 | * Disable rc6 on Sandybridge |
| 2363 | */ |
| 2364 | if (INTEL_INFO(dev)->gen == 6) { |
| 2365 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
| 2366 | return INTEL_RC6_ENABLE; |
| 2367 | } |
| 2368 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
| 2369 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
| 2370 | } |
| 2371 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2372 | static void gen6_enable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2373 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2374 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2375 | struct intel_ring_buffer *ring; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2376 | u32 rp_state_cap; |
| 2377 | u32 gt_perf_status; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2378 | u32 pcu_mbox, rc6_mask = 0; |
| 2379 | u32 gtfifodbg; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2380 | int rc6_mode; |
| 2381 | int i; |
| 2382 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2383 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2384 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2385 | /* Here begins a magic sequence of register writes to enable |
| 2386 | * auto-downclocking. |
| 2387 | * |
| 2388 | * Perhaps there might be some value in exposing these to |
| 2389 | * userspace... |
| 2390 | */ |
| 2391 | I915_WRITE(GEN6_RC_STATE, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2392 | |
| 2393 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 2394 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 2395 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 2396 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 2397 | } |
| 2398 | |
| 2399 | gen6_gt_force_wake_get(dev_priv); |
| 2400 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2401 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 2402 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 2403 | |
| 2404 | /* In units of 100MHz */ |
| 2405 | dev_priv->max_delay = rp_state_cap & 0xff; |
| 2406 | dev_priv->min_delay = (rp_state_cap & 0xff0000) >> 16; |
| 2407 | dev_priv->cur_delay = 0; |
| 2408 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2409 | /* disable the counters and set deterministic thresholds */ |
| 2410 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 2411 | |
| 2412 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 2413 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 2414 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 2415 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 2416 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 2417 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2418 | for_each_ring(ring, dev_priv, i) |
| 2419 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2420 | |
| 2421 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 2422 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
| 2423 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
| 2424 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
| 2425 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 2426 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 2427 | /* Check if we are enabling RC6 */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2428 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 2429 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 2430 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 2431 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 2432 | /* We don't use those on Haswell */ |
| 2433 | if (!IS_HASWELL(dev)) { |
| 2434 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 2435 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2436 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 2437 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 2438 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 2439 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2440 | |
| 2441 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 2442 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
| 2443 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
| 2444 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2445 | |
| 2446 | I915_WRITE(GEN6_RC_CONTROL, |
| 2447 | rc6_mask | |
| 2448 | GEN6_RC_CTL_EI_MODE(1) | |
| 2449 | GEN6_RC_CTL_HW_ENABLE); |
| 2450 | |
| 2451 | I915_WRITE(GEN6_RPNSWREQ, |
| 2452 | GEN6_FREQUENCY(10) | |
| 2453 | GEN6_OFFSET(0) | |
| 2454 | GEN6_AGGRESSIVE_TURBO); |
| 2455 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 2456 | GEN6_FREQUENCY(12)); |
| 2457 | |
| 2458 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
| 2459 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2460 | dev_priv->max_delay << 24 | |
| 2461 | dev_priv->min_delay << 16); |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 2462 | |
| 2463 | if (IS_HASWELL(dev)) { |
| 2464 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 2465 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 2466 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 2467 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 2468 | } else { |
| 2469 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
| 2470 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); |
| 2471 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
| 2472 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
| 2473 | } |
| 2474 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2475 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 2476 | I915_WRITE(GEN6_RP_CONTROL, |
| 2477 | GEN6_RP_MEDIA_TURBO | |
Jesse Barnes | 89ba829 | 2012-05-22 09:30:33 -0700 | [diff] [blame] | 2478 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2479 | GEN6_RP_MEDIA_IS_GFX | |
| 2480 | GEN6_RP_ENABLE | |
| 2481 | GEN6_RP_UP_BUSY_AVG | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 2482 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2483 | |
| 2484 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 2485 | 500)) |
| 2486 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
| 2487 | |
| 2488 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 2489 | I915_WRITE(GEN6_PCODE_MAILBOX, |
| 2490 | GEN6_PCODE_READY | |
| 2491 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
| 2492 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 2493 | 500)) |
| 2494 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
| 2495 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2496 | /* Check for overclock support */ |
| 2497 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 2498 | 500)) |
| 2499 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
| 2500 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); |
| 2501 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); |
| 2502 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 2503 | 500)) |
| 2504 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
| 2505 | if (pcu_mbox & (1<<31)) { /* OC supported */ |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2506 | dev_priv->max_delay = pcu_mbox & 0xff; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2507 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
| 2508 | } |
| 2509 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2510 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2511 | |
| 2512 | /* requires MSI enabled */ |
Chris Wilson | ff92826 | 2012-07-05 15:02:17 +0100 | [diff] [blame] | 2513 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2514 | spin_lock_irq(&dev_priv->rps_lock); |
| 2515 | WARN_ON(dev_priv->pm_iir != 0); |
| 2516 | I915_WRITE(GEN6_PMIMR, 0); |
| 2517 | spin_unlock_irq(&dev_priv->rps_lock); |
| 2518 | /* enable all PM interrupts */ |
| 2519 | I915_WRITE(GEN6_PMINTRMSK, 0); |
| 2520 | |
| 2521 | gen6_gt_force_wake_put(dev_priv); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2522 | } |
| 2523 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2524 | static void gen6_update_ring_freq(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2525 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2526 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2527 | int min_freq = 15; |
| 2528 | int gpu_freq, ia_freq, max_ia_freq; |
| 2529 | int scaling_factor = 180; |
| 2530 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2531 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2532 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2533 | max_ia_freq = cpufreq_quick_get_max(0); |
| 2534 | /* |
| 2535 | * Default to measured freq if none found, PCU will ensure we don't go |
| 2536 | * over |
| 2537 | */ |
| 2538 | if (!max_ia_freq) |
| 2539 | max_ia_freq = tsc_khz; |
| 2540 | |
| 2541 | /* Convert from kHz to MHz */ |
| 2542 | max_ia_freq /= 1000; |
| 2543 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2544 | /* |
| 2545 | * For each potential GPU frequency, load a ring frequency we'd like |
| 2546 | * to use for memory access. We do this by specifying the IA frequency |
| 2547 | * the PCU should use as a reference to determine the ring frequency. |
| 2548 | */ |
| 2549 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; |
| 2550 | gpu_freq--) { |
| 2551 | int diff = dev_priv->max_delay - gpu_freq; |
| 2552 | |
| 2553 | /* |
| 2554 | * For GPU frequencies less than 750MHz, just use the lowest |
| 2555 | * ring freq. |
| 2556 | */ |
| 2557 | if (gpu_freq < min_freq) |
| 2558 | ia_freq = 800; |
| 2559 | else |
| 2560 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 2561 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 2562 | |
| 2563 | I915_WRITE(GEN6_PCODE_DATA, |
| 2564 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | |
| 2565 | gpu_freq); |
| 2566 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | |
| 2567 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
| 2568 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & |
| 2569 | GEN6_PCODE_READY) == 0, 10)) { |
| 2570 | DRM_ERROR("pcode write of freq table timed out\n"); |
| 2571 | continue; |
| 2572 | } |
| 2573 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2574 | } |
| 2575 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 2576 | void ironlake_teardown_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2577 | { |
| 2578 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2579 | |
| 2580 | if (dev_priv->renderctx) { |
| 2581 | i915_gem_object_unpin(dev_priv->renderctx); |
| 2582 | drm_gem_object_unreference(&dev_priv->renderctx->base); |
| 2583 | dev_priv->renderctx = NULL; |
| 2584 | } |
| 2585 | |
| 2586 | if (dev_priv->pwrctx) { |
| 2587 | i915_gem_object_unpin(dev_priv->pwrctx); |
| 2588 | drm_gem_object_unreference(&dev_priv->pwrctx->base); |
| 2589 | dev_priv->pwrctx = NULL; |
| 2590 | } |
| 2591 | } |
| 2592 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 2593 | static void ironlake_disable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2594 | { |
| 2595 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2596 | |
| 2597 | if (I915_READ(PWRCTXA)) { |
| 2598 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
| 2599 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
| 2600 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
| 2601 | 50); |
| 2602 | |
| 2603 | I915_WRITE(PWRCTXA, 0); |
| 2604 | POSTING_READ(PWRCTXA); |
| 2605 | |
| 2606 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
| 2607 | POSTING_READ(RSTDBYCTL); |
| 2608 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2609 | } |
| 2610 | |
| 2611 | static int ironlake_setup_rc6(struct drm_device *dev) |
| 2612 | { |
| 2613 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2614 | |
| 2615 | if (dev_priv->renderctx == NULL) |
| 2616 | dev_priv->renderctx = intel_alloc_context_page(dev); |
| 2617 | if (!dev_priv->renderctx) |
| 2618 | return -ENOMEM; |
| 2619 | |
| 2620 | if (dev_priv->pwrctx == NULL) |
| 2621 | dev_priv->pwrctx = intel_alloc_context_page(dev); |
| 2622 | if (!dev_priv->pwrctx) { |
| 2623 | ironlake_teardown_rc6(dev); |
| 2624 | return -ENOMEM; |
| 2625 | } |
| 2626 | |
| 2627 | return 0; |
| 2628 | } |
| 2629 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 2630 | static void ironlake_enable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2631 | { |
| 2632 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 2633 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2634 | int ret; |
| 2635 | |
| 2636 | /* rc6 disabled by default due to repeated reports of hanging during |
| 2637 | * boot and resume. |
| 2638 | */ |
| 2639 | if (!intel_enable_rc6(dev)) |
| 2640 | return; |
| 2641 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2642 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2643 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2644 | ret = ironlake_setup_rc6(dev); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 2645 | if (ret) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2646 | return; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2647 | |
| 2648 | /* |
| 2649 | * GPU can automatically power down the render unit if given a page |
| 2650 | * to save state. |
| 2651 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 2652 | ret = intel_ring_begin(ring, 6); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2653 | if (ret) { |
| 2654 | ironlake_teardown_rc6(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2655 | return; |
| 2656 | } |
| 2657 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 2658 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
| 2659 | intel_ring_emit(ring, MI_SET_CONTEXT); |
| 2660 | intel_ring_emit(ring, dev_priv->renderctx->gtt_offset | |
| 2661 | MI_MM_SPACE_GTT | |
| 2662 | MI_SAVE_EXT_STATE_EN | |
| 2663 | MI_RESTORE_EXT_STATE_EN | |
| 2664 | MI_RESTORE_INHIBIT); |
| 2665 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
| 2666 | intel_ring_emit(ring, MI_NOOP); |
| 2667 | intel_ring_emit(ring, MI_FLUSH); |
| 2668 | intel_ring_advance(ring); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2669 | |
| 2670 | /* |
| 2671 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
| 2672 | * does an implicit flush, combined with MI_FLUSH above, it should be |
| 2673 | * safe to assume that renderctx is valid |
| 2674 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 2675 | ret = intel_wait_ring_idle(ring); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2676 | if (ret) { |
| 2677 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
| 2678 | ironlake_teardown_rc6(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2679 | return; |
| 2680 | } |
| 2681 | |
| 2682 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
| 2683 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2684 | } |
| 2685 | |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 2686 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 2687 | { |
| 2688 | unsigned long freq; |
| 2689 | int div = (vidfreq & 0x3f0000) >> 16; |
| 2690 | int post = (vidfreq & 0x3000) >> 12; |
| 2691 | int pre = (vidfreq & 0x7); |
| 2692 | |
| 2693 | if (!pre) |
| 2694 | return 0; |
| 2695 | |
| 2696 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 2697 | |
| 2698 | return freq; |
| 2699 | } |
| 2700 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2701 | static const struct cparams { |
| 2702 | u16 i; |
| 2703 | u16 t; |
| 2704 | u16 m; |
| 2705 | u16 c; |
| 2706 | } cparams[] = { |
| 2707 | { 1, 1333, 301, 28664 }, |
| 2708 | { 1, 1066, 294, 24460 }, |
| 2709 | { 1, 800, 294, 25192 }, |
| 2710 | { 0, 1333, 276, 27605 }, |
| 2711 | { 0, 1066, 276, 27605 }, |
| 2712 | { 0, 800, 231, 23784 }, |
| 2713 | }; |
| 2714 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 2715 | /** |
| 2716 | * Lock protecting IPS related data structures |
| 2717 | * - i915_mch_dev |
| 2718 | * - dev_priv->max_delay |
| 2719 | * - dev_priv->min_delay |
| 2720 | * - dev_priv->fmax |
| 2721 | * - dev_priv->gpu_busy |
| 2722 | * - dev_priv->gfx_power |
| 2723 | */ |
| 2724 | static DEFINE_SPINLOCK(mchdev_lock); |
| 2725 | |
| 2726 | /* Global for IPS driver to get at the current i915 device. Protected by |
| 2727 | * mchdev_lock. */ |
| 2728 | static struct drm_i915_private *i915_mch_dev; |
| 2729 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2730 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 2731 | { |
| 2732 | u64 total_count, diff, ret; |
| 2733 | u32 count1, count2, count3, m = 0, c = 0; |
| 2734 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 2735 | int i; |
| 2736 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 2737 | assert_spin_locked(&mchdev_lock); |
| 2738 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2739 | diff1 = now - dev_priv->last_time1; |
| 2740 | |
| 2741 | /* Prevent division-by-zero if we are asking too fast. |
| 2742 | * Also, we don't get interesting results if we are polling |
| 2743 | * faster than once in 10ms, so just return the saved value |
| 2744 | * in such cases. |
| 2745 | */ |
| 2746 | if (diff1 <= 10) |
| 2747 | return dev_priv->chipset_power; |
| 2748 | |
| 2749 | count1 = I915_READ(DMIEC); |
| 2750 | count2 = I915_READ(DDREC); |
| 2751 | count3 = I915_READ(CSIEC); |
| 2752 | |
| 2753 | total_count = count1 + count2 + count3; |
| 2754 | |
| 2755 | /* FIXME: handle per-counter overflow */ |
| 2756 | if (total_count < dev_priv->last_count1) { |
| 2757 | diff = ~0UL - dev_priv->last_count1; |
| 2758 | diff += total_count; |
| 2759 | } else { |
| 2760 | diff = total_count - dev_priv->last_count1; |
| 2761 | } |
| 2762 | |
| 2763 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
| 2764 | if (cparams[i].i == dev_priv->c_m && |
| 2765 | cparams[i].t == dev_priv->r_t) { |
| 2766 | m = cparams[i].m; |
| 2767 | c = cparams[i].c; |
| 2768 | break; |
| 2769 | } |
| 2770 | } |
| 2771 | |
| 2772 | diff = div_u64(diff, diff1); |
| 2773 | ret = ((m * diff) + c); |
| 2774 | ret = div_u64(ret, 10); |
| 2775 | |
| 2776 | dev_priv->last_count1 = total_count; |
| 2777 | dev_priv->last_time1 = now; |
| 2778 | |
| 2779 | dev_priv->chipset_power = ret; |
| 2780 | |
| 2781 | return ret; |
| 2782 | } |
| 2783 | |
| 2784 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 2785 | { |
| 2786 | unsigned long m, x, b; |
| 2787 | u32 tsfs; |
| 2788 | |
| 2789 | tsfs = I915_READ(TSFS); |
| 2790 | |
| 2791 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 2792 | x = I915_READ8(TR1); |
| 2793 | |
| 2794 | b = tsfs & TSFS_INTR_MASK; |
| 2795 | |
| 2796 | return ((m * x) / 127) - b; |
| 2797 | } |
| 2798 | |
| 2799 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
| 2800 | { |
| 2801 | static const struct v_table { |
| 2802 | u16 vd; /* in .1 mil */ |
| 2803 | u16 vm; /* in .1 mil */ |
| 2804 | } v_table[] = { |
| 2805 | { 0, 0, }, |
| 2806 | { 375, 0, }, |
| 2807 | { 500, 0, }, |
| 2808 | { 625, 0, }, |
| 2809 | { 750, 0, }, |
| 2810 | { 875, 0, }, |
| 2811 | { 1000, 0, }, |
| 2812 | { 1125, 0, }, |
| 2813 | { 4125, 3000, }, |
| 2814 | { 4125, 3000, }, |
| 2815 | { 4125, 3000, }, |
| 2816 | { 4125, 3000, }, |
| 2817 | { 4125, 3000, }, |
| 2818 | { 4125, 3000, }, |
| 2819 | { 4125, 3000, }, |
| 2820 | { 4125, 3000, }, |
| 2821 | { 4125, 3000, }, |
| 2822 | { 4125, 3000, }, |
| 2823 | { 4125, 3000, }, |
| 2824 | { 4125, 3000, }, |
| 2825 | { 4125, 3000, }, |
| 2826 | { 4125, 3000, }, |
| 2827 | { 4125, 3000, }, |
| 2828 | { 4125, 3000, }, |
| 2829 | { 4125, 3000, }, |
| 2830 | { 4125, 3000, }, |
| 2831 | { 4125, 3000, }, |
| 2832 | { 4125, 3000, }, |
| 2833 | { 4125, 3000, }, |
| 2834 | { 4125, 3000, }, |
| 2835 | { 4125, 3000, }, |
| 2836 | { 4125, 3000, }, |
| 2837 | { 4250, 3125, }, |
| 2838 | { 4375, 3250, }, |
| 2839 | { 4500, 3375, }, |
| 2840 | { 4625, 3500, }, |
| 2841 | { 4750, 3625, }, |
| 2842 | { 4875, 3750, }, |
| 2843 | { 5000, 3875, }, |
| 2844 | { 5125, 4000, }, |
| 2845 | { 5250, 4125, }, |
| 2846 | { 5375, 4250, }, |
| 2847 | { 5500, 4375, }, |
| 2848 | { 5625, 4500, }, |
| 2849 | { 5750, 4625, }, |
| 2850 | { 5875, 4750, }, |
| 2851 | { 6000, 4875, }, |
| 2852 | { 6125, 5000, }, |
| 2853 | { 6250, 5125, }, |
| 2854 | { 6375, 5250, }, |
| 2855 | { 6500, 5375, }, |
| 2856 | { 6625, 5500, }, |
| 2857 | { 6750, 5625, }, |
| 2858 | { 6875, 5750, }, |
| 2859 | { 7000, 5875, }, |
| 2860 | { 7125, 6000, }, |
| 2861 | { 7250, 6125, }, |
| 2862 | { 7375, 6250, }, |
| 2863 | { 7500, 6375, }, |
| 2864 | { 7625, 6500, }, |
| 2865 | { 7750, 6625, }, |
| 2866 | { 7875, 6750, }, |
| 2867 | { 8000, 6875, }, |
| 2868 | { 8125, 7000, }, |
| 2869 | { 8250, 7125, }, |
| 2870 | { 8375, 7250, }, |
| 2871 | { 8500, 7375, }, |
| 2872 | { 8625, 7500, }, |
| 2873 | { 8750, 7625, }, |
| 2874 | { 8875, 7750, }, |
| 2875 | { 9000, 7875, }, |
| 2876 | { 9125, 8000, }, |
| 2877 | { 9250, 8125, }, |
| 2878 | { 9375, 8250, }, |
| 2879 | { 9500, 8375, }, |
| 2880 | { 9625, 8500, }, |
| 2881 | { 9750, 8625, }, |
| 2882 | { 9875, 8750, }, |
| 2883 | { 10000, 8875, }, |
| 2884 | { 10125, 9000, }, |
| 2885 | { 10250, 9125, }, |
| 2886 | { 10375, 9250, }, |
| 2887 | { 10500, 9375, }, |
| 2888 | { 10625, 9500, }, |
| 2889 | { 10750, 9625, }, |
| 2890 | { 10875, 9750, }, |
| 2891 | { 11000, 9875, }, |
| 2892 | { 11125, 10000, }, |
| 2893 | { 11250, 10125, }, |
| 2894 | { 11375, 10250, }, |
| 2895 | { 11500, 10375, }, |
| 2896 | { 11625, 10500, }, |
| 2897 | { 11750, 10625, }, |
| 2898 | { 11875, 10750, }, |
| 2899 | { 12000, 10875, }, |
| 2900 | { 12125, 11000, }, |
| 2901 | { 12250, 11125, }, |
| 2902 | { 12375, 11250, }, |
| 2903 | { 12500, 11375, }, |
| 2904 | { 12625, 11500, }, |
| 2905 | { 12750, 11625, }, |
| 2906 | { 12875, 11750, }, |
| 2907 | { 13000, 11875, }, |
| 2908 | { 13125, 12000, }, |
| 2909 | { 13250, 12125, }, |
| 2910 | { 13375, 12250, }, |
| 2911 | { 13500, 12375, }, |
| 2912 | { 13625, 12500, }, |
| 2913 | { 13750, 12625, }, |
| 2914 | { 13875, 12750, }, |
| 2915 | { 14000, 12875, }, |
| 2916 | { 14125, 13000, }, |
| 2917 | { 14250, 13125, }, |
| 2918 | { 14375, 13250, }, |
| 2919 | { 14500, 13375, }, |
| 2920 | { 14625, 13500, }, |
| 2921 | { 14750, 13625, }, |
| 2922 | { 14875, 13750, }, |
| 2923 | { 15000, 13875, }, |
| 2924 | { 15125, 14000, }, |
| 2925 | { 15250, 14125, }, |
| 2926 | { 15375, 14250, }, |
| 2927 | { 15500, 14375, }, |
| 2928 | { 15625, 14500, }, |
| 2929 | { 15750, 14625, }, |
| 2930 | { 15875, 14750, }, |
| 2931 | { 16000, 14875, }, |
| 2932 | { 16125, 15000, }, |
| 2933 | }; |
| 2934 | if (dev_priv->info->is_mobile) |
| 2935 | return v_table[pxvid].vm; |
| 2936 | else |
| 2937 | return v_table[pxvid].vd; |
| 2938 | } |
| 2939 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 2940 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2941 | { |
| 2942 | struct timespec now, diff1; |
| 2943 | u64 diff; |
| 2944 | unsigned long diffms; |
| 2945 | u32 count; |
| 2946 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 2947 | assert_spin_locked(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2948 | |
| 2949 | getrawmonotonic(&now); |
| 2950 | diff1 = timespec_sub(now, dev_priv->last_time2); |
| 2951 | |
| 2952 | /* Don't divide by 0 */ |
| 2953 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
| 2954 | if (!diffms) |
| 2955 | return; |
| 2956 | |
| 2957 | count = I915_READ(GFXEC); |
| 2958 | |
| 2959 | if (count < dev_priv->last_count2) { |
| 2960 | diff = ~0UL - dev_priv->last_count2; |
| 2961 | diff += count; |
| 2962 | } else { |
| 2963 | diff = count - dev_priv->last_count2; |
| 2964 | } |
| 2965 | |
| 2966 | dev_priv->last_count2 = count; |
| 2967 | dev_priv->last_time2 = now; |
| 2968 | |
| 2969 | /* More magic constants... */ |
| 2970 | diff = diff * 1181; |
| 2971 | diff = div_u64(diff, diffms * 10); |
| 2972 | dev_priv->gfx_power = diff; |
| 2973 | } |
| 2974 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 2975 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 2976 | { |
| 2977 | if (dev_priv->info->gen != 5) |
| 2978 | return; |
| 2979 | |
| 2980 | spin_lock(&mchdev_lock); |
| 2981 | |
| 2982 | __i915_update_gfx_val(dev_priv); |
| 2983 | |
| 2984 | spin_unlock(&mchdev_lock); |
| 2985 | } |
| 2986 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2987 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 2988 | { |
| 2989 | unsigned long t, corr, state1, corr2, state2; |
| 2990 | u32 pxvid, ext_v; |
| 2991 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 2992 | assert_spin_locked(&mchdev_lock); |
| 2993 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 2994 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); |
| 2995 | pxvid = (pxvid >> 24) & 0x7f; |
| 2996 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 2997 | |
| 2998 | state1 = ext_v; |
| 2999 | |
| 3000 | t = i915_mch_val(dev_priv); |
| 3001 | |
| 3002 | /* Revel in the empirically derived constants */ |
| 3003 | |
| 3004 | /* Correction factor in 1/100000 units */ |
| 3005 | if (t > 80) |
| 3006 | corr = ((t * 2349) + 135940); |
| 3007 | else if (t >= 50) |
| 3008 | corr = ((t * 964) + 29317); |
| 3009 | else /* < 50 */ |
| 3010 | corr = ((t * 301) + 1004); |
| 3011 | |
| 3012 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 3013 | corr /= 100000; |
| 3014 | corr2 = (corr * dev_priv->corr); |
| 3015 | |
| 3016 | state2 = (corr2 * state1) / 10000; |
| 3017 | state2 /= 100; /* convert to mW */ |
| 3018 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 3019 | __i915_update_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3020 | |
| 3021 | return dev_priv->gfx_power + state2; |
| 3022 | } |
| 3023 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3024 | /** |
| 3025 | * i915_read_mch_val - return value for IPS use |
| 3026 | * |
| 3027 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 3028 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 3029 | */ |
| 3030 | unsigned long i915_read_mch_val(void) |
| 3031 | { |
| 3032 | struct drm_i915_private *dev_priv; |
| 3033 | unsigned long chipset_val, graphics_val, ret = 0; |
| 3034 | |
| 3035 | spin_lock(&mchdev_lock); |
| 3036 | if (!i915_mch_dev) |
| 3037 | goto out_unlock; |
| 3038 | dev_priv = i915_mch_dev; |
| 3039 | |
| 3040 | chipset_val = i915_chipset_val(dev_priv); |
| 3041 | graphics_val = i915_gfx_val(dev_priv); |
| 3042 | |
| 3043 | ret = chipset_val + graphics_val; |
| 3044 | |
| 3045 | out_unlock: |
| 3046 | spin_unlock(&mchdev_lock); |
| 3047 | |
| 3048 | return ret; |
| 3049 | } |
| 3050 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 3051 | |
| 3052 | /** |
| 3053 | * i915_gpu_raise - raise GPU frequency limit |
| 3054 | * |
| 3055 | * Raise the limit; IPS indicates we have thermal headroom. |
| 3056 | */ |
| 3057 | bool i915_gpu_raise(void) |
| 3058 | { |
| 3059 | struct drm_i915_private *dev_priv; |
| 3060 | bool ret = true; |
| 3061 | |
| 3062 | spin_lock(&mchdev_lock); |
| 3063 | if (!i915_mch_dev) { |
| 3064 | ret = false; |
| 3065 | goto out_unlock; |
| 3066 | } |
| 3067 | dev_priv = i915_mch_dev; |
| 3068 | |
| 3069 | if (dev_priv->max_delay > dev_priv->fmax) |
| 3070 | dev_priv->max_delay--; |
| 3071 | |
| 3072 | out_unlock: |
| 3073 | spin_unlock(&mchdev_lock); |
| 3074 | |
| 3075 | return ret; |
| 3076 | } |
| 3077 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 3078 | |
| 3079 | /** |
| 3080 | * i915_gpu_lower - lower GPU frequency limit |
| 3081 | * |
| 3082 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 3083 | * frequency maximum. |
| 3084 | */ |
| 3085 | bool i915_gpu_lower(void) |
| 3086 | { |
| 3087 | struct drm_i915_private *dev_priv; |
| 3088 | bool ret = true; |
| 3089 | |
| 3090 | spin_lock(&mchdev_lock); |
| 3091 | if (!i915_mch_dev) { |
| 3092 | ret = false; |
| 3093 | goto out_unlock; |
| 3094 | } |
| 3095 | dev_priv = i915_mch_dev; |
| 3096 | |
| 3097 | if (dev_priv->max_delay < dev_priv->min_delay) |
| 3098 | dev_priv->max_delay++; |
| 3099 | |
| 3100 | out_unlock: |
| 3101 | spin_unlock(&mchdev_lock); |
| 3102 | |
| 3103 | return ret; |
| 3104 | } |
| 3105 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 3106 | |
| 3107 | /** |
| 3108 | * i915_gpu_busy - indicate GPU business to IPS |
| 3109 | * |
| 3110 | * Tell the IPS driver whether or not the GPU is busy. |
| 3111 | */ |
| 3112 | bool i915_gpu_busy(void) |
| 3113 | { |
| 3114 | struct drm_i915_private *dev_priv; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 3115 | struct intel_ring_buffer *ring; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3116 | bool ret = false; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 3117 | int i; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3118 | |
| 3119 | spin_lock(&mchdev_lock); |
| 3120 | if (!i915_mch_dev) |
| 3121 | goto out_unlock; |
| 3122 | dev_priv = i915_mch_dev; |
| 3123 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 3124 | for_each_ring(ring, dev_priv, i) |
| 3125 | ret |= !list_empty(&ring->request_list); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3126 | |
| 3127 | out_unlock: |
| 3128 | spin_unlock(&mchdev_lock); |
| 3129 | |
| 3130 | return ret; |
| 3131 | } |
| 3132 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 3133 | |
| 3134 | /** |
| 3135 | * i915_gpu_turbo_disable - disable graphics turbo |
| 3136 | * |
| 3137 | * Disable graphics turbo by resetting the max frequency and setting the |
| 3138 | * current frequency to the default. |
| 3139 | */ |
| 3140 | bool i915_gpu_turbo_disable(void) |
| 3141 | { |
| 3142 | struct drm_i915_private *dev_priv; |
| 3143 | bool ret = true; |
| 3144 | |
| 3145 | spin_lock(&mchdev_lock); |
| 3146 | if (!i915_mch_dev) { |
| 3147 | ret = false; |
| 3148 | goto out_unlock; |
| 3149 | } |
| 3150 | dev_priv = i915_mch_dev; |
| 3151 | |
| 3152 | dev_priv->max_delay = dev_priv->fstart; |
| 3153 | |
| 3154 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) |
| 3155 | ret = false; |
| 3156 | |
| 3157 | out_unlock: |
| 3158 | spin_unlock(&mchdev_lock); |
| 3159 | |
| 3160 | return ret; |
| 3161 | } |
| 3162 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 3163 | |
| 3164 | /** |
| 3165 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 3166 | * IPS got loaded first. |
| 3167 | * |
| 3168 | * This awkward dance is so that neither module has to depend on the |
| 3169 | * other in order for IPS to do the appropriate communication of |
| 3170 | * GPU turbo limits to i915. |
| 3171 | */ |
| 3172 | static void |
| 3173 | ips_ping_for_i915_load(void) |
| 3174 | { |
| 3175 | void (*link)(void); |
| 3176 | |
| 3177 | link = symbol_get(ips_link_to_i915_driver); |
| 3178 | if (link) { |
| 3179 | link(); |
| 3180 | symbol_put(ips_link_to_i915_driver); |
| 3181 | } |
| 3182 | } |
| 3183 | |
| 3184 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
| 3185 | { |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 3186 | /* We only register the i915 ips part with intel-ips once everything is |
| 3187 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3188 | spin_lock(&mchdev_lock); |
| 3189 | i915_mch_dev = dev_priv; |
| 3190 | dev_priv->mchdev_lock = &mchdev_lock; |
| 3191 | spin_unlock(&mchdev_lock); |
| 3192 | |
| 3193 | ips_ping_for_i915_load(); |
| 3194 | } |
| 3195 | |
| 3196 | void intel_gpu_ips_teardown(void) |
| 3197 | { |
| 3198 | spin_lock(&mchdev_lock); |
| 3199 | i915_mch_dev = NULL; |
| 3200 | spin_unlock(&mchdev_lock); |
| 3201 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3202 | static void intel_init_emon(struct drm_device *dev) |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 3203 | { |
| 3204 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3205 | u32 lcfuse; |
| 3206 | u8 pxw[16]; |
| 3207 | int i; |
| 3208 | |
| 3209 | /* Disable to program */ |
| 3210 | I915_WRITE(ECR, 0); |
| 3211 | POSTING_READ(ECR); |
| 3212 | |
| 3213 | /* Program energy weights for various events */ |
| 3214 | I915_WRITE(SDEW, 0x15040d00); |
| 3215 | I915_WRITE(CSIEW0, 0x007f0000); |
| 3216 | I915_WRITE(CSIEW1, 0x1e220004); |
| 3217 | I915_WRITE(CSIEW2, 0x04000004); |
| 3218 | |
| 3219 | for (i = 0; i < 5; i++) |
| 3220 | I915_WRITE(PEW + (i * 4), 0); |
| 3221 | for (i = 0; i < 3; i++) |
| 3222 | I915_WRITE(DEW + (i * 4), 0); |
| 3223 | |
| 3224 | /* Program P-state weights to account for frequency power adjustment */ |
| 3225 | for (i = 0; i < 16; i++) { |
| 3226 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 3227 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 3228 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 3229 | PXVFREQ_PX_SHIFT; |
| 3230 | unsigned long val; |
| 3231 | |
| 3232 | val = vid * vid; |
| 3233 | val *= (freq / 1000); |
| 3234 | val *= 255; |
| 3235 | val /= (127*127*900); |
| 3236 | if (val > 0xff) |
| 3237 | DRM_ERROR("bad pxval: %ld\n", val); |
| 3238 | pxw[i] = val; |
| 3239 | } |
| 3240 | /* Render standby states get 0 weight */ |
| 3241 | pxw[14] = 0; |
| 3242 | pxw[15] = 0; |
| 3243 | |
| 3244 | for (i = 0; i < 4; i++) { |
| 3245 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 3246 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 3247 | I915_WRITE(PXW + (i * 4), val); |
| 3248 | } |
| 3249 | |
| 3250 | /* Adjust magic regs to magic values (more experimental results) */ |
| 3251 | I915_WRITE(OGW0, 0); |
| 3252 | I915_WRITE(OGW1, 0); |
| 3253 | I915_WRITE(EG0, 0x00007f00); |
| 3254 | I915_WRITE(EG1, 0x0000000e); |
| 3255 | I915_WRITE(EG2, 0x000e0000); |
| 3256 | I915_WRITE(EG3, 0x68000300); |
| 3257 | I915_WRITE(EG4, 0x42000000); |
| 3258 | I915_WRITE(EG5, 0x00140031); |
| 3259 | I915_WRITE(EG6, 0); |
| 3260 | I915_WRITE(EG7, 0); |
| 3261 | |
| 3262 | for (i = 0; i < 8; i++) |
| 3263 | I915_WRITE(PXWL + (i * 4), 0); |
| 3264 | |
| 3265 | /* Enable PMON + select events */ |
| 3266 | I915_WRITE(ECR, 0x80000019); |
| 3267 | |
| 3268 | lcfuse = I915_READ(LCFUSE02); |
| 3269 | |
| 3270 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); |
| 3271 | } |
| 3272 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3273 | void intel_disable_gt_powersave(struct drm_device *dev) |
| 3274 | { |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3275 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3276 | ironlake_disable_drps(dev); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3277 | ironlake_disable_rc6(dev); |
| 3278 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3279 | gen6_disable_rps(dev); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3280 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3281 | } |
| 3282 | |
| 3283 | void intel_enable_gt_powersave(struct drm_device *dev) |
| 3284 | { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3285 | if (IS_IRONLAKE_M(dev)) { |
| 3286 | ironlake_enable_drps(dev); |
| 3287 | ironlake_enable_rc6(dev); |
| 3288 | intel_init_emon(dev); |
Eugeni Dodonov | 7cf50fc | 2012-07-02 11:51:06 -0300 | [diff] [blame] | 3289 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3290 | gen6_enable_rps(dev); |
| 3291 | gen6_update_ring_freq(dev); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3292 | } |
| 3293 | } |
| 3294 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3295 | static void ironlake_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3296 | { |
| 3297 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3298 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 3299 | |
| 3300 | /* Required for FBC */ |
| 3301 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
| 3302 | DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 3303 | DPFDUNIT_CLOCK_GATE_DISABLE; |
| 3304 | /* Required for CxSR */ |
| 3305 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
| 3306 | |
| 3307 | I915_WRITE(PCH_3DCGDIS0, |
| 3308 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 3309 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 3310 | I915_WRITE(PCH_3DCGDIS1, |
| 3311 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 3312 | |
| 3313 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
| 3314 | |
| 3315 | /* |
| 3316 | * According to the spec the following bits should be set in |
| 3317 | * order to enable memory self-refresh |
| 3318 | * The bit 22/21 of 0x42004 |
| 3319 | * The bit 5 of 0x42020 |
| 3320 | * The bit 15 of 0x45000 |
| 3321 | */ |
| 3322 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 3323 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 3324 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
| 3325 | I915_WRITE(ILK_DSPCLK_GATE, |
| 3326 | (I915_READ(ILK_DSPCLK_GATE) | |
| 3327 | ILK_DPARB_CLK_GATE)); |
| 3328 | I915_WRITE(DISP_ARB_CTL, |
| 3329 | (I915_READ(DISP_ARB_CTL) | |
| 3330 | DISP_FBC_WM_DIS)); |
| 3331 | I915_WRITE(WM3_LP_ILK, 0); |
| 3332 | I915_WRITE(WM2_LP_ILK, 0); |
| 3333 | I915_WRITE(WM1_LP_ILK, 0); |
| 3334 | |
| 3335 | /* |
| 3336 | * Based on the document from hardware guys the following bits |
| 3337 | * should be set unconditionally in order to enable FBC. |
| 3338 | * The bit 22 of 0x42000 |
| 3339 | * The bit 22 of 0x42004 |
| 3340 | * The bit 7,8,9 of 0x42020. |
| 3341 | */ |
| 3342 | if (IS_IRONLAKE_M(dev)) { |
| 3343 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 3344 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 3345 | ILK_FBCQ_DIS); |
| 3346 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 3347 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 3348 | ILK_DPARB_GATE); |
| 3349 | I915_WRITE(ILK_DSPCLK_GATE, |
| 3350 | I915_READ(ILK_DSPCLK_GATE) | |
| 3351 | ILK_DPFC_DIS1 | |
| 3352 | ILK_DPFC_DIS2 | |
| 3353 | ILK_CLK_FBC); |
| 3354 | } |
| 3355 | |
| 3356 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 3357 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 3358 | ILK_ELPIN_409_SELECT); |
| 3359 | I915_WRITE(_3D_CHICKEN2, |
| 3360 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 3361 | _3D_CHICKEN2_WM_READ_PIPELINED); |
| 3362 | } |
| 3363 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3364 | static void gen6_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3365 | { |
| 3366 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3367 | int pipe; |
| 3368 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 3369 | |
| 3370 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
| 3371 | |
| 3372 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 3373 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 3374 | ILK_ELPIN_409_SELECT); |
| 3375 | |
| 3376 | I915_WRITE(WM3_LP_ILK, 0); |
| 3377 | I915_WRITE(WM2_LP_ILK, 0); |
| 3378 | I915_WRITE(WM1_LP_ILK, 0); |
| 3379 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3380 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 3381 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3382 | |
| 3383 | I915_WRITE(GEN6_UCGCTL1, |
| 3384 | I915_READ(GEN6_UCGCTL1) | |
| 3385 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
| 3386 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
| 3387 | |
| 3388 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 3389 | * gating disable must be set. Failure to set it results in |
| 3390 | * flickering pixels due to Z write ordering failures after |
| 3391 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 3392 | * Sanctuary and Tropics, and apparently anything else with |
| 3393 | * alpha test or pixel discard. |
| 3394 | * |
| 3395 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 3396 | * but we didn't debug actual testcases to find it out. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 3397 | * |
| 3398 | * Also apply WaDisableVDSUnitClockGating and |
| 3399 | * WaDisableRCPBUnitClockGating. |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3400 | */ |
| 3401 | I915_WRITE(GEN6_UCGCTL2, |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 3402 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3403 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 3404 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 3405 | |
| 3406 | /* Bspec says we need to always set all mask bits. */ |
| 3407 | I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) | |
| 3408 | _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL); |
| 3409 | |
| 3410 | /* |
| 3411 | * According to the spec the following bits should be |
| 3412 | * set in order to enable memory self-refresh and fbc: |
| 3413 | * The bit21 and bit22 of 0x42000 |
| 3414 | * The bit21 and bit22 of 0x42004 |
| 3415 | * The bit5 and bit7 of 0x42020 |
| 3416 | * The bit14 of 0x70180 |
| 3417 | * The bit14 of 0x71180 |
| 3418 | */ |
| 3419 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 3420 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 3421 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 3422 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 3423 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 3424 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
| 3425 | I915_WRITE(ILK_DSPCLK_GATE, |
| 3426 | I915_READ(ILK_DSPCLK_GATE) | |
| 3427 | ILK_DPARB_CLK_GATE | |
| 3428 | ILK_DPFD_CLK_GATE); |
| 3429 | |
Jesse Barnes | b4ae3f2 | 2012-06-14 11:04:48 -0700 | [diff] [blame] | 3430 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 3431 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 3432 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3433 | for_each_pipe(pipe) { |
| 3434 | I915_WRITE(DSPCNTR(pipe), |
| 3435 | I915_READ(DSPCNTR(pipe)) | |
| 3436 | DISPPLANE_TRICKLE_FEED_DISABLE); |
| 3437 | intel_flush_display_plane(dev_priv, pipe); |
| 3438 | } |
| 3439 | } |
| 3440 | |
| 3441 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
| 3442 | { |
| 3443 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
| 3444 | |
| 3445 | reg &= ~GEN7_FF_SCHED_MASK; |
| 3446 | reg |= GEN7_FF_TS_SCHED_HW; |
| 3447 | reg |= GEN7_FF_VS_SCHED_HW; |
| 3448 | reg |= GEN7_FF_DS_SCHED_HW; |
| 3449 | |
| 3450 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
| 3451 | } |
| 3452 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 3453 | static void haswell_init_clock_gating(struct drm_device *dev) |
| 3454 | { |
| 3455 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3456 | int pipe; |
| 3457 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 3458 | |
| 3459 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
| 3460 | |
| 3461 | I915_WRITE(WM3_LP_ILK, 0); |
| 3462 | I915_WRITE(WM2_LP_ILK, 0); |
| 3463 | I915_WRITE(WM1_LP_ILK, 0); |
| 3464 | |
| 3465 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
| 3466 | * This implements the WaDisableRCZUnitClockGating workaround. |
| 3467 | */ |
| 3468 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
| 3469 | |
| 3470 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
| 3471 | |
| 3472 | I915_WRITE(IVB_CHICKEN3, |
| 3473 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 3474 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 3475 | |
| 3476 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
| 3477 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 3478 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 3479 | |
| 3480 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
| 3481 | I915_WRITE(GEN7_L3CNTLREG1, |
| 3482 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 3483 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
| 3484 | GEN7_WA_L3_CHICKEN_MODE); |
| 3485 | |
| 3486 | /* This is required by WaCatErrorRejectionIssue */ |
| 3487 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 3488 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 3489 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 3490 | |
| 3491 | for_each_pipe(pipe) { |
| 3492 | I915_WRITE(DSPCNTR(pipe), |
| 3493 | I915_READ(DSPCNTR(pipe)) | |
| 3494 | DISPPLANE_TRICKLE_FEED_DISABLE); |
| 3495 | intel_flush_display_plane(dev_priv, pipe); |
| 3496 | } |
| 3497 | |
| 3498 | gen7_setup_fixed_func_scheduler(dev_priv); |
| 3499 | |
| 3500 | /* WaDisable4x2SubspanOptimization */ |
| 3501 | I915_WRITE(CACHE_MODE_1, |
| 3502 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 3503 | |
| 3504 | /* XXX: This is a workaround for early silicon revisions and should be |
| 3505 | * removed later. |
| 3506 | */ |
| 3507 | I915_WRITE(WM_DBG, |
| 3508 | I915_READ(WM_DBG) | |
| 3509 | WM_DBG_DISALLOW_MULTIPLE_LP | |
| 3510 | WM_DBG_DISALLOW_SPRITE | |
| 3511 | WM_DBG_DISALLOW_MAXFIFO); |
| 3512 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 3513 | } |
| 3514 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3515 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3516 | { |
| 3517 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3518 | int pipe; |
| 3519 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 3520 | uint32_t snpcr; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3521 | |
| 3522 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
| 3523 | |
| 3524 | I915_WRITE(WM3_LP_ILK, 0); |
| 3525 | I915_WRITE(WM2_LP_ILK, 0); |
| 3526 | I915_WRITE(WM1_LP_ILK, 0); |
| 3527 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3528 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
| 3529 | |
| 3530 | I915_WRITE(IVB_CHICKEN3, |
| 3531 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 3532 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 3533 | |
| 3534 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
| 3535 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 3536 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 3537 | |
| 3538 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
| 3539 | I915_WRITE(GEN7_L3CNTLREG1, |
| 3540 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 3541 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
| 3542 | GEN7_WA_L3_CHICKEN_MODE); |
| 3543 | |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 3544 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 3545 | * gating disable must be set. Failure to set it results in |
| 3546 | * flickering pixels due to Z write ordering failures after |
| 3547 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 3548 | * Sanctuary and Tropics, and apparently anything else with |
| 3549 | * alpha test or pixel discard. |
| 3550 | * |
| 3551 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 3552 | * but we didn't debug actual testcases to find it out. |
| 3553 | * |
| 3554 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
| 3555 | * This implements the WaDisableRCZUnitClockGating workaround. |
| 3556 | */ |
| 3557 | I915_WRITE(GEN6_UCGCTL2, |
| 3558 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
| 3559 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 3560 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3561 | /* This is required by WaCatErrorRejectionIssue */ |
| 3562 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 3563 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 3564 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 3565 | |
| 3566 | for_each_pipe(pipe) { |
| 3567 | I915_WRITE(DSPCNTR(pipe), |
| 3568 | I915_READ(DSPCNTR(pipe)) | |
| 3569 | DISPPLANE_TRICKLE_FEED_DISABLE); |
| 3570 | intel_flush_display_plane(dev_priv, pipe); |
| 3571 | } |
| 3572 | |
Jesse Barnes | b4ae3f2 | 2012-06-14 11:04:48 -0700 | [diff] [blame] | 3573 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 3574 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 3575 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3576 | gen7_setup_fixed_func_scheduler(dev_priv); |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 3577 | |
| 3578 | /* WaDisable4x2SubspanOptimization */ |
| 3579 | I915_WRITE(CACHE_MODE_1, |
| 3580 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 3581 | |
| 3582 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 3583 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 3584 | snpcr |= GEN6_MBC_SNPCR_MED; |
| 3585 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3586 | } |
| 3587 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3588 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3589 | { |
| 3590 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3591 | int pipe; |
| 3592 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 3593 | |
| 3594 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
| 3595 | |
| 3596 | I915_WRITE(WM3_LP_ILK, 0); |
| 3597 | I915_WRITE(WM2_LP_ILK, 0); |
| 3598 | I915_WRITE(WM1_LP_ILK, 0); |
| 3599 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3600 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
| 3601 | |
| 3602 | I915_WRITE(IVB_CHICKEN3, |
| 3603 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 3604 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 3605 | |
| 3606 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
| 3607 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 3608 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 3609 | |
| 3610 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
| 3611 | I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 3612 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
| 3613 | |
| 3614 | /* This is required by WaCatErrorRejectionIssue */ |
| 3615 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 3616 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 3617 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 3618 | |
Jesse Barnes | b4ae3f2 | 2012-06-14 11:04:48 -0700 | [diff] [blame] | 3619 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 3620 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 3621 | |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 3622 | |
| 3623 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 3624 | * gating disable must be set. Failure to set it results in |
| 3625 | * flickering pixels due to Z write ordering failures after |
| 3626 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 3627 | * Sanctuary and Tropics, and apparently anything else with |
| 3628 | * alpha test or pixel discard. |
| 3629 | * |
| 3630 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 3631 | * but we didn't debug actual testcases to find it out. |
| 3632 | * |
| 3633 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
| 3634 | * This implements the WaDisableRCZUnitClockGating workaround. |
| 3635 | * |
| 3636 | * Also apply WaDisableVDSUnitClockGating and |
| 3637 | * WaDisableRCPBUnitClockGating. |
| 3638 | */ |
| 3639 | I915_WRITE(GEN6_UCGCTL2, |
| 3640 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
Jesse Barnes | 6edaa7f | 2012-06-14 11:04:49 -0700 | [diff] [blame] | 3641 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 3642 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
| 3643 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 3644 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 3645 | |
Jesse Barnes | e3f33d4 | 2012-06-14 11:04:50 -0700 | [diff] [blame] | 3646 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
| 3647 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3648 | for_each_pipe(pipe) { |
| 3649 | I915_WRITE(DSPCNTR(pipe), |
| 3650 | I915_READ(DSPCNTR(pipe)) | |
| 3651 | DISPPLANE_TRICKLE_FEED_DISABLE); |
| 3652 | intel_flush_display_plane(dev_priv, pipe); |
| 3653 | } |
| 3654 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3655 | I915_WRITE(CACHE_MODE_1, |
| 3656 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Jesse Barnes | 7983117 | 2012-06-20 10:53:12 -0700 | [diff] [blame] | 3657 | |
| 3658 | /* |
| 3659 | * On ValleyView, the GUnit needs to signal the GT |
| 3660 | * when flip and other events complete. So enable |
| 3661 | * all the GUnit->GT interrupts here |
| 3662 | */ |
| 3663 | I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | |
| 3664 | PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | |
| 3665 | SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | |
| 3666 | PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | |
| 3667 | PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | |
| 3668 | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | |
| 3669 | PLANEA_FLIPDONE_INT_EN); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3670 | } |
| 3671 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3672 | static void g4x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3673 | { |
| 3674 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3675 | uint32_t dspclk_gate; |
| 3676 | |
| 3677 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 3678 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 3679 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 3680 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 3681 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 3682 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 3683 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 3684 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 3685 | if (IS_GM45(dev)) |
| 3686 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 3687 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
| 3688 | } |
| 3689 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3690 | static void crestline_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3691 | { |
| 3692 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3693 | |
| 3694 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 3695 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 3696 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 3697 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 3698 | I915_WRITE16(DEUC, 0); |
| 3699 | } |
| 3700 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3701 | static void broadwater_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3702 | { |
| 3703 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3704 | |
| 3705 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 3706 | I965_RCC_CLOCK_GATE_DISABLE | |
| 3707 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 3708 | I965_ISC_CLOCK_GATE_DISABLE | |
| 3709 | I965_FBC_CLOCK_GATE_DISABLE); |
| 3710 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 3711 | } |
| 3712 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3713 | static void gen3_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3714 | { |
| 3715 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3716 | u32 dstate = I915_READ(D_STATE); |
| 3717 | |
| 3718 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 3719 | DSTATE_DOT_CLOCK_GATING; |
| 3720 | I915_WRITE(D_STATE, dstate); |
Chris Wilson | 13a86b8 | 2012-04-24 14:51:43 +0100 | [diff] [blame] | 3721 | |
| 3722 | if (IS_PINEVIEW(dev)) |
| 3723 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3724 | } |
| 3725 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3726 | static void i85x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3727 | { |
| 3728 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3729 | |
| 3730 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 3731 | } |
| 3732 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3733 | static void i830_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3734 | { |
| 3735 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3736 | |
| 3737 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 3738 | } |
| 3739 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3740 | static void ibx_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3741 | { |
| 3742 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3743 | |
| 3744 | /* |
| 3745 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 3746 | * gating for the panel power sequencer or it will fail to |
| 3747 | * start up when no ports are active. |
| 3748 | */ |
| 3749 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 3750 | } |
| 3751 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3752 | static void cpt_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 3753 | { |
| 3754 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3755 | int pipe; |
| 3756 | |
| 3757 | /* |
| 3758 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 3759 | * gating for the panel power sequencer or it will fail to |
| 3760 | * start up when no ports are active. |
| 3761 | */ |
| 3762 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 3763 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 3764 | DPLS_EDP_PPS_FIX_DIS); |
| 3765 | /* Without this, mode sets may fail silently on FDI */ |
| 3766 | for_each_pipe(pipe) |
| 3767 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); |
| 3768 | } |
| 3769 | |
| 3770 | void intel_init_clock_gating(struct drm_device *dev) |
| 3771 | { |
| 3772 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3773 | |
| 3774 | dev_priv->display.init_clock_gating(dev); |
| 3775 | |
| 3776 | if (dev_priv->display.init_pch_clock_gating) |
| 3777 | dev_priv->display.init_pch_clock_gating(dev); |
| 3778 | } |
| 3779 | |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 3780 | /* Starting with Haswell, we have different power wells for |
| 3781 | * different parts of the GPU. This attempts to enable them all. |
| 3782 | */ |
| 3783 | void intel_init_power_wells(struct drm_device *dev) |
| 3784 | { |
| 3785 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3786 | unsigned long power_wells[] = { |
| 3787 | HSW_PWR_WELL_CTL1, |
| 3788 | HSW_PWR_WELL_CTL2, |
| 3789 | HSW_PWR_WELL_CTL4 |
| 3790 | }; |
| 3791 | int i; |
| 3792 | |
| 3793 | if (!IS_HASWELL(dev)) |
| 3794 | return; |
| 3795 | |
| 3796 | mutex_lock(&dev->struct_mutex); |
| 3797 | |
| 3798 | for (i = 0; i < ARRAY_SIZE(power_wells); i++) { |
| 3799 | int well = I915_READ(power_wells[i]); |
| 3800 | |
| 3801 | if ((well & HSW_PWR_WELL_STATE) == 0) { |
| 3802 | I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); |
| 3803 | if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) |
| 3804 | DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); |
| 3805 | } |
| 3806 | } |
| 3807 | |
| 3808 | mutex_unlock(&dev->struct_mutex); |
| 3809 | } |
| 3810 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3811 | /* Set up chip specific power management-related functions */ |
| 3812 | void intel_init_pm(struct drm_device *dev) |
| 3813 | { |
| 3814 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3815 | |
| 3816 | if (I915_HAS_FBC(dev)) { |
| 3817 | if (HAS_PCH_SPLIT(dev)) { |
| 3818 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
| 3819 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
| 3820 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 3821 | } else if (IS_GM45(dev)) { |
| 3822 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 3823 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 3824 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
| 3825 | } else if (IS_CRESTLINE(dev)) { |
| 3826 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 3827 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 3828 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
| 3829 | } |
| 3830 | /* 855GM needs testing */ |
| 3831 | } |
| 3832 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 3833 | /* For cxsr */ |
| 3834 | if (IS_PINEVIEW(dev)) |
| 3835 | i915_pineview_get_mem_freq(dev); |
| 3836 | else if (IS_GEN5(dev)) |
| 3837 | i915_ironlake_get_mem_freq(dev); |
| 3838 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3839 | /* For FIFO watermark updates */ |
| 3840 | if (HAS_PCH_SPLIT(dev)) { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3841 | if (HAS_PCH_IBX(dev)) |
| 3842 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; |
| 3843 | else if (HAS_PCH_CPT(dev)) |
| 3844 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; |
| 3845 | |
| 3846 | if (IS_GEN5(dev)) { |
| 3847 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
| 3848 | dev_priv->display.update_wm = ironlake_update_wm; |
| 3849 | else { |
| 3850 | DRM_DEBUG_KMS("Failed to get proper latency. " |
| 3851 | "Disable CxSR\n"); |
| 3852 | dev_priv->display.update_wm = NULL; |
| 3853 | } |
| 3854 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
| 3855 | } else if (IS_GEN6(dev)) { |
| 3856 | if (SNB_READ_WM0_LATENCY()) { |
| 3857 | dev_priv->display.update_wm = sandybridge_update_wm; |
| 3858 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
| 3859 | } else { |
| 3860 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 3861 | "Disable CxSR\n"); |
| 3862 | dev_priv->display.update_wm = NULL; |
| 3863 | } |
| 3864 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
| 3865 | } else if (IS_IVYBRIDGE(dev)) { |
| 3866 | /* FIXME: detect B0+ stepping and use auto training */ |
| 3867 | if (SNB_READ_WM0_LATENCY()) { |
| 3868 | dev_priv->display.update_wm = sandybridge_update_wm; |
| 3869 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
| 3870 | } else { |
| 3871 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 3872 | "Disable CxSR\n"); |
| 3873 | dev_priv->display.update_wm = NULL; |
| 3874 | } |
| 3875 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Eugeni Dodonov | 6b8a5ee | 2012-05-09 15:37:23 -0300 | [diff] [blame] | 3876 | } else if (IS_HASWELL(dev)) { |
| 3877 | if (SNB_READ_WM0_LATENCY()) { |
| 3878 | dev_priv->display.update_wm = sandybridge_update_wm; |
| 3879 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 3880 | dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; |
Eugeni Dodonov | 6b8a5ee | 2012-05-09 15:37:23 -0300 | [diff] [blame] | 3881 | } else { |
| 3882 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 3883 | "Disable CxSR\n"); |
| 3884 | dev_priv->display.update_wm = NULL; |
| 3885 | } |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 3886 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3887 | } else |
| 3888 | dev_priv->display.update_wm = NULL; |
| 3889 | } else if (IS_VALLEYVIEW(dev)) { |
| 3890 | dev_priv->display.update_wm = valleyview_update_wm; |
| 3891 | dev_priv->display.init_clock_gating = |
| 3892 | valleyview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 3893 | } else if (IS_PINEVIEW(dev)) { |
| 3894 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
| 3895 | dev_priv->is_ddr3, |
| 3896 | dev_priv->fsb_freq, |
| 3897 | dev_priv->mem_freq)) { |
| 3898 | DRM_INFO("failed to find known CxSR latency " |
| 3899 | "(found ddr%s fsb freq %d, mem freq %d), " |
| 3900 | "disabling CxSR\n", |
| 3901 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
| 3902 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 3903 | /* Disable CxSR and never update its watermark again */ |
| 3904 | pineview_disable_cxsr(dev); |
| 3905 | dev_priv->display.update_wm = NULL; |
| 3906 | } else |
| 3907 | dev_priv->display.update_wm = pineview_update_wm; |
| 3908 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 3909 | } else if (IS_G4X(dev)) { |
| 3910 | dev_priv->display.update_wm = g4x_update_wm; |
| 3911 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 3912 | } else if (IS_GEN4(dev)) { |
| 3913 | dev_priv->display.update_wm = i965_update_wm; |
| 3914 | if (IS_CRESTLINE(dev)) |
| 3915 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 3916 | else if (IS_BROADWATER(dev)) |
| 3917 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 3918 | } else if (IS_GEN3(dev)) { |
| 3919 | dev_priv->display.update_wm = i9xx_update_wm; |
| 3920 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 3921 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 3922 | } else if (IS_I865G(dev)) { |
| 3923 | dev_priv->display.update_wm = i830_update_wm; |
| 3924 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 3925 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
| 3926 | } else if (IS_I85X(dev)) { |
| 3927 | dev_priv->display.update_wm = i9xx_update_wm; |
| 3928 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
| 3929 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 3930 | } else { |
| 3931 | dev_priv->display.update_wm = i830_update_wm; |
| 3932 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
| 3933 | if (IS_845G(dev)) |
| 3934 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
| 3935 | else |
| 3936 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
| 3937 | } |
| 3938 | } |
| 3939 | |
Eugeni Dodonov | 6590190 | 2012-07-02 11:51:11 -0300 | [diff] [blame] | 3940 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 3941 | { |
| 3942 | u32 gt_thread_status_mask; |
| 3943 | |
| 3944 | if (IS_HASWELL(dev_priv->dev)) |
| 3945 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
| 3946 | else |
| 3947 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
| 3948 | |
| 3949 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 3950 | * thread to wake up. |
| 3951 | */ |
| 3952 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
| 3953 | DRM_ERROR("GT thread status wait timed out\n"); |
| 3954 | } |
| 3955 | |
| 3956 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 3957 | { |
| 3958 | u32 forcewake_ack; |
| 3959 | |
| 3960 | if (IS_HASWELL(dev_priv->dev)) |
| 3961 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 3962 | else |
| 3963 | forcewake_ack = FORCEWAKE_ACK; |
| 3964 | |
| 3965 | if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500)) |
| 3966 | DRM_ERROR("Force wake wait timed out\n"); |
| 3967 | |
| 3968 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
| 3969 | |
| 3970 | if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) |
| 3971 | DRM_ERROR("Force wake wait timed out\n"); |
| 3972 | |
| 3973 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 3974 | } |
| 3975 | |
| 3976 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
| 3977 | { |
| 3978 | u32 forcewake_ack; |
| 3979 | |
| 3980 | if (IS_HASWELL(dev_priv->dev)) |
| 3981 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 3982 | else |
| 3983 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 3984 | |
| 3985 | if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500)) |
| 3986 | DRM_ERROR("Force wake wait timed out\n"); |
| 3987 | |
| 3988 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); |
| 3989 | |
| 3990 | if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) |
| 3991 | DRM_ERROR("Force wake wait timed out\n"); |
| 3992 | |
| 3993 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 3994 | } |
| 3995 | |
| 3996 | /* |
| 3997 | * Generally this is called implicitly by the register read function. However, |
| 3998 | * if some sequence requires the GT to not power down then this function should |
| 3999 | * be called at the beginning of the sequence followed by a call to |
| 4000 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 4001 | */ |
| 4002 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 4003 | { |
| 4004 | unsigned long irqflags; |
| 4005 | |
| 4006 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
| 4007 | if (dev_priv->forcewake_count++ == 0) |
| 4008 | dev_priv->gt.force_wake_get(dev_priv); |
| 4009 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
| 4010 | } |
| 4011 | |
| 4012 | void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 4013 | { |
| 4014 | u32 gtfifodbg; |
| 4015 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); |
| 4016 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
| 4017 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
| 4018 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
| 4019 | } |
| 4020 | |
| 4021 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 4022 | { |
| 4023 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
| 4024 | /* The below doubles as a POSTING_READ */ |
| 4025 | gen6_gt_check_fifodbg(dev_priv); |
| 4026 | } |
| 4027 | |
| 4028 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
| 4029 | { |
| 4030 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); |
| 4031 | /* The below doubles as a POSTING_READ */ |
| 4032 | gen6_gt_check_fifodbg(dev_priv); |
| 4033 | } |
| 4034 | |
| 4035 | /* |
| 4036 | * see gen6_gt_force_wake_get() |
| 4037 | */ |
| 4038 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 4039 | { |
| 4040 | unsigned long irqflags; |
| 4041 | |
| 4042 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
| 4043 | if (--dev_priv->forcewake_count == 0) |
| 4044 | dev_priv->gt.force_wake_put(dev_priv); |
| 4045 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
| 4046 | } |
| 4047 | |
| 4048 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 4049 | { |
| 4050 | int ret = 0; |
| 4051 | |
| 4052 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 4053 | int loop = 500; |
| 4054 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 4055 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 4056 | udelay(10); |
| 4057 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 4058 | } |
| 4059 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 4060 | ++ret; |
| 4061 | dev_priv->gt_fifo_count = fifo; |
| 4062 | } |
| 4063 | dev_priv->gt_fifo_count--; |
| 4064 | |
| 4065 | return ret; |
| 4066 | } |
| 4067 | |
| 4068 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
| 4069 | { |
| 4070 | /* Already awake? */ |
| 4071 | if ((I915_READ(0x130094) & 0xa1) == 0xa1) |
| 4072 | return; |
| 4073 | |
| 4074 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff); |
| 4075 | POSTING_READ(FORCEWAKE_VLV); |
| 4076 | |
| 4077 | if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500)) |
| 4078 | DRM_ERROR("Force wake wait timed out\n"); |
| 4079 | |
| 4080 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 4081 | } |
| 4082 | |
| 4083 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
| 4084 | { |
| 4085 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000); |
| 4086 | /* FIXME: confirm VLV behavior with Punit folks */ |
| 4087 | POSTING_READ(FORCEWAKE_VLV); |
| 4088 | } |
| 4089 | |
| 4090 | void intel_gt_init(struct drm_device *dev) |
| 4091 | { |
| 4092 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4093 | |
| 4094 | spin_lock_init(&dev_priv->gt_lock); |
| 4095 | |
| 4096 | if (IS_VALLEYVIEW(dev)) { |
| 4097 | dev_priv->gt.force_wake_get = vlv_force_wake_get; |
| 4098 | dev_priv->gt.force_wake_put = vlv_force_wake_put; |
| 4099 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 4100 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
| 4101 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
| 4102 | |
| 4103 | /* IVB configs may use multi-threaded forcewake */ |
| 4104 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
| 4105 | u32 ecobus; |
| 4106 | |
| 4107 | /* A small trick here - if the bios hasn't configured |
| 4108 | * MT forcewake, and if the device is in RC6, then |
| 4109 | * force_wake_mt_get will not wake the device and the |
| 4110 | * ECOBUS read will return zero. Which will be |
| 4111 | * (correctly) interpreted by the test below as MT |
| 4112 | * forcewake being disabled. |
| 4113 | */ |
| 4114 | mutex_lock(&dev->struct_mutex); |
| 4115 | __gen6_gt_force_wake_mt_get(dev_priv); |
| 4116 | ecobus = I915_READ_NOTRACE(ECOBUS); |
| 4117 | __gen6_gt_force_wake_mt_put(dev_priv); |
| 4118 | mutex_unlock(&dev->struct_mutex); |
| 4119 | |
| 4120 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 4121 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); |
| 4122 | dev_priv->gt.force_wake_get = |
| 4123 | __gen6_gt_force_wake_mt_get; |
| 4124 | dev_priv->gt.force_wake_put = |
| 4125 | __gen6_gt_force_wake_mt_put; |
| 4126 | } |
| 4127 | } |
| 4128 | } |
| 4129 | } |
| 4130 | |