Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
| 3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
Thierry Reding | 9eb9b22 | 2013-09-24 16:32:47 +0200 | [diff] [blame] | 11 | #include <linux/debugfs.h> |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 12 | #include <linux/gpio.h> |
Thierry Reding | 9eb9b22 | 2013-09-24 16:32:47 +0200 | [diff] [blame] | 13 | #include <linux/hdmi.h> |
| 14 | #include <linux/regulator/consumer.h> |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 15 | #include <linux/reset.h> |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 16 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 17 | #include <drm/drm_atomic_helper.h> |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 18 | #include <drm/drm_crtc.h> |
| 19 | #include <drm/drm_crtc_helper.h> |
| 20 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 21 | #include "hdmi.h" |
| 22 | #include "drm.h" |
| 23 | #include "dc.h" |
| 24 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 25 | struct tmds_config { |
| 26 | unsigned int pclk; |
| 27 | u32 pll0; |
| 28 | u32 pll1; |
| 29 | u32 pe_current; |
| 30 | u32 drive_current; |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 31 | u32 peak_current; |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 32 | }; |
| 33 | |
| 34 | struct tegra_hdmi_config { |
| 35 | const struct tmds_config *tmds; |
| 36 | unsigned int num_tmds; |
| 37 | |
| 38 | unsigned long fuse_override_offset; |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 39 | u32 fuse_override_value; |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 40 | |
| 41 | bool has_sor_io_peak_current; |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 42 | }; |
| 43 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 44 | struct tegra_hdmi { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 45 | struct host1x_client client; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 46 | struct tegra_output output; |
| 47 | struct device *dev; |
| 48 | |
Thierry Reding | fb50a11 | 2014-02-28 16:57:34 +0100 | [diff] [blame] | 49 | struct regulator *hdmi; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 50 | struct regulator *pll; |
Thierry Reding | 8868568 | 2014-04-16 10:24:12 +0200 | [diff] [blame] | 51 | struct regulator *vdd; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 52 | |
| 53 | void __iomem *regs; |
| 54 | unsigned int irq; |
| 55 | |
| 56 | struct clk *clk_parent; |
| 57 | struct clk *clk; |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 58 | struct reset_control *rst; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 59 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 60 | const struct tegra_hdmi_config *config; |
| 61 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 62 | unsigned int audio_source; |
| 63 | unsigned int audio_freq; |
| 64 | bool stereo; |
| 65 | bool dvi; |
| 66 | |
| 67 | struct drm_info_list *debugfs_files; |
| 68 | struct drm_minor *minor; |
| 69 | struct dentry *debugfs; |
| 70 | }; |
| 71 | |
| 72 | static inline struct tegra_hdmi * |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 73 | host1x_client_to_hdmi(struct host1x_client *client) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 74 | { |
| 75 | return container_of(client, struct tegra_hdmi, client); |
| 76 | } |
| 77 | |
| 78 | static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output) |
| 79 | { |
| 80 | return container_of(output, struct tegra_hdmi, output); |
| 81 | } |
| 82 | |
| 83 | #define HDMI_AUDIOCLK_FREQ 216000000 |
| 84 | #define HDMI_REKEY_DEFAULT 56 |
| 85 | |
| 86 | enum { |
| 87 | AUTO = 0, |
| 88 | SPDIF, |
| 89 | HDA, |
| 90 | }; |
| 91 | |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 92 | static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, |
| 93 | unsigned long offset) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 94 | { |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 95 | return readl(hdmi->regs + (offset << 2)); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 96 | } |
| 97 | |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 98 | static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, |
| 99 | unsigned long offset) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 100 | { |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 101 | writel(value, hdmi->regs + (offset << 2)); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | struct tegra_hdmi_audio_config { |
| 105 | unsigned int pclk; |
| 106 | unsigned int n; |
| 107 | unsigned int cts; |
| 108 | unsigned int aval; |
| 109 | }; |
| 110 | |
| 111 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = { |
| 112 | { 25200000, 4096, 25200, 24000 }, |
| 113 | { 27000000, 4096, 27000, 24000 }, |
| 114 | { 74250000, 4096, 74250, 24000 }, |
| 115 | { 148500000, 4096, 148500, 24000 }, |
| 116 | { 0, 0, 0, 0 }, |
| 117 | }; |
| 118 | |
| 119 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = { |
| 120 | { 25200000, 5880, 26250, 25000 }, |
| 121 | { 27000000, 5880, 28125, 25000 }, |
| 122 | { 74250000, 4704, 61875, 20000 }, |
| 123 | { 148500000, 4704, 123750, 20000 }, |
| 124 | { 0, 0, 0, 0 }, |
| 125 | }; |
| 126 | |
| 127 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = { |
| 128 | { 25200000, 6144, 25200, 24000 }, |
| 129 | { 27000000, 6144, 27000, 24000 }, |
| 130 | { 74250000, 6144, 74250, 24000 }, |
| 131 | { 148500000, 6144, 148500, 24000 }, |
| 132 | { 0, 0, 0, 0 }, |
| 133 | }; |
| 134 | |
| 135 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = { |
| 136 | { 25200000, 11760, 26250, 25000 }, |
| 137 | { 27000000, 11760, 28125, 25000 }, |
| 138 | { 74250000, 9408, 61875, 20000 }, |
| 139 | { 148500000, 9408, 123750, 20000 }, |
| 140 | { 0, 0, 0, 0 }, |
| 141 | }; |
| 142 | |
| 143 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = { |
| 144 | { 25200000, 12288, 25200, 24000 }, |
| 145 | { 27000000, 12288, 27000, 24000 }, |
| 146 | { 74250000, 12288, 74250, 24000 }, |
| 147 | { 148500000, 12288, 148500, 24000 }, |
| 148 | { 0, 0, 0, 0 }, |
| 149 | }; |
| 150 | |
| 151 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = { |
| 152 | { 25200000, 23520, 26250, 25000 }, |
| 153 | { 27000000, 23520, 28125, 25000 }, |
| 154 | { 74250000, 18816, 61875, 20000 }, |
| 155 | { 148500000, 18816, 123750, 20000 }, |
| 156 | { 0, 0, 0, 0 }, |
| 157 | }; |
| 158 | |
| 159 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = { |
| 160 | { 25200000, 24576, 25200, 24000 }, |
| 161 | { 27000000, 24576, 27000, 24000 }, |
| 162 | { 74250000, 24576, 74250, 24000 }, |
| 163 | { 148500000, 24576, 148500, 24000 }, |
| 164 | { 0, 0, 0, 0 }, |
| 165 | }; |
| 166 | |
Thierry Reding | f27db96 | 2013-09-30 15:14:41 +0200 | [diff] [blame] | 167 | static const struct tmds_config tegra20_tmds_config[] = { |
Lucas Stach | fa416dd | 2012-12-19 21:38:55 +0000 | [diff] [blame] | 168 | { /* slow pixel clock modes */ |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 169 | .pclk = 27000000, |
| 170 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 171 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | |
| 172 | SOR_PLL_TX_REG_LOAD(3), |
| 173 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE, |
| 174 | .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | |
| 175 | PE_CURRENT1(PE_CURRENT_0_0_mA) | |
| 176 | PE_CURRENT2(PE_CURRENT_0_0_mA) | |
| 177 | PE_CURRENT3(PE_CURRENT_0_0_mA), |
| 178 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | |
| 179 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | |
| 180 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | |
| 181 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), |
Lucas Stach | fa416dd | 2012-12-19 21:38:55 +0000 | [diff] [blame] | 182 | }, |
| 183 | { /* high pixel clock modes */ |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 184 | .pclk = UINT_MAX, |
| 185 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 186 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | |
| 187 | SOR_PLL_TX_REG_LOAD(3), |
| 188 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, |
| 189 | .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | |
| 190 | PE_CURRENT1(PE_CURRENT_6_0_mA) | |
| 191 | PE_CURRENT2(PE_CURRENT_6_0_mA) | |
| 192 | PE_CURRENT3(PE_CURRENT_6_0_mA), |
| 193 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | |
| 194 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | |
| 195 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | |
| 196 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), |
| 197 | }, |
| 198 | }; |
| 199 | |
Thierry Reding | f27db96 | 2013-09-30 15:14:41 +0200 | [diff] [blame] | 200 | static const struct tmds_config tegra30_tmds_config[] = { |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 201 | { /* 480p modes */ |
| 202 | .pclk = 27000000, |
| 203 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 204 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | |
| 205 | SOR_PLL_TX_REG_LOAD(0), |
| 206 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE, |
| 207 | .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | |
| 208 | PE_CURRENT1(PE_CURRENT_0_0_mA) | |
| 209 | PE_CURRENT2(PE_CURRENT_0_0_mA) | |
| 210 | PE_CURRENT3(PE_CURRENT_0_0_mA), |
| 211 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | |
| 212 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | |
| 213 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | |
| 214 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), |
| 215 | }, { /* 720p modes */ |
| 216 | .pclk = 74250000, |
| 217 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 218 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | |
| 219 | SOR_PLL_TX_REG_LOAD(0), |
| 220 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, |
| 221 | .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | |
| 222 | PE_CURRENT1(PE_CURRENT_5_0_mA) | |
| 223 | PE_CURRENT2(PE_CURRENT_5_0_mA) | |
| 224 | PE_CURRENT3(PE_CURRENT_5_0_mA), |
| 225 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | |
| 226 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | |
| 227 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | |
| 228 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), |
| 229 | }, { /* 1080p modes */ |
| 230 | .pclk = UINT_MAX, |
| 231 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 232 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) | |
| 233 | SOR_PLL_TX_REG_LOAD(0), |
| 234 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, |
| 235 | .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | |
| 236 | PE_CURRENT1(PE_CURRENT_5_0_mA) | |
| 237 | PE_CURRENT2(PE_CURRENT_5_0_mA) | |
| 238 | PE_CURRENT3(PE_CURRENT_5_0_mA), |
| 239 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | |
| 240 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | |
| 241 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | |
| 242 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), |
| 243 | }, |
| 244 | }; |
| 245 | |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 246 | static const struct tmds_config tegra114_tmds_config[] = { |
| 247 | { /* 480p/576p / 25.2MHz/27MHz modes */ |
| 248 | .pclk = 27000000, |
| 249 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 250 | SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, |
| 251 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), |
| 252 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | |
| 253 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | |
| 254 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | |
| 255 | PE_CURRENT3(PE_CURRENT_0_mA_T114), |
| 256 | .drive_current = |
| 257 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 258 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 259 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 260 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), |
| 261 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | |
| 262 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | |
| 263 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | |
| 264 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), |
| 265 | }, { /* 720p / 74.25MHz modes */ |
| 266 | .pclk = 74250000, |
| 267 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 268 | SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, |
| 269 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | |
| 270 | SOR_PLL_TMDS_TERMADJ(0), |
| 271 | .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | |
| 272 | PE_CURRENT1(PE_CURRENT_15_mA_T114) | |
| 273 | PE_CURRENT2(PE_CURRENT_15_mA_T114) | |
| 274 | PE_CURRENT3(PE_CURRENT_15_mA_T114), |
| 275 | .drive_current = |
| 276 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 277 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 278 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 279 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), |
| 280 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | |
| 281 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | |
| 282 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | |
| 283 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), |
| 284 | }, { /* 1080p / 148.5MHz modes */ |
| 285 | .pclk = 148500000, |
| 286 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 287 | SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, |
| 288 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | |
| 289 | SOR_PLL_TMDS_TERMADJ(0), |
| 290 | .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | |
| 291 | PE_CURRENT1(PE_CURRENT_10_mA_T114) | |
| 292 | PE_CURRENT2(PE_CURRENT_10_mA_T114) | |
| 293 | PE_CURRENT3(PE_CURRENT_10_mA_T114), |
| 294 | .drive_current = |
| 295 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | |
| 296 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | |
| 297 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | |
| 298 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), |
| 299 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | |
| 300 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | |
| 301 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | |
| 302 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), |
| 303 | }, { /* 225/297MHz modes */ |
| 304 | .pclk = UINT_MAX, |
| 305 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 306 | SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, |
| 307 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) |
| 308 | | SOR_PLL_TMDS_TERM_ENABLE, |
| 309 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | |
| 310 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | |
| 311 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | |
| 312 | PE_CURRENT3(PE_CURRENT_0_mA_T114), |
| 313 | .drive_current = |
| 314 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | |
| 315 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | |
| 316 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | |
| 317 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), |
| 318 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | |
| 319 | PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | |
| 320 | PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | |
| 321 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), |
| 322 | }, |
| 323 | }; |
| 324 | |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 325 | static const struct tmds_config tegra124_tmds_config[] = { |
| 326 | { /* 480p/576p / 25.2MHz/27MHz modes */ |
| 327 | .pclk = 27000000, |
| 328 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 329 | SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, |
| 330 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), |
| 331 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | |
| 332 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | |
| 333 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | |
| 334 | PE_CURRENT3(PE_CURRENT_0_mA_T114), |
| 335 | .drive_current = |
| 336 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 337 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 338 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 339 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), |
| 340 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | |
| 341 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | |
| 342 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | |
| 343 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), |
| 344 | }, { /* 720p / 74.25MHz modes */ |
| 345 | .pclk = 74250000, |
| 346 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 347 | SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, |
| 348 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | |
| 349 | SOR_PLL_TMDS_TERMADJ(0), |
| 350 | .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | |
| 351 | PE_CURRENT1(PE_CURRENT_15_mA_T114) | |
| 352 | PE_CURRENT2(PE_CURRENT_15_mA_T114) | |
| 353 | PE_CURRENT3(PE_CURRENT_15_mA_T114), |
| 354 | .drive_current = |
| 355 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 356 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 357 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | |
| 358 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), |
| 359 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | |
| 360 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | |
| 361 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | |
| 362 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), |
| 363 | }, { /* 1080p / 148.5MHz modes */ |
| 364 | .pclk = 148500000, |
| 365 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 366 | SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, |
| 367 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | |
| 368 | SOR_PLL_TMDS_TERMADJ(0), |
| 369 | .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | |
| 370 | PE_CURRENT1(PE_CURRENT_10_mA_T114) | |
| 371 | PE_CURRENT2(PE_CURRENT_10_mA_T114) | |
| 372 | PE_CURRENT3(PE_CURRENT_10_mA_T114), |
| 373 | .drive_current = |
| 374 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | |
| 375 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | |
| 376 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | |
| 377 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), |
| 378 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | |
| 379 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | |
| 380 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | |
| 381 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), |
| 382 | }, { /* 225/297MHz modes */ |
| 383 | .pclk = UINT_MAX, |
| 384 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | |
| 385 | SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, |
| 386 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) |
| 387 | | SOR_PLL_TMDS_TERM_ENABLE, |
| 388 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | |
| 389 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | |
| 390 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | |
| 391 | PE_CURRENT3(PE_CURRENT_0_mA_T114), |
| 392 | .drive_current = |
| 393 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | |
| 394 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | |
| 395 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | |
| 396 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), |
| 397 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | |
| 398 | PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | |
| 399 | PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | |
| 400 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), |
| 401 | }, |
| 402 | }; |
| 403 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 404 | static const struct tegra_hdmi_audio_config * |
| 405 | tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) |
| 406 | { |
| 407 | const struct tegra_hdmi_audio_config *table; |
| 408 | |
| 409 | switch (audio_freq) { |
| 410 | case 32000: |
| 411 | table = tegra_hdmi_audio_32k; |
| 412 | break; |
| 413 | |
| 414 | case 44100: |
| 415 | table = tegra_hdmi_audio_44_1k; |
| 416 | break; |
| 417 | |
| 418 | case 48000: |
| 419 | table = tegra_hdmi_audio_48k; |
| 420 | break; |
| 421 | |
| 422 | case 88200: |
| 423 | table = tegra_hdmi_audio_88_2k; |
| 424 | break; |
| 425 | |
| 426 | case 96000: |
| 427 | table = tegra_hdmi_audio_96k; |
| 428 | break; |
| 429 | |
| 430 | case 176400: |
| 431 | table = tegra_hdmi_audio_176_4k; |
| 432 | break; |
| 433 | |
| 434 | case 192000: |
| 435 | table = tegra_hdmi_audio_192k; |
| 436 | break; |
| 437 | |
| 438 | default: |
| 439 | return NULL; |
| 440 | } |
| 441 | |
| 442 | while (table->pclk) { |
| 443 | if (table->pclk == pclk) |
| 444 | return table; |
| 445 | |
| 446 | table++; |
| 447 | } |
| 448 | |
| 449 | return NULL; |
| 450 | } |
| 451 | |
| 452 | static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) |
| 453 | { |
| 454 | const unsigned int freqs[] = { |
| 455 | 32000, 44100, 48000, 88200, 96000, 176400, 192000 |
| 456 | }; |
| 457 | unsigned int i; |
| 458 | |
| 459 | for (i = 0; i < ARRAY_SIZE(freqs); i++) { |
| 460 | unsigned int f = freqs[i]; |
| 461 | unsigned int eight_half; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 462 | unsigned int delta; |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 463 | u32 value; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 464 | |
| 465 | if (f > 96000) |
| 466 | delta = 2; |
Thierry Reding | 17a8b6b | 2013-12-16 10:01:24 +0100 | [diff] [blame] | 467 | else if (f > 48000) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 468 | delta = 6; |
| 469 | else |
| 470 | delta = 9; |
| 471 | |
| 472 | eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); |
| 473 | value = AUDIO_FS_LOW(eight_half - delta) | |
| 474 | AUDIO_FS_HIGH(eight_half + delta); |
| 475 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk) |
| 480 | { |
| 481 | struct device_node *node = hdmi->dev->of_node; |
| 482 | const struct tegra_hdmi_audio_config *config; |
| 483 | unsigned int offset = 0; |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 484 | u32 value; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 485 | |
| 486 | switch (hdmi->audio_source) { |
| 487 | case HDA: |
| 488 | value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL; |
| 489 | break; |
| 490 | |
| 491 | case SPDIF: |
| 492 | value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; |
| 493 | break; |
| 494 | |
| 495 | default: |
| 496 | value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO; |
| 497 | break; |
| 498 | } |
| 499 | |
| 500 | if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { |
| 501 | value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) | |
| 502 | AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0); |
| 503 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); |
| 504 | } else { |
| 505 | value |= AUDIO_CNTRL0_INJECT_NULLSMPL; |
| 506 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); |
| 507 | |
| 508 | value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) | |
| 509 | AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0); |
| 510 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); |
| 511 | } |
| 512 | |
| 513 | config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk); |
| 514 | if (!config) { |
| 515 | dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n", |
| 516 | hdmi->audio_freq, pclk); |
| 517 | return -EINVAL; |
| 518 | } |
| 519 | |
| 520 | tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL); |
| 521 | |
| 522 | value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE | |
| 523 | AUDIO_N_VALUE(config->n - 1); |
| 524 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); |
| 525 | |
| 526 | tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE, |
| 527 | HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); |
| 528 | |
| 529 | value = ACR_SUBPACK_CTS(config->cts); |
| 530 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); |
| 531 | |
| 532 | value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1); |
| 533 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE); |
| 534 | |
| 535 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N); |
| 536 | value &= ~AUDIO_N_RESETF; |
| 537 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); |
| 538 | |
| 539 | if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { |
| 540 | switch (hdmi->audio_freq) { |
| 541 | case 32000: |
| 542 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320; |
| 543 | break; |
| 544 | |
| 545 | case 44100: |
| 546 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441; |
| 547 | break; |
| 548 | |
| 549 | case 48000: |
| 550 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480; |
| 551 | break; |
| 552 | |
| 553 | case 88200: |
| 554 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882; |
| 555 | break; |
| 556 | |
| 557 | case 96000: |
| 558 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960; |
| 559 | break; |
| 560 | |
| 561 | case 176400: |
| 562 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764; |
| 563 | break; |
| 564 | |
| 565 | case 192000: |
| 566 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920; |
| 567 | break; |
| 568 | } |
| 569 | |
| 570 | tegra_hdmi_writel(hdmi, config->aval, offset); |
| 571 | } |
| 572 | |
| 573 | tegra_hdmi_setup_audio_fs_tables(hdmi); |
| 574 | |
| 575 | return 0; |
| 576 | } |
| 577 | |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 578 | static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 579 | { |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 580 | u32 value = 0; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 581 | size_t i; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 582 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 583 | for (i = size; i > 0; i--) |
| 584 | value = (value << 8) | ptr[i - 1]; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 585 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 586 | return value; |
| 587 | } |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 588 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 589 | static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data, |
| 590 | size_t size) |
| 591 | { |
| 592 | const u8 *ptr = data; |
| 593 | unsigned long offset; |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 594 | size_t i, j; |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 595 | u32 value; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 596 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 597 | switch (ptr[0]) { |
| 598 | case HDMI_INFOFRAME_TYPE_AVI: |
| 599 | offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER; |
| 600 | break; |
| 601 | |
| 602 | case HDMI_INFOFRAME_TYPE_AUDIO: |
| 603 | offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER; |
| 604 | break; |
| 605 | |
| 606 | case HDMI_INFOFRAME_TYPE_VENDOR: |
| 607 | offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER; |
| 608 | break; |
| 609 | |
| 610 | default: |
| 611 | dev_err(hdmi->dev, "unsupported infoframe type: %02x\n", |
| 612 | ptr[0]); |
| 613 | return; |
| 614 | } |
| 615 | |
| 616 | value = INFOFRAME_HEADER_TYPE(ptr[0]) | |
| 617 | INFOFRAME_HEADER_VERSION(ptr[1]) | |
| 618 | INFOFRAME_HEADER_LEN(ptr[2]); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 619 | tegra_hdmi_writel(hdmi, value, offset); |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 620 | offset++; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 621 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 622 | /* |
| 623 | * Each subpack contains 7 bytes, divided into: |
| 624 | * - subpack_low: bytes 0 - 3 |
| 625 | * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 626 | */ |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 627 | for (i = 3, j = 0; i < size; i += 7, j += 8) { |
| 628 | size_t rem = size - i, num = min_t(size_t, rem, 4); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 629 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 630 | value = tegra_hdmi_subpack(&ptr[i], num); |
| 631 | tegra_hdmi_writel(hdmi, value, offset++); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 632 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 633 | num = min_t(size_t, rem - num, 3); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 634 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 635 | value = tegra_hdmi_subpack(&ptr[i + 4], num); |
| 636 | tegra_hdmi_writel(hdmi, value, offset++); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 637 | } |
| 638 | } |
| 639 | |
| 640 | static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi, |
| 641 | struct drm_display_mode *mode) |
| 642 | { |
| 643 | struct hdmi_avi_infoframe frame; |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 644 | u8 buffer[17]; |
| 645 | ssize_t err; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 646 | |
| 647 | if (hdmi->dvi) { |
| 648 | tegra_hdmi_writel(hdmi, 0, |
| 649 | HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); |
| 650 | return; |
| 651 | } |
| 652 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 653 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
| 654 | if (err < 0) { |
| 655 | dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err); |
| 656 | return; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 657 | } |
| 658 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 659 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 660 | if (err < 0) { |
| 661 | dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err); |
| 662 | return; |
| 663 | } |
| 664 | |
| 665 | tegra_hdmi_write_infopack(hdmi, buffer, err); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 666 | |
| 667 | tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE, |
| 668 | HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); |
| 669 | } |
| 670 | |
| 671 | static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi) |
| 672 | { |
| 673 | struct hdmi_audio_infoframe frame; |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 674 | u8 buffer[14]; |
| 675 | ssize_t err; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 676 | |
| 677 | if (hdmi->dvi) { |
| 678 | tegra_hdmi_writel(hdmi, 0, |
| 679 | HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); |
| 680 | return; |
| 681 | } |
| 682 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 683 | err = hdmi_audio_infoframe_init(&frame); |
| 684 | if (err < 0) { |
Thierry Reding | ef284c7 | 2013-10-16 19:51:22 +0200 | [diff] [blame] | 685 | dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n", |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 686 | err); |
| 687 | return; |
| 688 | } |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 689 | |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 690 | frame.channels = 2; |
| 691 | |
| 692 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 693 | if (err < 0) { |
| 694 | dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n", |
| 695 | err); |
| 696 | return; |
| 697 | } |
| 698 | |
| 699 | /* |
| 700 | * The audio infoframe has only one set of subpack registers, so the |
| 701 | * infoframe needs to be truncated. One set of subpack registers can |
| 702 | * contain 7 bytes. Including the 3 byte header only the first 10 |
| 703 | * bytes can be programmed. |
| 704 | */ |
Thierry Reding | ef284c7 | 2013-10-16 19:51:22 +0200 | [diff] [blame] | 705 | tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err)); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 706 | |
| 707 | tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE, |
| 708 | HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); |
| 709 | } |
| 710 | |
| 711 | static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi) |
| 712 | { |
Lespiau, Damien | ae84b90 | 2013-08-19 16:59:02 +0100 | [diff] [blame] | 713 | struct hdmi_vendor_infoframe frame; |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 714 | u8 buffer[10]; |
| 715 | ssize_t err; |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 716 | u32 value; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 717 | |
| 718 | if (!hdmi->stereo) { |
| 719 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 720 | value &= ~GENERIC_CTRL_ENABLE; |
| 721 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 722 | return; |
| 723 | } |
| 724 | |
Lespiau, Damien | ae84b90 | 2013-08-19 16:59:02 +0100 | [diff] [blame] | 725 | hdmi_vendor_infoframe_init(&frame); |
Lespiau, Damien | a26a58e8 | 2013-08-19 16:58:59 +0100 | [diff] [blame] | 726 | frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING; |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 727 | |
Lespiau, Damien | ae84b90 | 2013-08-19 16:59:02 +0100 | [diff] [blame] | 728 | err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); |
Thierry Reding | ac24c22 | 2012-11-23 15:14:00 +0100 | [diff] [blame] | 729 | if (err < 0) { |
| 730 | dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n", |
| 731 | err); |
| 732 | return; |
| 733 | } |
| 734 | |
| 735 | tegra_hdmi_write_infopack(hdmi, buffer, err); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 736 | |
| 737 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 738 | value |= GENERIC_CTRL_ENABLE; |
| 739 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 740 | } |
| 741 | |
| 742 | static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, |
| 743 | const struct tmds_config *tmds) |
| 744 | { |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 745 | u32 value; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 746 | |
| 747 | tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); |
| 748 | tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); |
| 749 | tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); |
| 750 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 751 | tegra_hdmi_writel(hdmi, tmds->drive_current, |
| 752 | HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); |
| 753 | |
| 754 | value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset); |
| 755 | value |= hdmi->config->fuse_override_value; |
| 756 | tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset); |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 757 | |
| 758 | if (hdmi->config->has_sor_io_peak_current) |
| 759 | tegra_hdmi_writel(hdmi, tmds->peak_current, |
| 760 | HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 761 | } |
| 762 | |
Mikko Perttunen | 9f15912 | 2013-08-28 18:48:38 +0300 | [diff] [blame] | 763 | static bool tegra_output_is_hdmi(struct tegra_output *output) |
| 764 | { |
| 765 | struct edid *edid; |
| 766 | |
| 767 | if (!output->connector.edid_blob_ptr) |
| 768 | return false; |
| 769 | |
| 770 | edid = (struct edid *)output->connector.edid_blob_ptr->data; |
| 771 | |
| 772 | return drm_detect_hdmi_monitor(edid); |
| 773 | } |
| 774 | |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 775 | static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 776 | .dpms = drm_atomic_helper_connector_dpms, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 777 | .reset = drm_atomic_helper_connector_reset, |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 778 | .detect = tegra_output_connector_detect, |
| 779 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 780 | .destroy = tegra_output_connector_destroy, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 781 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 782 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 783 | }; |
| 784 | |
| 785 | static enum drm_mode_status |
| 786 | tegra_hdmi_connector_mode_valid(struct drm_connector *connector, |
| 787 | struct drm_display_mode *mode) |
| 788 | { |
| 789 | struct tegra_output *output = connector_to_output(connector); |
| 790 | struct tegra_hdmi *hdmi = to_hdmi(output); |
| 791 | unsigned long pclk = mode->clock * 1000; |
| 792 | enum drm_mode_status status = MODE_OK; |
| 793 | struct clk *parent; |
| 794 | long err; |
| 795 | |
| 796 | parent = clk_get_parent(hdmi->clk_parent); |
| 797 | |
| 798 | err = clk_round_rate(parent, pclk * 4); |
| 799 | if (err <= 0) |
| 800 | status = MODE_NOCLOCK; |
| 801 | |
| 802 | return status; |
| 803 | } |
| 804 | |
| 805 | static const struct drm_connector_helper_funcs |
| 806 | tegra_hdmi_connector_helper_funcs = { |
| 807 | .get_modes = tegra_output_connector_get_modes, |
| 808 | .mode_valid = tegra_hdmi_connector_mode_valid, |
| 809 | .best_encoder = tegra_output_connector_best_encoder, |
| 810 | }; |
| 811 | |
| 812 | static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = { |
| 813 | .destroy = tegra_output_encoder_destroy, |
| 814 | }; |
| 815 | |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 816 | static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder) |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 817 | { |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 818 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); |
| 819 | u32 value; |
| 820 | |
| 821 | /* |
| 822 | * The following accesses registers of the display controller, so make |
| 823 | * sure it's only executed when the output is attached to one. |
| 824 | */ |
| 825 | if (dc) { |
| 826 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 827 | value &= ~HDMI_ENABLE; |
| 828 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 829 | |
| 830 | tegra_dc_commit(dc); |
| 831 | } |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 832 | } |
| 833 | |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 834 | static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder) |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 835 | { |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 836 | struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 837 | unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 838 | struct tegra_output *output = encoder_to_output(encoder); |
| 839 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); |
| 840 | struct device_node *node = output->dev->of_node; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 841 | struct tegra_hdmi *hdmi = to_hdmi(output); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 842 | unsigned int pulse_start, div82, pclk; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 843 | int retries = 1000; |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 844 | u32 value; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 845 | int err; |
| 846 | |
Mikko Perttunen | 9f15912 | 2013-08-28 18:48:38 +0300 | [diff] [blame] | 847 | hdmi->dvi = !tegra_output_is_hdmi(output); |
| 848 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 849 | pclk = mode->clock * 1000; |
| 850 | h_sync_width = mode->hsync_end - mode->hsync_start; |
Lucas Stach | 4049508 | 2012-12-19 21:38:52 +0000 | [diff] [blame] | 851 | h_back_porch = mode->htotal - mode->hsync_end; |
| 852 | h_front_porch = mode->hsync_start - mode->hdisplay; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 853 | |
Thierry Reding | c03bf1b | 2015-02-18 10:34:08 +0100 | [diff] [blame] | 854 | err = clk_set_rate(hdmi->clk, pclk); |
| 855 | if (err < 0) { |
| 856 | dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", |
| 857 | err); |
| 858 | } |
| 859 | |
| 860 | DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); |
| 861 | |
Thierry Reding | 8c8282c | 2014-04-16 10:46:24 +0200 | [diff] [blame] | 862 | /* power up sequence */ |
| 863 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); |
| 864 | value &= ~SOR_PLL_PDBG; |
| 865 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); |
| 866 | |
| 867 | usleep_range(10, 20); |
| 868 | |
| 869 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); |
| 870 | value &= ~SOR_PLL_PWR; |
| 871 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); |
| 872 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 873 | tegra_dc_writel(dc, VSYNC_H_POSITION(1), |
| 874 | DC_DISP_DISP_TIMING_OPTIONS); |
Thierry Reding | 472a6d1f | 2015-08-05 16:39:55 +0200 | [diff] [blame] | 875 | tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 876 | DC_DISP_DISP_COLOR_CONTROL); |
| 877 | |
| 878 | /* video_preamble uses h_pulse2 */ |
| 879 | pulse_start = 1 + h_sync_width + h_back_porch - 10; |
| 880 | |
Thierry Reding | 8fd3ffa | 2015-04-27 14:48:35 +0200 | [diff] [blame] | 881 | tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 882 | |
| 883 | value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE | |
| 884 | PULSE_LAST_END_A; |
| 885 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); |
| 886 | |
| 887 | value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8); |
| 888 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); |
| 889 | |
| 890 | value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) | |
| 891 | VSYNC_WINDOW_ENABLE; |
| 892 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); |
| 893 | |
| 894 | if (dc->pipe) |
| 895 | value = HDMI_SRC_DISPLAYB; |
| 896 | else |
| 897 | value = HDMI_SRC_DISPLAYA; |
| 898 | |
| 899 | if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) || |
| 900 | (mode->vdisplay == 576))) |
| 901 | tegra_hdmi_writel(hdmi, |
| 902 | value | ARM_VIDEO_RANGE_FULL, |
| 903 | HDMI_NV_PDISP_INPUT_CONTROL); |
| 904 | else |
| 905 | tegra_hdmi_writel(hdmi, |
| 906 | value | ARM_VIDEO_RANGE_LIMITED, |
| 907 | HDMI_NV_PDISP_INPUT_CONTROL); |
| 908 | |
| 909 | div82 = clk_get_rate(hdmi->clk) / 1000000 * 4; |
| 910 | value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); |
| 911 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK); |
| 912 | |
| 913 | if (!hdmi->dvi) { |
| 914 | err = tegra_hdmi_setup_audio(hdmi, pclk); |
| 915 | if (err < 0) |
| 916 | hdmi->dvi = true; |
| 917 | } |
| 918 | |
| 919 | if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) { |
| 920 | /* |
| 921 | * TODO: add ELD support |
| 922 | */ |
| 923 | } |
| 924 | |
| 925 | rekey = HDMI_REKEY_DEFAULT; |
| 926 | value = HDMI_CTRL_REKEY(rekey); |
| 927 | value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + |
| 928 | h_front_porch - rekey - 18) / 32); |
| 929 | |
| 930 | if (!hdmi->dvi) |
| 931 | value |= HDMI_CTRL_ENABLE; |
| 932 | |
| 933 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL); |
| 934 | |
| 935 | if (hdmi->dvi) |
| 936 | tegra_hdmi_writel(hdmi, 0x0, |
| 937 | HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 938 | else |
| 939 | tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO, |
| 940 | HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 941 | |
| 942 | tegra_hdmi_setup_avi_infoframe(hdmi, mode); |
| 943 | tegra_hdmi_setup_audio_infoframe(hdmi); |
| 944 | tegra_hdmi_setup_stereo_infoframe(hdmi); |
| 945 | |
| 946 | /* TMDS CONFIG */ |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 947 | for (i = 0; i < hdmi->config->num_tmds; i++) { |
| 948 | if (pclk <= hdmi->config->tmds[i].pclk) { |
| 949 | tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 950 | break; |
| 951 | } |
| 952 | } |
| 953 | |
| 954 | tegra_hdmi_writel(hdmi, |
Thierry Reding | 5c1c071 | 2015-01-28 16:32:52 +0100 | [diff] [blame] | 955 | SOR_SEQ_PU_PC(0) | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 956 | SOR_SEQ_PU_PC_ALT(0) | |
| 957 | SOR_SEQ_PD_PC(8) | |
| 958 | SOR_SEQ_PD_PC_ALT(8), |
| 959 | HDMI_NV_PDISP_SOR_SEQ_CTL); |
| 960 | |
| 961 | value = SOR_SEQ_INST_WAIT_TIME(1) | |
| 962 | SOR_SEQ_INST_WAIT_UNITS_VSYNC | |
| 963 | SOR_SEQ_INST_HALT | |
| 964 | SOR_SEQ_INST_PIN_A_LOW | |
| 965 | SOR_SEQ_INST_PIN_B_LOW | |
| 966 | SOR_SEQ_INST_DRIVE_PWM_OUT_LO; |
| 967 | |
| 968 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); |
| 969 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); |
| 970 | |
Thierry Reding | 9cbfc73 | 2014-04-16 10:47:36 +0200 | [diff] [blame] | 971 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 972 | value &= ~SOR_CSTM_ROTCLK(~0); |
| 973 | value |= SOR_CSTM_ROTCLK(2); |
Thierry Reding | 9cbfc73 | 2014-04-16 10:47:36 +0200 | [diff] [blame] | 974 | value |= SOR_CSTM_PLLDIV; |
| 975 | value &= ~SOR_CSTM_LVDS_ENABLE; |
| 976 | value &= ~SOR_CSTM_MODE_MASK; |
| 977 | value |= SOR_CSTM_MODE_TMDS; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 978 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); |
| 979 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 980 | /* start SOR */ |
| 981 | tegra_hdmi_writel(hdmi, |
| 982 | SOR_PWR_NORMAL_STATE_PU | |
| 983 | SOR_PWR_NORMAL_START_NORMAL | |
| 984 | SOR_PWR_SAFE_STATE_PD | |
| 985 | SOR_PWR_SETTING_NEW_TRIGGER, |
| 986 | HDMI_NV_PDISP_SOR_PWR); |
| 987 | tegra_hdmi_writel(hdmi, |
| 988 | SOR_PWR_NORMAL_STATE_PU | |
| 989 | SOR_PWR_NORMAL_START_NORMAL | |
| 990 | SOR_PWR_SAFE_STATE_PD | |
| 991 | SOR_PWR_SETTING_NEW_DONE, |
| 992 | HDMI_NV_PDISP_SOR_PWR); |
| 993 | |
| 994 | do { |
| 995 | BUG_ON(--retries < 0); |
| 996 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR); |
| 997 | } while (value & SOR_PWR_SETTING_NEW_PENDING); |
| 998 | |
| 999 | value = SOR_STATE_ASY_CRCMODE_COMPLETE | |
| 1000 | SOR_STATE_ASY_OWNER_HEAD0 | |
| 1001 | SOR_STATE_ASY_SUBOWNER_BOTH | |
| 1002 | SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A | |
| 1003 | SOR_STATE_ASY_DEPOL_POS; |
| 1004 | |
| 1005 | /* setup sync polarities */ |
| 1006 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1007 | value |= SOR_STATE_ASY_HSYNCPOL_POS; |
| 1008 | |
| 1009 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 1010 | value |= SOR_STATE_ASY_HSYNCPOL_NEG; |
| 1011 | |
| 1012 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1013 | value |= SOR_STATE_ASY_VSYNCPOL_POS; |
| 1014 | |
| 1015 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 1016 | value |= SOR_STATE_ASY_VSYNCPOL_NEG; |
| 1017 | |
| 1018 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2); |
| 1019 | |
| 1020 | value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL; |
| 1021 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1); |
| 1022 | |
| 1023 | tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); |
| 1024 | tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0); |
| 1025 | tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED, |
| 1026 | HDMI_NV_PDISP_SOR_STATE1); |
| 1027 | tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); |
| 1028 | |
Thierry Reding | 72d3028 | 2013-12-12 11:06:55 +0100 | [diff] [blame] | 1029 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 1030 | value |= HDMI_ENABLE; |
| 1031 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1032 | |
Thierry Reding | 62b9e06 | 2014-11-21 17:33:33 +0100 | [diff] [blame] | 1033 | tegra_dc_commit(dc); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1034 | |
| 1035 | /* TODO: add HDCP support */ |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1036 | } |
| 1037 | |
Thierry Reding | a9825a6 | 2014-12-08 16:33:03 +0100 | [diff] [blame] | 1038 | static int |
| 1039 | tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder, |
| 1040 | struct drm_crtc_state *crtc_state, |
| 1041 | struct drm_connector_state *conn_state) |
| 1042 | { |
| 1043 | struct tegra_output *output = encoder_to_output(encoder); |
| 1044 | struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); |
| 1045 | unsigned long pclk = crtc_state->mode.clock * 1000; |
| 1046 | struct tegra_hdmi *hdmi = to_hdmi(output); |
| 1047 | int err; |
| 1048 | |
| 1049 | err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent, |
| 1050 | pclk, 0); |
| 1051 | if (err < 0) { |
| 1052 | dev_err(output->dev, "failed to setup CRTC state: %d\n", err); |
| 1053 | return err; |
| 1054 | } |
| 1055 | |
| 1056 | return err; |
| 1057 | } |
| 1058 | |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1059 | static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1060 | .disable = tegra_hdmi_encoder_disable, |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 1061 | .enable = tegra_hdmi_encoder_enable, |
Thierry Reding | a9825a6 | 2014-12-08 16:33:03 +0100 | [diff] [blame] | 1062 | .atomic_check = tegra_hdmi_encoder_atomic_check, |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1063 | }; |
| 1064 | |
| 1065 | static int tegra_hdmi_show_regs(struct seq_file *s, void *data) |
| 1066 | { |
| 1067 | struct drm_info_node *node = s->private; |
| 1068 | struct tegra_hdmi *hdmi = node->info_ent->data; |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 1069 | struct drm_crtc *crtc = hdmi->output.encoder.crtc; |
| 1070 | struct drm_device *drm = node->minor->dev; |
| 1071 | int err = 0; |
Mikko Perttunen | ccaddfe | 2013-07-30 11:35:03 +0300 | [diff] [blame] | 1072 | |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 1073 | drm_modeset_lock_all(drm); |
| 1074 | |
| 1075 | if (!crtc || !crtc->state->active) { |
| 1076 | err = -EBUSY; |
| 1077 | goto unlock; |
| 1078 | } |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1079 | |
| 1080 | #define DUMP_REG(name) \ |
Thierry Reding | 4ee8cee | 2014-12-08 16:25:14 +0100 | [diff] [blame] | 1081 | seq_printf(s, "%-56s %#05x %08x\n", #name, name, \ |
| 1082 | tegra_hdmi_readl(hdmi, name)) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1083 | |
| 1084 | DUMP_REG(HDMI_CTXSW); |
| 1085 | DUMP_REG(HDMI_NV_PDISP_SOR_STATE0); |
| 1086 | DUMP_REG(HDMI_NV_PDISP_SOR_STATE1); |
| 1087 | DUMP_REG(HDMI_NV_PDISP_SOR_STATE2); |
| 1088 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB); |
| 1089 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB); |
| 1090 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB); |
| 1091 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB); |
| 1092 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB); |
| 1093 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB); |
| 1094 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB); |
| 1095 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB); |
| 1096 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB); |
| 1097 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB); |
| 1098 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB); |
| 1099 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB); |
| 1100 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL); |
| 1101 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE); |
| 1102 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB); |
| 1103 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB); |
| 1104 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB); |
| 1105 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2); |
| 1106 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1); |
| 1107 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI); |
| 1108 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB); |
| 1109 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB); |
| 1110 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0); |
| 1111 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0); |
| 1112 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1); |
| 1113 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2); |
| 1114 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); |
| 1115 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS); |
| 1116 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER); |
| 1117 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW); |
| 1118 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH); |
| 1119 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); |
| 1120 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS); |
| 1121 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER); |
| 1122 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW); |
| 1123 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH); |
| 1124 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW); |
| 1125 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH); |
| 1126 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL); |
| 1127 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS); |
| 1128 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER); |
| 1129 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW); |
| 1130 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH); |
| 1131 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW); |
| 1132 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH); |
| 1133 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW); |
| 1134 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH); |
| 1135 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW); |
| 1136 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH); |
| 1137 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL); |
| 1138 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW); |
| 1139 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH); |
| 1140 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); |
| 1141 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); |
| 1142 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW); |
| 1143 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH); |
| 1144 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW); |
| 1145 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH); |
| 1146 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW); |
| 1147 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH); |
| 1148 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW); |
| 1149 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH); |
| 1150 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW); |
| 1151 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH); |
| 1152 | DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL); |
| 1153 | DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT); |
| 1154 | DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); |
| 1155 | DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL); |
| 1156 | DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS); |
| 1157 | DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK); |
| 1158 | DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1); |
| 1159 | DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2); |
| 1160 | DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0); |
| 1161 | DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1); |
| 1162 | DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA); |
| 1163 | DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE); |
| 1164 | DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1); |
| 1165 | DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2); |
| 1166 | DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL); |
| 1167 | DUMP_REG(HDMI_NV_PDISP_SOR_CAP); |
| 1168 | DUMP_REG(HDMI_NV_PDISP_SOR_PWR); |
| 1169 | DUMP_REG(HDMI_NV_PDISP_SOR_TEST); |
| 1170 | DUMP_REG(HDMI_NV_PDISP_SOR_PLL0); |
| 1171 | DUMP_REG(HDMI_NV_PDISP_SOR_PLL1); |
| 1172 | DUMP_REG(HDMI_NV_PDISP_SOR_PLL2); |
| 1173 | DUMP_REG(HDMI_NV_PDISP_SOR_CSTM); |
| 1174 | DUMP_REG(HDMI_NV_PDISP_SOR_LVDS); |
| 1175 | DUMP_REG(HDMI_NV_PDISP_SOR_CRCA); |
| 1176 | DUMP_REG(HDMI_NV_PDISP_SOR_CRCB); |
| 1177 | DUMP_REG(HDMI_NV_PDISP_SOR_BLANK); |
| 1178 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL); |
| 1179 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0)); |
| 1180 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1)); |
| 1181 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2)); |
| 1182 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3)); |
| 1183 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4)); |
| 1184 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5)); |
| 1185 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6)); |
| 1186 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7)); |
| 1187 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8)); |
| 1188 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9)); |
| 1189 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10)); |
| 1190 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11)); |
| 1191 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12)); |
| 1192 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13)); |
| 1193 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14)); |
| 1194 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15)); |
| 1195 | DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0); |
| 1196 | DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1); |
| 1197 | DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0); |
| 1198 | DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1); |
| 1199 | DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0); |
| 1200 | DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1); |
| 1201 | DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0); |
| 1202 | DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1); |
| 1203 | DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0); |
| 1204 | DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1); |
| 1205 | DUMP_REG(HDMI_NV_PDISP_SOR_TRIG); |
| 1206 | DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK); |
| 1207 | DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); |
| 1208 | DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0); |
| 1209 | DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1); |
| 1210 | DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2); |
| 1211 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0)); |
| 1212 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1)); |
| 1213 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2)); |
| 1214 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3)); |
| 1215 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4)); |
| 1216 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5)); |
| 1217 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6)); |
| 1218 | DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH); |
| 1219 | DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD); |
| 1220 | DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0); |
| 1221 | DUMP_REG(HDMI_NV_PDISP_AUDIO_N); |
| 1222 | DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING); |
| 1223 | DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK); |
| 1224 | DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL); |
| 1225 | DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL); |
| 1226 | DUMP_REG(HDMI_NV_PDISP_SCRATCH); |
| 1227 | DUMP_REG(HDMI_NV_PDISP_PE_CURRENT); |
| 1228 | DUMP_REG(HDMI_NV_PDISP_KEY_CTRL); |
| 1229 | DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0); |
| 1230 | DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1); |
| 1231 | DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2); |
| 1232 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0); |
| 1233 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1); |
| 1234 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2); |
| 1235 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3); |
| 1236 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG); |
| 1237 | DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX); |
| 1238 | DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); |
| 1239 | DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); |
| 1240 | DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1241 | DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1242 | |
| 1243 | #undef DUMP_REG |
| 1244 | |
Thierry Reding | 29871b2 | 2015-07-29 09:46:40 +0200 | [diff] [blame] | 1245 | unlock: |
| 1246 | drm_modeset_unlock_all(drm); |
| 1247 | return err; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1248 | } |
| 1249 | |
| 1250 | static struct drm_info_list debugfs_files[] = { |
| 1251 | { "regs", tegra_hdmi_show_regs, 0, NULL }, |
| 1252 | }; |
| 1253 | |
| 1254 | static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi, |
| 1255 | struct drm_minor *minor) |
| 1256 | { |
| 1257 | unsigned int i; |
| 1258 | int err; |
| 1259 | |
| 1260 | hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root); |
| 1261 | if (!hdmi->debugfs) |
| 1262 | return -ENOMEM; |
| 1263 | |
| 1264 | hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
| 1265 | GFP_KERNEL); |
| 1266 | if (!hdmi->debugfs_files) { |
| 1267 | err = -ENOMEM; |
| 1268 | goto remove; |
| 1269 | } |
| 1270 | |
| 1271 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) |
| 1272 | hdmi->debugfs_files[i].data = hdmi; |
| 1273 | |
| 1274 | err = drm_debugfs_create_files(hdmi->debugfs_files, |
| 1275 | ARRAY_SIZE(debugfs_files), |
| 1276 | hdmi->debugfs, minor); |
| 1277 | if (err < 0) |
| 1278 | goto free; |
| 1279 | |
| 1280 | hdmi->minor = minor; |
| 1281 | |
| 1282 | return 0; |
| 1283 | |
| 1284 | free: |
| 1285 | kfree(hdmi->debugfs_files); |
| 1286 | hdmi->debugfs_files = NULL; |
| 1287 | remove: |
| 1288 | debugfs_remove(hdmi->debugfs); |
| 1289 | hdmi->debugfs = NULL; |
| 1290 | |
| 1291 | return err; |
| 1292 | } |
| 1293 | |
Thierry Reding | 4009c22 | 2014-12-19 15:47:30 +0100 | [diff] [blame] | 1294 | static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1295 | { |
| 1296 | drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files), |
| 1297 | hdmi->minor); |
| 1298 | hdmi->minor = NULL; |
| 1299 | |
| 1300 | kfree(hdmi->debugfs_files); |
| 1301 | hdmi->debugfs_files = NULL; |
| 1302 | |
| 1303 | debugfs_remove(hdmi->debugfs); |
| 1304 | hdmi->debugfs = NULL; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1305 | } |
| 1306 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1307 | static int tegra_hdmi_init(struct host1x_client *client) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1308 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1309 | struct drm_device *drm = dev_get_drvdata(client->parent); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1310 | struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1311 | int err; |
| 1312 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1313 | hdmi->output.dev = client->dev; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1314 | |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1315 | drm_connector_init(drm, &hdmi->output.connector, |
| 1316 | &tegra_hdmi_connector_funcs, |
| 1317 | DRM_MODE_CONNECTOR_HDMIA); |
| 1318 | drm_connector_helper_add(&hdmi->output.connector, |
| 1319 | &tegra_hdmi_connector_helper_funcs); |
| 1320 | hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF; |
| 1321 | |
| 1322 | drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs, |
Ville Syrjälä | 13a3d91 | 2015-12-09 16:20:18 +0200 | [diff] [blame] | 1323 | DRM_MODE_ENCODER_TMDS, NULL); |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1324 | drm_encoder_helper_add(&hdmi->output.encoder, |
| 1325 | &tegra_hdmi_encoder_helper_funcs); |
| 1326 | |
| 1327 | drm_mode_connector_attach_encoder(&hdmi->output.connector, |
| 1328 | &hdmi->output.encoder); |
| 1329 | drm_connector_register(&hdmi->output.connector); |
| 1330 | |
Thierry Reding | ea130b2 | 2014-12-19 15:51:35 +0100 | [diff] [blame] | 1331 | err = tegra_output_init(drm, &hdmi->output); |
| 1332 | if (err < 0) { |
| 1333 | dev_err(client->dev, "failed to initialize output: %d\n", err); |
| 1334 | return err; |
| 1335 | } |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1336 | |
Thierry Reding | ea130b2 | 2014-12-19 15:51:35 +0100 | [diff] [blame] | 1337 | hdmi->output.encoder.possible_crtcs = 0x3; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1338 | |
| 1339 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1340 | err = tegra_hdmi_debugfs_init(hdmi, drm->primary); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1341 | if (err < 0) |
| 1342 | dev_err(client->dev, "debugfs setup failed: %d\n", err); |
| 1343 | } |
| 1344 | |
Thierry Reding | fb50a11 | 2014-02-28 16:57:34 +0100 | [diff] [blame] | 1345 | err = regulator_enable(hdmi->hdmi); |
| 1346 | if (err < 0) { |
| 1347 | dev_err(client->dev, "failed to enable HDMI regulator: %d\n", |
| 1348 | err); |
| 1349 | return err; |
| 1350 | } |
| 1351 | |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1352 | err = regulator_enable(hdmi->pll); |
| 1353 | if (err < 0) { |
| 1354 | dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); |
| 1355 | return err; |
| 1356 | } |
| 1357 | |
| 1358 | err = regulator_enable(hdmi->vdd); |
| 1359 | if (err < 0) { |
| 1360 | dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); |
| 1361 | return err; |
| 1362 | } |
| 1363 | |
| 1364 | err = clk_prepare_enable(hdmi->clk); |
| 1365 | if (err < 0) { |
| 1366 | dev_err(hdmi->dev, "failed to enable clock: %d\n", err); |
| 1367 | return err; |
| 1368 | } |
| 1369 | |
| 1370 | reset_control_deassert(hdmi->rst); |
| 1371 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1372 | return 0; |
| 1373 | } |
| 1374 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1375 | static int tegra_hdmi_exit(struct host1x_client *client) |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1376 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1377 | struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1378 | |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1379 | tegra_output_exit(&hdmi->output); |
| 1380 | |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1381 | reset_control_assert(hdmi->rst); |
Thierry Reding | 375e118 | 2015-01-28 16:14:26 +0100 | [diff] [blame] | 1382 | clk_disable_unprepare(hdmi->clk); |
Thierry Reding | 5968271 | 2014-11-28 16:50:59 +0100 | [diff] [blame] | 1383 | |
| 1384 | regulator_disable(hdmi->vdd); |
| 1385 | regulator_disable(hdmi->pll); |
Thierry Reding | fb50a11 | 2014-02-28 16:57:34 +0100 | [diff] [blame] | 1386 | regulator_disable(hdmi->hdmi); |
| 1387 | |
Thierry Reding | 4009c22 | 2014-12-19 15:47:30 +0100 | [diff] [blame] | 1388 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
| 1389 | tegra_hdmi_debugfs_exit(hdmi); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1390 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1391 | return 0; |
| 1392 | } |
| 1393 | |
| 1394 | static const struct host1x_client_ops hdmi_client_ops = { |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1395 | .init = tegra_hdmi_init, |
| 1396 | .exit = tegra_hdmi_exit, |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1397 | }; |
| 1398 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1399 | static const struct tegra_hdmi_config tegra20_hdmi_config = { |
| 1400 | .tmds = tegra20_tmds_config, |
| 1401 | .num_tmds = ARRAY_SIZE(tegra20_tmds_config), |
| 1402 | .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, |
| 1403 | .fuse_override_value = 1 << 31, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1404 | .has_sor_io_peak_current = false, |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1405 | }; |
| 1406 | |
| 1407 | static const struct tegra_hdmi_config tegra30_hdmi_config = { |
| 1408 | .tmds = tegra30_tmds_config, |
| 1409 | .num_tmds = ARRAY_SIZE(tegra30_tmds_config), |
| 1410 | .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, |
| 1411 | .fuse_override_value = 1 << 31, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1412 | .has_sor_io_peak_current = false, |
| 1413 | }; |
| 1414 | |
| 1415 | static const struct tegra_hdmi_config tegra114_hdmi_config = { |
| 1416 | .tmds = tegra114_tmds_config, |
| 1417 | .num_tmds = ARRAY_SIZE(tegra114_tmds_config), |
| 1418 | .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, |
| 1419 | .fuse_override_value = 1 << 31, |
| 1420 | .has_sor_io_peak_current = true, |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1421 | }; |
| 1422 | |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1423 | static const struct tegra_hdmi_config tegra124_hdmi_config = { |
| 1424 | .tmds = tegra124_tmds_config, |
| 1425 | .num_tmds = ARRAY_SIZE(tegra124_tmds_config), |
| 1426 | .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, |
| 1427 | .fuse_override_value = 1 << 31, |
| 1428 | .has_sor_io_peak_current = true, |
| 1429 | }; |
| 1430 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1431 | static const struct of_device_id tegra_hdmi_of_match[] = { |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1432 | { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config }, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1433 | { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1434 | { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, |
| 1435 | { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, |
| 1436 | { }, |
| 1437 | }; |
Stephen Warren | ef70728 | 2014-06-18 16:21:55 -0600 | [diff] [blame] | 1438 | MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match); |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1439 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1440 | static int tegra_hdmi_probe(struct platform_device *pdev) |
| 1441 | { |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1442 | const struct of_device_id *match; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1443 | struct tegra_hdmi *hdmi; |
| 1444 | struct resource *regs; |
| 1445 | int err; |
| 1446 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1447 | match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node); |
| 1448 | if (!match) |
| 1449 | return -ENODEV; |
| 1450 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1451 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); |
| 1452 | if (!hdmi) |
| 1453 | return -ENOMEM; |
| 1454 | |
Thierry Reding | 59af059 | 2013-10-14 09:43:05 +0200 | [diff] [blame] | 1455 | hdmi->config = match->data; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1456 | hdmi->dev = &pdev->dev; |
| 1457 | hdmi->audio_source = AUTO; |
| 1458 | hdmi->audio_freq = 44100; |
| 1459 | hdmi->stereo = false; |
| 1460 | hdmi->dvi = false; |
| 1461 | |
| 1462 | hdmi->clk = devm_clk_get(&pdev->dev, NULL); |
| 1463 | if (IS_ERR(hdmi->clk)) { |
| 1464 | dev_err(&pdev->dev, "failed to get clock\n"); |
| 1465 | return PTR_ERR(hdmi->clk); |
| 1466 | } |
| 1467 | |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 1468 | hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi"); |
| 1469 | if (IS_ERR(hdmi->rst)) { |
| 1470 | dev_err(&pdev->dev, "failed to get reset\n"); |
| 1471 | return PTR_ERR(hdmi->rst); |
| 1472 | } |
| 1473 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1474 | hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
| 1475 | if (IS_ERR(hdmi->clk_parent)) |
| 1476 | return PTR_ERR(hdmi->clk_parent); |
| 1477 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1478 | err = clk_set_parent(hdmi->clk, hdmi->clk_parent); |
| 1479 | if (err < 0) { |
| 1480 | dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); |
| 1481 | return err; |
| 1482 | } |
| 1483 | |
Thierry Reding | fb50a11 | 2014-02-28 16:57:34 +0100 | [diff] [blame] | 1484 | hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi"); |
| 1485 | if (IS_ERR(hdmi->hdmi)) { |
| 1486 | dev_err(&pdev->dev, "failed to get HDMI regulator\n"); |
| 1487 | return PTR_ERR(hdmi->hdmi); |
| 1488 | } |
| 1489 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1490 | hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); |
| 1491 | if (IS_ERR(hdmi->pll)) { |
| 1492 | dev_err(&pdev->dev, "failed to get PLL regulator\n"); |
| 1493 | return PTR_ERR(hdmi->pll); |
| 1494 | } |
| 1495 | |
Thierry Reding | 8868568 | 2014-04-16 10:24:12 +0200 | [diff] [blame] | 1496 | hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); |
| 1497 | if (IS_ERR(hdmi->vdd)) { |
| 1498 | dev_err(&pdev->dev, "failed to get VDD regulator\n"); |
| 1499 | return PTR_ERR(hdmi->vdd); |
| 1500 | } |
| 1501 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1502 | hdmi->output.dev = &pdev->dev; |
| 1503 | |
Thierry Reding | 59d29c0 | 2013-10-14 14:26:42 +0200 | [diff] [blame] | 1504 | err = tegra_output_probe(&hdmi->output); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1505 | if (err < 0) |
| 1506 | return err; |
| 1507 | |
| 1508 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | d4ed602 | 2013-01-21 11:09:02 +0100 | [diff] [blame] | 1509 | hdmi->regs = devm_ioremap_resource(&pdev->dev, regs); |
| 1510 | if (IS_ERR(hdmi->regs)) |
| 1511 | return PTR_ERR(hdmi->regs); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1512 | |
| 1513 | err = platform_get_irq(pdev, 0); |
| 1514 | if (err < 0) |
| 1515 | return err; |
| 1516 | |
| 1517 | hdmi->irq = err; |
| 1518 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1519 | INIT_LIST_HEAD(&hdmi->client.list); |
| 1520 | hdmi->client.ops = &hdmi_client_ops; |
| 1521 | hdmi->client.dev = &pdev->dev; |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1522 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1523 | err = host1x_client_register(&hdmi->client); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1524 | if (err < 0) { |
| 1525 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 1526 | err); |
| 1527 | return err; |
| 1528 | } |
| 1529 | |
| 1530 | platform_set_drvdata(pdev, hdmi); |
| 1531 | |
| 1532 | return 0; |
| 1533 | } |
| 1534 | |
| 1535 | static int tegra_hdmi_remove(struct platform_device *pdev) |
| 1536 | { |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1537 | struct tegra_hdmi *hdmi = platform_get_drvdata(pdev); |
| 1538 | int err; |
| 1539 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1540 | err = host1x_client_unregister(&hdmi->client); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1541 | if (err < 0) { |
| 1542 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 1543 | err); |
| 1544 | return err; |
| 1545 | } |
| 1546 | |
Thierry Reding | 328ec69 | 2014-12-19 15:55:08 +0100 | [diff] [blame] | 1547 | tegra_output_remove(&hdmi->output); |
Thierry Reding | 59d29c0 | 2013-10-14 14:26:42 +0200 | [diff] [blame] | 1548 | |
Thierry Reding | d06e7f8f6 | 2014-04-16 10:43:41 +0200 | [diff] [blame] | 1549 | clk_disable_unprepare(hdmi->clk_parent); |
| 1550 | clk_disable_unprepare(hdmi->clk); |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1551 | |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 1555 | struct platform_driver tegra_hdmi_driver = { |
| 1556 | .driver = { |
| 1557 | .name = "tegra-hdmi", |
| 1558 | .owner = THIS_MODULE, |
| 1559 | .of_match_table = tegra_hdmi_of_match, |
| 1560 | }, |
| 1561 | .probe = tegra_hdmi_probe, |
| 1562 | .remove = tegra_hdmi_remove, |
| 1563 | }; |