blob: a882514389cd05a35e503c8b0adb2bb39ba91ae4 [file] [log] [blame]
Thierry Redingedec4af2012-11-15 21:28:23 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef TEGRA_HDMI_H
11#define TEGRA_HDMI_H 1
12
Thierry Redingedec4af2012-11-15 21:28:23 +000013/* register definitions */
14#define HDMI_CTXSW 0x00
15
16#define HDMI_NV_PDISP_SOR_STATE0 0x01
17#define SOR_STATE_UPDATE (1 << 0)
18
19#define HDMI_NV_PDISP_SOR_STATE1 0x02
20#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
21#define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
22#define SOR_STATE_ATTACHED (1 << 3)
23
24#define HDMI_NV_PDISP_SOR_STATE2 0x03
25#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
26#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
27#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
28#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
29#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
30#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
31#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
32#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
33#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
34#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
35#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
36#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
37#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
38#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
39#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
40#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
41#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
42
43#define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
44#define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
45#define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
46#define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
47#define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
48#define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
49#define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
50#define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
51#define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
52#define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
53#define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
54#define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
55#define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
56#define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
57#define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
58#define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
59#define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
60#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
61#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
62#define HDMI_NV_PDISP_RG_HDCP_RI 0x17
63#define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
64#define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
65#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
66#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
67#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
68#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
69
70#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
71#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
72#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
73#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
74#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
75#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
76#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
77#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
78#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
79#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
80#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
81#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
82
83#define INFOFRAME_CTRL_ENABLE (1 << 0)
84
85#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
86#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
87#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
88
89#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
90#define GENERIC_CTRL_ENABLE (1 << 0)
91#define GENERIC_CTRL_OTHER (1 << 4)
92#define GENERIC_CTRL_SINGLE (1 << 8)
93#define GENERIC_CTRL_HBLANK (1 << 12)
94#define GENERIC_CTRL_AUDIO (1 << 16)
95
96#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
97#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
98#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
99#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
100#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
101#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
102#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
103#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
104#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
105#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
106
107#define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
108#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
109#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
110#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
111#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
112#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
113#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
114#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
115#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
116#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
117#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
118#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
119#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
120#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
121#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
122
123#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
124#define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
125#define ACR_ENABLE (1 << 31)
126
127#define HDMI_NV_PDISP_HDMI_CTRL 0x44
128#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
129#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
130#define HDMI_CTRL_ENABLE (1 << 30)
131
132#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
133#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
134#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
135#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
136#define VSYNC_WINDOW_ENABLE (1 << 31)
137
138#define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
139#define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
140#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
141#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
142#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
143#define HDMI_NV_PDISP_HDMI_EMU0 0x4c
144#define HDMI_NV_PDISP_HDMI_EMU1 0x4d
145#define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
146
147#define HDMI_NV_PDISP_HDMI_SPARE 0x4f
148#define SPARE_HW_CTS (1 << 0)
149#define SPARE_FORCE_SW_CTS (1 << 1)
150#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
151
152#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
153#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
154#define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53
155#define HDMI_NV_PDISP_SOR_CAP 0x54
156#define HDMI_NV_PDISP_SOR_PWR 0x55
157#define SOR_PWR_NORMAL_STATE_PD (0 << 0)
158#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
159#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
160#define SOR_PWR_NORMAL_START_ALT (1 << 1)
161#define SOR_PWR_SAFE_STATE_PD (0 << 16)
162#define SOR_PWR_SAFE_STATE_PU (1 << 16)
163#define SOR_PWR_SETTING_NEW_DONE (0 << 31)
164#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
165#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
166
167#define HDMI_NV_PDISP_SOR_TEST 0x56
168#define HDMI_NV_PDISP_SOR_PLL0 0x57
169#define SOR_PLL_PWR (1 << 0)
170#define SOR_PLL_PDBG (1 << 1)
171#define SOR_PLL_VCAPD (1 << 2)
172#define SOR_PLL_PDPORT (1 << 3)
173#define SOR_PLL_RESISTORSEL (1 << 4)
174#define SOR_PLL_PULLDOWN (1 << 5)
175#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
176#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
177#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
178#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
179#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
180
181#define HDMI_NV_PDISP_SOR_PLL1 0x58
182#define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
183#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
184#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
185#define SOR_PLL_PE_EN (1 << 28)
186#define SOR_PLL_HALF_FULL_PE (1 << 29)
187#define SOR_PLL_S_D_PIN_PE (1 << 30)
188
189#define HDMI_NV_PDISP_SOR_PLL2 0x59
190
191#define HDMI_NV_PDISP_SOR_CSTM 0x5a
192#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
Thierry Reding9cbfc732014-04-16 10:47:36 +0200193#define SOR_CSTM_PLLDIV (1 << 21)
194#define SOR_CSTM_LVDS_ENABLE (1 << 16)
195#define SOR_CSTM_MODE_LVDS (0 << 12)
196#define SOR_CSTM_MODE_TMDS (1 << 12)
197#define SOR_CSTM_MODE_MASK (3 << 12)
Thierry Redingedec4af2012-11-15 21:28:23 +0000198
199#define HDMI_NV_PDISP_SOR_LVDS 0x5b
200#define HDMI_NV_PDISP_SOR_CRCA 0x5c
201#define HDMI_NV_PDISP_SOR_CRCB 0x5d
202#define HDMI_NV_PDISP_SOR_BLANK 0x5e
203#define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
Thierry Reding5c1c0712015-01-28 16:32:52 +0100204#define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
Thierry Redingedec4af2012-11-15 21:28:23 +0000205#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
206#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
207#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
208#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
209#define SOR_SEQ_STATUS (1 << 28)
210#define SOR_SEQ_SWITCH (1 << 30)
211
212#define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x))
213
214#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
215#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
216#define SOR_SEQ_INST_HALT (1 << 15)
217#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
218#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
219#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
220#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
221#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
222
223#define HDMI_NV_PDISP_SOR_VCRCA0 0x72
224#define HDMI_NV_PDISP_SOR_VCRCA1 0x73
225#define HDMI_NV_PDISP_SOR_CCRCA0 0x74
226#define HDMI_NV_PDISP_SOR_CCRCA1 0x75
227#define HDMI_NV_PDISP_SOR_EDATAA0 0x76
228#define HDMI_NV_PDISP_SOR_EDATAA1 0x77
229#define HDMI_NV_PDISP_SOR_COUNTA0 0x78
230#define HDMI_NV_PDISP_SOR_COUNTA1 0x79
231#define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
232#define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
233#define HDMI_NV_PDISP_SOR_TRIG 0x7c
234#define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
235
236#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
237#define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
238#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
239#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
240#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +0200241#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)
242#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)
243#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
244#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
Thierry Redingedec4af2012-11-15 21:28:23 +0000245
246#define DRIVE_CURRENT_1_500_mA 0x00
247#define DRIVE_CURRENT_1_875_mA 0x01
248#define DRIVE_CURRENT_2_250_mA 0x02
249#define DRIVE_CURRENT_2_625_mA 0x03
250#define DRIVE_CURRENT_3_000_mA 0x04
251#define DRIVE_CURRENT_3_375_mA 0x05
252#define DRIVE_CURRENT_3_750_mA 0x06
253#define DRIVE_CURRENT_4_125_mA 0x07
254#define DRIVE_CURRENT_4_500_mA 0x08
255#define DRIVE_CURRENT_4_875_mA 0x09
256#define DRIVE_CURRENT_5_250_mA 0x0a
257#define DRIVE_CURRENT_5_625_mA 0x0b
258#define DRIVE_CURRENT_6_000_mA 0x0c
259#define DRIVE_CURRENT_6_375_mA 0x0d
260#define DRIVE_CURRENT_6_750_mA 0x0e
261#define DRIVE_CURRENT_7_125_mA 0x0f
262#define DRIVE_CURRENT_7_500_mA 0x10
263#define DRIVE_CURRENT_7_875_mA 0x11
264#define DRIVE_CURRENT_8_250_mA 0x12
265#define DRIVE_CURRENT_8_625_mA 0x13
266#define DRIVE_CURRENT_9_000_mA 0x14
267#define DRIVE_CURRENT_9_375_mA 0x15
268#define DRIVE_CURRENT_9_750_mA 0x16
269#define DRIVE_CURRENT_10_125_mA 0x17
270#define DRIVE_CURRENT_10_500_mA 0x18
271#define DRIVE_CURRENT_10_875_mA 0x19
272#define DRIVE_CURRENT_11_250_mA 0x1a
273#define DRIVE_CURRENT_11_625_mA 0x1b
274#define DRIVE_CURRENT_12_000_mA 0x1c
275#define DRIVE_CURRENT_12_375_mA 0x1d
276#define DRIVE_CURRENT_12_750_mA 0x1e
277#define DRIVE_CURRENT_13_125_mA 0x1f
278#define DRIVE_CURRENT_13_500_mA 0x20
279#define DRIVE_CURRENT_13_875_mA 0x21
280#define DRIVE_CURRENT_14_250_mA 0x22
281#define DRIVE_CURRENT_14_625_mA 0x23
282#define DRIVE_CURRENT_15_000_mA 0x24
283#define DRIVE_CURRENT_15_375_mA 0x25
284#define DRIVE_CURRENT_15_750_mA 0x26
285#define DRIVE_CURRENT_16_125_mA 0x27
286#define DRIVE_CURRENT_16_500_mA 0x28
287#define DRIVE_CURRENT_16_875_mA 0x29
288#define DRIVE_CURRENT_17_250_mA 0x2a
289#define DRIVE_CURRENT_17_625_mA 0x2b
290#define DRIVE_CURRENT_18_000_mA 0x2c
291#define DRIVE_CURRENT_18_375_mA 0x2d
292#define DRIVE_CURRENT_18_750_mA 0x2e
293#define DRIVE_CURRENT_19_125_mA 0x2f
294#define DRIVE_CURRENT_19_500_mA 0x30
295#define DRIVE_CURRENT_19_875_mA 0x31
296#define DRIVE_CURRENT_20_250_mA 0x32
297#define DRIVE_CURRENT_20_625_mA 0x33
298#define DRIVE_CURRENT_21_000_mA 0x34
299#define DRIVE_CURRENT_21_375_mA 0x35
300#define DRIVE_CURRENT_21_750_mA 0x36
301#define DRIVE_CURRENT_22_125_mA 0x37
302#define DRIVE_CURRENT_22_500_mA 0x38
303#define DRIVE_CURRENT_22_875_mA 0x39
304#define DRIVE_CURRENT_23_250_mA 0x3a
305#define DRIVE_CURRENT_23_625_mA 0x3b
306#define DRIVE_CURRENT_24_000_mA 0x3c
307#define DRIVE_CURRENT_24_375_mA 0x3d
308#define DRIVE_CURRENT_24_750_mA 0x3e
309
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +0200310#define DRIVE_CURRENT_0_000_mA_T114 0x00
311#define DRIVE_CURRENT_0_400_mA_T114 0x01
312#define DRIVE_CURRENT_0_800_mA_T114 0x02
313#define DRIVE_CURRENT_1_200_mA_T114 0x03
314#define DRIVE_CURRENT_1_600_mA_T114 0x04
315#define DRIVE_CURRENT_2_000_mA_T114 0x05
316#define DRIVE_CURRENT_2_400_mA_T114 0x06
317#define DRIVE_CURRENT_2_800_mA_T114 0x07
318#define DRIVE_CURRENT_3_200_mA_T114 0x08
319#define DRIVE_CURRENT_3_600_mA_T114 0x09
320#define DRIVE_CURRENT_4_000_mA_T114 0x0a
321#define DRIVE_CURRENT_4_400_mA_T114 0x0b
322#define DRIVE_CURRENT_4_800_mA_T114 0x0c
323#define DRIVE_CURRENT_5_200_mA_T114 0x0d
324#define DRIVE_CURRENT_5_600_mA_T114 0x0e
325#define DRIVE_CURRENT_6_000_mA_T114 0x0f
326#define DRIVE_CURRENT_6_400_mA_T114 0x10
327#define DRIVE_CURRENT_6_800_mA_T114 0x11
328#define DRIVE_CURRENT_7_200_mA_T114 0x12
329#define DRIVE_CURRENT_7_600_mA_T114 0x13
330#define DRIVE_CURRENT_8_000_mA_T114 0x14
331#define DRIVE_CURRENT_8_400_mA_T114 0x15
332#define DRIVE_CURRENT_8_800_mA_T114 0x16
333#define DRIVE_CURRENT_9_200_mA_T114 0x17
334#define DRIVE_CURRENT_9_600_mA_T114 0x18
335#define DRIVE_CURRENT_10_000_mA_T114 0x19
336#define DRIVE_CURRENT_10_400_mA_T114 0x1a
337#define DRIVE_CURRENT_10_800_mA_T114 0x1b
338#define DRIVE_CURRENT_11_200_mA_T114 0x1c
339#define DRIVE_CURRENT_11_600_mA_T114 0x1d
340#define DRIVE_CURRENT_12_000_mA_T114 0x1e
341#define DRIVE_CURRENT_12_400_mA_T114 0x1f
342#define DRIVE_CURRENT_12_800_mA_T114 0x20
343#define DRIVE_CURRENT_13_200_mA_T114 0x21
344#define DRIVE_CURRENT_13_600_mA_T114 0x22
345#define DRIVE_CURRENT_14_000_mA_T114 0x23
346#define DRIVE_CURRENT_14_400_mA_T114 0x24
347#define DRIVE_CURRENT_14_800_mA_T114 0x25
348#define DRIVE_CURRENT_15_200_mA_T114 0x26
349#define DRIVE_CURRENT_15_600_mA_T114 0x27
350#define DRIVE_CURRENT_16_000_mA_T114 0x28
351#define DRIVE_CURRENT_16_400_mA_T114 0x29
352#define DRIVE_CURRENT_16_800_mA_T114 0x2a
353#define DRIVE_CURRENT_17_200_mA_T114 0x2b
354#define DRIVE_CURRENT_17_600_mA_T114 0x2c
355#define DRIVE_CURRENT_18_000_mA_T114 0x2d
356#define DRIVE_CURRENT_18_400_mA_T114 0x2e
357#define DRIVE_CURRENT_18_800_mA_T114 0x2f
358#define DRIVE_CURRENT_19_200_mA_T114 0x30
359#define DRIVE_CURRENT_19_600_mA_T114 0x31
360#define DRIVE_CURRENT_20_000_mA_T114 0x32
361#define DRIVE_CURRENT_20_400_mA_T114 0x33
362#define DRIVE_CURRENT_20_800_mA_T114 0x34
363#define DRIVE_CURRENT_21_200_mA_T114 0x35
364#define DRIVE_CURRENT_21_600_mA_T114 0x36
365#define DRIVE_CURRENT_22_000_mA_T114 0x37
366#define DRIVE_CURRENT_22_400_mA_T114 0x38
367#define DRIVE_CURRENT_22_800_mA_T114 0x39
368#define DRIVE_CURRENT_23_200_mA_T114 0x3a
369#define DRIVE_CURRENT_23_600_mA_T114 0x3b
370#define DRIVE_CURRENT_24_000_mA_T114 0x3c
371#define DRIVE_CURRENT_24_400_mA_T114 0x3d
372#define DRIVE_CURRENT_24_800_mA_T114 0x3e
373#define DRIVE_CURRENT_25_200_mA_T114 0x3f
374#define DRIVE_CURRENT_25_400_mA_T114 0x40
375#define DRIVE_CURRENT_25_800_mA_T114 0x41
376#define DRIVE_CURRENT_26_200_mA_T114 0x42
377#define DRIVE_CURRENT_26_600_mA_T114 0x43
378#define DRIVE_CURRENT_27_000_mA_T114 0x44
379#define DRIVE_CURRENT_27_400_mA_T114 0x45
380#define DRIVE_CURRENT_27_800_mA_T114 0x46
381#define DRIVE_CURRENT_28_200_mA_T114 0x47
382
Thierry Redingedec4af2012-11-15 21:28:23 +0000383#define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
384#define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
385#define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
386
387#define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
388#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
389#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
390
391#define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
392#define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
393#define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
394#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
395#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
396#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
397#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
398#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
399
400#define HDMI_NV_PDISP_AUDIO_N 0x8c
401#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
402#define AUDIO_N_RESETF (1 << 20)
403#define AUDIO_N_GENERATE_NORMAL (0 << 24)
404#define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
405
406#define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
407#define HDMI_NV_PDISP_SOR_REFCLK 0x95
408#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
409#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
410
411#define HDMI_NV_PDISP_CRC_CONTROL 0x96
412#define HDMI_NV_PDISP_INPUT_CONTROL 0x97
413#define HDMI_SRC_DISPLAYA (0 << 0)
414#define HDMI_SRC_DISPLAYB (1 << 0)
415#define ARM_VIDEO_RANGE_FULL (0 << 1)
416#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
417
418#define HDMI_NV_PDISP_SCRATCH 0x98
419#define HDMI_NV_PDISP_PE_CURRENT 0x99
420#define PE_CURRENT0(x) (((x) & 0xf) << 0)
421#define PE_CURRENT1(x) (((x) & 0xf) << 8)
422#define PE_CURRENT2(x) (((x) & 0xf) << 16)
423#define PE_CURRENT3(x) (((x) & 0xf) << 24)
424
425#define PE_CURRENT_0_0_mA 0x0
426#define PE_CURRENT_0_5_mA 0x1
427#define PE_CURRENT_1_0_mA 0x2
428#define PE_CURRENT_1_5_mA 0x3
429#define PE_CURRENT_2_0_mA 0x4
430#define PE_CURRENT_2_5_mA 0x5
431#define PE_CURRENT_3_0_mA 0x6
432#define PE_CURRENT_3_5_mA 0x7
433#define PE_CURRENT_4_0_mA 0x8
434#define PE_CURRENT_4_5_mA 0x9
435#define PE_CURRENT_5_0_mA 0xa
436#define PE_CURRENT_5_5_mA 0xb
437#define PE_CURRENT_6_0_mA 0xc
438#define PE_CURRENT_6_5_mA 0xd
439#define PE_CURRENT_7_0_mA 0xe
440#define PE_CURRENT_7_5_mA 0xf
441
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +0200442#define PE_CURRENT_0_mA_T114 0x0
443#define PE_CURRENT_1_mA_T114 0x1
444#define PE_CURRENT_2_mA_T114 0x2
445#define PE_CURRENT_3_mA_T114 0x3
446#define PE_CURRENT_4_mA_T114 0x4
447#define PE_CURRENT_5_mA_T114 0x5
448#define PE_CURRENT_6_mA_T114 0x6
449#define PE_CURRENT_7_mA_T114 0x7
450#define PE_CURRENT_8_mA_T114 0x8
451#define PE_CURRENT_9_mA_T114 0x9
452#define PE_CURRENT_10_mA_T114 0xa
453#define PE_CURRENT_11_mA_T114 0xb
454#define PE_CURRENT_12_mA_T114 0xc
455#define PE_CURRENT_13_mA_T114 0xd
456#define PE_CURRENT_14_mA_T114 0xe
457#define PE_CURRENT_15_mA_T114 0xf
458
Thierry Redingedec4af2012-11-15 21:28:23 +0000459#define HDMI_NV_PDISP_KEY_CTRL 0x9a
460#define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
461#define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
462#define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
463#define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
464#define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
465#define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
466#define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
467#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
468#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
469
470#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac
471#define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
472#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc
473#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd
474
475#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf
476#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0
477#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1
478#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2
479#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3
480#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4
481#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
482#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
483
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +0200484#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1
485#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
486#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)
487#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
488#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
489
490#define PEAK_CURRENT_0_000_mA 0x00
491#define PEAK_CURRENT_0_200_mA 0x01
492#define PEAK_CURRENT_0_400_mA 0x02
493#define PEAK_CURRENT_0_600_mA 0x03
494#define PEAK_CURRENT_0_800_mA 0x04
495#define PEAK_CURRENT_1_000_mA 0x05
496#define PEAK_CURRENT_1_200_mA 0x06
497#define PEAK_CURRENT_1_400_mA 0x07
498#define PEAK_CURRENT_1_600_mA 0x08
499#define PEAK_CURRENT_1_800_mA 0x09
500#define PEAK_CURRENT_2_000_mA 0x0a
501#define PEAK_CURRENT_2_200_mA 0x0b
502#define PEAK_CURRENT_2_400_mA 0x0c
503#define PEAK_CURRENT_2_600_mA 0x0d
504#define PEAK_CURRENT_2_800_mA 0x0e
505#define PEAK_CURRENT_3_000_mA 0x0f
506#define PEAK_CURRENT_3_200_mA 0x10
507#define PEAK_CURRENT_3_400_mA 0x11
508#define PEAK_CURRENT_3_600_mA 0x12
509#define PEAK_CURRENT_3_800_mA 0x13
510#define PEAK_CURRENT_4_000_mA 0x14
511#define PEAK_CURRENT_4_200_mA 0x15
512#define PEAK_CURRENT_4_400_mA 0x16
513#define PEAK_CURRENT_4_600_mA 0x17
514#define PEAK_CURRENT_4_800_mA 0x18
515#define PEAK_CURRENT_5_000_mA 0x19
516#define PEAK_CURRENT_5_200_mA 0x1a
517#define PEAK_CURRENT_5_400_mA 0x1b
518#define PEAK_CURRENT_5_600_mA 0x1c
519#define PEAK_CURRENT_5_800_mA 0x1d
520#define PEAK_CURRENT_6_000_mA 0x1e
521#define PEAK_CURRENT_6_200_mA 0x1f
522#define PEAK_CURRENT_6_400_mA 0x20
523#define PEAK_CURRENT_6_600_mA 0x21
524#define PEAK_CURRENT_6_800_mA 0x22
525#define PEAK_CURRENT_7_000_mA 0x23
526#define PEAK_CURRENT_7_200_mA 0x24
527#define PEAK_CURRENT_7_400_mA 0x25
528#define PEAK_CURRENT_7_600_mA 0x26
529#define PEAK_CURRENT_7_800_mA 0x27
530#define PEAK_CURRENT_8_000_mA 0x28
531#define PEAK_CURRENT_8_200_mA 0x29
532#define PEAK_CURRENT_8_400_mA 0x2a
533#define PEAK_CURRENT_8_600_mA 0x2b
534#define PEAK_CURRENT_8_800_mA 0x2c
535#define PEAK_CURRENT_9_000_mA 0x2d
536#define PEAK_CURRENT_9_200_mA 0x2e
537#define PEAK_CURRENT_9_400_mA 0x2f
538
539#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2
540
Thierry Redingedec4af2012-11-15 21:28:23 +0000541#endif /* TEGRA_HDMI_H */