Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1 | /* |
| 2 | * drivers/spi/spi-fsl-dspi.c |
| 3 | * |
| 4 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Freescale DSPI driver |
| 7 | * This file contains a driver for the Freescale DSPI |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/sched.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/spi/spi.h> |
| 27 | #include <linux/spi/spi_bitbang.h> |
| 28 | #include <linux/pm_runtime.h> |
| 29 | #include <linux/of.h> |
| 30 | #include <linux/of_device.h> |
| 31 | |
| 32 | #define DRIVER_NAME "fsl-dspi" |
| 33 | |
| 34 | #define TRAN_STATE_RX_VOID 0x01 |
| 35 | #define TRAN_STATE_TX_VOID 0x02 |
| 36 | #define TRAN_STATE_WORD_ODD_NUM 0x04 |
| 37 | |
| 38 | #define DSPI_FIFO_SIZE 4 |
| 39 | |
| 40 | #define SPI_MCR 0x00 |
| 41 | #define SPI_MCR_MASTER (1 << 31) |
| 42 | #define SPI_MCR_PCSIS (0x3F << 16) |
| 43 | #define SPI_MCR_CLR_TXF (1 << 11) |
| 44 | #define SPI_MCR_CLR_RXF (1 << 10) |
| 45 | |
| 46 | #define SPI_TCR 0x08 |
| 47 | |
| 48 | #define SPI_CTAR(x) (0x0c + (x * 4)) |
| 49 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
| 50 | #define SPI_CTAR_CPOL(x) ((x) << 26) |
| 51 | #define SPI_CTAR_CPHA(x) ((x) << 25) |
| 52 | #define SPI_CTAR_LSBFE(x) ((x) << 24) |
| 53 | #define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22) |
| 54 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
| 55 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) |
| 56 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) |
| 57 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) |
| 58 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) |
| 59 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) |
| 60 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) |
| 61 | |
| 62 | #define SPI_CTAR0_SLAVE 0x0c |
| 63 | |
| 64 | #define SPI_SR 0x2c |
| 65 | #define SPI_SR_EOQF 0x10000000 |
| 66 | |
| 67 | #define SPI_RSER 0x30 |
| 68 | #define SPI_RSER_EOQFE 0x10000000 |
| 69 | |
| 70 | #define SPI_PUSHR 0x34 |
| 71 | #define SPI_PUSHR_CONT (1 << 31) |
| 72 | #define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28) |
| 73 | #define SPI_PUSHR_EOQ (1 << 27) |
| 74 | #define SPI_PUSHR_CTCNT (1 << 26) |
| 75 | #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) |
| 76 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) |
| 77 | |
| 78 | #define SPI_PUSHR_SLAVE 0x34 |
| 79 | |
| 80 | #define SPI_POPR 0x38 |
| 81 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) |
| 82 | |
| 83 | #define SPI_TXFR0 0x3c |
| 84 | #define SPI_TXFR1 0x40 |
| 85 | #define SPI_TXFR2 0x44 |
| 86 | #define SPI_TXFR3 0x48 |
| 87 | #define SPI_RXFR0 0x7c |
| 88 | #define SPI_RXFR1 0x80 |
| 89 | #define SPI_RXFR2 0x84 |
| 90 | #define SPI_RXFR3 0x88 |
| 91 | |
| 92 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) |
| 93 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) |
| 94 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) |
| 95 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) |
| 96 | |
| 97 | #define SPI_CS_INIT 0x01 |
| 98 | #define SPI_CS_ASSERT 0x02 |
| 99 | #define SPI_CS_DROP 0x04 |
| 100 | |
| 101 | struct chip_data { |
| 102 | u32 mcr_val; |
| 103 | u32 ctar_val; |
| 104 | u16 void_write_data; |
| 105 | }; |
| 106 | |
| 107 | struct fsl_dspi { |
| 108 | struct spi_bitbang bitbang; |
| 109 | struct platform_device *pdev; |
| 110 | |
Jingoo Han | 2ef3599 | 2013-09-05 15:51:21 +0900 | [diff] [blame] | 111 | void __iomem *base; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 112 | int irq; |
| 113 | struct clk *clk; |
| 114 | |
| 115 | struct spi_transfer *cur_transfer; |
| 116 | struct chip_data *cur_chip; |
| 117 | size_t len; |
| 118 | void *tx; |
| 119 | void *tx_end; |
| 120 | void *rx; |
| 121 | void *rx_end; |
| 122 | char dataflags; |
| 123 | u8 cs; |
| 124 | u16 void_write_data; |
| 125 | |
| 126 | wait_queue_head_t waitq; |
| 127 | u32 waitflags; |
| 128 | }; |
| 129 | |
| 130 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) |
| 131 | { |
| 132 | return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK) |
| 133 | == SPI_FRAME_BITS(8)) ? 0 : 1; |
| 134 | } |
| 135 | |
| 136 | static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits) |
| 137 | { |
| 138 | u32 temp; |
| 139 | |
| 140 | temp = readl(dspi->base + SPI_CTAR(dspi->cs)); |
| 141 | temp &= ~SPI_FRAME_BITS_MASK; |
| 142 | temp |= SPI_FRAME_BITS(bits); |
| 143 | writel(temp, dspi->base + SPI_CTAR(dspi->cs)); |
| 144 | } |
| 145 | |
| 146 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
| 147 | unsigned long clkrate) |
| 148 | { |
| 149 | /* Valid baud rate pre-scaler values */ |
| 150 | int pbr_tbl[4] = {2, 3, 5, 7}; |
| 151 | int brs[16] = { 2, 4, 6, 8, |
| 152 | 16, 32, 64, 128, |
| 153 | 256, 512, 1024, 2048, |
| 154 | 4096, 8192, 16384, 32768 }; |
| 155 | int temp, i = 0, j = 0; |
| 156 | |
| 157 | temp = clkrate / 2 / speed_hz; |
| 158 | |
| 159 | for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++) |
| 160 | for (j = 0; j < ARRAY_SIZE(brs); j++) { |
| 161 | if (pbr_tbl[i] * brs[j] >= temp) { |
| 162 | *pbr = i; |
| 163 | *br = j; |
| 164 | return; |
| 165 | } |
| 166 | } |
| 167 | |
Uwe Kleine-König | b444d1d | 2013-09-10 10:46:33 +0200 | [diff] [blame] | 168 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\ |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 169 | ,we use the max prescaler value.\n", speed_hz, clkrate); |
| 170 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; |
| 171 | *br = ARRAY_SIZE(brs) - 1; |
| 172 | } |
| 173 | |
| 174 | static int dspi_transfer_write(struct fsl_dspi *dspi) |
| 175 | { |
| 176 | int tx_count = 0; |
| 177 | int tx_word; |
| 178 | u16 d16; |
| 179 | u8 d8; |
| 180 | u32 dspi_pushr = 0; |
| 181 | int first = 1; |
| 182 | |
| 183 | tx_word = is_double_byte_mode(dspi); |
| 184 | |
| 185 | /* If we are in word mode, but only have a single byte to transfer |
| 186 | * then switch to byte mode temporarily. Will switch back at the |
| 187 | * end of the transfer. |
| 188 | */ |
| 189 | if (tx_word && (dspi->len == 1)) { |
| 190 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; |
| 191 | set_bit_mode(dspi, 8); |
| 192 | tx_word = 0; |
| 193 | } |
| 194 | |
| 195 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { |
| 196 | if (tx_word) { |
| 197 | if (dspi->len == 1) |
| 198 | break; |
| 199 | |
| 200 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) { |
| 201 | d16 = *(u16 *)dspi->tx; |
| 202 | dspi->tx += 2; |
| 203 | } else { |
| 204 | d16 = dspi->void_write_data; |
| 205 | } |
| 206 | |
| 207 | dspi_pushr = SPI_PUSHR_TXDATA(d16) | |
| 208 | SPI_PUSHR_PCS(dspi->cs) | |
| 209 | SPI_PUSHR_CTAS(dspi->cs) | |
| 210 | SPI_PUSHR_CONT; |
| 211 | |
| 212 | dspi->len -= 2; |
| 213 | } else { |
| 214 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) { |
| 215 | |
| 216 | d8 = *(u8 *)dspi->tx; |
| 217 | dspi->tx++; |
| 218 | } else { |
| 219 | d8 = (u8)dspi->void_write_data; |
| 220 | } |
| 221 | |
| 222 | dspi_pushr = SPI_PUSHR_TXDATA(d8) | |
| 223 | SPI_PUSHR_PCS(dspi->cs) | |
| 224 | SPI_PUSHR_CTAS(dspi->cs) | |
| 225 | SPI_PUSHR_CONT; |
| 226 | |
| 227 | dspi->len--; |
| 228 | } |
| 229 | |
| 230 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
| 231 | /* last transfer in the transfer */ |
| 232 | dspi_pushr |= SPI_PUSHR_EOQ; |
| 233 | } else if (tx_word && (dspi->len == 1)) |
| 234 | dspi_pushr |= SPI_PUSHR_EOQ; |
| 235 | |
| 236 | if (first) { |
| 237 | first = 0; |
| 238 | dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */ |
| 239 | } |
| 240 | |
| 241 | writel(dspi_pushr, dspi->base + SPI_PUSHR); |
| 242 | tx_count++; |
| 243 | } |
| 244 | |
| 245 | return tx_count * (tx_word + 1); |
| 246 | } |
| 247 | |
| 248 | static int dspi_transfer_read(struct fsl_dspi *dspi) |
| 249 | { |
| 250 | int rx_count = 0; |
| 251 | int rx_word = is_double_byte_mode(dspi); |
| 252 | u16 d; |
| 253 | while ((dspi->rx < dspi->rx_end) |
| 254 | && (rx_count < DSPI_FIFO_SIZE)) { |
| 255 | if (rx_word) { |
| 256 | if ((dspi->rx_end - dspi->rx) == 1) |
| 257 | break; |
| 258 | |
| 259 | d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); |
| 260 | |
| 261 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
| 262 | *(u16 *)dspi->rx = d; |
| 263 | dspi->rx += 2; |
| 264 | |
| 265 | } else { |
| 266 | d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); |
| 267 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
| 268 | *(u8 *)dspi->rx = d; |
| 269 | dspi->rx++; |
| 270 | } |
| 271 | rx_count++; |
| 272 | } |
| 273 | |
| 274 | return rx_count; |
| 275 | } |
| 276 | |
| 277 | static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t) |
| 278 | { |
| 279 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
| 280 | dspi->cur_transfer = t; |
| 281 | dspi->cur_chip = spi_get_ctldata(spi); |
| 282 | dspi->cs = spi->chip_select; |
| 283 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
| 284 | |
| 285 | dspi->dataflags = 0; |
| 286 | dspi->tx = (void *)t->tx_buf; |
| 287 | dspi->tx_end = dspi->tx + t->len; |
| 288 | dspi->rx = t->rx_buf; |
| 289 | dspi->rx_end = dspi->rx + t->len; |
| 290 | dspi->len = t->len; |
| 291 | |
| 292 | if (!dspi->rx) |
| 293 | dspi->dataflags |= TRAN_STATE_RX_VOID; |
| 294 | |
| 295 | if (!dspi->tx) |
| 296 | dspi->dataflags |= TRAN_STATE_TX_VOID; |
| 297 | |
| 298 | writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR); |
| 299 | writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs)); |
| 300 | writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER); |
| 301 | |
| 302 | if (t->speed_hz) |
| 303 | writel(dspi->cur_chip->ctar_val, |
| 304 | dspi->base + SPI_CTAR(dspi->cs)); |
| 305 | |
| 306 | dspi_transfer_write(dspi); |
| 307 | |
| 308 | if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) |
| 309 | dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); |
| 310 | dspi->waitflags = 0; |
| 311 | |
| 312 | return t->len - dspi->len; |
| 313 | } |
| 314 | |
| 315 | static void dspi_chipselect(struct spi_device *spi, int value) |
| 316 | { |
| 317 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
| 318 | u32 pushr = readl(dspi->base + SPI_PUSHR); |
| 319 | |
| 320 | switch (value) { |
| 321 | case BITBANG_CS_ACTIVE: |
| 322 | pushr |= SPI_PUSHR_CONT; |
Axel Lin | e07725b | 2014-01-08 22:27:54 +0800 | [diff] [blame] | 323 | break; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 324 | case BITBANG_CS_INACTIVE: |
| 325 | pushr &= ~SPI_PUSHR_CONT; |
Axel Lin | e07725b | 2014-01-08 22:27:54 +0800 | [diff] [blame] | 326 | break; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | writel(pushr, dspi->base + SPI_PUSHR); |
| 330 | } |
| 331 | |
| 332 | static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
| 333 | { |
| 334 | struct chip_data *chip; |
| 335 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
| 336 | unsigned char br = 0, pbr = 0, fmsz = 0; |
| 337 | |
| 338 | /* Only alloc on first setup */ |
| 339 | chip = spi_get_ctldata(spi); |
| 340 | if (chip == NULL) { |
| 341 | chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL); |
| 342 | if (!chip) |
| 343 | return -ENOMEM; |
| 344 | } |
| 345 | |
| 346 | chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | |
| 347 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; |
| 348 | if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { |
| 349 | fmsz = spi->bits_per_word - 1; |
| 350 | } else { |
| 351 | pr_err("Invalid wordsize\n"); |
| 352 | kfree(chip); |
| 353 | return -ENODEV; |
| 354 | } |
| 355 | |
| 356 | chip->void_write_data = 0; |
| 357 | |
| 358 | hz_to_spi_baud(&pbr, &br, |
| 359 | spi->max_speed_hz, clk_get_rate(dspi->clk)); |
| 360 | |
| 361 | chip->ctar_val = SPI_CTAR_FMSZ(fmsz) |
| 362 | | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) |
| 363 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) |
| 364 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) |
| 365 | | SPI_CTAR_PBR(pbr) |
| 366 | | SPI_CTAR_BR(br); |
| 367 | |
| 368 | spi_set_ctldata(spi, chip); |
| 369 | |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | static int dspi_setup(struct spi_device *spi) |
| 374 | { |
| 375 | if (!spi->max_speed_hz) |
| 376 | return -EINVAL; |
| 377 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 378 | return dspi_setup_transfer(spi, NULL); |
| 379 | } |
| 380 | |
| 381 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
| 382 | { |
| 383 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; |
| 384 | |
| 385 | writel(SPI_SR_EOQF, dspi->base + SPI_SR); |
| 386 | |
| 387 | dspi_transfer_read(dspi); |
| 388 | |
| 389 | if (!dspi->len) { |
| 390 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) |
| 391 | set_bit_mode(dspi, 16); |
| 392 | dspi->waitflags = 1; |
| 393 | wake_up_interruptible(&dspi->waitq); |
| 394 | } else { |
| 395 | dspi_transfer_write(dspi); |
| 396 | |
| 397 | return IRQ_HANDLED; |
| 398 | } |
| 399 | |
| 400 | return IRQ_HANDLED; |
| 401 | } |
| 402 | |
| 403 | static struct of_device_id fsl_dspi_dt_ids[] = { |
| 404 | { .compatible = "fsl,vf610-dspi", .data = NULL, }, |
| 405 | { /* sentinel */ } |
| 406 | }; |
| 407 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); |
| 408 | |
| 409 | #ifdef CONFIG_PM_SLEEP |
| 410 | static int dspi_suspend(struct device *dev) |
| 411 | { |
| 412 | struct spi_master *master = dev_get_drvdata(dev); |
| 413 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
| 414 | |
| 415 | spi_master_suspend(master); |
| 416 | clk_disable_unprepare(dspi->clk); |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static int dspi_resume(struct device *dev) |
| 422 | { |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 423 | struct spi_master *master = dev_get_drvdata(dev); |
| 424 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
| 425 | |
| 426 | clk_prepare_enable(dspi->clk); |
| 427 | spi_master_resume(master); |
| 428 | |
| 429 | return 0; |
| 430 | } |
| 431 | #endif /* CONFIG_PM_SLEEP */ |
| 432 | |
| 433 | static const struct dev_pm_ops dspi_pm = { |
| 434 | SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume) |
| 435 | }; |
| 436 | |
| 437 | static int dspi_probe(struct platform_device *pdev) |
| 438 | { |
| 439 | struct device_node *np = pdev->dev.of_node; |
| 440 | struct spi_master *master; |
| 441 | struct fsl_dspi *dspi; |
| 442 | struct resource *res; |
| 443 | int ret = 0, cs_num, bus_num; |
| 444 | |
| 445 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); |
| 446 | if (!master) |
| 447 | return -ENOMEM; |
| 448 | |
| 449 | dspi = spi_master_get_devdata(master); |
| 450 | dspi->pdev = pdev; |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 451 | dspi->bitbang.master = master; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 452 | dspi->bitbang.chipselect = dspi_chipselect; |
| 453 | dspi->bitbang.setup_transfer = dspi_setup_transfer; |
| 454 | dspi->bitbang.txrx_bufs = dspi_txrx_transfer; |
| 455 | dspi->bitbang.master->setup = dspi_setup; |
| 456 | dspi->bitbang.master->dev.of_node = pdev->dev.of_node; |
| 457 | |
| 458 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
| 459 | master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | |
| 460 | SPI_BPW_MASK(16); |
| 461 | |
| 462 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); |
| 463 | if (ret < 0) { |
| 464 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); |
| 465 | goto out_master_put; |
| 466 | } |
| 467 | master->num_chipselect = cs_num; |
| 468 | |
| 469 | ret = of_property_read_u32(np, "bus-num", &bus_num); |
| 470 | if (ret < 0) { |
| 471 | dev_err(&pdev->dev, "can't get bus-num\n"); |
| 472 | goto out_master_put; |
| 473 | } |
| 474 | master->bus_num = bus_num; |
| 475 | |
| 476 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 477 | dspi->base = devm_ioremap_resource(&pdev->dev, res); |
Wei Yongjun | 272bfbd | 2013-09-11 19:15:08 +0800 | [diff] [blame] | 478 | if (IS_ERR(dspi->base)) { |
| 479 | ret = PTR_ERR(dspi->base); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 480 | goto out_master_put; |
| 481 | } |
| 482 | |
| 483 | dspi->irq = platform_get_irq(pdev, 0); |
| 484 | if (dspi->irq < 0) { |
| 485 | dev_err(&pdev->dev, "can't get platform irq\n"); |
| 486 | ret = dspi->irq; |
| 487 | goto out_master_put; |
| 488 | } |
| 489 | |
| 490 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, |
| 491 | pdev->name, dspi); |
| 492 | if (ret < 0) { |
| 493 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); |
| 494 | goto out_master_put; |
| 495 | } |
| 496 | |
| 497 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); |
| 498 | if (IS_ERR(dspi->clk)) { |
| 499 | ret = PTR_ERR(dspi->clk); |
| 500 | dev_err(&pdev->dev, "unable to get clock\n"); |
| 501 | goto out_master_put; |
| 502 | } |
| 503 | clk_prepare_enable(dspi->clk); |
| 504 | |
| 505 | init_waitqueue_head(&dspi->waitq); |
Axel Lin | 017145f | 2014-02-14 12:49:12 +0800 | [diff] [blame^] | 506 | platform_set_drvdata(pdev, master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 507 | |
| 508 | ret = spi_bitbang_start(&dspi->bitbang); |
| 509 | if (ret != 0) { |
| 510 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); |
| 511 | goto out_clk_put; |
| 512 | } |
| 513 | |
| 514 | pr_info(KERN_INFO "Freescale DSPI master initialized\n"); |
| 515 | return ret; |
| 516 | |
| 517 | out_clk_put: |
| 518 | clk_disable_unprepare(dspi->clk); |
| 519 | out_master_put: |
| 520 | spi_master_put(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 521 | |
| 522 | return ret; |
| 523 | } |
| 524 | |
| 525 | static int dspi_remove(struct platform_device *pdev) |
| 526 | { |
Axel Lin | 017145f | 2014-02-14 12:49:12 +0800 | [diff] [blame^] | 527 | struct spi_master *master = platform_get_drvdata(pdev); |
| 528 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 529 | |
| 530 | /* Disconnect from the SPI framework */ |
| 531 | spi_bitbang_stop(&dspi->bitbang); |
Wei Yongjun | 05209f4 | 2013-10-12 15:15:31 +0800 | [diff] [blame] | 532 | clk_disable_unprepare(dspi->clk); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 533 | spi_master_put(dspi->bitbang.master); |
| 534 | |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static struct platform_driver fsl_dspi_driver = { |
| 539 | .driver.name = DRIVER_NAME, |
| 540 | .driver.of_match_table = fsl_dspi_dt_ids, |
| 541 | .driver.owner = THIS_MODULE, |
| 542 | .driver.pm = &dspi_pm, |
| 543 | .probe = dspi_probe, |
| 544 | .remove = dspi_remove, |
| 545 | }; |
| 546 | module_platform_driver(fsl_dspi_driver); |
| 547 | |
| 548 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); |
Uwe Kleine-König | b444d1d | 2013-09-10 10:46:33 +0200 | [diff] [blame] | 549 | MODULE_LICENSE("GPL"); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 550 | MODULE_ALIAS("platform:" DRIVER_NAME); |