Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 33 | #include <uapi/drm/i915_drm.h> |
Tvrtko Ursulin | 93b81f5 | 2015-02-10 17:16:05 +0000 | [diff] [blame] | 34 | #include <uapi/drm/drm_fourcc.h> |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 35 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 36 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 38 | #include "intel_ringbuffer.h" |
Oscar Mateo | b20385f | 2014-07-24 17:04:10 +0100 | [diff] [blame] | 39 | #include "intel_lrc.h" |
Ben Widawsky | 0260c42 | 2014-03-22 22:47:21 -0700 | [diff] [blame] | 40 | #include "i915_gem_gtt.h" |
Oscar Mateo | 564ddb2 | 2014-08-21 11:40:54 +0100 | [diff] [blame] | 41 | #include "i915_gem_render_state.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 42 | #include <linux/io-mapping.h> |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 43 | #include <linux/i2c.h> |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 44 | #include <linux/i2c-algo-bit.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 45 | #include <drm/intel-gtt.h> |
Daniel Vetter | ba8286f | 2014-09-11 07:43:25 +0200 | [diff] [blame] | 46 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
Daniel Vetter | d9fc941 | 2014-09-23 15:46:53 +0200 | [diff] [blame] | 47 | #include <drm/drm_gem.h> |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 48 | #include <linux/backlight.h> |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 49 | #include <linux/hashtable.h> |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 50 | #include <linux/intel-iommu.h> |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 51 | #include <linux/kref.h> |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 52 | #include <linux/pm_qos.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 53 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | /* General customization: |
| 55 | */ |
| 56 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | #define DRIVER_NAME "i915" |
| 58 | #define DRIVER_DESC "Intel Graphics" |
Daniel Vetter | 1ff27a3 | 2015-03-27 20:21:01 +0100 | [diff] [blame] | 59 | #define DRIVER_DATE "20150327" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | |
Mika Kuoppala | c883ef1 | 2014-10-28 17:32:30 +0200 | [diff] [blame] | 61 | #undef WARN_ON |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 62 | /* Many gcc seem to no see through this and fall over :( */ |
| 63 | #if 0 |
| 64 | #define WARN_ON(x) ({ \ |
| 65 | bool __i915_warn_cond = (x); \ |
| 66 | if (__builtin_constant_p(__i915_warn_cond)) \ |
| 67 | BUILD_BUG_ON(__i915_warn_cond); \ |
| 68 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) |
| 69 | #else |
| 70 | #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") |
| 71 | #endif |
| 72 | |
Jani Nikula | cd9bfac | 2015-03-12 13:01:12 +0200 | [diff] [blame] | 73 | #undef WARN_ON_ONCE |
| 74 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")") |
| 75 | |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 76 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
| 77 | (long) (x), __func__); |
Mika Kuoppala | c883ef1 | 2014-10-28 17:32:30 +0200 | [diff] [blame] | 78 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 79 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
| 80 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions |
| 81 | * which may not necessarily be a user visible problem. This will either |
| 82 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to |
| 83 | * enable distros and users to tailor their preferred amount of i915 abrt |
| 84 | * spam. |
| 85 | */ |
| 86 | #define I915_STATE_WARN(condition, format...) ({ \ |
| 87 | int __ret_warn_on = !!(condition); \ |
| 88 | if (unlikely(__ret_warn_on)) { \ |
| 89 | if (i915.verbose_state_checks) \ |
Jani Nikula | 2f3408c | 2015-01-12 15:45:31 +0200 | [diff] [blame] | 90 | WARN(1, format); \ |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 91 | else \ |
| 92 | DRM_ERROR(format); \ |
| 93 | } \ |
| 94 | unlikely(__ret_warn_on); \ |
| 95 | }) |
| 96 | |
| 97 | #define I915_STATE_WARN_ON(condition) ({ \ |
| 98 | int __ret_warn_on = !!(condition); \ |
| 99 | if (unlikely(__ret_warn_on)) { \ |
| 100 | if (i915.verbose_state_checks) \ |
Jani Nikula | 2f3408c | 2015-01-12 15:45:31 +0200 | [diff] [blame] | 101 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 102 | else \ |
| 103 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ |
| 104 | } \ |
| 105 | unlikely(__ret_warn_on); \ |
| 106 | }) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 107 | |
| 108 | enum pipe { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 109 | INVALID_PIPE = -1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 110 | PIPE_A = 0, |
| 111 | PIPE_B, |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 112 | PIPE_C, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 113 | _PIPE_EDP, |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 114 | I915_MAX_PIPES = _PIPE_EDP |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 115 | }; |
| 116 | #define pipe_name(p) ((p) + 'A') |
| 117 | |
| 118 | enum transcoder { |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 119 | TRANSCODER_A = 0, |
| 120 | TRANSCODER_B, |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 121 | TRANSCODER_C, |
| 122 | TRANSCODER_EDP, |
| 123 | I915_MAX_TRANSCODERS |
Damien Lespiau | 84139d1 | 2014-03-28 00:18:32 +0530 | [diff] [blame] | 124 | }; |
| 125 | #define transcoder_name(t) ((t) + 'A') |
| 126 | |
| 127 | /* |
| 128 | * This is the maximum (across all platforms) number of planes (primary + |
| 129 | * sprites) that can be active at the same time on one pipe. |
| 130 | * |
| 131 | * This value doesn't count the cursor plane. |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 132 | */ |
| 133 | #define I915_MAX_PLANES 3 |
| 134 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 135 | enum plane { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 136 | PLANE_A = 0, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 137 | PLANE_B, |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 138 | PLANE_C, |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 139 | }; |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 140 | #define plane_name(p) ((p) + 'A') |
Eugeni Dodonov | 2b13952 | 2012-03-29 12:32:22 -0300 | [diff] [blame] | 141 | |
| 142 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
| 143 | |
| 144 | enum port { |
| 145 | PORT_A = 0, |
| 146 | PORT_B, |
| 147 | PORT_C, |
| 148 | PORT_D, |
| 149 | PORT_E, |
| 150 | I915_MAX_PORTS |
Chon Ming Lee | a09cadd | 2014-04-09 13:28:14 +0300 | [diff] [blame] | 151 | }; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 152 | #define port_name(p) ((p) + 'A') |
| 153 | |
| 154 | #define I915_NUM_PHYS_VLV 2 |
| 155 | |
| 156 | enum dpio_channel { |
| 157 | DPIO_CH0, |
| 158 | DPIO_CH1 |
| 159 | }; |
| 160 | |
| 161 | enum dpio_phy { |
| 162 | DPIO_PHY0, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 163 | DPIO_PHY1 |
| 164 | }; |
| 165 | |
| 166 | enum intel_display_power_domain { |
| 167 | POWER_DOMAIN_PIPE_A, |
| 168 | POWER_DOMAIN_PIPE_B, |
| 169 | POWER_DOMAIN_PIPE_C, |
| 170 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
| 171 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
| 172 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 173 | POWER_DOMAIN_TRANSCODER_A, |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 174 | POWER_DOMAIN_TRANSCODER_B, |
| 175 | POWER_DOMAIN_TRANSCODER_C, |
| 176 | POWER_DOMAIN_TRANSCODER_EDP, |
| 177 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
| 178 | POWER_DOMAIN_PORT_DDI_A_4_LANES, |
| 179 | POWER_DOMAIN_PORT_DDI_B_2_LANES, |
| 180 | POWER_DOMAIN_PORT_DDI_B_4_LANES, |
| 181 | POWER_DOMAIN_PORT_DDI_C_2_LANES, |
| 182 | POWER_DOMAIN_PORT_DDI_C_4_LANES, |
| 183 | POWER_DOMAIN_PORT_DDI_D_2_LANES, |
| 184 | POWER_DOMAIN_PORT_DDI_D_4_LANES, |
Ville Syrjälä | cdf8dd7 | 2013-09-16 17:38:30 +0300 | [diff] [blame] | 185 | POWER_DOMAIN_PORT_DSI, |
Imre Deak | fbeeaa2 | 2013-11-25 17:15:28 +0200 | [diff] [blame] | 186 | POWER_DOMAIN_PORT_CRT, |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 187 | POWER_DOMAIN_PORT_OTHER, |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 188 | POWER_DOMAIN_VGA, |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 189 | POWER_DOMAIN_AUDIO, |
| 190 | POWER_DOMAIN_PLLS, |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 191 | POWER_DOMAIN_AUX_A, |
| 192 | POWER_DOMAIN_AUX_B, |
| 193 | POWER_DOMAIN_AUX_C, |
| 194 | POWER_DOMAIN_AUX_D, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 195 | POWER_DOMAIN_INIT, |
| 196 | |
| 197 | POWER_DOMAIN_NUM, |
| 198 | }; |
| 199 | |
| 200 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
| 201 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
| 202 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 203 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
| 204 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
| 205 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 206 | |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 207 | enum hpd_pin { |
| 208 | HPD_NONE = 0, |
| 209 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
| 210 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
| 211 | HPD_CRT, |
| 212 | HPD_SDVO_B, |
| 213 | HPD_SDVO_C, |
| 214 | HPD_PORT_B, |
| 215 | HPD_PORT_C, |
| 216 | HPD_PORT_D, |
| 217 | HPD_NUM_PINS |
| 218 | }; |
| 219 | |
Chris Wilson | 2a2d548 | 2012-12-03 11:49:06 +0000 | [diff] [blame] | 220 | #define I915_GEM_GPU_DOMAINS \ |
| 221 | (I915_GEM_DOMAIN_RENDER | \ |
| 222 | I915_GEM_DOMAIN_SAMPLER | \ |
| 223 | I915_GEM_DOMAIN_COMMAND | \ |
| 224 | I915_GEM_DOMAIN_INSTRUCTION | \ |
| 225 | I915_GEM_DOMAIN_VERTEX) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 226 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 227 | #define for_each_pipe(__dev_priv, __p) \ |
| 228 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) |
Damien Lespiau | dd74078 | 2015-02-28 14:54:08 +0000 | [diff] [blame] | 229 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
| 230 | for ((__p) = 0; \ |
| 231 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ |
| 232 | (__p)++) |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 233 | #define for_each_sprite(__dev_priv, __p, __s) \ |
| 234 | for ((__s) = 0; \ |
| 235 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ |
| 236 | (__s)++) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 237 | |
Damien Lespiau | d79b814 | 2014-05-13 23:32:23 +0100 | [diff] [blame] | 238 | #define for_each_crtc(dev, crtc) \ |
| 239 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 240 | |
Damien Lespiau | d063ae4 | 2014-05-13 23:32:21 +0100 | [diff] [blame] | 241 | #define for_each_intel_crtc(dev, intel_crtc) \ |
| 242 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) |
| 243 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 244 | #define for_each_intel_encoder(dev, intel_encoder) \ |
| 245 | list_for_each_entry(intel_encoder, \ |
| 246 | &(dev)->mode_config.encoder_list, \ |
| 247 | base.head) |
| 248 | |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 249 | #define for_each_intel_connector(dev, intel_connector) \ |
| 250 | list_for_each_entry(intel_connector, \ |
| 251 | &dev->mode_config.connector_list, \ |
| 252 | base.head) |
| 253 | |
| 254 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 255 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
| 256 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
| 257 | if ((intel_encoder)->base.crtc == (__crtc)) |
| 258 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 259 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
| 260 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ |
| 261 | if ((intel_connector)->base.encoder == (__encoder)) |
| 262 | |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 263 | #define for_each_power_domain(domain, mask) \ |
| 264 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
| 265 | if ((1 << (domain)) & (mask)) |
| 266 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 267 | struct drm_i915_private; |
Chris Wilson | ad46cb5 | 2014-08-07 14:20:40 +0100 | [diff] [blame] | 268 | struct i915_mm_struct; |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 269 | struct i915_mmu_object; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 270 | |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 271 | enum intel_dpll_id { |
| 272 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
| 273 | /* real shared dpll ids must be >= 0 */ |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 274 | DPLL_ID_PCH_PLL_A = 0, |
| 275 | DPLL_ID_PCH_PLL_B = 1, |
Satheeshakrishna M | 429d47d | 2014-11-13 14:55:14 +0000 | [diff] [blame] | 276 | /* hsw/bdw */ |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 277 | DPLL_ID_WRPLL1 = 0, |
| 278 | DPLL_ID_WRPLL2 = 1, |
Satheeshakrishna M | 429d47d | 2014-11-13 14:55:14 +0000 | [diff] [blame] | 279 | /* skl */ |
| 280 | DPLL_ID_SKL_DPLL1 = 0, |
| 281 | DPLL_ID_SKL_DPLL2 = 1, |
| 282 | DPLL_ID_SKL_DPLL3 = 2, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 283 | }; |
Satheeshakrishna M | 429d47d | 2014-11-13 14:55:14 +0000 | [diff] [blame] | 284 | #define I915_NUM_PLLS 3 |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 285 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 286 | struct intel_dpll_hw_state { |
Damien Lespiau | dcfc355 | 2014-07-29 18:06:16 +0100 | [diff] [blame] | 287 | /* i9xx, pch plls */ |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 288 | uint32_t dpll; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 289 | uint32_t dpll_md; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 290 | uint32_t fp0; |
| 291 | uint32_t fp1; |
Damien Lespiau | dcfc355 | 2014-07-29 18:06:16 +0100 | [diff] [blame] | 292 | |
| 293 | /* hsw, bdw */ |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 294 | uint32_t wrpll; |
Satheeshakrishna M | d1a2dc7 | 2014-11-13 14:55:18 +0000 | [diff] [blame] | 295 | |
| 296 | /* skl */ |
| 297 | /* |
| 298 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in |
| 299 | * lower part of crtl1 and they get shifted into position when writing |
| 300 | * the register. This allows us to easily compare the state to share |
| 301 | * the DPLL. |
| 302 | */ |
| 303 | uint32_t ctrl1; |
| 304 | /* HDMI only, 0 when used for DP */ |
| 305 | uint32_t cfgcr1, cfgcr2; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 306 | }; |
| 307 | |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 308 | struct intel_shared_dpll_config { |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 309 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 310 | struct intel_dpll_hw_state hw_state; |
| 311 | }; |
| 312 | |
| 313 | struct intel_shared_dpll { |
| 314 | struct intel_shared_dpll_config config; |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 315 | struct intel_shared_dpll_config *new_config; |
| 316 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 318 | bool on; /* is the PLL actually active? Disabled during modeset */ |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 319 | const char *name; |
| 320 | /* should match the index in the dev_priv->shared_dplls array */ |
| 321 | enum intel_dpll_id id; |
Daniel Vetter | 96f6128 | 2014-06-25 22:01:58 +0300 | [diff] [blame] | 322 | /* The mode_set hook is optional and should be used together with the |
| 323 | * intel_prepare_shared_dpll function. */ |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 324 | void (*mode_set)(struct drm_i915_private *dev_priv, |
| 325 | struct intel_shared_dpll *pll); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 326 | void (*enable)(struct drm_i915_private *dev_priv, |
| 327 | struct intel_shared_dpll *pll); |
| 328 | void (*disable)(struct drm_i915_private *dev_priv, |
| 329 | struct intel_shared_dpll *pll); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 330 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 331 | struct intel_shared_dpll *pll, |
| 332 | struct intel_dpll_hw_state *hw_state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | |
Satheeshakrishna M | 429d47d | 2014-11-13 14:55:14 +0000 | [diff] [blame] | 335 | #define SKL_DPLL0 0 |
| 336 | #define SKL_DPLL1 1 |
| 337 | #define SKL_DPLL2 2 |
| 338 | #define SKL_DPLL3 3 |
| 339 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 340 | /* Used by dp and fdi links */ |
| 341 | struct intel_link_m_n { |
| 342 | uint32_t tu; |
| 343 | uint32_t gmch_m; |
| 344 | uint32_t gmch_n; |
| 345 | uint32_t link_m; |
| 346 | uint32_t link_n; |
| 347 | }; |
| 348 | |
| 349 | void intel_link_compute_m_n(int bpp, int nlanes, |
| 350 | int pixel_clock, int link_clock, |
| 351 | struct intel_link_m_n *m_n); |
| 352 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | /* Interface history: |
| 354 | * |
| 355 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 356 | * 1.2: Add Power Management |
| 357 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 358 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 359 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 360 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 361 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | */ |
| 363 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 364 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | #define DRIVER_PATCHLEVEL 0 |
| 366 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 367 | #define WATCH_LISTS 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 368 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 369 | struct opregion_header; |
| 370 | struct opregion_acpi; |
| 371 | struct opregion_swsci; |
| 372 | struct opregion_asle; |
| 373 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 374 | struct intel_opregion { |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 375 | struct opregion_header __iomem *header; |
| 376 | struct opregion_acpi __iomem *acpi; |
| 377 | struct opregion_swsci __iomem *swsci; |
Jani Nikula | ebde53c | 2013-09-02 10:38:59 +0300 | [diff] [blame] | 378 | u32 swsci_gbda_sub_functions; |
| 379 | u32 swsci_sbcb_sub_functions; |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 380 | struct opregion_asle __iomem *asle; |
| 381 | void __iomem *vbt; |
Chris Wilson | 01fe9db | 2011-01-16 19:37:30 +0000 | [diff] [blame] | 382 | u32 __iomem *lid_state; |
Jani Nikula | 91a60f2 | 2013-10-31 18:55:48 +0200 | [diff] [blame] | 383 | struct work_struct asle_work; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 384 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 385 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 386 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 387 | struct intel_overlay; |
| 388 | struct intel_overlay_error_state; |
| 389 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 390 | #define I915_FENCE_REG_NONE -1 |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 391 | #define I915_MAX_NUM_FENCES 32 |
| 392 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
| 393 | #define I915_MAX_NUM_FENCE_BITS 6 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 394 | |
| 395 | struct drm_i915_fence_reg { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 396 | struct list_head lru_list; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 397 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 398 | int pin_count; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 399 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 400 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 401 | struct sdvo_device_mapping { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 402 | u8 initialized; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 403 | u8 dvo_port; |
| 404 | u8 slave_addr; |
| 405 | u8 dvo_wiring; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 406 | u8 i2c_pin; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 407 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 408 | }; |
| 409 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 410 | struct intel_display_error_state; |
| 411 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 412 | struct drm_i915_error_state { |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 413 | struct kref ref; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 414 | struct timeval time; |
| 415 | |
Mika Kuoppala | cb38300 | 2014-02-25 17:11:25 +0200 | [diff] [blame] | 416 | char error_msg[128]; |
Mika Kuoppala | 48b031e | 2014-02-25 17:11:27 +0200 | [diff] [blame] | 417 | u32 reset_count; |
Mika Kuoppala | 62d5d69 | 2014-02-25 17:11:28 +0200 | [diff] [blame] | 418 | u32 suspend_count; |
Mika Kuoppala | cb38300 | 2014-02-25 17:11:25 +0200 | [diff] [blame] | 419 | |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 420 | /* Generic register state */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 421 | u32 eir; |
| 422 | u32 pgtbl_er; |
Ben Widawsky | be998e2 | 2012-04-26 16:03:00 -0700 | [diff] [blame] | 423 | u32 ier; |
Rodrigo Vivi | 885ea5a | 2014-08-05 10:07:13 -0700 | [diff] [blame] | 424 | u32 gtier[4]; |
Ben Widawsky | b9a3906 | 2012-06-04 14:42:52 -0700 | [diff] [blame] | 425 | u32 ccid; |
Chris Wilson | 0f3b684 | 2013-01-15 12:05:55 +0000 | [diff] [blame] | 426 | u32 derrmr; |
| 427 | u32 forcewake; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 428 | u32 error; /* gen6+ */ |
| 429 | u32 err_int; /* gen7 */ |
Mika Kuoppala | 6c826f3 | 2015-03-24 14:54:19 +0200 | [diff] [blame] | 430 | u32 fault_data0; /* gen8, gen9 */ |
| 431 | u32 fault_data1; /* gen8, gen9 */ |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 432 | u32 done_reg; |
Ben Widawsky | 91ec5d1 | 2014-01-30 00:19:39 -0800 | [diff] [blame] | 433 | u32 gac_eco; |
| 434 | u32 gam_ecochk; |
| 435 | u32 gab_ctl; |
| 436 | u32 gfx_mode; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 437 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 438 | u64 fence[I915_MAX_NUM_FENCES]; |
| 439 | struct intel_overlay_error_state *overlay; |
| 440 | struct intel_display_error_state *display; |
Ben Widawsky | 0ca36d7 | 2014-06-30 09:53:41 -0700 | [diff] [blame] | 441 | struct drm_i915_error_object *semaphore_obj; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 442 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 443 | struct drm_i915_error_ring { |
Chris Wilson | 372fbb8 | 2014-01-27 13:52:34 +0000 | [diff] [blame] | 444 | bool valid; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 445 | /* Software tracked state */ |
| 446 | bool waiting; |
| 447 | int hangcheck_score; |
| 448 | enum intel_ring_hangcheck_action hangcheck_action; |
| 449 | int num_requests; |
| 450 | |
| 451 | /* our own tracking of ring head and tail */ |
| 452 | u32 cpu_ring_head; |
| 453 | u32 cpu_ring_tail; |
| 454 | |
| 455 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; |
| 456 | |
| 457 | /* Register state */ |
| 458 | u32 tail; |
| 459 | u32 head; |
| 460 | u32 ctl; |
| 461 | u32 hws; |
| 462 | u32 ipeir; |
| 463 | u32 ipehr; |
| 464 | u32 instdone; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 465 | u32 bbstate; |
| 466 | u32 instpm; |
| 467 | u32 instps; |
| 468 | u32 seqno; |
| 469 | u64 bbaddr; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 470 | u64 acthd; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 471 | u32 fault_reg; |
Ben Widawsky | 13ffadd | 2014-04-01 16:31:07 -0700 | [diff] [blame] | 472 | u64 faddr; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 473 | u32 rc_psmi; /* sleep state */ |
| 474 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; |
| 475 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 476 | struct drm_i915_error_object { |
| 477 | int page_count; |
| 478 | u32 gtt_offset; |
| 479 | u32 *pages[0]; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 480 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 481 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 482 | struct drm_i915_error_request { |
| 483 | long jiffies; |
| 484 | u32 seqno; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 485 | u32 tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 486 | } *requests; |
Ben Widawsky | 6c7a01e | 2014-01-30 00:19:40 -0800 | [diff] [blame] | 487 | |
| 488 | struct { |
| 489 | u32 gfx_mode; |
| 490 | union { |
| 491 | u64 pdp[4]; |
| 492 | u32 pp_dir_base; |
| 493 | }; |
| 494 | } vm_info; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 495 | |
| 496 | pid_t pid; |
| 497 | char comm[TASK_COMM_LEN]; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 498 | } ring[I915_NUM_RINGS]; |
Chris Wilson | 3a44873 | 2014-08-12 20:05:47 +0100 | [diff] [blame] | 499 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 500 | struct drm_i915_error_buffer { |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 501 | u32 size; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 502 | u32 name; |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 503 | u32 rseqno, wseqno; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 504 | u32 gtt_offset; |
| 505 | u32 read_domains; |
| 506 | u32 write_domain; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 507 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 508 | s32 pinned:2; |
| 509 | u32 tiling:2; |
| 510 | u32 dirty:1; |
| 511 | u32 purgeable:1; |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 512 | u32 userptr:1; |
Daniel Vetter | 5d1333f | 2012-02-16 11:03:29 +0100 | [diff] [blame] | 513 | s32 ring:4; |
Chris Wilson | f56383c | 2013-09-25 10:23:19 +0100 | [diff] [blame] | 514 | u32 cache_level:3; |
Ben Widawsky | 95f5301 | 2013-07-31 17:00:15 -0700 | [diff] [blame] | 515 | } **active_bo, **pinned_bo; |
Ben Widawsky | 6c7a01e | 2014-01-30 00:19:40 -0800 | [diff] [blame] | 516 | |
Ben Widawsky | 95f5301 | 2013-07-31 17:00:15 -0700 | [diff] [blame] | 517 | u32 *active_bo_count, *pinned_bo_count; |
Chris Wilson | 3a44873 | 2014-08-12 20:05:47 +0100 | [diff] [blame] | 518 | u32 vm_count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 519 | }; |
| 520 | |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 521 | struct intel_connector; |
Jani Nikula | 820d2d7 | 2014-10-27 16:26:47 +0200 | [diff] [blame] | 522 | struct intel_encoder; |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 523 | struct intel_crtc_state; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 524 | struct intel_initial_plane_config; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 525 | struct intel_crtc; |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 526 | struct intel_limit; |
| 527 | struct dpll; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 528 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 529 | struct drm_i915_display_funcs { |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 530 | bool (*fbc_enabled)(struct drm_device *dev); |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 531 | void (*enable_fbc)(struct drm_crtc *crtc); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 532 | void (*disable_fbc)(struct drm_device *dev); |
| 533 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 534 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 535 | /** |
| 536 | * find_dpll() - Find the best values for the PLL |
| 537 | * @limit: limits for the PLL |
| 538 | * @crtc: current CRTC |
| 539 | * @target: target frequency in kHz |
| 540 | * @refclk: reference clock frequency in kHz |
| 541 | * @match_clock: if provided, @best_clock P divider must |
| 542 | * match the P divider from @match_clock |
| 543 | * used for LVDS downclocking |
| 544 | * @best_clock: best PLL values found |
| 545 | * |
| 546 | * Returns true on success, false on failure. |
| 547 | */ |
| 548 | bool (*find_dpll)(const struct intel_limit *limit, |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 549 | struct intel_crtc_state *crtc_state, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 550 | int target, int refclk, |
| 551 | struct dpll *match_clock, |
| 552 | struct dpll *best_clock); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 553 | void (*update_wm)(struct drm_crtc *crtc); |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 554 | void (*update_sprite_wm)(struct drm_plane *plane, |
| 555 | struct drm_crtc *crtc, |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 556 | uint32_t sprite_width, uint32_t sprite_height, |
| 557 | int pixel_size, bool enable, bool scaled); |
Ander Conselvan de Oliveira | 679dacd | 2015-03-20 16:18:15 +0200 | [diff] [blame] | 558 | void (*modeset_global_resources)(struct drm_atomic_state *state); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 559 | /* Returns the active state of the crtc, and if the crtc is active, |
| 560 | * fills out the pipe-config with the hw state. */ |
| 561 | bool (*get_pipe_config)(struct intel_crtc *, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 562 | struct intel_crtc_state *); |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 563 | void (*get_initial_plane_config)(struct intel_crtc *, |
| 564 | struct intel_initial_plane_config *); |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 565 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
| 566 | struct intel_crtc_state *crtc_state); |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 567 | void (*crtc_enable)(struct drm_crtc *crtc); |
| 568 | void (*crtc_disable)(struct drm_crtc *crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 569 | void (*off)(struct drm_crtc *crtc); |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 570 | void (*audio_codec_enable)(struct drm_connector *connector, |
| 571 | struct intel_encoder *encoder, |
| 572 | struct drm_display_mode *mode); |
| 573 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 574 | void (*fdi_link_train)(struct drm_crtc *crtc); |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 575 | void (*init_clock_gating)(struct drm_device *dev); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 576 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
| 577 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 578 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 579 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 580 | uint32_t flags); |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 581 | void (*update_primary_plane)(struct drm_crtc *crtc, |
| 582 | struct drm_framebuffer *fb, |
| 583 | int x, int y); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 584 | void (*hpd_irq_setup)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 585 | /* clock updates for mode set */ |
| 586 | /* cursor updates */ |
| 587 | /* render clock increase/decrease */ |
| 588 | /* display clock increase/decrease */ |
| 589 | /* pll clock increase/decrease */ |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 590 | |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 591 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 592 | uint32_t (*get_backlight)(struct intel_connector *connector); |
| 593 | void (*set_backlight)(struct intel_connector *connector, |
| 594 | uint32_t level); |
| 595 | void (*disable_backlight)(struct intel_connector *connector); |
| 596 | void (*enable_backlight)(struct intel_connector *connector); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 597 | }; |
| 598 | |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 599 | enum forcewake_domain_id { |
| 600 | FW_DOMAIN_ID_RENDER = 0, |
| 601 | FW_DOMAIN_ID_BLITTER, |
| 602 | FW_DOMAIN_ID_MEDIA, |
| 603 | |
| 604 | FW_DOMAIN_ID_COUNT |
| 605 | }; |
| 606 | |
| 607 | enum forcewake_domains { |
| 608 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), |
| 609 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), |
| 610 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), |
| 611 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | |
| 612 | FORCEWAKE_BLITTER | |
| 613 | FORCEWAKE_MEDIA) |
| 614 | }; |
| 615 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 616 | struct intel_uncore_funcs { |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 617 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 618 | enum forcewake_domains domains); |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 619 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 620 | enum forcewake_domains domains); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 621 | |
| 622 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 623 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 624 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 625 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 626 | |
| 627 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
| 628 | uint8_t val, bool trace); |
| 629 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
| 630 | uint16_t val, bool trace); |
| 631 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
| 632 | uint32_t val, bool trace); |
| 633 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
| 634 | uint64_t val, bool trace); |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 635 | }; |
| 636 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 637 | struct intel_uncore { |
| 638 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
| 639 | |
| 640 | struct intel_uncore_funcs funcs; |
| 641 | |
| 642 | unsigned fifo_count; |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 643 | enum forcewake_domains fw_domains; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 644 | |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 645 | struct intel_uncore_forcewake_domain { |
| 646 | struct drm_i915_private *i915; |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 647 | enum forcewake_domain_id id; |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 648 | unsigned wake_count; |
| 649 | struct timer_list timer; |
Mika Kuoppala | 05a2fb1 | 2015-01-19 16:20:43 +0200 | [diff] [blame] | 650 | u32 reg_set; |
| 651 | u32 val_set; |
| 652 | u32 val_clear; |
| 653 | u32 reg_ack; |
| 654 | u32 reg_post; |
| 655 | u32 val_reset; |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 656 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 657 | }; |
| 658 | |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 659 | /* Iterate over initialised fw domains */ |
| 660 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ |
| 661 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ |
| 662 | (i__) < FW_DOMAIN_ID_COUNT; \ |
| 663 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ |
| 664 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
| 665 | |
| 666 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ |
| 667 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) |
| 668 | |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 669 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
| 670 | func(is_mobile) sep \ |
| 671 | func(is_i85x) sep \ |
| 672 | func(is_i915g) sep \ |
| 673 | func(is_i945gm) sep \ |
| 674 | func(is_g33) sep \ |
| 675 | func(need_gfx_hws) sep \ |
| 676 | func(is_g4x) sep \ |
| 677 | func(is_pineview) sep \ |
| 678 | func(is_broadwater) sep \ |
| 679 | func(is_crestline) sep \ |
| 680 | func(is_ivybridge) sep \ |
| 681 | func(is_valleyview) sep \ |
| 682 | func(is_haswell) sep \ |
Satheeshakrishna M | 7201c0b | 2014-04-02 11:24:50 +0530 | [diff] [blame] | 683 | func(is_skylake) sep \ |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 684 | func(is_preliminary) sep \ |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 685 | func(has_fbc) sep \ |
| 686 | func(has_pipe_cxsr) sep \ |
| 687 | func(has_hotplug) sep \ |
| 688 | func(cursor_needs_physical) sep \ |
| 689 | func(has_overlay) sep \ |
| 690 | func(overlay_needs_physical) sep \ |
| 691 | func(supports_tv) sep \ |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 692 | func(has_llc) sep \ |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 693 | func(has_ddi) sep \ |
| 694 | func(has_fpga_dbg) |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 695 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 696 | #define DEFINE_FLAG(name) u8 name:1 |
| 697 | #define SEP_SEMICOLON ; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 698 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 699 | struct intel_device_info { |
Ville Syrjälä | 10fce67 | 2013-01-24 15:29:28 +0200 | [diff] [blame] | 700 | u32 display_mmio_offset; |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 701 | u16 device_id; |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 702 | u8 num_pipes:3; |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 703 | u8 num_sprites[I915_MAX_PIPES]; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 704 | u8 gen; |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 705 | u8 ring_mask; /* Rings supported by the HW */ |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 706 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 707 | /* Register offsets for the various display pipes and transcoders */ |
| 708 | int pipe_offsets[I915_MAX_TRANSCODERS]; |
| 709 | int trans_offsets[I915_MAX_TRANSCODERS]; |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 710 | int palette_offsets[I915_MAX_PIPES]; |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 711 | int cursor_offsets[I915_MAX_PIPES]; |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 712 | |
| 713 | /* Slice/subslice/EU info */ |
| 714 | u8 slice_total; |
| 715 | u8 subslice_total; |
| 716 | u8 subslice_per_slice; |
| 717 | u8 eu_total; |
| 718 | u8 eu_per_subslice; |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 719 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
| 720 | u8 subslice_7eu[3]; |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 721 | u8 has_slice_pg:1; |
| 722 | u8 has_subslice_pg:1; |
| 723 | u8 has_eu_pg:1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 724 | }; |
| 725 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 726 | #undef DEFINE_FLAG |
| 727 | #undef SEP_SEMICOLON |
| 728 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 729 | enum i915_cache_level { |
| 730 | I915_CACHE_NONE = 0, |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 731 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
| 732 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
| 733 | caches, eg sampler/render caches, and the |
| 734 | large Last-Level-Cache. LLC is coherent with |
| 735 | the CPU, but L3 is only visible to the GPU. */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 736 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 737 | }; |
| 738 | |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 739 | struct i915_ctx_hang_stats { |
| 740 | /* This context had batch pending when hang was declared */ |
| 741 | unsigned batch_pending; |
| 742 | |
| 743 | /* This context had batch active when hang was declared */ |
| 744 | unsigned batch_active; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 745 | |
| 746 | /* Time when this context was last blamed for a GPU reset */ |
| 747 | unsigned long guilty_ts; |
| 748 | |
Chris Wilson | 676fa57 | 2014-12-24 08:13:39 -0800 | [diff] [blame] | 749 | /* If the contexts causes a second GPU hang within this time, |
| 750 | * it is permanently banned from submitting any more work. |
| 751 | */ |
| 752 | unsigned long ban_period_seconds; |
| 753 | |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 754 | /* This context is banned to submit more work */ |
| 755 | bool banned; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 756 | }; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 757 | |
| 758 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 759 | #define DEFAULT_CONTEXT_HANDLE 0 |
Oscar Mateo | 31b7a88 | 2014-07-03 16:28:01 +0100 | [diff] [blame] | 760 | /** |
| 761 | * struct intel_context - as the name implies, represents a context. |
| 762 | * @ref: reference count. |
| 763 | * @user_handle: userspace tracking identity for this context. |
| 764 | * @remap_slice: l3 row remapping information. |
| 765 | * @file_priv: filp associated with this context (NULL for global default |
| 766 | * context). |
| 767 | * @hang_stats: information about the role of this context in possible GPU |
| 768 | * hangs. |
| 769 | * @vm: virtual memory space used by this context. |
| 770 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
| 771 | * initialized (legacy ring submission mechanism only). |
| 772 | * @link: link in the global list of contexts. |
| 773 | * |
| 774 | * Contexts are memory images used by the hardware to store copies of their |
| 775 | * internal state. |
| 776 | */ |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 777 | struct intel_context { |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 778 | struct kref ref; |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 779 | int user_handle; |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 780 | uint8_t remap_slice; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 781 | struct drm_i915_file_private *file_priv; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 782 | struct i915_ctx_hang_stats hang_stats; |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 783 | struct i915_hw_ppgtt *ppgtt; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 784 | |
Oscar Mateo | c9e003a | 2014-07-24 17:04:13 +0100 | [diff] [blame] | 785 | /* Legacy ring buffer submission */ |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 786 | struct { |
| 787 | struct drm_i915_gem_object *rcs_state; |
| 788 | bool initialized; |
| 789 | } legacy_hw_ctx; |
| 790 | |
Oscar Mateo | c9e003a | 2014-07-24 17:04:13 +0100 | [diff] [blame] | 791 | /* Execlists */ |
Oscar Mateo | 564ddb2 | 2014-08-21 11:40:54 +0100 | [diff] [blame] | 792 | bool rcs_initialized; |
Oscar Mateo | c9e003a | 2014-07-24 17:04:13 +0100 | [diff] [blame] | 793 | struct { |
| 794 | struct drm_i915_gem_object *state; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 795 | struct intel_ringbuffer *ringbuf; |
Mika Kuoppala | a7cbede | 2015-01-13 11:32:25 +0200 | [diff] [blame] | 796 | int pin_count; |
Oscar Mateo | c9e003a | 2014-07-24 17:04:13 +0100 | [diff] [blame] | 797 | } engine[I915_NUM_RINGS]; |
| 798 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 799 | struct list_head link; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 800 | }; |
| 801 | |
Paulo Zanoni | a4001f1 | 2015-02-13 17:23:44 -0200 | [diff] [blame] | 802 | enum fb_op_origin { |
| 803 | ORIGIN_GTT, |
| 804 | ORIGIN_CPU, |
| 805 | ORIGIN_CS, |
| 806 | ORIGIN_FLIP, |
| 807 | }; |
| 808 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 809 | struct i915_fbc { |
Jani Nikula | 60ee5cd | 2015-02-05 12:04:27 +0200 | [diff] [blame] | 810 | unsigned long uncompressed_size; |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 811 | unsigned threshold; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 812 | unsigned int fb_id; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 813 | unsigned int possible_framebuffer_bits; |
| 814 | unsigned int busy_bits; |
Paulo Zanoni | e35fef2 | 2015-02-09 14:46:29 -0200 | [diff] [blame] | 815 | struct intel_crtc *crtc; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 816 | int y; |
| 817 | |
Ben Widawsky | c421388 | 2014-06-19 12:06:10 -0700 | [diff] [blame] | 818 | struct drm_mm_node compressed_fb; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 819 | struct drm_mm_node *compressed_llb; |
| 820 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 821 | bool false_color; |
| 822 | |
Paulo Zanoni | 9adccc6 | 2014-09-19 16:04:55 -0300 | [diff] [blame] | 823 | /* Tracks whether the HW is actually enabled, not whether the feature is |
| 824 | * possible. */ |
| 825 | bool enabled; |
| 826 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 827 | struct intel_fbc_work { |
| 828 | struct delayed_work work; |
| 829 | struct drm_crtc *crtc; |
| 830 | struct drm_framebuffer *fb; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 831 | } *fbc_work; |
| 832 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 833 | enum no_fbc_reason { |
| 834 | FBC_OK, /* FBC is enabled */ |
| 835 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 836 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
| 837 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
| 838 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 839 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 840 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 841 | FBC_NOT_TILED, /* buffer not tiled */ |
| 842 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
| 843 | FBC_MODULE_PARAM, |
| 844 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
| 845 | } no_fbc_reason; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 846 | }; |
| 847 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 848 | /** |
| 849 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
| 850 | * LOW_RR is the lowest eDP panel refresh rate found from EDID |
| 851 | * parsing for same resolution. |
| 852 | */ |
| 853 | enum drrs_refresh_rate_type { |
| 854 | DRRS_HIGH_RR, |
| 855 | DRRS_LOW_RR, |
| 856 | DRRS_MAX_RR, /* RR count */ |
| 857 | }; |
| 858 | |
| 859 | enum drrs_support_type { |
| 860 | DRRS_NOT_SUPPORTED = 0, |
| 861 | STATIC_DRRS_SUPPORT = 1, |
| 862 | SEAMLESS_DRRS_SUPPORT = 2 |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 863 | }; |
| 864 | |
Daniel Vetter | 2807cf6 | 2014-07-11 10:30:11 -0700 | [diff] [blame] | 865 | struct intel_dp; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 866 | struct i915_drrs { |
| 867 | struct mutex mutex; |
| 868 | struct delayed_work work; |
| 869 | struct intel_dp *dp; |
| 870 | unsigned busy_frontbuffer_bits; |
| 871 | enum drrs_refresh_rate_type refresh_rate_type; |
| 872 | enum drrs_support_type type; |
| 873 | }; |
| 874 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 875 | struct i915_psr { |
Daniel Vetter | f0355c4 | 2014-07-11 10:30:15 -0700 | [diff] [blame] | 876 | struct mutex lock; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 877 | bool sink_support; |
| 878 | bool source_ok; |
Daniel Vetter | 2807cf6 | 2014-07-11 10:30:11 -0700 | [diff] [blame] | 879 | struct intel_dp *enabled; |
Rodrigo Vivi | 7c8f8a7 | 2014-06-13 05:10:03 -0700 | [diff] [blame] | 880 | bool active; |
| 881 | struct delayed_work work; |
Daniel Vetter | 9ca1530 | 2014-07-11 10:30:16 -0700 | [diff] [blame] | 882 | unsigned busy_frontbuffer_bits; |
Rodrigo Vivi | 0243f7b | 2015-01-12 10:14:32 -0800 | [diff] [blame] | 883 | bool link_standby; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 884 | }; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 885 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 886 | enum intel_pch { |
Paulo Zanoni | f035083 | 2012-07-03 18:48:16 -0300 | [diff] [blame] | 887 | PCH_NONE = 0, /* No PCH present */ |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 888 | PCH_IBX, /* Ibexpeak PCH */ |
| 889 | PCH_CPT, /* Cougarpoint PCH */ |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 890 | PCH_LPT, /* Lynxpoint PCH */ |
Satheeshakrishna M | e7e7ea2 | 2014-04-09 11:08:57 +0530 | [diff] [blame] | 891 | PCH_SPT, /* Sunrisepoint PCH */ |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 892 | PCH_NOP, |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 893 | }; |
| 894 | |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 895 | enum intel_sbi_destination { |
| 896 | SBI_ICLK, |
| 897 | SBI_MPHY, |
| 898 | }; |
| 899 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 900 | #define QUIRK_PIPEA_FORCE (1<<0) |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 901 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 902 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
Scot Doyle | 9c72cc6 | 2014-07-03 23:27:50 +0000 | [diff] [blame] | 903 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 904 | #define QUIRK_PIPEB_FORCE (1<<4) |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 905 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 906 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 907 | struct intel_fbdev; |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 908 | struct intel_fbc_work; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 909 | |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 910 | struct intel_gmbus { |
| 911 | struct i2c_adapter adapter; |
Chris Wilson | f2ce9fa | 2012-11-10 15:58:21 +0000 | [diff] [blame] | 912 | u32 force_bit; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 913 | u32 reg0; |
Daniel Vetter | 36c785f | 2012-02-14 22:37:22 +0100 | [diff] [blame] | 914 | u32 gpio_reg; |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 915 | struct i2c_algo_bit_data bit_algo; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 916 | struct drm_i915_private *dev_priv; |
| 917 | }; |
| 918 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 919 | struct i915_suspend_saved_registers { |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 920 | u32 saveDSPARB; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 921 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 922 | u32 savePP_ON_DELAYS; |
| 923 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 924 | u32 savePP_ON; |
| 925 | u32 savePP_OFF; |
| 926 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 927 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 928 | u32 saveFBC_CONTROL; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 929 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 930 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 931 | u32 saveSWF0[16]; |
| 932 | u32 saveSWF1[16]; |
| 933 | u32 saveSWF2[3]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 934 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 935 | u32 savePCH_PORT_HOTPLUG; |
Jesse Barnes | 9f49c37 | 2014-12-10 12:16:05 -0800 | [diff] [blame] | 936 | u16 saveGCDGMBUS; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 937 | }; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 938 | |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 939 | struct vlv_s0ix_state { |
| 940 | /* GAM */ |
| 941 | u32 wr_watermark; |
| 942 | u32 gfx_prio_ctrl; |
| 943 | u32 arb_mode; |
| 944 | u32 gfx_pend_tlb0; |
| 945 | u32 gfx_pend_tlb1; |
| 946 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; |
| 947 | u32 media_max_req_count; |
| 948 | u32 gfx_max_req_count; |
| 949 | u32 render_hwsp; |
| 950 | u32 ecochk; |
| 951 | u32 bsd_hwsp; |
| 952 | u32 blt_hwsp; |
| 953 | u32 tlb_rd_addr; |
| 954 | |
| 955 | /* MBC */ |
| 956 | u32 g3dctl; |
| 957 | u32 gsckgctl; |
| 958 | u32 mbctl; |
| 959 | |
| 960 | /* GCP */ |
| 961 | u32 ucgctl1; |
| 962 | u32 ucgctl3; |
| 963 | u32 rcgctl1; |
| 964 | u32 rcgctl2; |
| 965 | u32 rstctl; |
| 966 | u32 misccpctl; |
| 967 | |
| 968 | /* GPM */ |
| 969 | u32 gfxpause; |
| 970 | u32 rpdeuhwtc; |
| 971 | u32 rpdeuc; |
| 972 | u32 ecobus; |
| 973 | u32 pwrdwnupctl; |
| 974 | u32 rp_down_timeout; |
| 975 | u32 rp_deucsw; |
| 976 | u32 rcubmabdtmr; |
| 977 | u32 rcedata; |
| 978 | u32 spare2gh; |
| 979 | |
| 980 | /* Display 1 CZ domain */ |
| 981 | u32 gt_imr; |
| 982 | u32 gt_ier; |
| 983 | u32 pm_imr; |
| 984 | u32 pm_ier; |
| 985 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; |
| 986 | |
| 987 | /* GT SA CZ domain */ |
| 988 | u32 tilectl; |
| 989 | u32 gt_fifoctl; |
| 990 | u32 gtlc_wake_ctrl; |
| 991 | u32 gtlc_survive; |
| 992 | u32 pmwgicz; |
| 993 | |
| 994 | /* Display 2 CZ domain */ |
| 995 | u32 gu_ctl0; |
| 996 | u32 gu_ctl1; |
| 997 | u32 clock_gate_dis2; |
| 998 | }; |
| 999 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1000 | struct intel_rps_ei { |
| 1001 | u32 cz_clock; |
| 1002 | u32 render_c0; |
| 1003 | u32 media_c0; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1004 | }; |
| 1005 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1006 | struct intel_gen6_power_mgmt { |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 1007 | /* |
| 1008 | * work, interrupts_enabled and pm_iir are protected by |
| 1009 | * dev_priv->irq_lock |
| 1010 | */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1011 | struct work_struct work; |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 1012 | bool interrupts_enabled; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1013 | u32 pm_iir; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1014 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1015 | /* Frequencies are stored in potentially platform dependent multiples. |
| 1016 | * In other words, *_freq needs to be multiplied by X to be interesting. |
| 1017 | * Soft limits are those which are used for the dynamic reclocking done |
| 1018 | * by the driver (raise frequencies under heavy loads, and lower for |
| 1019 | * lighter loads). Hard limits are those imposed by the hardware. |
| 1020 | * |
| 1021 | * A distinction is made for overclocking, which is never enabled by |
| 1022 | * default, and is considered to be above the hard limit if it's |
| 1023 | * possible at all. |
| 1024 | */ |
| 1025 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ |
| 1026 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ |
| 1027 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ |
| 1028 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ |
| 1029 | u8 min_freq; /* AKA RPn. Minimum frequency */ |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 1030 | u8 idle_freq; /* Frequency to request when we are idle */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1031 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
| 1032 | u8 rp1_freq; /* "less than" RP0 power/freqency */ |
| 1033 | u8 rp0_freq; /* Non-overclocked max frequency. */ |
Deepak S | 67c3bf6 | 2014-07-10 13:16:24 +0530 | [diff] [blame] | 1034 | u32 cz_freq; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 1035 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1036 | int last_adj; |
| 1037 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
| 1038 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 1039 | bool enabled; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 1040 | struct delayed_work delayed_resume_work; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1041 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1042 | /* manual wa residency calculations */ |
| 1043 | struct intel_rps_ei up_ei, down_ei; |
| 1044 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1045 | /* |
| 1046 | * Protects RPS/RC6 register access and PCU communication. |
| 1047 | * Must be taken after struct_mutex if nested. |
| 1048 | */ |
| 1049 | struct mutex hw_lock; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1050 | }; |
| 1051 | |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1052 | /* defined intel_pm.c */ |
| 1053 | extern spinlock_t mchdev_lock; |
| 1054 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1055 | struct intel_ilk_power_mgmt { |
| 1056 | u8 cur_delay; |
| 1057 | u8 min_delay; |
| 1058 | u8 max_delay; |
| 1059 | u8 fmax; |
| 1060 | u8 fstart; |
| 1061 | |
| 1062 | u64 last_count1; |
| 1063 | unsigned long last_time1; |
| 1064 | unsigned long chipset_power; |
| 1065 | u64 last_count2; |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1066 | u64 last_time2; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1067 | unsigned long gfx_power; |
| 1068 | u8 corr; |
| 1069 | |
| 1070 | int c_m; |
| 1071 | int r_t; |
| 1072 | }; |
| 1073 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 1074 | struct drm_i915_private; |
| 1075 | struct i915_power_well; |
| 1076 | |
| 1077 | struct i915_power_well_ops { |
| 1078 | /* |
| 1079 | * Synchronize the well's hw state to match the current sw state, for |
| 1080 | * example enable/disable it based on the current refcount. Called |
| 1081 | * during driver init and resume time, possibly after first calling |
| 1082 | * the enable/disable handlers. |
| 1083 | */ |
| 1084 | void (*sync_hw)(struct drm_i915_private *dev_priv, |
| 1085 | struct i915_power_well *power_well); |
| 1086 | /* |
| 1087 | * Enable the well and resources that depend on it (for example |
| 1088 | * interrupts located on the well). Called after the 0->1 refcount |
| 1089 | * transition. |
| 1090 | */ |
| 1091 | void (*enable)(struct drm_i915_private *dev_priv, |
| 1092 | struct i915_power_well *power_well); |
| 1093 | /* |
| 1094 | * Disable the well and resources that depend on it. Called after |
| 1095 | * the 1->0 refcount transition. |
| 1096 | */ |
| 1097 | void (*disable)(struct drm_i915_private *dev_priv, |
| 1098 | struct i915_power_well *power_well); |
| 1099 | /* Returns the hw enabled state. */ |
| 1100 | bool (*is_enabled)(struct drm_i915_private *dev_priv, |
| 1101 | struct i915_power_well *power_well); |
| 1102 | }; |
| 1103 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1104 | /* Power well structure for haswell */ |
| 1105 | struct i915_power_well { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1106 | const char *name; |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 1107 | bool always_on; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1108 | /* power well enable/disable usage count */ |
| 1109 | int count; |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 1110 | /* cached hw enabled state */ |
| 1111 | bool hw_enabled; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1112 | unsigned long domains; |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 1113 | unsigned long data; |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 1114 | const struct i915_power_well_ops *ops; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1115 | }; |
| 1116 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1117 | struct i915_power_domains { |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 1118 | /* |
| 1119 | * Power wells needed for initialization at driver init and suspend |
| 1120 | * time are on. They are kept on until after the first modeset. |
| 1121 | */ |
| 1122 | bool init_power_on; |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 1123 | bool initializing; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1124 | int power_well_count; |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 1125 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1126 | struct mutex lock; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 1127 | int domain_use_count[POWER_DOMAIN_NUM]; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1128 | struct i915_power_well *power_wells; |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1129 | }; |
| 1130 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1131 | #define MAX_L3_SLICES 2 |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1132 | struct intel_l3_parity { |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1133 | u32 *remap_info[MAX_L3_SLICES]; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1134 | struct work_struct error_work; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1135 | int which_slice; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1136 | }; |
| 1137 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 1138 | struct i915_gem_batch_pool { |
| 1139 | struct drm_device *dev; |
| 1140 | struct list_head cache_list; |
| 1141 | }; |
| 1142 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1143 | struct i915_gem_mm { |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1144 | /** Memory allocator for GTT stolen memory */ |
| 1145 | struct drm_mm stolen; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1146 | /** List of all objects in gtt_space. Used to restore gtt |
| 1147 | * mappings on resume */ |
| 1148 | struct list_head bound_list; |
| 1149 | /** |
| 1150 | * List of objects which are not bound to the GTT (thus |
| 1151 | * are idle and not used by the GPU) but still have |
| 1152 | * (presumably uncached) pages still attached. |
| 1153 | */ |
| 1154 | struct list_head unbound_list; |
| 1155 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 1156 | /* |
| 1157 | * A pool of objects to use as shadow copies of client batch buffers |
| 1158 | * when the command parser is enabled. Prevents the client from |
| 1159 | * modifying the batch contents after software parsing. |
| 1160 | */ |
| 1161 | struct i915_gem_batch_pool batch_pool; |
| 1162 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1163 | /** Usable portion of the GTT for GEM */ |
| 1164 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
| 1165 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1166 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
| 1167 | struct i915_hw_ppgtt *aliasing_ppgtt; |
| 1168 | |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 1169 | struct notifier_block oom_notifier; |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 1170 | struct shrinker shrinker; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1171 | bool shrinker_no_lock_stealing; |
| 1172 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1173 | /** LRU list of objects with fence regs on them. */ |
| 1174 | struct list_head fence_list; |
| 1175 | |
| 1176 | /** |
| 1177 | * We leave the user IRQ off as much as possible, |
| 1178 | * but this means that requests will finish and never |
| 1179 | * be retired once the system goes idle. Set a timer to |
| 1180 | * fire periodically while the ring is running. When it |
| 1181 | * fires, go retire requests. |
| 1182 | */ |
| 1183 | struct delayed_work retire_work; |
| 1184 | |
| 1185 | /** |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1186 | * When we detect an idle GPU, we want to turn on |
| 1187 | * powersaving features. So once we see that there |
| 1188 | * are no more requests outstanding and no more |
| 1189 | * arrive within a small period of time, we fire |
| 1190 | * off the idle_work. |
| 1191 | */ |
| 1192 | struct delayed_work idle_work; |
| 1193 | |
| 1194 | /** |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1195 | * Are we in a non-interruptible section of code like |
| 1196 | * modesetting? |
| 1197 | */ |
| 1198 | bool interruptible; |
| 1199 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 1200 | /** |
| 1201 | * Is the GPU currently considered idle, or busy executing userspace |
| 1202 | * requests? Whilst idle, we attempt to power down the hardware and |
| 1203 | * display clocks. In order to reduce the effect on performance, there |
| 1204 | * is a slight delay before we do so. |
| 1205 | */ |
| 1206 | bool busy; |
| 1207 | |
Daniel Vetter | bdf1e7e | 2014-05-21 17:37:52 +0200 | [diff] [blame] | 1208 | /* the indicator for dispatch video commands on two BSD rings */ |
| 1209 | int bsd_ring_dispatch_index; |
| 1210 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1211 | /** Bit 6 swizzling required for X tiling */ |
| 1212 | uint32_t bit_6_swizzle_x; |
| 1213 | /** Bit 6 swizzling required for Y tiling */ |
| 1214 | uint32_t bit_6_swizzle_y; |
| 1215 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1216 | /* accounting, useful for userland debugging */ |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 1217 | spinlock_t object_stat_lock; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1218 | size_t object_memory; |
| 1219 | u32 object_count; |
| 1220 | }; |
| 1221 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1222 | struct drm_i915_error_state_buf { |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 1223 | struct drm_i915_private *i915; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1224 | unsigned bytes; |
| 1225 | unsigned size; |
| 1226 | int err; |
| 1227 | u8 *buf; |
| 1228 | loff_t start; |
| 1229 | loff_t pos; |
| 1230 | }; |
| 1231 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 1232 | struct i915_error_state_file_priv { |
| 1233 | struct drm_device *dev; |
| 1234 | struct drm_i915_error_state *error; |
| 1235 | }; |
| 1236 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1237 | struct i915_gpu_error { |
| 1238 | /* For hangcheck timer */ |
| 1239 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
| 1240 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 1241 | /* Hang gpu twice in this window and your context gets banned */ |
| 1242 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
| 1243 | |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 1244 | struct workqueue_struct *hangcheck_wq; |
| 1245 | struct delayed_work hangcheck_work; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1246 | |
| 1247 | /* For reset and error_state handling. */ |
| 1248 | spinlock_t lock; |
| 1249 | /* Protected by the above dev->gpu_error.lock. */ |
| 1250 | struct drm_i915_error_state *first_error; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1251 | |
| 1252 | unsigned long missed_irq_rings; |
| 1253 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1254 | /** |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1255 | * State variable controlling the reset flow and count |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1256 | * |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1257 | * This is a counter which gets incremented when reset is triggered, |
| 1258 | * and again when reset has been handled. So odd values (lowest bit set) |
| 1259 | * means that reset is in progress and even values that |
| 1260 | * (reset_counter >> 1):th reset was successfully completed. |
| 1261 | * |
| 1262 | * If reset is not completed succesfully, the I915_WEDGE bit is |
| 1263 | * set meaning that hardware is terminally sour and there is no |
| 1264 | * recovery. All waiters on the reset_queue will be woken when |
| 1265 | * that happens. |
| 1266 | * |
| 1267 | * This counter is used by the wait_seqno code to notice that reset |
| 1268 | * event happened and it needs to restart the entire ioctl (since most |
| 1269 | * likely the seqno it waited for won't ever signal anytime soon). |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1270 | * |
| 1271 | * This is important for lock-free wait paths, where no contended lock |
| 1272 | * naturally enforces the correct ordering between the bail-out of the |
| 1273 | * waiter and the gpu reset work code. |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1274 | */ |
| 1275 | atomic_t reset_counter; |
| 1276 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1277 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1278 | #define I915_WEDGED (1 << 31) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1279 | |
| 1280 | /** |
| 1281 | * Waitqueue to signal when the reset has completed. Used by clients |
| 1282 | * that wait for dev_priv->mm.wedged to settle. |
| 1283 | */ |
| 1284 | wait_queue_head_t reset_queue; |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1285 | |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 1286 | /* Userspace knobs for gpu hang simulation; |
| 1287 | * combines both a ring mask, and extra flags |
| 1288 | */ |
| 1289 | u32 stop_rings; |
| 1290 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) |
| 1291 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1292 | |
| 1293 | /* For missed irq/seqno simulation. */ |
| 1294 | unsigned int test_irq_rings; |
McAulay, Alistair | 6689c16 | 2014-08-15 18:51:35 +0100 | [diff] [blame] | 1295 | |
| 1296 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
| 1297 | bool reload_in_reset; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1298 | }; |
| 1299 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1300 | enum modeset_restore { |
| 1301 | MODESET_ON_LID_OPEN, |
| 1302 | MODESET_DONE, |
| 1303 | MODESET_SUSPENDED, |
| 1304 | }; |
| 1305 | |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1306 | struct ddi_vbt_port_info { |
Damien Lespiau | ce4dd49 | 2014-08-01 11:07:54 +0100 | [diff] [blame] | 1307 | /* |
| 1308 | * This is an index in the HDMI/DVI DDI buffer translation table. |
| 1309 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't |
| 1310 | * populate this field. |
| 1311 | */ |
| 1312 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1313 | uint8_t hdmi_level_shift; |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 1314 | |
| 1315 | uint8_t supports_dvi:1; |
| 1316 | uint8_t supports_hdmi:1; |
| 1317 | uint8_t supports_dp:1; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1318 | }; |
| 1319 | |
Rodrigo Vivi | bfd7ebd | 2014-11-14 08:52:30 -0800 | [diff] [blame] | 1320 | enum psr_lines_to_wait { |
| 1321 | PSR_0_LINES_TO_WAIT = 0, |
| 1322 | PSR_1_LINE_TO_WAIT, |
| 1323 | PSR_4_LINES_TO_WAIT, |
| 1324 | PSR_8_LINES_TO_WAIT |
Pradeep Bhat | 83a7280 | 2014-03-28 10:14:57 +0530 | [diff] [blame] | 1325 | }; |
| 1326 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1327 | struct intel_vbt_data { |
| 1328 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 1329 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
| 1330 | |
| 1331 | /* Feature bits */ |
| 1332 | unsigned int int_tv_support:1; |
| 1333 | unsigned int lvds_dither:1; |
| 1334 | unsigned int lvds_vbt:1; |
| 1335 | unsigned int int_crt_support:1; |
| 1336 | unsigned int lvds_use_ssc:1; |
| 1337 | unsigned int display_clock_mode:1; |
| 1338 | unsigned int fdi_rx_polarity_inverted:1; |
Shobhit Kumar | 3e6bd01 | 2014-05-27 19:33:59 +0530 | [diff] [blame] | 1339 | unsigned int has_mipi:1; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1340 | int lvds_ssc_freq; |
| 1341 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
| 1342 | |
Pradeep Bhat | 83a7280 | 2014-03-28 10:14:57 +0530 | [diff] [blame] | 1343 | enum drrs_support_type drrs_type; |
| 1344 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1345 | /* eDP */ |
| 1346 | int edp_rate; |
| 1347 | int edp_lanes; |
| 1348 | int edp_preemphasis; |
| 1349 | int edp_vswing; |
| 1350 | bool edp_initialized; |
| 1351 | bool edp_support; |
| 1352 | int edp_bpp; |
Sonika Jindal | 9a57f5b | 2015-02-25 10:29:11 +0530 | [diff] [blame] | 1353 | bool edp_low_vswing; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1354 | struct edp_power_seq edp_pps; |
| 1355 | |
Jani Nikula | f00076d | 2013-12-14 20:38:29 -0200 | [diff] [blame] | 1356 | struct { |
Rodrigo Vivi | bfd7ebd | 2014-11-14 08:52:30 -0800 | [diff] [blame] | 1357 | bool full_link; |
| 1358 | bool require_aux_wakeup; |
| 1359 | int idle_frames; |
| 1360 | enum psr_lines_to_wait lines_to_wait; |
| 1361 | int tp1_wakeup_time; |
| 1362 | int tp2_tp3_wakeup_time; |
| 1363 | } psr; |
| 1364 | |
| 1365 | struct { |
Jani Nikula | f00076d | 2013-12-14 20:38:29 -0200 | [diff] [blame] | 1366 | u16 pwm_freq_hz; |
Jani Nikula | 39fbc9c | 2014-04-09 11:22:06 +0300 | [diff] [blame] | 1367 | bool present; |
Jani Nikula | f00076d | 2013-12-14 20:38:29 -0200 | [diff] [blame] | 1368 | bool active_low_pwm; |
Jani Nikula | 1de6068 | 2014-06-24 18:27:39 +0300 | [diff] [blame] | 1369 | u8 min_brightness; /* min_brightness/255 of max */ |
Jani Nikula | f00076d | 2013-12-14 20:38:29 -0200 | [diff] [blame] | 1370 | } backlight; |
| 1371 | |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 1372 | /* MIPI DSI */ |
| 1373 | struct { |
Shobhit Kumar | 3e6bd01 | 2014-05-27 19:33:59 +0530 | [diff] [blame] | 1374 | u16 port; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 1375 | u16 panel_id; |
Shobhit Kumar | d3b542f | 2014-04-14 11:00:34 +0530 | [diff] [blame] | 1376 | struct mipi_config *config; |
| 1377 | struct mipi_pps_data *pps; |
| 1378 | u8 seq_version; |
| 1379 | u32 size; |
| 1380 | u8 *data; |
| 1381 | u8 *sequence[MIPI_SEQ_MAX]; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 1382 | } dsi; |
| 1383 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1384 | int crt_ddc_pin; |
| 1385 | |
| 1386 | int child_dev_num; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 1387 | union child_device_config *child_dev; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1388 | |
| 1389 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1390 | }; |
| 1391 | |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 1392 | enum intel_ddb_partitioning { |
| 1393 | INTEL_DDB_PART_1_2, |
| 1394 | INTEL_DDB_PART_5_6, /* IVB+ */ |
| 1395 | }; |
| 1396 | |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 1397 | struct intel_wm_level { |
| 1398 | bool enable; |
| 1399 | uint32_t pri_val; |
| 1400 | uint32_t spr_val; |
| 1401 | uint32_t cur_val; |
| 1402 | uint32_t fbc_val; |
| 1403 | }; |
| 1404 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1405 | struct ilk_wm_values { |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1406 | uint32_t wm_pipe[3]; |
| 1407 | uint32_t wm_lp[3]; |
| 1408 | uint32_t wm_lp_spr[3]; |
| 1409 | uint32_t wm_linetime[3]; |
| 1410 | bool enable_fbc_wm; |
| 1411 | enum intel_ddb_partitioning partitioning; |
| 1412 | }; |
| 1413 | |
Ville Syrjälä | 0018fda | 2015-03-05 21:19:45 +0200 | [diff] [blame] | 1414 | struct vlv_wm_values { |
| 1415 | struct { |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 1416 | uint16_t primary; |
| 1417 | uint16_t sprite[2]; |
| 1418 | uint8_t cursor; |
| 1419 | } pipe[3]; |
| 1420 | |
| 1421 | struct { |
| 1422 | uint16_t plane; |
| 1423 | uint8_t cursor; |
| 1424 | } sr; |
| 1425 | |
| 1426 | struct { |
Ville Syrjälä | 0018fda | 2015-03-05 21:19:45 +0200 | [diff] [blame] | 1427 | uint8_t cursor; |
| 1428 | uint8_t sprite[2]; |
| 1429 | uint8_t primary; |
| 1430 | } ddl[3]; |
| 1431 | }; |
| 1432 | |
Damien Lespiau | c193924 | 2014-11-04 17:06:41 +0000 | [diff] [blame] | 1433 | struct skl_ddb_entry { |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 1434 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
Damien Lespiau | c193924 | 2014-11-04 17:06:41 +0000 | [diff] [blame] | 1435 | }; |
| 1436 | |
| 1437 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) |
| 1438 | { |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 1439 | return entry->end - entry->start; |
Damien Lespiau | c193924 | 2014-11-04 17:06:41 +0000 | [diff] [blame] | 1440 | } |
| 1441 | |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 1442 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
| 1443 | const struct skl_ddb_entry *e2) |
| 1444 | { |
| 1445 | if (e1->start == e2->start && e1->end == e2->end) |
| 1446 | return true; |
| 1447 | |
| 1448 | return false; |
| 1449 | } |
| 1450 | |
Damien Lespiau | c193924 | 2014-11-04 17:06:41 +0000 | [diff] [blame] | 1451 | struct skl_ddb_allocation { |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 1452 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
Damien Lespiau | c193924 | 2014-11-04 17:06:41 +0000 | [diff] [blame] | 1453 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
| 1454 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; |
| 1455 | }; |
| 1456 | |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 1457 | struct skl_wm_values { |
| 1458 | bool dirty[I915_MAX_PIPES]; |
Damien Lespiau | c193924 | 2014-11-04 17:06:41 +0000 | [diff] [blame] | 1459 | struct skl_ddb_allocation ddb; |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 1460 | uint32_t wm_linetime[I915_MAX_PIPES]; |
| 1461 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; |
| 1462 | uint32_t cursor[I915_MAX_PIPES][8]; |
| 1463 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
| 1464 | uint32_t cursor_trans[I915_MAX_PIPES]; |
| 1465 | }; |
| 1466 | |
| 1467 | struct skl_wm_level { |
| 1468 | bool plane_en[I915_MAX_PLANES]; |
Damien Lespiau | b99f58d | 2014-11-04 17:06:56 +0000 | [diff] [blame] | 1469 | bool cursor_en; |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 1470 | uint16_t plane_res_b[I915_MAX_PLANES]; |
| 1471 | uint8_t plane_res_l[I915_MAX_PLANES]; |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 1472 | uint16_t cursor_res_b; |
| 1473 | uint8_t cursor_res_l; |
| 1474 | }; |
| 1475 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1476 | /* |
Paulo Zanoni | 765dab6 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 1477 | * This struct helps tracking the state needed for runtime PM, which puts the |
| 1478 | * device in PCI D3 state. Notice that when this happens, nothing on the |
| 1479 | * graphics device works, even register access, so we don't get interrupts nor |
| 1480 | * anything else. |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1481 | * |
Paulo Zanoni | 765dab6 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 1482 | * Every piece of our code that needs to actually touch the hardware needs to |
| 1483 | * either call intel_runtime_pm_get or call intel_display_power_get with the |
| 1484 | * appropriate power domain. |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 1485 | * |
Paulo Zanoni | 765dab6 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 1486 | * Our driver uses the autosuspend delay feature, which means we'll only really |
| 1487 | * suspend if we stay with zero refcount for a certain amount of time. The |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1488 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
Paulo Zanoni | 765dab6 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 1489 | * it can be changed with the standard runtime PM files from sysfs. |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1490 | * |
| 1491 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
| 1492 | * goes back to false exactly before we reenable the IRQs. We use this variable |
| 1493 | * to check if someone is trying to enable/disable IRQs while they're supposed |
| 1494 | * to be disabled. This shouldn't happen and we'll print some error messages in |
Paulo Zanoni | 730488b | 2014-03-07 20:12:32 -0300 | [diff] [blame] | 1495 | * case it happens. |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1496 | * |
Paulo Zanoni | 765dab6 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 1497 | * For more, read the Documentation/power/runtime_pm.txt. |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1498 | */ |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 1499 | struct i915_runtime_pm { |
| 1500 | bool suspended; |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 1501 | bool irqs_enabled; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1502 | }; |
| 1503 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1504 | enum intel_pipe_crc_source { |
| 1505 | INTEL_PIPE_CRC_SOURCE_NONE, |
| 1506 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
| 1507 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
| 1508 | INTEL_PIPE_CRC_SOURCE_PF, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1509 | INTEL_PIPE_CRC_SOURCE_PIPE, |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 1510 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
| 1511 | INTEL_PIPE_CRC_SOURCE_TV, |
| 1512 | INTEL_PIPE_CRC_SOURCE_DP_B, |
| 1513 | INTEL_PIPE_CRC_SOURCE_DP_C, |
| 1514 | INTEL_PIPE_CRC_SOURCE_DP_D, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 1515 | INTEL_PIPE_CRC_SOURCE_AUTO, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1516 | INTEL_PIPE_CRC_SOURCE_MAX, |
| 1517 | }; |
| 1518 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1519 | struct intel_pipe_crc_entry { |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1520 | uint32_t frame; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1521 | uint32_t crc[5]; |
| 1522 | }; |
| 1523 | |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1524 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1525 | struct intel_pipe_crc { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1526 | spinlock_t lock; |
| 1527 | bool opened; /* exclusive access to the result file */ |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 1528 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1529 | enum intel_pipe_crc_source source; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1530 | int head, tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1531 | wait_queue_head_t wq; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1532 | }; |
| 1533 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 1534 | struct i915_frontbuffer_tracking { |
| 1535 | struct mutex lock; |
| 1536 | |
| 1537 | /* |
| 1538 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or |
| 1539 | * scheduled flips. |
| 1540 | */ |
| 1541 | unsigned busy_bits; |
| 1542 | unsigned flip_bits; |
| 1543 | }; |
| 1544 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1545 | struct i915_wa_reg { |
| 1546 | u32 addr; |
| 1547 | u32 value; |
| 1548 | /* bitmask representing WA bits */ |
| 1549 | u32 mask; |
| 1550 | }; |
| 1551 | |
| 1552 | #define I915_MAX_WA_REGS 16 |
| 1553 | |
| 1554 | struct i915_workarounds { |
| 1555 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; |
| 1556 | u32 count; |
| 1557 | }; |
| 1558 | |
Yu Zhang | cf9d289 | 2015-02-10 19:05:47 +0800 | [diff] [blame] | 1559 | struct i915_virtual_gpu { |
| 1560 | bool active; |
| 1561 | }; |
| 1562 | |
Jani Nikula | 77fec55 | 2014-03-31 14:27:22 +0300 | [diff] [blame] | 1563 | struct drm_i915_private { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1564 | struct drm_device *dev; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1565 | struct kmem_cache *slab; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1566 | |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 1567 | const struct intel_device_info info; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1568 | |
| 1569 | int relative_constants_mode; |
| 1570 | |
| 1571 | void __iomem *regs; |
| 1572 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1573 | struct intel_uncore uncore; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1574 | |
Yu Zhang | cf9d289 | 2015-02-10 19:05:47 +0800 | [diff] [blame] | 1575 | struct i915_virtual_gpu vgpu; |
| 1576 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1577 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
| 1578 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1579 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1580 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
| 1581 | * controller on different i2c buses. */ |
| 1582 | struct mutex gmbus_mutex; |
| 1583 | |
| 1584 | /** |
| 1585 | * Base address of the gmbus and gpio block. |
| 1586 | */ |
| 1587 | uint32_t gpio_mmio_base; |
| 1588 | |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 1589 | /* MMIO base address for MIPI regs */ |
| 1590 | uint32_t mipi_mmio_base; |
| 1591 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1592 | wait_queue_head_t gmbus_wait_queue; |
| 1593 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1594 | struct pci_dev *bridge_dev; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1595 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1596 | struct drm_i915_gem_object *semaphore_obj; |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1597 | uint32_t last_seqno, next_seqno; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1598 | |
Daniel Vetter | ba8286f | 2014-09-11 07:43:25 +0200 | [diff] [blame] | 1599 | struct drm_dma_handle *status_page_dmah; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1600 | struct resource mch_res; |
| 1601 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1602 | /* protects the irq masks */ |
| 1603 | spinlock_t irq_lock; |
| 1604 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 1605 | /* protects the mmio flip data */ |
| 1606 | spinlock_t mmio_flip_lock; |
| 1607 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 1608 | bool display_irqs_enabled; |
| 1609 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1610 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
| 1611 | struct pm_qos_request pm_qos; |
| 1612 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1613 | /* DPIO indirect register protection */ |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1614 | struct mutex dpio_lock; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1615 | |
| 1616 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1617 | union { |
| 1618 | u32 irq_mask; |
| 1619 | u32 de_irq_mask[I915_MAX_PIPES]; |
| 1620 | }; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1621 | u32 gt_irq_mask; |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 1622 | u32 pm_irq_mask; |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1623 | u32 pm_rps_events; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1624 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1625 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1626 | struct work_struct hotplug_work; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1627 | struct { |
| 1628 | unsigned long hpd_last_jiffies; |
| 1629 | int hpd_cnt; |
| 1630 | enum { |
| 1631 | HPD_ENABLED = 0, |
| 1632 | HPD_DISABLED = 1, |
| 1633 | HPD_MARK_DISABLED = 2 |
| 1634 | } hpd_mark; |
| 1635 | } hpd_stats[HPD_NUM_PINS]; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1636 | u32 hpd_event_bits; |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 1637 | struct delayed_work hotplug_reenable_work; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1638 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1639 | struct i915_fbc fbc; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1640 | struct i915_drrs drrs; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1641 | struct intel_opregion opregion; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1642 | struct intel_vbt_data vbt; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1643 | |
Jesse Barnes | d9ceb81 | 2014-10-09 12:57:43 -0700 | [diff] [blame] | 1644 | bool preserve_bios_swizzle; |
| 1645 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1646 | /* overlay */ |
| 1647 | struct intel_overlay *overlay; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1648 | |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 1649 | /* backlight registers and fields in struct intel_panel */ |
Daniel Vetter | 07f11d4 | 2014-09-15 14:35:09 +0200 | [diff] [blame] | 1650 | struct mutex backlight_lock; |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 1651 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1652 | /* LVDS info */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1653 | bool no_aux_handshake; |
| 1654 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1655 | /* protects panel power sequencer state */ |
| 1656 | struct mutex pps_mutex; |
| 1657 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1658 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
| 1659 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 1660 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 1661 | |
| 1662 | unsigned int fsb_freq, mem_freq, is_ddr3; |
Imre Deak | d60c447 | 2014-03-27 17:45:10 +0200 | [diff] [blame] | 1663 | unsigned int vlv_cdclk_freq; |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 1664 | unsigned int hpll_freq; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1665 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1666 | /** |
| 1667 | * wq - Driver workqueue for GEM. |
| 1668 | * |
| 1669 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
| 1670 | * locks, for otherwise the flushing done in the pageflip code will |
| 1671 | * result in deadlocks. |
| 1672 | */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1673 | struct workqueue_struct *wq; |
| 1674 | |
| 1675 | /* Display functions */ |
| 1676 | struct drm_i915_display_funcs display; |
| 1677 | |
| 1678 | /* PCH chipset type */ |
| 1679 | enum intel_pch pch_type; |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 1680 | unsigned short pch_id; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1681 | |
| 1682 | unsigned long quirks; |
| 1683 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1684 | enum modeset_restore modeset_restore; |
| 1685 | struct mutex modeset_restore_lock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 1687 | struct list_head vm_list; /* Global list of all address spaces */ |
Ben Widawsky | 0260c42 | 2014-03-22 22:47:21 -0700 | [diff] [blame] | 1688 | struct i915_gtt gtt; /* VM representing the global address space */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1689 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1690 | struct i915_gem_mm mm; |
Chris Wilson | ad46cb5 | 2014-08-07 14:20:40 +0100 | [diff] [blame] | 1691 | DECLARE_HASHTABLE(mm_structs, 7); |
| 1692 | struct mutex mm_lock; |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1693 | |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1694 | /* Kernel Modesetting */ |
| 1695 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 1696 | struct sdvo_device_mapping sdvo_mappings[2]; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1697 | |
Damien Lespiau | 76c4ac0 | 2014-02-07 19:12:52 +0000 | [diff] [blame] | 1698 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
| 1699 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1700 | wait_queue_head_t pending_flip_queue; |
| 1701 | |
Daniel Vetter | c459787 | 2013-10-21 21:04:07 +0200 | [diff] [blame] | 1702 | #ifdef CONFIG_DEBUG_FS |
| 1703 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
| 1704 | #endif |
| 1705 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1706 | int num_shared_dpll; |
| 1707 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1708 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1709 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1710 | struct i915_workarounds workarounds; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 1711 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1712 | /* Reclocking support */ |
| 1713 | bool render_reclock_avail; |
| 1714 | bool lvds_downclock_avail; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 1715 | /* indicates the reduced downclock for LVDS*/ |
| 1716 | int lvds_downclock; |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 1717 | |
| 1718 | struct i915_frontbuffer_tracking fb_tracking; |
| 1719 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1720 | u16 orig_clock; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1721 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1722 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1723 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1724 | struct intel_l3_parity l3_parity; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1725 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 1726 | /* Cannot be determined by PCIID. You must always read a register. */ |
| 1727 | size_t ellc_size; |
| 1728 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1729 | /* gen6+ rps state */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1730 | struct intel_gen6_power_mgmt rps; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1731 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1732 | /* ilk-only ips/rps state. Everything in here is protected by the global |
| 1733 | * mchdev_lock in intel_pm.c */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1734 | struct intel_ilk_power_mgmt ips; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1735 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1736 | struct i915_power_domains power_domains; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1737 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1738 | struct i915_psr psr; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1739 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1740 | struct i915_gpu_error gpu_error; |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 1741 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 1742 | struct drm_i915_gem_object *vlv_pctx; |
| 1743 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1744 | #ifdef CONFIG_DRM_I915_FBDEV |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 1745 | /* list of fbdev register on this device */ |
| 1746 | struct intel_fbdev *fbdev; |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 1747 | struct work_struct fbdev_suspend_work; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1748 | #endif |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1749 | |
| 1750 | struct drm_property *broadcast_rgb_property; |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1751 | struct drm_property *force_audio_property; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1752 | |
Imre Deak | 58fddc2 | 2015-01-08 17:54:14 +0200 | [diff] [blame] | 1753 | /* hda/i915 audio component */ |
| 1754 | bool audio_component_registered; |
| 1755 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1756 | uint32_t hw_context_size; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1757 | struct list_head context_list; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1758 | |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 1759 | u32 fdi_rx_config; |
Paulo Zanoni | 68d18ad | 2012-12-01 12:04:26 -0200 | [diff] [blame] | 1760 | |
Daniel Vetter | 842f1c8 | 2014-03-10 10:01:44 +0100 | [diff] [blame] | 1761 | u32 suspend_count; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1762 | struct i915_suspend_saved_registers regfile; |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1763 | struct vlv_s0ix_state vlv_s0ix_state; |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1764 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1765 | struct { |
| 1766 | /* |
| 1767 | * Raw watermark latency values: |
| 1768 | * in 0.1us units for WM0, |
| 1769 | * in 0.5us units for WM1+. |
| 1770 | */ |
| 1771 | /* primary */ |
| 1772 | uint16_t pri_latency[5]; |
| 1773 | /* sprite */ |
| 1774 | uint16_t spr_latency[5]; |
| 1775 | /* cursor */ |
| 1776 | uint16_t cur_latency[5]; |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1777 | /* |
| 1778 | * Raw watermark memory latency values |
| 1779 | * for SKL for all 8 levels |
| 1780 | * in 1us units. |
| 1781 | */ |
| 1782 | uint16_t skl_latency[8]; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1783 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 1784 | /* |
| 1785 | * The skl_wm_values structure is a bit too big for stack |
| 1786 | * allocation, so we keep the staging struct where we store |
| 1787 | * intermediate results here instead. |
| 1788 | */ |
| 1789 | struct skl_wm_values skl_results; |
| 1790 | |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1791 | /* current hardware state */ |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 1792 | union { |
| 1793 | struct ilk_wm_values hw; |
| 1794 | struct skl_wm_values skl_hw; |
Ville Syrjälä | 0018fda | 2015-03-05 21:19:45 +0200 | [diff] [blame] | 1795 | struct vlv_wm_values vlv; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 1796 | }; |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1797 | } wm; |
| 1798 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1799 | struct i915_runtime_pm pm; |
| 1800 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1801 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; |
| 1802 | u32 long_hpd_port_mask; |
| 1803 | u32 short_hpd_port_mask; |
| 1804 | struct work_struct dig_port_work; |
| 1805 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1806 | /* |
| 1807 | * if we get a HPD irq from DP and a HPD irq from non-DP |
| 1808 | * the non-DP HPD could block the workqueue on a mode config |
| 1809 | * mutex getting, that userspace may have taken. However |
| 1810 | * userspace is waiting on the DP workqueue to run which is |
| 1811 | * blocked behind the non-DP one. |
| 1812 | */ |
| 1813 | struct workqueue_struct *dp_wq; |
| 1814 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 1815 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
| 1816 | struct { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 1817 | int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file, |
| 1818 | struct intel_engine_cs *ring, |
| 1819 | struct intel_context *ctx, |
| 1820 | struct drm_i915_gem_execbuffer2 *args, |
| 1821 | struct list_head *vmas, |
| 1822 | struct drm_i915_gem_object *batch_obj, |
| 1823 | u64 exec_start, u32 flags); |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 1824 | int (*init_rings)(struct drm_device *dev); |
| 1825 | void (*cleanup_ring)(struct intel_engine_cs *ring); |
| 1826 | void (*stop_ring)(struct intel_engine_cs *ring); |
| 1827 | } gt; |
| 1828 | |
John Harrison | 67e2937 | 2014-12-05 13:49:35 +0000 | [diff] [blame] | 1829 | uint32_t request_uniq; |
| 1830 | |
Daniel Vetter | bdf1e7e | 2014-05-21 17:37:52 +0200 | [diff] [blame] | 1831 | /* |
| 1832 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
| 1833 | * will be rejected. Instead look for a better place. |
| 1834 | */ |
Jani Nikula | 77fec55 | 2014-03-31 14:27:22 +0300 | [diff] [blame] | 1835 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1836 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1837 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
| 1838 | { |
| 1839 | return dev->dev_private; |
| 1840 | } |
| 1841 | |
Imre Deak | 888d0d4 | 2015-01-08 17:54:13 +0200 | [diff] [blame] | 1842 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
| 1843 | { |
| 1844 | return to_i915(dev_get_drvdata(dev)); |
| 1845 | } |
| 1846 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1847 | /* Iterate over initialised rings */ |
| 1848 | #define for_each_ring(ring__, dev_priv__, i__) \ |
| 1849 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
| 1850 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
| 1851 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 1852 | enum hdmi_force_audio { |
| 1853 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
| 1854 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
| 1855 | HDMI_AUDIO_AUTO, /* trust EDID */ |
| 1856 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
| 1857 | }; |
| 1858 | |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 1859 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1860 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1861 | struct drm_i915_gem_object_ops { |
| 1862 | /* Interface between the GEM object and its backing storage. |
| 1863 | * get_pages() is called once prior to the use of the associated set |
| 1864 | * of pages before to binding them into the GTT, and put_pages() is |
| 1865 | * called after we no longer need them. As we expect there to be |
| 1866 | * associated cost with migrating pages between the backing storage |
| 1867 | * and making them available for the GPU (e.g. clflush), we may hold |
| 1868 | * onto the pages after they are no longer referenced by the GPU |
| 1869 | * in case they may be used again shortly (for example migrating the |
| 1870 | * pages to a different memory domain within the GTT). put_pages() |
| 1871 | * will therefore most likely be called when the object itself is |
| 1872 | * being released or under memory pressure (where we attempt to |
| 1873 | * reap pages for the shrinker). |
| 1874 | */ |
| 1875 | int (*get_pages)(struct drm_i915_gem_object *); |
| 1876 | void (*put_pages)(struct drm_i915_gem_object *); |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 1877 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
| 1878 | void (*release)(struct drm_i915_gem_object *); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1879 | }; |
| 1880 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 1881 | /* |
| 1882 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is |
| 1883 | * considered to be the frontbuffer for the given plane interface-vise. This |
| 1884 | * doesn't mean that the hw necessarily already scans it out, but that any |
| 1885 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. |
| 1886 | * |
| 1887 | * We have one bit per pipe and per scanout plane type. |
| 1888 | */ |
| 1889 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 |
| 1890 | #define INTEL_FRONTBUFFER_BITS \ |
| 1891 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) |
| 1892 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
| 1893 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
| 1894 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ |
| 1895 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
| 1896 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ |
| 1897 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
| 1898 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
| 1899 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
Daniel Vetter | cc36513 | 2014-06-18 13:59:13 +0200 | [diff] [blame] | 1900 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
| 1901 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 1902 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1903 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 1904 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1905 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1906 | const struct drm_i915_gem_object_ops *ops; |
| 1907 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 1908 | /** List of VMAs backed by this object */ |
| 1909 | struct list_head vma_list; |
| 1910 | |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 1911 | /** Stolen memory for this object, instead of being backed by shmem. */ |
| 1912 | struct drm_mm_node *stolen; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1913 | struct list_head global_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1914 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1915 | struct list_head ring_list; |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 1916 | /** Used in execbuf to temporarily hold a ref */ |
| 1917 | struct list_head obj_exec_link; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1918 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 1919 | struct list_head batch_pool_list; |
| 1920 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1921 | /** |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1922 | * This is set if the object is on the active lists (has pending |
| 1923 | * rendering and so a non-zero seqno), and is not set if it i s on |
| 1924 | * inactive (ready to be unbound) list. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1925 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1926 | unsigned int active:1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1927 | |
| 1928 | /** |
| 1929 | * This is set if the object has been written to since last bound |
| 1930 | * to the GTT |
| 1931 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1932 | unsigned int dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1933 | |
| 1934 | /** |
| 1935 | * Fence register bits (if any) for this object. Will be set |
| 1936 | * as needed when mapped into the GTT. |
| 1937 | * Protected by dev->struct_mutex. |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1938 | */ |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1939 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1940 | |
| 1941 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1942 | * Advice: are the backing pages purgeable? |
| 1943 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1944 | unsigned int madv:2; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1945 | |
| 1946 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1947 | * Current tiling mode for the object. |
| 1948 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1949 | unsigned int tiling_mode:2; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 1950 | /** |
| 1951 | * Whether the tiling parameters for the currently associated fence |
| 1952 | * register have changed. Note that for the purposes of tracking |
| 1953 | * tiling changes we also treat the unfenced register, the register |
| 1954 | * slot that the object occupies whilst it executes a fenced |
| 1955 | * command (such as BLT on gen2/3), as a "fence". |
| 1956 | */ |
| 1957 | unsigned int fence_dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1958 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1959 | /** |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1960 | * Is the object at the current location in the gtt mappable and |
| 1961 | * fenceable? Used to avoid costly recalculations. |
| 1962 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1963 | unsigned int map_and_fenceable:1; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1964 | |
| 1965 | /** |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1966 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 1967 | * mappable by accident). Track pin and fault separate for a more |
| 1968 | * accurate mappable working set. |
| 1969 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1970 | unsigned int fault_mappable:1; |
| 1971 | unsigned int pin_mappable:1; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 1972 | unsigned int pin_display:1; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1973 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1974 | /* |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1975 | * Is the object to be mapped as read-only to the GPU |
| 1976 | * Only honoured if hardware has relevant pte bit |
| 1977 | */ |
| 1978 | unsigned long gt_ro:1; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 1979 | unsigned int cache_level:3; |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 1980 | unsigned int cache_dirty:1; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 1981 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1982 | unsigned int has_dma_mapping:1; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1983 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 1984 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
| 1985 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1986 | struct sg_table *pages; |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1987 | int pages_pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1988 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1989 | /* prime dma-buf support */ |
Dave Airlie | 9a70cc2 | 2012-05-22 13:09:21 +0100 | [diff] [blame] | 1990 | void *dma_buf_vmapping; |
| 1991 | int vmapping_count; |
| 1992 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 1993 | /** Breadcrumb of last rendering to the buffer. */ |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 1994 | struct drm_i915_gem_request *last_read_req; |
| 1995 | struct drm_i915_gem_request *last_write_req; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1996 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 1997 | struct drm_i915_gem_request *last_fenced_req; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1998 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1999 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2000 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2001 | |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 2002 | /** References from framebuffers, locks out tiling changes. */ |
| 2003 | unsigned long framebuffer_references; |
| 2004 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2005 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 2006 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2007 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 2008 | union { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 2009 | /** for phy allocated objects */ |
| 2010 | struct drm_dma_handle *phys_handle; |
| 2011 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 2012 | struct i915_gem_userptr { |
| 2013 | uintptr_t ptr; |
| 2014 | unsigned read_only :1; |
| 2015 | unsigned workers :4; |
| 2016 | #define I915_GEM_USERPTR_MAX_WORKERS 15 |
| 2017 | |
Chris Wilson | ad46cb5 | 2014-08-07 14:20:40 +0100 | [diff] [blame] | 2018 | struct i915_mm_struct *mm; |
| 2019 | struct i915_mmu_object *mmu_object; |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 2020 | struct work_struct *work; |
| 2021 | } userptr; |
| 2022 | }; |
| 2023 | }; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 2024 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2025 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 2026 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 2027 | struct drm_i915_gem_object *new, |
| 2028 | unsigned frontbuffer_bits); |
| 2029 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2030 | /** |
| 2031 | * Request queue structure. |
| 2032 | * |
| 2033 | * The request queue allows us to note sequence numbers that have been emitted |
| 2034 | * and may be associated with active buffers to be retired. |
| 2035 | * |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 2036 | * By keeping this list, we can avoid having to do questionable sequence |
| 2037 | * number comparisons on buffer last_read|write_seqno. It also allows an |
| 2038 | * emission time to be associated with the request for tracking how far ahead |
| 2039 | * of the GPU the submission is. |
Nick Hoath | b3a3899 | 2015-02-19 16:30:47 +0000 | [diff] [blame] | 2040 | * |
| 2041 | * The requests are reference counted, so upon creation they should have an |
| 2042 | * initial reference taken using kref_init |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2043 | */ |
| 2044 | struct drm_i915_gem_request { |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2045 | struct kref ref; |
| 2046 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2047 | /** On Which ring this request was generated */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2048 | struct intel_engine_cs *ring; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2049 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2050 | /** GEM sequence number associated with this request. */ |
| 2051 | uint32_t seqno; |
| 2052 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2053 | /** Position in the ringbuffer of the start of the request */ |
| 2054 | u32 head; |
| 2055 | |
Nick Hoath | 72f95af | 2015-01-15 13:10:37 +0000 | [diff] [blame] | 2056 | /** |
| 2057 | * Position in the ringbuffer of the start of the postfix. |
| 2058 | * This is required to calculate the maximum available ringbuffer |
| 2059 | * space without overwriting the postfix. |
| 2060 | */ |
| 2061 | u32 postfix; |
| 2062 | |
| 2063 | /** Position in the ringbuffer of the end of the whole request */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2064 | u32 tail; |
| 2065 | |
Nick Hoath | b3a3899 | 2015-02-19 16:30:47 +0000 | [diff] [blame] | 2066 | /** |
Dave Airlie | a8c6ecb | 2015-03-09 19:58:30 +1000 | [diff] [blame] | 2067 | * Context and ring buffer related to this request |
Nick Hoath | b3a3899 | 2015-02-19 16:30:47 +0000 | [diff] [blame] | 2068 | * Contexts are refcounted, so when this request is associated with a |
| 2069 | * context, we must increment the context's refcount, to guarantee that |
| 2070 | * it persists while any request is linked to it. Requests themselves |
| 2071 | * are also refcounted, so the request will only be freed when the last |
| 2072 | * reference to it is dismissed, and the code in |
| 2073 | * i915_gem_request_free() will then decrement the refcount on the |
| 2074 | * context. |
| 2075 | */ |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2076 | struct intel_context *ctx; |
John Harrison | 98e1bd4 | 2015-02-13 11:48:12 +0000 | [diff] [blame] | 2077 | struct intel_ringbuffer *ringbuf; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2078 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2079 | /** Batch buffer related to this request if any */ |
| 2080 | struct drm_i915_gem_object *batch_obj; |
| 2081 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2082 | /** Time at which this request was emitted, in jiffies. */ |
| 2083 | unsigned long emitted_jiffies; |
| 2084 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2085 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2086 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2087 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2088 | struct drm_i915_file_private *file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2089 | /** file_priv list entry for this request */ |
| 2090 | struct list_head client_list; |
John Harrison | 67e2937 | 2014-12-05 13:49:35 +0000 | [diff] [blame] | 2091 | |
Mika Kuoppala | 071c92d | 2015-02-12 10:26:02 +0200 | [diff] [blame] | 2092 | /** process identifier submitting this request */ |
| 2093 | struct pid *pid; |
| 2094 | |
John Harrison | 67e2937 | 2014-12-05 13:49:35 +0000 | [diff] [blame] | 2095 | uint32_t uniq; |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2096 | |
| 2097 | /** |
| 2098 | * The ELSP only accepts two elements at a time, so we queue |
| 2099 | * context/tail pairs on a given queue (ring->execlist_queue) until the |
| 2100 | * hardware is available. The queue serves a double purpose: we also use |
| 2101 | * it to keep track of the up to 2 contexts currently in the hardware |
| 2102 | * (usually one in execution and the other queued up by the GPU): We |
| 2103 | * only remove elements from the head of the queue when the hardware |
| 2104 | * informs us that an element has been completed. |
| 2105 | * |
| 2106 | * All accesses to the queue are mediated by a spinlock |
| 2107 | * (ring->execlist_lock). |
| 2108 | */ |
| 2109 | |
| 2110 | /** Execlist link in the submission queue.*/ |
| 2111 | struct list_head execlist_link; |
| 2112 | |
| 2113 | /** Execlists no. of times this request has been sent to the ELSP */ |
| 2114 | int elsp_submitted; |
| 2115 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2116 | }; |
| 2117 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2118 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
| 2119 | struct intel_context *ctx); |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2120 | void i915_gem_request_free(struct kref *req_ref); |
| 2121 | |
John Harrison | b793a00 | 2014-11-24 18:49:25 +0000 | [diff] [blame] | 2122 | static inline uint32_t |
| 2123 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) |
| 2124 | { |
| 2125 | return req ? req->seqno : 0; |
| 2126 | } |
| 2127 | |
| 2128 | static inline struct intel_engine_cs * |
| 2129 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) |
| 2130 | { |
| 2131 | return req ? req->ring : NULL; |
| 2132 | } |
| 2133 | |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2134 | static inline void |
| 2135 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
| 2136 | { |
| 2137 | kref_get(&req->ref); |
| 2138 | } |
| 2139 | |
| 2140 | static inline void |
| 2141 | i915_gem_request_unreference(struct drm_i915_gem_request *req) |
| 2142 | { |
Daniel Vetter | f245860 | 2014-11-26 10:26:05 +0100 | [diff] [blame] | 2143 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2144 | kref_put(&req->ref, i915_gem_request_free); |
| 2145 | } |
| 2146 | |
Chris Wilson | 41037f9 | 2015-03-27 11:01:36 +0000 | [diff] [blame] | 2147 | static inline void |
| 2148 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) |
| 2149 | { |
| 2150 | if (req && !atomic_add_unless(&req->ref.refcount, -1, 1)) { |
| 2151 | struct drm_device *dev = req->ring->dev; |
| 2152 | |
| 2153 | mutex_lock(&dev->struct_mutex); |
| 2154 | if (likely(atomic_dec_and_test(&req->ref.refcount))) |
| 2155 | i915_gem_request_free(&req->ref); |
| 2156 | mutex_unlock(&dev->struct_mutex); |
| 2157 | } |
| 2158 | } |
| 2159 | |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2160 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
| 2161 | struct drm_i915_gem_request *src) |
| 2162 | { |
| 2163 | if (src) |
| 2164 | i915_gem_request_reference(src); |
| 2165 | |
| 2166 | if (*pdst) |
| 2167 | i915_gem_request_unreference(*pdst); |
| 2168 | |
| 2169 | *pdst = src; |
| 2170 | } |
| 2171 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2172 | /* |
| 2173 | * XXX: i915_gem_request_completed should be here but currently needs the |
| 2174 | * definition of i915_seqno_passed() which is below. It will be moved in |
| 2175 | * a later patch when the call to i915_seqno_passed() is obsoleted... |
| 2176 | */ |
| 2177 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2178 | struct drm_i915_file_private { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2179 | struct drm_i915_private *dev_priv; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 2180 | struct drm_file *file; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2181 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2182 | struct { |
Luis R. Rodriguez | 99057c8 | 2012-11-29 12:45:06 -0800 | [diff] [blame] | 2183 | spinlock_t lock; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2184 | struct list_head request_list; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2185 | struct delayed_work idle_work; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2186 | } mm; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 2187 | struct idr context_idr; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 2188 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2189 | atomic_t rps_wait_boost; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2190 | struct intel_engine_cs *bsd_ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2191 | }; |
| 2192 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2193 | /* |
| 2194 | * A command that requires special handling by the command parser. |
| 2195 | */ |
| 2196 | struct drm_i915_cmd_descriptor { |
| 2197 | /* |
| 2198 | * Flags describing how the command parser processes the command. |
| 2199 | * |
| 2200 | * CMD_DESC_FIXED: The command has a fixed length if this is set, |
| 2201 | * a length mask if not set |
| 2202 | * CMD_DESC_SKIP: The command is allowed but does not follow the |
| 2203 | * standard length encoding for the opcode range in |
| 2204 | * which it falls |
| 2205 | * CMD_DESC_REJECT: The command is never allowed |
| 2206 | * CMD_DESC_REGISTER: The command should be checked against the |
| 2207 | * register whitelist for the appropriate ring |
| 2208 | * CMD_DESC_MASTER: The command is allowed if the submitting process |
| 2209 | * is the DRM master |
| 2210 | */ |
| 2211 | u32 flags; |
| 2212 | #define CMD_DESC_FIXED (1<<0) |
| 2213 | #define CMD_DESC_SKIP (1<<1) |
| 2214 | #define CMD_DESC_REJECT (1<<2) |
| 2215 | #define CMD_DESC_REGISTER (1<<3) |
| 2216 | #define CMD_DESC_BITMASK (1<<4) |
| 2217 | #define CMD_DESC_MASTER (1<<5) |
| 2218 | |
| 2219 | /* |
| 2220 | * The command's unique identification bits and the bitmask to get them. |
| 2221 | * This isn't strictly the opcode field as defined in the spec and may |
| 2222 | * also include type, subtype, and/or subop fields. |
| 2223 | */ |
| 2224 | struct { |
| 2225 | u32 value; |
| 2226 | u32 mask; |
| 2227 | } cmd; |
| 2228 | |
| 2229 | /* |
| 2230 | * The command's length. The command is either fixed length (i.e. does |
| 2231 | * not include a length field) or has a length field mask. The flag |
| 2232 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has |
| 2233 | * a length mask. All command entries in a command table must include |
| 2234 | * length information. |
| 2235 | */ |
| 2236 | union { |
| 2237 | u32 fixed; |
| 2238 | u32 mask; |
| 2239 | } length; |
| 2240 | |
| 2241 | /* |
| 2242 | * Describes where to find a register address in the command to check |
| 2243 | * against the ring's register whitelist. Only valid if flags has the |
| 2244 | * CMD_DESC_REGISTER bit set. |
| 2245 | */ |
| 2246 | struct { |
| 2247 | u32 offset; |
| 2248 | u32 mask; |
| 2249 | } reg; |
| 2250 | |
| 2251 | #define MAX_CMD_DESC_BITMASKS 3 |
| 2252 | /* |
| 2253 | * Describes command checks where a particular dword is masked and |
| 2254 | * compared against an expected value. If the command does not match |
| 2255 | * the expected value, the parser rejects it. Only valid if flags has |
| 2256 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero |
| 2257 | * are valid. |
Brad Volkin | d4d4803 | 2014-02-18 10:15:54 -0800 | [diff] [blame] | 2258 | * |
| 2259 | * If the check specifies a non-zero condition_mask then the parser |
| 2260 | * only performs the check when the bits specified by condition_mask |
| 2261 | * are non-zero. |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2262 | */ |
| 2263 | struct { |
| 2264 | u32 offset; |
| 2265 | u32 mask; |
| 2266 | u32 expected; |
Brad Volkin | d4d4803 | 2014-02-18 10:15:54 -0800 | [diff] [blame] | 2267 | u32 condition_offset; |
| 2268 | u32 condition_mask; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2269 | } bits[MAX_CMD_DESC_BITMASKS]; |
| 2270 | }; |
| 2271 | |
| 2272 | /* |
| 2273 | * A table of commands requiring special handling by the command parser. |
| 2274 | * |
| 2275 | * Each ring has an array of tables. Each table consists of an array of command |
| 2276 | * descriptors, which must be sorted with command opcodes in ascending order. |
| 2277 | */ |
| 2278 | struct drm_i915_cmd_table { |
| 2279 | const struct drm_i915_cmd_descriptor *table; |
| 2280 | int count; |
| 2281 | }; |
| 2282 | |
Chris Wilson | dbbe912 | 2014-08-09 19:18:43 +0100 | [diff] [blame] | 2283 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
Chris Wilson | 7312e2d | 2014-08-13 12:14:12 +0100 | [diff] [blame] | 2284 | #define __I915__(p) ({ \ |
| 2285 | struct drm_i915_private *__p; \ |
| 2286 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ |
| 2287 | __p = (struct drm_i915_private *)p; \ |
| 2288 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ |
| 2289 | __p = to_i915((struct drm_device *)p); \ |
| 2290 | else \ |
| 2291 | BUILD_BUG(); \ |
| 2292 | __p; \ |
| 2293 | }) |
Chris Wilson | dbbe912 | 2014-08-09 19:18:43 +0100 | [diff] [blame] | 2294 | #define INTEL_INFO(p) (&__I915__(p)->info) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2295 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
Hoath, Nicholas | e90a21d | 2015-02-05 10:47:17 +0000 | [diff] [blame] | 2296 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2297 | |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2298 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
| 2299 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2300 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2301 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2302 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2303 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
| 2304 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2305 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 2306 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 2307 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2308 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2309 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2310 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
| 2311 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2312 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 2313 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2314 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
Jesse Barnes | 4b65177 | 2011-04-28 14:33:09 -0700 | [diff] [blame] | 2315 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2316 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
| 2317 | INTEL_DEVID(dev) == 0x0152 || \ |
| 2318 | INTEL_DEVID(dev) == 0x015a) |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 2319 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
Ville Syrjälä | 6df4027 | 2014-04-09 13:28:00 +0300 | [diff] [blame] | 2320 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 2321 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
Ville Syrjälä | 8179f1f | 2014-04-09 13:27:59 +0300 | [diff] [blame] | 2322 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
Satheeshakrishna M | 7201c0b | 2014-04-02 11:24:50 +0530 | [diff] [blame] | 2323 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2324 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
Paulo Zanoni | ed1c9e2 | 2013-08-12 14:34:08 -0300 | [diff] [blame] | 2325 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2326 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 2327 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
Rodrigo Vivi | 6b96d70 | 2015-01-19 16:16:15 -0800 | [diff] [blame] | 2328 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
Rodrigo Vivi | 0dc6f20 | 2015-01-21 11:46:32 -0800 | [diff] [blame] | 2329 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2330 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
Rodrigo Vivi | a0fcbd9 | 2014-09-19 20:16:26 -0400 | [diff] [blame] | 2331 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
| 2332 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 2333 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2334 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 2335 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2336 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
Paulo Zanoni | 9bbfd20 | 2014-04-29 11:00:22 -0300 | [diff] [blame] | 2337 | /* ULX machines are also considered ULT. */ |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 2338 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
| 2339 | INTEL_DEVID(dev) == 0x0A1E) |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 2340 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2341 | |
Hoath, Nicholas | e90a21d | 2015-02-05 10:47:17 +0000 | [diff] [blame] | 2342 | #define SKL_REVID_A0 (0x0) |
| 2343 | #define SKL_REVID_B0 (0x1) |
| 2344 | #define SKL_REVID_C0 (0x2) |
| 2345 | #define SKL_REVID_D0 (0x3) |
Damien Lespiau | 8bc0ccf | 2015-02-09 19:33:18 +0000 | [diff] [blame] | 2346 | #define SKL_REVID_E0 (0x4) |
Hoath, Nicholas | e90a21d | 2015-02-05 10:47:17 +0000 | [diff] [blame] | 2347 | |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 2348 | /* |
| 2349 | * The genX designation typically refers to the render engine, so render |
| 2350 | * capability related checks should use IS_GEN, while display and other checks |
| 2351 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
| 2352 | * chips, etc.). |
| 2353 | */ |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2354 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 2355 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 2356 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 2357 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 2358 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 2359 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
Ben Widawsky | d298084 | 2013-11-02 21:06:59 -0700 | [diff] [blame] | 2360 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
Damien Lespiau | b71252d | 2013-02-13 15:27:24 +0000 | [diff] [blame] | 2361 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2362 | |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 2363 | #define RENDER_RING (1<<RCS) |
| 2364 | #define BSD_RING (1<<VCS) |
| 2365 | #define BLT_RING (1<<BCS) |
| 2366 | #define VEBOX_RING (1<<VECS) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2367 | #define BSD2_RING (1<<VCS2) |
Ben Widawsky | 63c42e5 | 2014-04-18 18:04:27 -0300 | [diff] [blame] | 2368 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2369 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
Ben Widawsky | 63c42e5 | 2014-04-18 18:04:27 -0300 | [diff] [blame] | 2370 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
| 2371 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
| 2372 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
| 2373 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
Chris Wilson | f2fbc69 | 2014-08-24 19:35:31 +0100 | [diff] [blame] | 2374 | __I915__(dev)->ellc_size) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2375 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 2376 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2377 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
Oscar Mateo | d7f621e | 2014-07-24 17:04:49 +0100 | [diff] [blame] | 2378 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
Jesse Barnes | 692ef70 | 2014-08-05 07:51:18 -0700 | [diff] [blame] | 2379 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
| 2380 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 2381 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2382 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2383 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 2384 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2385 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
| 2386 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 2387 | /* |
| 2388 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts |
| 2389 | * even when in MSI mode. This results in spurious interrupt warnings if the |
| 2390 | * legacy irq no. is shared with another device. The kernel then disables that |
| 2391 | * interrupt source and so prevents the other device from working properly. |
| 2392 | */ |
| 2393 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
| 2394 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2395 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2396 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 2397 | * rows, which changed the alignment requirements and fence programming. |
| 2398 | */ |
| 2399 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 2400 | IS_I915GM(dev))) |
| 2401 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 2402 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 2403 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2404 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 2405 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2406 | |
| 2407 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 2408 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 2409 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2410 | |
Damien Lespiau | dbf7786 | 2014-10-01 20:04:14 +0100 | [diff] [blame] | 2411 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 2412 | |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 2413 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 2414 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2415 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
Sonika Jindal | e3d9984 | 2015-01-22 14:30:54 +0530 | [diff] [blame] | 2416 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
| 2417 | IS_SKYLAKE(dev)) |
Paulo Zanoni | 6157d3c | 2014-03-07 20:12:37 -0300 | [diff] [blame] | 2418 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
Imre Deak | fd7f8cc | 2014-04-14 20:41:30 +0300 | [diff] [blame] | 2419 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) |
Rodrigo Vivi | 58abf1d | 2014-10-07 07:06:50 -0700 | [diff] [blame] | 2420 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
| 2421 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2422 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 2423 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
| 2424 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 2425 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 2426 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
| 2427 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
| 2428 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
Satheeshakrishna M | e7e7ea2 | 2014-04-09 11:08:57 +0530 | [diff] [blame] | 2429 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
| 2430 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 2431 | |
Chris Wilson | f2fbc69 | 2014-08-24 19:35:31 +0100 | [diff] [blame] | 2432 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
Satheeshakrishna M | e7e7ea2 | 2014-04-09 11:08:57 +0530 | [diff] [blame] | 2433 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 2434 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2435 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 2436 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 2437 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
Paulo Zanoni | 45e6e3a | 2012-07-03 15:57:32 -0300 | [diff] [blame] | 2438 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2439 | |
Sonika Jindal | 5fafe29 | 2014-07-21 15:23:38 +0530 | [diff] [blame] | 2440 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
| 2441 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 2442 | /* DPF == dynamic parity feature */ |
| 2443 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 2444 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 2445 | |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 2446 | #define GT_FREQUENCY_MULTIPLIER 50 |
Akash Goel | de43ae9 | 2015-03-06 11:07:14 +0530 | [diff] [blame] | 2447 | #define GEN9_FREQ_SCALER 3 |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 2448 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2449 | #include "i915_trace.h" |
| 2450 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 2451 | extern const struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 2452 | extern int i915_max_ioctl; |
| 2453 | |
Imre Deak | fc49b3d | 2014-10-23 19:23:27 +0300 | [diff] [blame] | 2454 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); |
| 2455 | extern int i915_resume_legacy(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2456 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2457 | /* i915_params.c */ |
| 2458 | struct i915_params { |
| 2459 | int modeset; |
| 2460 | int panel_ignore_lid; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2461 | int semaphores; |
| 2462 | unsigned int lvds_downclock; |
| 2463 | int lvds_channel_mode; |
| 2464 | int panel_use_ssc; |
| 2465 | int vbt_sdvo_panel_type; |
| 2466 | int enable_rc6; |
| 2467 | int enable_fbc; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2468 | int enable_ppgtt; |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 2469 | int enable_execlists; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2470 | int enable_psr; |
| 2471 | unsigned int preliminary_hw_support; |
| 2472 | int disable_power_well; |
| 2473 | int enable_ips; |
Damien Lespiau | e5aa654 | 2014-02-07 19:12:53 +0000 | [diff] [blame] | 2474 | int invert_brightness; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2475 | int enable_cmd_parser; |
Damien Lespiau | e5aa654 | 2014-02-07 19:12:53 +0000 | [diff] [blame] | 2476 | /* leave bools at the end to not create holes */ |
| 2477 | bool enable_hangcheck; |
| 2478 | bool fastboot; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2479 | bool prefault_disable; |
Daniel Vetter | 5bedeb2 | 2015-03-03 18:03:47 +0100 | [diff] [blame] | 2480 | bool load_detect_test; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2481 | bool reset; |
Damien Lespiau | a0bae57 | 2014-02-10 17:20:55 +0000 | [diff] [blame] | 2482 | bool disable_display; |
Daniel Vetter | 7a10dfa | 2014-04-01 09:33:47 +0200 | [diff] [blame] | 2483 | bool disable_vtd_wa; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 2484 | int use_mmio_flip; |
Chris Wilson | 48572ed | 2014-12-18 10:55:50 +0000 | [diff] [blame] | 2485 | int mmio_debug; |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 2486 | bool verbose_state_checks; |
Matt Roper | b2e7723 | 2015-01-22 16:53:12 -0800 | [diff] [blame] | 2487 | bool nuclear_pageflip; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2488 | }; |
| 2489 | extern struct i915_params i915 __read_mostly; |
| 2490 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2491 | /* i915_dma.c */ |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 2492 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2493 | extern int i915_driver_unload(struct drm_device *); |
John Harrison | 2885f6a | 2014-06-26 18:23:52 +0100 | [diff] [blame] | 2494 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2495 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 2496 | extern void i915_driver_preclose(struct drm_device *dev, |
John Harrison | 2885f6a | 2014-06-26 18:23:52 +0100 | [diff] [blame] | 2497 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2498 | extern void i915_driver_postclose(struct drm_device *dev, |
John Harrison | 2885f6a | 2014-06-26 18:23:52 +0100 | [diff] [blame] | 2499 | struct drm_file *file); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2500 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2501 | #ifdef CONFIG_COMPAT |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 2502 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 2503 | unsigned long arg); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2504 | #endif |
Ben Widawsky | 8e96d9c | 2012-06-04 14:42:56 -0700 | [diff] [blame] | 2505 | extern int intel_gpu_reset(struct drm_device *dev); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 2506 | extern int i915_reset(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2507 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 2508 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 2509 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 2510 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 2511 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
Imre Deak | 1d0d343 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 2512 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2513 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2514 | /* i915_irq.c */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2515 | void i915_queue_hangcheck(struct drm_device *dev); |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2516 | __printf(3, 4) |
| 2517 | void i915_handle_error(struct drm_device *dev, bool wedged, |
| 2518 | const char *fmt, ...); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2519 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 2520 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
| 2521 | extern void intel_hpd_init(struct drm_i915_private *dev_priv); |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 2522 | int intel_irq_install(struct drm_i915_private *dev_priv); |
| 2523 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2524 | |
| 2525 | extern void intel_uncore_sanitize(struct drm_device *dev); |
Imre Deak | 1001860 | 2014-06-06 12:59:39 +0300 | [diff] [blame] | 2526 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
| 2527 | bool restore_forcewake); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2528 | extern void intel_uncore_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2529 | extern void intel_uncore_check_errors(struct drm_device *dev); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 2530 | extern void intel_uncore_fini(struct drm_device *dev); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 2531 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 2532 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 2533 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 2534 | enum forcewake_domains domains); |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 2535 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
Mika Kuoppala | 48c1026 | 2015-01-16 11:34:41 +0200 | [diff] [blame] | 2536 | enum forcewake_domains domains); |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 2537 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
Yu Zhang | cf9d289 | 2015-02-10 19:05:47 +0800 | [diff] [blame] | 2538 | static inline bool intel_vgpu_active(struct drm_device *dev) |
| 2539 | { |
| 2540 | return to_i915(dev)->vgpu.active; |
| 2541 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2542 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2543 | void |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 2544 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2545 | u32 status_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2546 | |
| 2547 | void |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 2548 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2549 | u32 status_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2550 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 2551 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
| 2552 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 2553 | void |
| 2554 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); |
| 2555 | void |
| 2556 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); |
| 2557 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 2558 | uint32_t interrupt_mask, |
| 2559 | uint32_t enabled_irq_mask); |
| 2560 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
| 2561 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
| 2562 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
| 2563 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 2564 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2565 | /* i915_gem.c */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2566 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 2567 | struct drm_file *file_priv); |
| 2568 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 2569 | struct drm_file *file_priv); |
| 2570 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 2571 | struct drm_file *file_priv); |
| 2572 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 2573 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2574 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2575 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2576 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 2577 | struct drm_file *file_priv); |
| 2578 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 2579 | struct drm_file *file_priv); |
Oscar Mateo | ba8b7cc | 2014-07-24 17:04:33 +0100 | [diff] [blame] | 2580 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
| 2581 | struct intel_engine_cs *ring); |
| 2582 | void i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
| 2583 | struct drm_file *file, |
| 2584 | struct intel_engine_cs *ring, |
| 2585 | struct drm_i915_gem_object *obj); |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 2586 | int i915_gem_ringbuffer_submission(struct drm_device *dev, |
| 2587 | struct drm_file *file, |
| 2588 | struct intel_engine_cs *ring, |
| 2589 | struct intel_context *ctx, |
| 2590 | struct drm_i915_gem_execbuffer2 *args, |
| 2591 | struct list_head *vmas, |
| 2592 | struct drm_i915_gem_object *batch_obj, |
| 2593 | u64 exec_start, u32 flags); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2594 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 2595 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 2596 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 2597 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2598 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 2599 | struct drm_file *file_priv); |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 2600 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 2601 | struct drm_file *file); |
| 2602 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 2603 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2604 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 2605 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2606 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 2607 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2608 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 2609 | struct drm_file *file_priv); |
| 2610 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 2611 | struct drm_file *file_priv); |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 2612 | int i915_gem_init_userptr(struct drm_device *dev); |
| 2613 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
| 2614 | struct drm_file *file); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 2615 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 2616 | struct drm_file *file_priv); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2617 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
| 2618 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2619 | void i915_gem_load(struct drm_device *dev); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 2620 | void *i915_gem_object_alloc(struct drm_device *dev); |
| 2621 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2622 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 2623 | const struct drm_i915_gem_object_ops *ops); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2624 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 2625 | size_t size); |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 2626 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 2627 | struct i915_address_space *vm); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2628 | void i915_gem_free_object(struct drm_gem_object *obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2629 | void i915_gem_vma_destroy(struct i915_vma *vma); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 2630 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2631 | #define PIN_MAPPABLE 0x1 |
| 2632 | #define PIN_NONBLOCK 0x2 |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 2633 | #define PIN_GLOBAL 0x4 |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 2634 | #define PIN_OFFSET_BIAS 0x8 |
| 2635 | #define PIN_OFFSET_MASK (~4095) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2636 | int __must_check |
| 2637 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 2638 | struct i915_address_space *vm, |
| 2639 | uint32_t alignment, |
| 2640 | uint64_t flags); |
| 2641 | int __must_check |
| 2642 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
| 2643 | const struct i915_ggtt_view *view, |
| 2644 | uint32_t alignment, |
| 2645 | uint64_t flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2646 | |
| 2647 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, |
| 2648 | u32 flags); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2649 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2650 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
Paulo Zanoni | 48018a5 | 2013-12-13 15:22:31 -0200 | [diff] [blame] | 2651 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2652 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2653 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 2654 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 2655 | int *needs_clflush); |
| 2656 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2657 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2658 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
| 2659 | { |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2660 | struct sg_page_iter sg_iter; |
Chris Wilson | 1cf8378 | 2012-10-10 12:11:52 +0100 | [diff] [blame] | 2661 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2662 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2663 | return sg_page_iter_page(&sg_iter); |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2664 | |
| 2665 | return NULL; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2666 | } |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2667 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
| 2668 | { |
| 2669 | BUG_ON(obj->pages == NULL); |
| 2670 | obj->pages_pin_count++; |
| 2671 | } |
| 2672 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
| 2673 | { |
| 2674 | BUG_ON(obj->pages_pin_count == 0); |
| 2675 | obj->pages_pin_count--; |
| 2676 | } |
| 2677 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2678 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2679 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2680 | struct intel_engine_cs *to); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2681 | void i915_vma_move_to_active(struct i915_vma *vma, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2682 | struct intel_engine_cs *ring); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2683 | int i915_gem_dumb_create(struct drm_file *file_priv, |
| 2684 | struct drm_device *dev, |
| 2685 | struct drm_mode_create_dumb *args); |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2686 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
| 2687 | uint32_t handle, uint64_t *offset); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2688 | /** |
| 2689 | * Returns true if seq1 is later than seq2. |
| 2690 | */ |
| 2691 | static inline bool |
| 2692 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 2693 | { |
| 2694 | return (int32_t)(seq1 - seq2) >= 0; |
| 2695 | } |
| 2696 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2697 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
| 2698 | bool lazy_coherency) |
| 2699 | { |
| 2700 | u32 seqno; |
| 2701 | |
| 2702 | BUG_ON(req == NULL); |
| 2703 | |
| 2704 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
| 2705 | |
| 2706 | return i915_seqno_passed(seqno, req->seqno); |
| 2707 | } |
| 2708 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2709 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
| 2710 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2711 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2712 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2713 | |
Daniel Vetter | d8ffa60 | 2014-05-13 12:11:26 +0200 | [diff] [blame] | 2714 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
| 2715 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2716 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2717 | struct drm_i915_gem_request * |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2718 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2719 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2720 | bool i915_gem_retire_requests(struct drm_device *dev); |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2721 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2722 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 2723 | bool interruptible); |
John Harrison | b6660d5 | 2014-11-24 18:49:30 +0000 | [diff] [blame] | 2724 | int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 2725 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2726 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
| 2727 | { |
| 2728 | return unlikely(atomic_read(&error->reset_counter) |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2729 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2730 | } |
| 2731 | |
| 2732 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
| 2733 | { |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2734 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
| 2735 | } |
| 2736 | |
| 2737 | static inline u32 i915_reset_count(struct i915_gpu_error *error) |
| 2738 | { |
| 2739 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2740 | } |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2741 | |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 2742 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
| 2743 | { |
| 2744 | return dev_priv->gpu_error.stop_rings == 0 || |
| 2745 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; |
| 2746 | } |
| 2747 | |
| 2748 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) |
| 2749 | { |
| 2750 | return dev_priv->gpu_error.stop_rings == 0 || |
| 2751 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; |
| 2752 | } |
| 2753 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2754 | void i915_gem_reset(struct drm_device *dev); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 2755 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2756 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 2757 | int __must_check i915_gem_init(struct drm_device *dev); |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 2758 | int i915_gem_init_rings(struct drm_device *dev); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2759 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2760 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2761 | void i915_gem_init_swizzling(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2762 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2763 | int __must_check i915_gpu_idle(struct drm_device *dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 2764 | int __must_check i915_gem_suspend(struct drm_device *dev); |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2765 | int __i915_add_request(struct intel_engine_cs *ring, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2766 | struct drm_file *file, |
John Harrison | 9400ae5 | 2014-11-24 18:49:36 +0000 | [diff] [blame] | 2767 | struct drm_i915_gem_object *batch_obj); |
| 2768 | #define i915_add_request(ring) \ |
| 2769 | __i915_add_request(ring, NULL, NULL) |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 2770 | int __i915_wait_request(struct drm_i915_gem_request *req, |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 2771 | unsigned reset_counter, |
| 2772 | bool interruptible, |
| 2773 | s64 *timeout, |
| 2774 | struct drm_i915_file_private *file_priv); |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2775 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2776 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2777 | int __must_check |
| 2778 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 2779 | bool write); |
| 2780 | int __must_check |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 2781 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
| 2782 | int __must_check |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2783 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2784 | u32 alignment, |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 2785 | struct intel_engine_cs *pipelined, |
| 2786 | const struct i915_ggtt_view *view); |
| 2787 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
| 2788 | const struct i915_ggtt_view *view); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 2789 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 2790 | int align); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2791 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2792 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2793 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2794 | uint32_t |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 2795 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
| 2796 | uint32_t |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2797 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 2798 | int tiling_mode, bool fenced); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2799 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2800 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2801 | enum i915_cache_level cache_level); |
| 2802 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2803 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
| 2804 | struct dma_buf *dma_buf); |
| 2805 | |
| 2806 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
| 2807 | struct drm_gem_object *gem_obj, int flags); |
| 2808 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2809 | void i915_gem_restore_fences(struct drm_device *dev); |
| 2810 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2811 | unsigned long |
| 2812 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 2813 | const struct i915_ggtt_view *view); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2814 | unsigned long |
| 2815 | i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 2816 | struct i915_address_space *vm); |
| 2817 | static inline unsigned long |
| 2818 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2819 | { |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 2820 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2821 | } |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2822 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2823 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2824 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 2825 | const struct i915_ggtt_view *view); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2826 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2827 | struct i915_address_space *vm); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2828 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2829 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 2830 | struct i915_address_space *vm); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2831 | struct i915_vma * |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2832 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 2833 | struct i915_address_space *vm); |
| 2834 | struct i915_vma * |
| 2835 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
| 2836 | const struct i915_ggtt_view *view); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2837 | |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 2838 | struct i915_vma * |
| 2839 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2840 | struct i915_address_space *vm); |
| 2841 | struct i915_vma * |
| 2842 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, |
| 2843 | const struct i915_ggtt_view *view); |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2844 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2845 | static inline struct i915_vma * |
| 2846 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
| 2847 | { |
| 2848 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2849 | } |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2850 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2851 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2852 | /* Some GGTT VM helpers */ |
Daniel Vetter | 5dc383b | 2014-08-06 15:04:49 +0200 | [diff] [blame] | 2853 | #define i915_obj_to_ggtt(obj) \ |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2854 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
| 2855 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
| 2856 | { |
| 2857 | struct i915_address_space *ggtt = |
| 2858 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
| 2859 | return vm == ggtt; |
| 2860 | } |
| 2861 | |
Daniel Vetter | 841cd77 | 2014-08-06 15:04:48 +0200 | [diff] [blame] | 2862 | static inline struct i915_hw_ppgtt * |
| 2863 | i915_vm_to_ppgtt(struct i915_address_space *vm) |
| 2864 | { |
| 2865 | WARN_ON(i915_is_ggtt(vm)); |
| 2866 | |
| 2867 | return container_of(vm, struct i915_hw_ppgtt, base); |
| 2868 | } |
| 2869 | |
| 2870 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2871 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
| 2872 | { |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 2873 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2874 | } |
| 2875 | |
| 2876 | static inline unsigned long |
| 2877 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
| 2878 | { |
Daniel Vetter | 5dc383b | 2014-08-06 15:04:49 +0200 | [diff] [blame] | 2879 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2880 | } |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2881 | |
| 2882 | static inline int __must_check |
| 2883 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
| 2884 | uint32_t alignment, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2885 | unsigned flags) |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2886 | { |
Daniel Vetter | 5dc383b | 2014-08-06 15:04:49 +0200 | [diff] [blame] | 2887 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
| 2888 | alignment, flags | PIN_GLOBAL); |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2889 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2890 | |
Daniel Vetter | b287110 | 2014-02-14 14:01:19 +0100 | [diff] [blame] | 2891 | static inline int |
| 2892 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
| 2893 | { |
| 2894 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); |
| 2895 | } |
| 2896 | |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 2897 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
| 2898 | const struct i915_ggtt_view *view); |
| 2899 | static inline void |
| 2900 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
| 2901 | { |
| 2902 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); |
| 2903 | } |
Daniel Vetter | b287110 | 2014-02-14 14:01:19 +0100 | [diff] [blame] | 2904 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2905 | /* i915_gem_context.c */ |
Ben Widawsky | 8245be3 | 2013-11-06 13:56:29 -0200 | [diff] [blame] | 2906 | int __must_check i915_gem_context_init(struct drm_device *dev); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2907 | void i915_gem_context_fini(struct drm_device *dev); |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2908 | void i915_gem_context_reset(struct drm_device *dev); |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 2909 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 2910 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2911 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2912 | int i915_switch_context(struct intel_engine_cs *ring, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2913 | struct intel_context *to); |
| 2914 | struct intel_context * |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 2915 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2916 | void i915_gem_context_free(struct kref *ctx_ref); |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 2917 | struct drm_i915_gem_object * |
| 2918 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2919 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2920 | { |
Chris Wilson | 691e641 | 2014-04-09 09:07:36 +0100 | [diff] [blame] | 2921 | kref_get(&ctx->ref); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2922 | } |
| 2923 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2924 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2925 | { |
Chris Wilson | 691e641 | 2014-04-09 09:07:36 +0100 | [diff] [blame] | 2926 | kref_put(&ctx->ref, i915_gem_context_free); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2927 | } |
| 2928 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2929 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2930 | { |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 2931 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2932 | } |
| 2933 | |
Ben Widawsky | 8462481 | 2012-06-04 14:42:54 -0700 | [diff] [blame] | 2934 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 2935 | struct drm_file *file); |
| 2936 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 2937 | struct drm_file *file); |
Chris Wilson | c9dc0f3 | 2014-12-24 08:13:40 -0800 | [diff] [blame] | 2938 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
| 2939 | struct drm_file *file_priv); |
| 2940 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
| 2941 | struct drm_file *file_priv); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2942 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2943 | /* i915_gem_evict.c */ |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 2944 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
| 2945 | struct i915_address_space *vm, |
| 2946 | int min_size, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2947 | unsigned alignment, |
| 2948 | unsigned cache_level, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 2949 | unsigned long start, |
| 2950 | unsigned long end, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2951 | unsigned flags); |
Ben Widawsky | 68c8c17 | 2013-09-11 14:57:50 -0700 | [diff] [blame] | 2952 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2953 | int i915_gem_evict_everything(struct drm_device *dev); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2954 | |
Ben Widawsky | 0260c42 | 2014-03-22 22:47:21 -0700 | [diff] [blame] | 2955 | /* belongs in i915_gem_gtt.h */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2956 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
| 2957 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2958 | if (INTEL_INFO(dev)->gen < 6) |
| 2959 | intel_gtt_chipset_flush(); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2960 | } |
Ben Widawsky | 246cbfb | 2013-12-06 14:11:14 -0800 | [diff] [blame] | 2961 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2962 | /* i915_gem_stolen.c */ |
| 2963 | int i915_gem_init_stolen(struct drm_device *dev); |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 2964 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 2965 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2966 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2967 | struct drm_i915_gem_object * |
| 2968 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
Chris Wilson | 866d12b | 2013-02-19 13:31:37 -0800 | [diff] [blame] | 2969 | struct drm_i915_gem_object * |
| 2970 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
| 2971 | u32 stolen_offset, |
| 2972 | u32 gtt_offset, |
| 2973 | u32 size); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2974 | |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 2975 | /* i915_gem_shrinker.c */ |
| 2976 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, |
| 2977 | long target, |
| 2978 | unsigned flags); |
| 2979 | #define I915_SHRINK_PURGEABLE 0x1 |
| 2980 | #define I915_SHRINK_UNBOUND 0x2 |
| 2981 | #define I915_SHRINK_BOUND 0x4 |
| 2982 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
| 2983 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); |
| 2984 | |
| 2985 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2986 | /* i915_gem_tiling.c */ |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 2987 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 2988 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 2989 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 2990 | |
| 2991 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 2992 | obj->tiling_mode != I915_TILING_NONE; |
| 2993 | } |
| 2994 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2995 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2996 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 2997 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2998 | |
| 2999 | /* i915_gem_debug.c */ |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3000 | #if WATCH_LISTS |
| 3001 | int i915_verify_lists(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3002 | #else |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3003 | #define i915_verify_lists(dev) 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3004 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3005 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3006 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3007 | int i915_debugfs_init(struct drm_minor *minor); |
| 3008 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 3009 | #ifdef CONFIG_DEBUG_FS |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3010 | void intel_display_crc_init(struct drm_device *dev); |
| 3011 | #else |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 3012 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3013 | #endif |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 3014 | |
| 3015 | /* i915_gpu_error.c */ |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 3016 | __printf(2, 3) |
| 3017 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 3018 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
| 3019 | const struct i915_error_state_file_priv *error); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 3020 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 3021 | struct drm_i915_private *i915, |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 3022 | size_t count, loff_t pos); |
| 3023 | static inline void i915_error_state_buf_release( |
| 3024 | struct drm_i915_error_state_buf *eb) |
| 3025 | { |
| 3026 | kfree(eb->buf); |
| 3027 | } |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3028 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
| 3029 | const char *error_msg); |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 3030 | void i915_error_state_get(struct drm_device *dev, |
| 3031 | struct i915_error_state_file_priv *error_priv); |
| 3032 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
| 3033 | void i915_destroy_error_state(struct drm_device *dev); |
| 3034 | |
| 3035 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 3036 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3037 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 3038 | /* i915_gem_batch_pool.c */ |
| 3039 | void i915_gem_batch_pool_init(struct drm_device *dev, |
| 3040 | struct i915_gem_batch_pool *pool); |
| 3041 | void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool); |
| 3042 | struct drm_i915_gem_object* |
| 3043 | i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size); |
| 3044 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 3045 | /* i915_cmd_parser.c */ |
Brad Volkin | d728c8e | 2014-02-18 10:15:56 -0800 | [diff] [blame] | 3046 | int i915_cmd_parser_get_version(void); |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3047 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
| 3048 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); |
| 3049 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); |
| 3050 | int i915_parse_cmds(struct intel_engine_cs *ring, |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 3051 | struct drm_i915_gem_object *batch_obj, |
Brad Volkin | 78a4237 | 2014-12-11 12:13:09 -0800 | [diff] [blame] | 3052 | struct drm_i915_gem_object *shadow_batch_obj, |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 3053 | u32 batch_start_offset, |
Brad Volkin | b9ffd80 | 2014-12-11 12:13:10 -0800 | [diff] [blame] | 3054 | u32 batch_len, |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 3055 | bool is_master); |
| 3056 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 3057 | /* i915_suspend.c */ |
| 3058 | extern int i915_save_state(struct drm_device *dev); |
| 3059 | extern int i915_restore_state(struct drm_device *dev); |
| 3060 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 3061 | /* i915_sysfs.c */ |
| 3062 | void i915_setup_sysfs(struct drm_device *dev_priv); |
| 3063 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
| 3064 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 3065 | /* intel_i2c.c */ |
| 3066 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 3067 | extern void intel_teardown_gmbus(struct drm_device *dev); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 3068 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 3069 | { |
Jani Nikula | 988c701 | 2015-03-27 00:20:19 +0200 | [diff] [blame^] | 3070 | return (port >= GMBUS_PIN_SSC && port <= GMBUS_PIN_DPD); |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 3071 | } |
| 3072 | |
| 3073 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
| 3074 | struct drm_i915_private *dev_priv, unsigned port); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 3075 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 3076 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 3077 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
Chris Wilson | b8232e9 | 2010-09-28 16:41:32 +0100 | [diff] [blame] | 3078 | { |
| 3079 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 3080 | } |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 3081 | extern void intel_i2c_reset(struct drm_device *dev); |
| 3082 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 3083 | /* intel_opregion.c */ |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 3084 | #ifdef CONFIG_ACPI |
Lv Zheng | 27d50c8 | 2013-12-06 16:52:05 +0800 | [diff] [blame] | 3085 | extern int intel_opregion_setup(struct drm_device *dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 3086 | extern void intel_opregion_init(struct drm_device *dev); |
| 3087 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 3088 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 3089 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
| 3090 | bool enable); |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 3091 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
| 3092 | pci_power_t state); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 3093 | #else |
Lv Zheng | 27d50c8 | 2013-12-06 16:52:05 +0800 | [diff] [blame] | 3094 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 3095 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 3096 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 3097 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 3098 | static inline int |
| 3099 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
| 3100 | { |
| 3101 | return 0; |
| 3102 | } |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 3103 | static inline int |
| 3104 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
| 3105 | { |
| 3106 | return 0; |
| 3107 | } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 3108 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 3109 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 3110 | /* intel_acpi.c */ |
| 3111 | #ifdef CONFIG_ACPI |
| 3112 | extern void intel_register_dsm_handler(void); |
| 3113 | extern void intel_unregister_dsm_handler(void); |
| 3114 | #else |
| 3115 | static inline void intel_register_dsm_handler(void) { return; } |
| 3116 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 3117 | #endif /* CONFIG_ACPI */ |
| 3118 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3119 | /* modesetting */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 3120 | extern void intel_modeset_init_hw(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3121 | extern void intel_modeset_init(struct drm_device *dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 3122 | extern void intel_modeset_gem_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3123 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 3124 | extern void intel_connector_unregister(struct intel_connector *); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 3125 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 3126 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 3127 | bool force_restore); |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 3128 | extern void i915_redisable_vga(struct drm_device *dev); |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 3129 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 3130 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 3131 | extern void intel_init_pch_refclk(struct drm_device *dev); |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 3132 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 3133 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
| 3134 | bool enable); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3135 | extern void intel_detect_pch(struct drm_device *dev); |
| 3136 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 3137 | extern int intel_enable_rc6(const struct drm_device *dev); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 3138 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3139 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 3140 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
| 3141 | struct drm_file *file); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 3142 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
| 3143 | struct drm_file *file); |
Jesse Barnes | 575155a | 2012-03-28 13:39:37 -0700 | [diff] [blame] | 3144 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 3145 | /* overlay */ |
| 3146 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 3147 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
| 3148 | struct intel_overlay_error_state *error); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 3149 | |
| 3150 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 3151 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 3152 | struct drm_device *dev, |
| 3153 | struct intel_display_error_state *error); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 3154 | |
Tom O'Rourke | 151a49d | 2014-11-13 18:50:10 -0800 | [diff] [blame] | 3155 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
| 3156 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 3157 | |
| 3158 | /* intel_sideband.c */ |
Deepak S | 707b6e3 | 2015-01-16 20:42:17 +0530 | [diff] [blame] | 3159 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
| 3160 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3161 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 3162 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
| 3163 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 3164 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
| 3165 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 3166 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
| 3167 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jesse Barnes | f341915 | 2013-11-04 11:52:44 -0800 | [diff] [blame] | 3168 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
| 3169 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 3170 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
| 3171 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 3172 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
| 3173 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 3174 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 3175 | enum intel_sbi_destination destination); |
| 3176 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 3177 | enum intel_sbi_destination destination); |
Shobhit Kumar | e9fe51c | 2013-12-10 12:14:55 +0530 | [diff] [blame] | 3178 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
| 3179 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3180 | |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 3181 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
| 3182 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3183 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 3184 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
| 3185 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 3186 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 3187 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
| 3188 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
| 3189 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
| 3190 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 3191 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 3192 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
| 3193 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
| 3194 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
| 3195 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 3196 | |
Chris Wilson | 698b313 | 2014-03-21 13:16:43 +0000 | [diff] [blame] | 3197 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
| 3198 | * will be implemented using 2 32-bit writes in an arbitrary order with |
| 3199 | * an arbitrary delay between them. This can cause the hardware to |
| 3200 | * act upon the intermediate value, possibly leading to corruption and |
| 3201 | * machine death. You have been warned. |
| 3202 | */ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 3203 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
| 3204 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 3205 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 3206 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
| 3207 | u32 upper = I915_READ(upper_reg); \ |
| 3208 | u32 lower = I915_READ(lower_reg); \ |
| 3209 | u32 tmp = I915_READ(upper_reg); \ |
| 3210 | if (upper != tmp) { \ |
| 3211 | upper = tmp; \ |
| 3212 | lower = I915_READ(lower_reg); \ |
| 3213 | WARN_ON(I915_READ(upper_reg) != upper); \ |
| 3214 | } \ |
| 3215 | (u64)upper << 32 | lower; }) |
| 3216 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 3217 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 3218 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 3219 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 3220 | /* "Broadcast RGB" property */ |
| 3221 | #define INTEL_BROADCAST_RGB_AUTO 0 |
| 3222 | #define INTEL_BROADCAST_RGB_FULL 1 |
| 3223 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 3224 | |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 3225 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
| 3226 | { |
Sonika Jindal | 92e23b9 | 2014-07-21 15:23:40 +0530 | [diff] [blame] | 3227 | if (IS_VALLEYVIEW(dev)) |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 3228 | return VLV_VGACNTRL; |
Sonika Jindal | 92e23b9 | 2014-07-21 15:23:40 +0530 | [diff] [blame] | 3229 | else if (INTEL_INFO(dev)->gen >= 5) |
| 3230 | return CPU_VGACNTRL; |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 3231 | else |
| 3232 | return VGACNTRL; |
| 3233 | } |
| 3234 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 3235 | static inline void __user *to_user_ptr(u64 address) |
| 3236 | { |
| 3237 | return (void __user *)(uintptr_t)address; |
| 3238 | } |
| 3239 | |
Imre Deak | df97729 | 2013-05-21 20:03:17 +0300 | [diff] [blame] | 3240 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
| 3241 | { |
| 3242 | unsigned long j = msecs_to_jiffies(m); |
| 3243 | |
| 3244 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 3245 | } |
| 3246 | |
Daniel Vetter | 7bd0e22 | 2014-12-04 11:12:54 +0100 | [diff] [blame] | 3247 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
| 3248 | { |
| 3249 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); |
| 3250 | } |
| 3251 | |
Imre Deak | df97729 | 2013-05-21 20:03:17 +0300 | [diff] [blame] | 3252 | static inline unsigned long |
| 3253 | timespec_to_jiffies_timeout(const struct timespec *value) |
| 3254 | { |
| 3255 | unsigned long j = timespec_to_jiffies(value); |
| 3256 | |
| 3257 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 3258 | } |
| 3259 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 3260 | /* |
| 3261 | * If you need to wait X milliseconds between events A and B, but event B |
| 3262 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of |
| 3263 | * when event A happened, then just before event B you call this function and |
| 3264 | * pass the timestamp as the first argument, and X as the second argument. |
| 3265 | */ |
| 3266 | static inline void |
| 3267 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) |
| 3268 | { |
Imre Deak | ec5e0cf | 2014-01-29 13:25:40 +0200 | [diff] [blame] | 3269 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 3270 | |
| 3271 | /* |
| 3272 | * Don't re-read the value of "jiffies" every time since it may change |
| 3273 | * behind our back and break the math. |
| 3274 | */ |
| 3275 | tmp_jiffies = jiffies; |
| 3276 | target_jiffies = timestamp_jiffies + |
| 3277 | msecs_to_jiffies_timeout(to_wait_ms); |
| 3278 | |
| 3279 | if (time_after(target_jiffies, tmp_jiffies)) { |
Imre Deak | ec5e0cf | 2014-01-29 13:25:40 +0200 | [diff] [blame] | 3280 | remaining_jiffies = target_jiffies - tmp_jiffies; |
| 3281 | while (remaining_jiffies) |
| 3282 | remaining_jiffies = |
| 3283 | schedule_timeout_uninterruptible(remaining_jiffies); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 3284 | } |
| 3285 | } |
| 3286 | |
John Harrison | 581c26e8 | 2014-11-24 18:49:39 +0000 | [diff] [blame] | 3287 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
| 3288 | struct drm_i915_gem_request *req) |
| 3289 | { |
| 3290 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) |
| 3291 | i915_gem_request_assign(&ring->trace_irq_req, req); |
| 3292 | } |
| 3293 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3294 | #endif |