blob: 997b4178249a42f4a731dd1913601b204ce67ce4 [file] [log] [blame]
Loc Ho81d01bf2014-03-14 17:53:20 -06001/*
2 * AppliedMicro X-Gene SoC SATA Host Controller Driver
3 *
4 * Copyright (c) 2014, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 * Tuan Phan <tphan@apm.com>
7 * Suman Tripathi <stripathi@apm.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * NOTE: PM support is not currently available.
23 *
24 */
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/ahci_platform.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/phy/phy.h>
31#include "ahci.h"
32
33/* Max # of disk per a controller */
34#define MAX_AHCI_CHN_PERCTR 2
35
36/* MUX CSR */
37#define SATA_ENET_CONFIG_REG 0x00000000
38#define CFG_SATA_ENET_SELECT_MASK 0x00000001
39
40/* SATA core host controller CSR */
41#define SLVRDERRATTRIBUTES 0x00000000
42#define SLVWRERRATTRIBUTES 0x00000004
43#define MSTRDERRATTRIBUTES 0x00000008
44#define MSTWRERRATTRIBUTES 0x0000000c
45#define BUSCTLREG 0x00000014
46#define IOFMSTRWAUX 0x00000018
47#define INTSTATUSMASK 0x0000002c
48#define ERRINTSTATUS 0x00000030
49#define ERRINTSTATUSMASK 0x00000034
50
51/* SATA host AHCI CSR */
52#define PORTCFG 0x000000a4
53#define PORTADDR_SET(dst, src) \
54 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
55#define PORTPHY1CFG 0x000000a8
56#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
57 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
58#define PORTPHY2CFG 0x000000ac
59#define PORTPHY3CFG 0x000000b0
60#define PORTPHY4CFG 0x000000b4
61#define PORTPHY5CFG 0x000000b8
62#define SCTL0 0x0000012C
63#define PORTPHY5CFG_RTCHG_SET(dst, src) \
64 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
65#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
66 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
67#define PORTAXICFG 0x000000bc
68#define PORTAXICFG_OUTTRANS_SET(dst, src) \
69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
Suman Tripathiaeae4dc2014-07-29 12:24:49 +053070#define PORTRANSCFG 0x000000c8
71#define PORTRANSCFG_RXWM_SET(dst, src) \
72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
Loc Ho81d01bf2014-03-14 17:53:20 -060073
74/* SATA host controller AXI CSR */
75#define INT_SLV_TMOMASK 0x00000010
76
77/* SATA diagnostic CSR */
78#define CFG_MEM_RAM_SHUTDOWN 0x00000070
79#define BLOCK_MEM_RDY 0x00000074
80
81struct xgene_ahci_context {
82 struct ahci_host_priv *hpriv;
83 struct device *dev;
84 void __iomem *csr_core; /* Core CSR address of IP */
85 void __iomem *csr_diag; /* Diag CSR address of IP */
86 void __iomem *csr_axi; /* AXI CSR address of IP */
87 void __iomem *csr_mux; /* MUX CSR address of IP */
88};
89
90static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
91{
92 dev_dbg(ctx->dev, "Release memory from shutdown\n");
93 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
94 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
95 msleep(1); /* reset may take up to 1ms */
96 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
97 dev_err(ctx->dev, "failed to release memory from shutdown\n");
98 return -ENODEV;
99 }
100 return 0;
101}
102
103/**
104 * xgene_ahci_read_id - Read ID data from the specified device
105 * @dev: device
106 * @tf: proposed taskfile
107 * @id: data buffer
108 *
109 * This custom read ID function is required due to the fact that the HW
110 * does not support DEVSLP and the controller state machine may get stuck
111 * after processing the ID query command.
112 */
113static unsigned int xgene_ahci_read_id(struct ata_device *dev,
114 struct ata_taskfile *tf, u16 *id)
115{
116 u32 err_mask;
117 void __iomem *port_mmio = ahci_port_base(dev->link->ap);
118
119 err_mask = ata_do_dev_read_id(dev, tf, id);
120 if (err_mask)
121 return err_mask;
122
123 /*
124 * Mask reserved area. Word78 spec of Link Power Management
125 * bit15-8: reserved
126 * bit7: NCQ autosence
127 * bit6: Software settings preservation supported
128 * bit5: reserved
129 * bit4: In-order sata delivery supported
130 * bit3: DIPM requests supported
131 * bit2: DMA Setup FIS Auto-Activate optimization supported
132 * bit1: DMA Setup FIX non-Zero buffer offsets supported
133 * bit0: Reserved
134 *
135 * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
136 */
137 id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8);
138
139 /*
140 * Due to HW errata, restart the port if no other command active.
141 * Otherwise the controller may get stuck.
142 */
143 if (!readl(port_mmio + PORT_CMD_ISSUE)) {
144 writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD);
145 readl(port_mmio + PORT_CMD); /* Force a barrier */
146 writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD);
147 readl(port_mmio + PORT_CMD); /* Force a barrier */
148 }
149 return 0;
150}
151
152static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
153{
154 void __iomem *mmio = ctx->hpriv->mmio;
155 u32 val;
156
157 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
158 mmio, channel);
159 val = readl(mmio + PORTCFG);
160 val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
161 writel(val, mmio + PORTCFG);
162 readl(mmio + PORTCFG); /* Force a barrier */
163 /* Disable fix rate */
164 writel(0x0001fffe, mmio + PORTPHY1CFG);
165 readl(mmio + PORTPHY1CFG); /* Force a barrier */
Suman Tripathi0185b1b2014-07-29 12:24:51 +0530166 writel(0x28183219, mmio + PORTPHY2CFG);
Loc Ho81d01bf2014-03-14 17:53:20 -0600167 readl(mmio + PORTPHY2CFG); /* Force a barrier */
Suman Tripathi0185b1b2014-07-29 12:24:51 +0530168 writel(0x13081008, mmio + PORTPHY3CFG);
Loc Ho81d01bf2014-03-14 17:53:20 -0600169 readl(mmio + PORTPHY3CFG); /* Force a barrier */
Suman Tripathi0185b1b2014-07-29 12:24:51 +0530170 writel(0x00480815, mmio + PORTPHY4CFG);
Loc Ho81d01bf2014-03-14 17:53:20 -0600171 readl(mmio + PORTPHY4CFG); /* Force a barrier */
172 /* Set window negotiation */
173 val = readl(mmio + PORTPHY5CFG);
174 val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
175 writel(val, mmio + PORTPHY5CFG);
176 readl(mmio + PORTPHY5CFG); /* Force a barrier */
177 val = readl(mmio + PORTAXICFG);
178 val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
179 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
180 writel(val, mmio + PORTAXICFG);
181 readl(mmio + PORTAXICFG); /* Force a barrier */
Suman Tripathiaeae4dc2014-07-29 12:24:49 +0530182 /* Set the watermark threshold of the receive FIFO */
183 val = readl(mmio + PORTRANSCFG);
184 val = PORTRANSCFG_RXWM_SET(val, 0x30);
185 writel(val, mmio + PORTRANSCFG);
Loc Ho81d01bf2014-03-14 17:53:20 -0600186}
187
188/**
189 * xgene_ahci_do_hardreset - Issue the actual COMRESET
190 * @link: link to reset
191 * @deadline: deadline jiffies for the operation
192 * @online: Return value to indicate if device online
193 *
194 * Due to the limitation of the hardware PHY, a difference set of setting is
195 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
196 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
197 * report disparity error and etc. In addition, during COMRESET, there can
198 * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
199 * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following
200 * algorithm is followed to proper configure the hardware PHY during COMRESET:
201 *
202 * Alg Part 1:
203 * 1. Start the PHY at Gen3 speed (default setting)
204 * 2. Issue the COMRESET
205 * 3. If no link, go to Alg Part 3
206 * 4. If link up, determine if the negotiated speed matches the PHY
207 * configured speed
208 * 5. If they matched, go to Alg Part 2
209 * 6. If they do not matched and first time, configure the PHY for the linked
210 * up disk speed and repeat step 2
211 * 7. Go to Alg Part 2
212 *
213 * Alg Part 2:
214 * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
215 * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
216 * 2. Go to Alg Part 3
217 *
218 * Alg Part 3:
219 * 1. Clear any pending from register PORT_SCR_ERR.
220 *
221 * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
222 * and until the underlying PHY supports an method to reset the receiver
223 * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
224 * an warning message will be printed.
225 */
226static int xgene_ahci_do_hardreset(struct ata_link *link,
227 unsigned long deadline, bool *online)
228{
229 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
230 struct ata_port *ap = link->ap;
231 struct ahci_host_priv *hpriv = ap->host->private_data;
232 struct xgene_ahci_context *ctx = hpriv->plat_data;
233 struct ahci_port_priv *pp = ap->private_data;
234 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
235 void __iomem *port_mmio = ahci_port_base(ap);
236 struct ata_taskfile tf;
237 int rc;
238 u32 val;
239
240 /* clear D2H reception area to properly wait for D2H FIS */
241 ata_tf_init(link->device, &tf);
242 tf.command = ATA_BUSY;
243 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
244 rc = sata_link_hardreset(link, timing, deadline, online,
245 ahci_check_ready);
246
247 val = readl(port_mmio + PORT_SCR_ERR);
248 if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
249 dev_warn(ctx->dev, "link has error\n");
250
251 /* clear all errors if any pending */
252 val = readl(port_mmio + PORT_SCR_ERR);
253 writel(val, port_mmio + PORT_SCR_ERR);
254
255 return rc;
256}
257
258static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
259 unsigned long deadline)
260{
261 struct ata_port *ap = link->ap;
262 struct ahci_host_priv *hpriv = ap->host->private_data;
263 void __iomem *port_mmio = ahci_port_base(ap);
264 bool online;
265 int rc;
266 u32 portcmd_saved;
267 u32 portclb_saved;
268 u32 portclbhi_saved;
269 u32 portrxfis_saved;
270 u32 portrxfishi_saved;
271
272 /* As hardreset resets these CSR, save it to restore later */
273 portcmd_saved = readl(port_mmio + PORT_CMD);
274 portclb_saved = readl(port_mmio + PORT_LST_ADDR);
275 portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
276 portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
277 portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
278
279 ahci_stop_engine(ap);
280
281 rc = xgene_ahci_do_hardreset(link, deadline, &online);
282
283 /* As controller hardreset clears them, restore them */
284 writel(portcmd_saved, port_mmio + PORT_CMD);
285 writel(portclb_saved, port_mmio + PORT_LST_ADDR);
286 writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
287 writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
288 writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
289
290 hpriv->start_engine(ap);
291
292 if (online)
293 *class = ahci_dev_classify(ap);
294
295 return rc;
296}
297
298static void xgene_ahci_host_stop(struct ata_host *host)
299{
300 struct ahci_host_priv *hpriv = host->private_data;
301
302 ahci_platform_disable_resources(hpriv);
303}
304
305static struct ata_port_operations xgene_ahci_ops = {
306 .inherits = &ahci_ops,
307 .host_stop = xgene_ahci_host_stop,
308 .hardreset = xgene_ahci_hardreset,
309 .read_id = xgene_ahci_read_id,
310};
311
312static const struct ata_port_info xgene_ahci_port_info = {
Loc Ho81d01bf2014-03-14 17:53:20 -0600313 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
314 .pio_mask = ATA_PIO4,
315 .udma_mask = ATA_UDMA6,
316 .port_ops = &xgene_ahci_ops,
317};
318
319static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
320{
321 struct xgene_ahci_context *ctx = hpriv->plat_data;
322 int i;
323 int rc;
324 u32 val;
325
326 /* Remove IP RAM out of shutdown */
327 rc = xgene_ahci_init_memram(ctx);
328 if (rc)
329 return rc;
330
331 for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
332 xgene_ahci_set_phy_cfg(ctx, i);
333
334 /* AXI disable Mask */
335 writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
336 readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
337 writel(0, ctx->csr_core + INTSTATUSMASK);
Loc Ho6a969182014-03-18 12:14:37 -0600338 val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
Loc Ho81d01bf2014-03-14 17:53:20 -0600339 dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
340 INTSTATUSMASK, val);
341
342 writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
343 readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
344 writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
345 readl(ctx->csr_axi + INT_SLV_TMOMASK);
346
347 /* Enable AXI Interrupt */
348 writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
349 writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
350 writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
351 writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
352
353 /* Enable coherency */
354 val = readl(ctx->csr_core + BUSCTLREG);
355 val &= ~0x00000002; /* Enable write coherency */
356 val &= ~0x00000001; /* Enable read coherency */
357 writel(val, ctx->csr_core + BUSCTLREG);
358
359 val = readl(ctx->csr_core + IOFMSTRWAUX);
360 val |= (1 << 3); /* Enable read coherency */
361 val |= (1 << 9); /* Enable write coherency */
362 writel(val, ctx->csr_core + IOFMSTRWAUX);
363 val = readl(ctx->csr_core + IOFMSTRWAUX);
364 dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
365 IOFMSTRWAUX, val);
366
367 return rc;
368}
369
370static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
371{
372 u32 val;
373
374 /* Check for optional MUX resource */
375 if (IS_ERR(ctx->csr_mux))
376 return 0;
377
378 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
379 val &= ~CFG_SATA_ENET_SELECT_MASK;
380 writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
381 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
382 return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
383}
384
385static int xgene_ahci_probe(struct platform_device *pdev)
386{
387 struct device *dev = &pdev->dev;
388 struct ahci_host_priv *hpriv;
389 struct xgene_ahci_context *ctx;
390 struct resource *res;
Kefeng Wangf9f36912014-05-14 14:13:41 +0800391 unsigned long hflags;
Loc Ho81d01bf2014-03-14 17:53:20 -0600392 int rc;
393
394 hpriv = ahci_platform_get_resources(pdev);
395 if (IS_ERR(hpriv))
396 return PTR_ERR(hpriv);
397
398 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
399 if (!ctx)
400 return -ENOMEM;
401
402 hpriv->plat_data = ctx;
403 ctx->hpriv = hpriv;
404 ctx->dev = dev;
405
406 /* Retrieve the IP core resource */
407 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
408 ctx->csr_core = devm_ioremap_resource(dev, res);
409 if (IS_ERR(ctx->csr_core))
410 return PTR_ERR(ctx->csr_core);
411
412 /* Retrieve the IP diagnostic resource */
413 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
414 ctx->csr_diag = devm_ioremap_resource(dev, res);
415 if (IS_ERR(ctx->csr_diag))
416 return PTR_ERR(ctx->csr_diag);
417
418 /* Retrieve the IP AXI resource */
419 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
420 ctx->csr_axi = devm_ioremap_resource(dev, res);
421 if (IS_ERR(ctx->csr_axi))
422 return PTR_ERR(ctx->csr_axi);
423
424 /* Retrieve the optional IP mux resource */
425 res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
426 ctx->csr_mux = devm_ioremap_resource(dev, res);
427
428 dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
429 hpriv->mmio);
430
431 /* Select ATA */
432 if ((rc = xgene_ahci_mux_select(ctx))) {
433 dev_err(dev, "SATA mux selection failed error %d\n", rc);
434 return -ENODEV;
435 }
436
437 /* Due to errata, HW requires full toggle transition */
438 rc = ahci_platform_enable_clks(hpriv);
439 if (rc)
440 goto disable_resources;
441 ahci_platform_disable_clks(hpriv);
442
443 rc = ahci_platform_enable_resources(hpriv);
444 if (rc)
445 goto disable_resources;
446
447 /* Configure the host controller */
448 xgene_ahci_hw_init(hpriv);
449
Kefeng Wangf9f36912014-05-14 14:13:41 +0800450 hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
451
452 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info,
453 hflags, 0, 0);
Loc Ho81d01bf2014-03-14 17:53:20 -0600454 if (rc)
455 goto disable_resources;
456
457 dev_dbg(dev, "X-Gene SATA host controller initialized\n");
458 return 0;
459
460disable_resources:
461 ahci_platform_disable_resources(hpriv);
462 return rc;
463}
464
465static const struct of_device_id xgene_ahci_of_match[] = {
466 {.compatible = "apm,xgene-ahci"},
467 {},
468};
469MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
470
471static struct platform_driver xgene_ahci_driver = {
472 .probe = xgene_ahci_probe,
473 .remove = ata_platform_remove_one,
474 .driver = {
475 .name = "xgene-ahci",
476 .owner = THIS_MODULE,
477 .of_match_table = xgene_ahci_of_match,
478 },
479};
480
481module_platform_driver(xgene_ahci_driver);
482
483MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
484MODULE_AUTHOR("Loc Ho <lho@apm.com>");
485MODULE_LICENSE("GPL");
486MODULE_VERSION("0.4");