Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 1 | /* |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 3 | * |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 4 | * Copyright 2007-2009 Freescale Semiconductor, Inc. |
| 5 | * Copyright 2008-2009 MontaVista Software, Inc. |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 6 | * |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 8 | * Recode: ZHANG WEI <wei.zhang@freescale.com> |
| 9 | * Rewrite the routing for Frescale PCI and PCI Express |
| 10 | * Roy Zang <tie-fei.zang@freescale.com> |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 11 | * MPC83xx PCI-Express support: |
| 12 | * Tony Li <tony.li@freescale.com> |
| 13 | * Anton Vorontsov <avorontsov@ru.mvista.com> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify it |
| 16 | * under the terms of the GNU General Public License as published by the |
| 17 | * Free Software Foundation; either version 2 of the License, or (at your |
| 18 | * option) any later version. |
| 19 | */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 20 | #include <linux/kernel.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 21 | #include <linux/pci.h> |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 22 | #include <linux/delay.h> |
| 23 | #include <linux/string.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/bootmem.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 26 | |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 27 | #include <asm/io.h> |
| 28 | #include <asm/prom.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 29 | #include <asm/pci-bridge.h> |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 30 | #include <asm/machdep.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 31 | #include <sysdev/fsl_soc.h> |
Roy Zang | 55c4499 | 2007-07-10 18:44:34 +0800 | [diff] [blame] | 32 | #include <sysdev/fsl_pci.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 33 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 34 | static int fsl_pcie_bus_fixup; |
| 35 | |
| 36 | static void __init quirk_fsl_pcie_header(struct pci_dev *dev) |
| 37 | { |
| 38 | /* if we aren't a PCIe don't bother */ |
| 39 | if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) |
| 40 | return; |
| 41 | |
| 42 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
| 43 | fsl_pcie_bus_fixup = 1; |
| 44 | return; |
| 45 | } |
| 46 | |
| 47 | static int __init fsl_pcie_check_link(struct pci_controller *hose) |
| 48 | { |
| 49 | u32 val; |
| 50 | |
| 51 | early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); |
| 52 | if (val < PCIE_LTSSM_L0) |
| 53 | return 1; |
| 54 | return 0; |
| 55 | } |
| 56 | |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 57 | #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 58 | static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, |
| 59 | unsigned int index, const struct resource *res, |
| 60 | resource_size_t offset) |
| 61 | { |
| 62 | resource_size_t pci_addr = res->start - offset; |
| 63 | resource_size_t phys_addr = res->start; |
| 64 | resource_size_t size = res->end - res->start + 1; |
| 65 | u32 flags = 0x80044000; /* enable & mem R/W */ |
| 66 | unsigned int i; |
| 67 | |
| 68 | pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", |
| 69 | (u64)res->start, (u64)size); |
| 70 | |
Trent Piepho | 565f376 | 2008-12-17 11:43:26 -0800 | [diff] [blame] | 71 | if (res->flags & IORESOURCE_PREFETCH) |
| 72 | flags |= 0x10000000; /* enable relaxed ordering */ |
| 73 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 74 | for (i = 0; size > 0; i++) { |
| 75 | unsigned int bits = min(__ilog2(size), |
| 76 | __ffs(pci_addr | phys_addr)); |
| 77 | |
| 78 | if (index + i >= 5) |
| 79 | return -1; |
| 80 | |
| 81 | out_be32(&pci->pow[index + i].potar, pci_addr >> 12); |
| 82 | out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); |
| 83 | out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); |
| 84 | out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); |
| 85 | |
| 86 | pci_addr += (resource_size_t)1U << bits; |
| 87 | phys_addr += (resource_size_t)1U << bits; |
| 88 | size -= (resource_size_t)1U << bits; |
| 89 | } |
| 90 | |
| 91 | return i; |
| 92 | } |
| 93 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 94 | /* atmu setup for fsl pci/pcie controller */ |
Anton Vorontsov | c9dadff | 2008-12-29 19:40:32 +0300 | [diff] [blame] | 95 | static void __init setup_pci_atmu(struct pci_controller *hose, |
| 96 | struct resource *rsrc) |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 97 | { |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 98 | struct ccsr_pci __iomem *pci; |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 99 | int i, j, n; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 100 | |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 101 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
| 102 | (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 103 | pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 104 | if (!pci) { |
| 105 | dev_err(hose->parent, "Unable to map ATMU registers\n"); |
| 106 | return; |
| 107 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 108 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 109 | /* Disable all windows (except powar0 since it's ignored) */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 110 | for(i = 1; i < 5; i++) |
| 111 | out_be32(&pci->pow[i].powar, 0); |
| 112 | for(i = 0; i < 3; i++) |
| 113 | out_be32(&pci->piw[i].piwar, 0); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 114 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 115 | /* Setup outbound MEM window */ |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 116 | for(i = 0, j = 1; i < 3; i++) { |
| 117 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) |
| 118 | continue; |
| 119 | |
| 120 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], |
| 121 | hose->pci_mem_offset); |
| 122 | |
| 123 | if (n < 0 || j >= 5) { |
| 124 | pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); |
| 125 | hose->mem_resources[i].flags |= IORESOURCE_DISABLED; |
| 126 | } else |
| 127 | j += n; |
| 128 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 129 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 130 | /* Setup outbound IO window */ |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 131 | if (hose->io_resource.flags & IORESOURCE_IO) { |
| 132 | if (j >= 5) { |
| 133 | pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); |
| 134 | } else { |
| 135 | pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " |
| 136 | "phy base 0x%016llx.\n", |
| 137 | (u64)hose->io_resource.start, |
| 138 | (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, |
| 139 | (u64)hose->io_base_phys); |
| 140 | out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); |
| 141 | out_be32(&pci->pow[j].potear, 0); |
| 142 | out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); |
| 143 | /* Enable, IO R/W */ |
| 144 | out_be32(&pci->pow[j].powar, 0x80088000 |
| 145 | | (__ilog2(hose->io_resource.end |
| 146 | - hose->io_resource.start + 1) - 1)); |
| 147 | } |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 148 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 149 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 150 | /* Setup 2G inbound Memory Window @ 1 */ |
| 151 | out_be32(&pci->piw[2].pitar, 0x00000000); |
| 152 | out_be32(&pci->piw[2].piwbar,0x00000000); |
| 153 | out_be32(&pci->piw[2].piwar, PIWAR_2G); |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 154 | |
Becky Bruce | 89d9334 | 2009-04-20 11:26:48 -0500 | [diff] [blame] | 155 | /* Save the base address and size covered by inbound window mappings */ |
| 156 | hose->dma_window_base_cur = 0x00000000; |
| 157 | hose->dma_window_size = 0x80000000; |
| 158 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 159 | iounmap(pci); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 160 | } |
| 161 | |
Anton Vorontsov | c9dadff | 2008-12-29 19:40:32 +0300 | [diff] [blame] | 162 | static void __init setup_pci_cmd(struct pci_controller *hose) |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 163 | { |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 164 | u16 cmd; |
Kumar Gala | eb12af4 | 2007-07-20 16:29:09 -0500 | [diff] [blame] | 165 | int cap_x; |
| 166 | |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 167 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
| 168 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 169 | | PCI_COMMAND_IO; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 170 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
Kumar Gala | eb12af4 | 2007-07-20 16:29:09 -0500 | [diff] [blame] | 171 | |
| 172 | cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); |
| 173 | if (cap_x) { |
| 174 | int pci_x_cmd = cap_x + PCI_X_CMD; |
| 175 | cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
| 176 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; |
| 177 | early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); |
| 178 | } else { |
| 179 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); |
| 180 | } |
Kumar Gala | 9ad494f | 2006-06-28 00:37:45 -0500 | [diff] [blame] | 181 | } |
| 182 | |
Anton Vorontsov | 692d103 | 2008-05-23 17:41:02 +0400 | [diff] [blame] | 183 | static void __init setup_pci_pcsrbar(struct pci_controller *hose) |
Jason Jin | 34e36c1 | 2008-05-23 16:32:46 +0800 | [diff] [blame] | 184 | { |
Anton Vorontsov | 692d103 | 2008-05-23 17:41:02 +0400 | [diff] [blame] | 185 | #ifdef CONFIG_PCI_MSI |
Jason Jin | 34e36c1 | 2008-05-23 16:32:46 +0800 | [diff] [blame] | 186 | phys_addr_t immr_base; |
| 187 | |
| 188 | immr_base = get_immrbase(); |
| 189 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base); |
Jason Jin | 34e36c1 | 2008-05-23 16:32:46 +0800 | [diff] [blame] | 190 | #endif |
Anton Vorontsov | 692d103 | 2008-05-23 17:41:02 +0400 | [diff] [blame] | 191 | } |
Jason Jin | 34e36c1 | 2008-05-23 16:32:46 +0800 | [diff] [blame] | 192 | |
Kumar Gala | 6c0a11c | 2007-07-19 15:29:53 -0500 | [diff] [blame] | 193 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
| 194 | { |
| 195 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; |
| 196 | int i; |
| 197 | |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 198 | if ((bus->parent == hose->bus) && |
| 199 | ((fsl_pcie_bus_fixup && |
| 200 | early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || |
| 201 | (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) |
| 202 | { |
| 203 | for (i = 0; i < 4; ++i) { |
| 204 | struct resource *res = bus->resource[i]; |
| 205 | struct resource *par = bus->parent->resource[i]; |
| 206 | if (res) { |
| 207 | res->start = 0; |
| 208 | res->end = 0; |
| 209 | res->flags = 0; |
| 210 | } |
| 211 | if (res && par) { |
| 212 | res->start = par->start; |
| 213 | res->end = par->end; |
| 214 | res->flags = par->flags; |
| 215 | } |
Kumar Gala | 6c0a11c | 2007-07-19 15:29:53 -0500 | [diff] [blame] | 216 | } |
| 217 | } |
| 218 | } |
| 219 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 220 | int __init fsl_add_bridge(struct device_node *dev, int is_primary) |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 221 | { |
| 222 | int len; |
| 223 | struct pci_controller *hose; |
| 224 | struct resource rsrc; |
Jeremy Kerr | 8efca49 | 2006-07-12 15:39:42 +1000 | [diff] [blame] | 225 | const int *bus_range; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 226 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 227 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 228 | |
| 229 | /* Fetch host bridge registers address */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 230 | if (of_address_to_resource(dev, 0, &rsrc)) { |
| 231 | printk(KERN_WARNING "Can't get pci register base!"); |
| 232 | return -ENOMEM; |
| 233 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 234 | |
| 235 | /* Get bus range if any */ |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 236 | bus_range = of_get_property(dev, "bus-range", &len); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 237 | if (bus_range == NULL || len < 2 * sizeof(int)) |
| 238 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 239 | " bus 0\n", dev->full_name); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 240 | |
Josh Boyer | 7fe519c | 2008-12-11 09:46:44 +0000 | [diff] [blame] | 241 | ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); |
Kumar Gala | dbf8471 | 2007-06-27 01:56:50 -0500 | [diff] [blame] | 242 | hose = pcibios_alloc_controller(dev); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 243 | if (!hose) |
| 244 | return -ENOMEM; |
Kumar Gala | dbf8471 | 2007-06-27 01:56:50 -0500 | [diff] [blame] | 245 | |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 246 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
Zhang Wei | bf7c036 | 2007-05-22 11:38:26 +0800 | [diff] [blame] | 247 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 248 | |
Kumar Gala | 2e56ff2 | 2007-07-19 16:07:35 -0500 | [diff] [blame] | 249 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
| 250 | PPC_INDIRECT_TYPE_BIG_ENDIAN); |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 251 | setup_pci_cmd(hose); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 252 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 253 | /* check PCI express link status */ |
Kumar Gala | 957ecff | 2007-07-11 13:31:58 -0500 | [diff] [blame] | 254 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
Kumar Gala | 7659c03 | 2007-07-25 00:29:53 -0500 | [diff] [blame] | 255 | hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | |
Kumar Gala | 957ecff | 2007-07-11 13:31:58 -0500 | [diff] [blame] | 256 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 257 | if (fsl_pcie_check_link(hose)) |
Kumar Gala | 957ecff | 2007-07-11 13:31:58 -0500 | [diff] [blame] | 258 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
| 259 | } |
Zhang Wei | e4725c2 | 2007-06-25 15:21:10 -0500 | [diff] [blame] | 260 | |
joe@perches.com | df3c901 | 2007-11-20 12:47:55 +1100 | [diff] [blame] | 261 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 262 | "Firmware bus number: %d->%d\n", |
| 263 | (unsigned long long)rsrc.start, hose->first_busno, |
| 264 | hose->last_busno); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 265 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 266 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 267 | hose, hose->cfg_addr, hose->cfg_data); |
| 268 | |
| 269 | /* Interpret the "ranges" property */ |
| 270 | /* This also maps the I/O region and sets isa_io/mem_base */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 271 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 272 | |
| 273 | /* Setup PEX window registers */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 274 | setup_pci_atmu(hose, &rsrc); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 275 | |
Jason Jin | 34e36c1 | 2008-05-23 16:32:46 +0800 | [diff] [blame] | 276 | /* Setup PEXCSRBAR */ |
Jason Jin | 34e36c1 | 2008-05-23 16:32:46 +0800 | [diff] [blame] | 277 | setup_pci_pcsrbar(hose); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 278 | return 0; |
| 279 | } |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 280 | |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 281 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header); |
| 282 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header); |
| 283 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header); |
| 284 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); |
| 285 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); |
| 286 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); |
| 287 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); |
Anton Vorontsov | bfa568d | 2009-05-02 06:16:47 +0400 | [diff] [blame] | 288 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); |
| 289 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 290 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); |
| 291 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); |
| 292 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); |
| 293 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header); |
| 294 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header); |
| 295 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header); |
| 296 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); |
| 297 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); |
| 298 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); |
| 299 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); |
Kumar Gala | 2f3804e | 2008-07-02 01:36:15 -0500 | [diff] [blame] | 300 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); |
| 301 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 302 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); |
| 303 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); |
| 304 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); |
Kumar Gala | 01af950 | 2009-04-15 14:38:40 -0500 | [diff] [blame^] | 305 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); |
| 306 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 307 | #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ |
| 308 | |
John Rigby | 3522580 | 2008-10-07 15:13:18 -0600 | [diff] [blame] | 309 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 310 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); |
| 311 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header); |
| 312 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header); |
| 313 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header); |
| 314 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header); |
| 315 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header); |
| 316 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header); |
| 317 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header); |
| 318 | |
| 319 | struct mpc83xx_pcie_priv { |
| 320 | void __iomem *cfg_type0; |
| 321 | void __iomem *cfg_type1; |
| 322 | u32 dev_base; |
| 323 | }; |
| 324 | |
| 325 | /* |
| 326 | * With the convention of u-boot, the PCIE outbound window 0 serves |
| 327 | * as configuration transactions outbound. |
| 328 | */ |
| 329 | #define PEX_OUTWIN0_BAR 0xCA4 |
| 330 | #define PEX_OUTWIN0_TAL 0xCA8 |
| 331 | #define PEX_OUTWIN0_TAH 0xCAC |
| 332 | |
| 333 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) |
| 334 | { |
| 335 | struct pci_controller *hose = bus->sysdata; |
| 336 | |
| 337 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) |
| 338 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 339 | /* |
| 340 | * Workaround for the HW bug: for Type 0 configure transactions the |
| 341 | * PCI-E controller does not check the device number bits and just |
| 342 | * assumes that the device number bits are 0. |
| 343 | */ |
| 344 | if (bus->number == hose->first_busno || |
| 345 | bus->primary == hose->first_busno) { |
| 346 | if (devfn & 0xf8) |
| 347 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 348 | } |
| 349 | |
| 350 | if (ppc_md.pci_exclude_device) { |
| 351 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
| 352 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 353 | } |
| 354 | |
| 355 | return PCIBIOS_SUCCESSFUL; |
| 356 | } |
| 357 | |
| 358 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, |
| 359 | unsigned int devfn, int offset) |
| 360 | { |
| 361 | struct pci_controller *hose = bus->sysdata; |
| 362 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
| 363 | u8 bus_no = bus->number - hose->first_busno; |
| 364 | u32 dev_base = bus_no << 24 | devfn << 16; |
| 365 | int ret; |
| 366 | |
| 367 | ret = mpc83xx_pcie_exclude_device(bus, devfn); |
| 368 | if (ret) |
| 369 | return NULL; |
| 370 | |
| 371 | offset &= 0xfff; |
| 372 | |
| 373 | /* Type 0 */ |
| 374 | if (bus->number == hose->first_busno) |
| 375 | return pcie->cfg_type0 + offset; |
| 376 | |
| 377 | if (pcie->dev_base == dev_base) |
| 378 | goto mapped; |
| 379 | |
| 380 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); |
| 381 | |
| 382 | pcie->dev_base = dev_base; |
| 383 | mapped: |
| 384 | return pcie->cfg_type1 + offset; |
| 385 | } |
| 386 | |
| 387 | static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, |
| 388 | int offset, int len, u32 *val) |
| 389 | { |
| 390 | void __iomem *cfg_addr; |
| 391 | |
| 392 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); |
| 393 | if (!cfg_addr) |
| 394 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 395 | |
| 396 | switch (len) { |
| 397 | case 1: |
| 398 | *val = in_8(cfg_addr); |
| 399 | break; |
| 400 | case 2: |
| 401 | *val = in_le16(cfg_addr); |
| 402 | break; |
| 403 | default: |
| 404 | *val = in_le32(cfg_addr); |
| 405 | break; |
| 406 | } |
| 407 | |
| 408 | return PCIBIOS_SUCCESSFUL; |
| 409 | } |
| 410 | |
| 411 | static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, |
| 412 | int offset, int len, u32 val) |
| 413 | { |
| 414 | void __iomem *cfg_addr; |
| 415 | |
| 416 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); |
| 417 | if (!cfg_addr) |
| 418 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 419 | |
| 420 | switch (len) { |
| 421 | case 1: |
| 422 | out_8(cfg_addr, val); |
| 423 | break; |
| 424 | case 2: |
| 425 | out_le16(cfg_addr, val); |
| 426 | break; |
| 427 | default: |
| 428 | out_le32(cfg_addr, val); |
| 429 | break; |
| 430 | } |
| 431 | |
| 432 | return PCIBIOS_SUCCESSFUL; |
| 433 | } |
| 434 | |
| 435 | static struct pci_ops mpc83xx_pcie_ops = { |
| 436 | .read = mpc83xx_pcie_read_config, |
| 437 | .write = mpc83xx_pcie_write_config, |
| 438 | }; |
| 439 | |
| 440 | static int __init mpc83xx_pcie_setup(struct pci_controller *hose, |
| 441 | struct resource *reg) |
| 442 | { |
| 443 | struct mpc83xx_pcie_priv *pcie; |
| 444 | u32 cfg_bar; |
| 445 | int ret = -ENOMEM; |
| 446 | |
| 447 | pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); |
| 448 | if (!pcie) |
| 449 | return ret; |
| 450 | |
| 451 | pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); |
| 452 | if (!pcie->cfg_type0) |
| 453 | goto err0; |
| 454 | |
| 455 | cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); |
| 456 | if (!cfg_bar) { |
| 457 | /* PCI-E isn't configured. */ |
| 458 | ret = -ENODEV; |
| 459 | goto err1; |
| 460 | } |
| 461 | |
| 462 | pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); |
| 463 | if (!pcie->cfg_type1) |
| 464 | goto err1; |
| 465 | |
| 466 | WARN_ON(hose->dn->data); |
| 467 | hose->dn->data = pcie; |
| 468 | hose->ops = &mpc83xx_pcie_ops; |
| 469 | |
| 470 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); |
| 471 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); |
| 472 | |
| 473 | if (fsl_pcie_check_link(hose)) |
| 474 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
| 475 | |
| 476 | return 0; |
| 477 | err1: |
| 478 | iounmap(pcie->cfg_type0); |
| 479 | err0: |
| 480 | kfree(pcie); |
| 481 | return ret; |
| 482 | |
| 483 | } |
| 484 | |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 485 | int __init mpc83xx_add_bridge(struct device_node *dev) |
| 486 | { |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 487 | int ret; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 488 | int len; |
| 489 | struct pci_controller *hose; |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 490 | struct resource rsrc_reg; |
| 491 | struct resource rsrc_cfg; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 492 | const int *bus_range; |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 493 | int primary; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 494 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 495 | if (!of_device_is_available(dev)) { |
| 496 | pr_warning("%s: disabled by the firmware.\n", |
| 497 | dev->full_name); |
| 498 | return -ENODEV; |
| 499 | } |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 500 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
| 501 | |
| 502 | /* Fetch host bridge registers address */ |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 503 | if (of_address_to_resource(dev, 0, &rsrc_reg)) { |
| 504 | printk(KERN_WARNING "Can't get pci register base!\n"); |
| 505 | return -ENOMEM; |
| 506 | } |
| 507 | |
| 508 | memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); |
| 509 | |
| 510 | if (of_address_to_resource(dev, 1, &rsrc_cfg)) { |
| 511 | printk(KERN_WARNING |
| 512 | "No pci config register base in dev tree, " |
| 513 | "using default\n"); |
| 514 | /* |
| 515 | * MPC83xx supports up to two host controllers |
| 516 | * one at 0x8500 has config space registers at 0x8300 |
| 517 | * one at 0x8600 has config space registers at 0x8380 |
| 518 | */ |
| 519 | if ((rsrc_reg.start & 0xfffff) == 0x8500) |
| 520 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; |
| 521 | else if ((rsrc_reg.start & 0xfffff) == 0x8600) |
| 522 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; |
| 523 | } |
| 524 | /* |
| 525 | * Controller at offset 0x8500 is primary |
| 526 | */ |
| 527 | if ((rsrc_reg.start & 0xfffff) == 0x8500) |
| 528 | primary = 1; |
| 529 | else |
| 530 | primary = 0; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 531 | |
| 532 | /* Get bus range if any */ |
| 533 | bus_range = of_get_property(dev, "bus-range", &len); |
| 534 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 535 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
| 536 | " bus 0\n", dev->full_name); |
| 537 | } |
| 538 | |
Josh Boyer | 7fe519c | 2008-12-11 09:46:44 +0000 | [diff] [blame] | 539 | ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 540 | hose = pcibios_alloc_controller(dev); |
| 541 | if (!hose) |
| 542 | return -ENOMEM; |
| 543 | |
| 544 | hose->first_busno = bus_range ? bus_range[0] : 0; |
| 545 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
| 546 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 547 | if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { |
| 548 | ret = mpc83xx_pcie_setup(hose, &rsrc_reg); |
| 549 | if (ret) |
| 550 | goto err0; |
| 551 | } else { |
| 552 | setup_indirect_pci(hose, rsrc_cfg.start, |
| 553 | rsrc_cfg.start + 4, 0); |
| 554 | } |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 555 | |
John Rigby | 3522580 | 2008-10-07 15:13:18 -0600 | [diff] [blame] | 556 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 557 | "Firmware bus number: %d->%d\n", |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 558 | (unsigned long long)rsrc_reg.start, hose->first_busno, |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 559 | hose->last_busno); |
| 560 | |
| 561 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
| 562 | hose, hose->cfg_addr, hose->cfg_data); |
| 563 | |
| 564 | /* Interpret the "ranges" property */ |
| 565 | /* This also maps the I/O region and sets isa_io/mem_base */ |
| 566 | pci_process_bridge_OF_ranges(hose, dev, primary); |
| 567 | |
| 568 | return 0; |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 569 | err0: |
| 570 | pcibios_free_controller(hose); |
| 571 | return ret; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 572 | } |
| 573 | #endif /* CONFIG_PPC_83xx */ |