blob: 6f7d34ad19ef34152e966434c577c1cb69c88a3e [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * Maybe PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME "pata_hpt366"
Alan Coxfecfda52007-03-08 19:34:28 +000030#define DRV_VERSION "0.6.1"
Jeff Garzik669a5db2006-08-29 18:12:40 -040031
32struct hpt_clock {
33 u8 xfer_speed;
34 u32 timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 * register access.
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
46 * register access.
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 * xfer.
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 * register access.
53 * 28 UDMA enable
54 * 29 DMA enable
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
56 * PIO.
57 * 31 FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
66
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
70
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
76 { 0, 0x0120d9d9 }
77};
78
79static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
85
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
89
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95 { 0, 0x0120a7a7 }
96};
97
98static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
104
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
108
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
114 { 0, 0x01208585 }
115};
116
117static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121 "Maxtor 90510D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125 NULL
126};
127
128static const char *bad_ata66_4[] = {
129 "IBM-DTLA-307075",
130 "IBM-DTLA-307060",
131 "IBM-DTLA-307045",
132 "IBM-DTLA-307030",
133 "IBM-DTLA-307020",
134 "IBM-DTLA-307015",
135 "IBM-DTLA-305040",
136 "IBM-DTLA-305030",
137 "IBM-DTLA-305020",
138 "IC35L010AVER07-0",
139 "IC35L020AVER07-0",
140 "IC35L030AVER07-0",
141 "IC35L040AVER07-0",
142 "IC35L060AVER07-0",
143 "WDC AC310200R",
144 NULL
145};
146
147static const char *bad_ata66_3[] = {
148 "WDC AC310200R",
149 NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900154 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 int i = 0;
156
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900159 while (list[i] != NULL) {
160 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 modestr, list[i]);
163 return 1;
164 }
165 i++;
166 }
167 return 0;
168}
169
170/**
171 * hpt366_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172 * @adev: ATA device
173 *
174 * Block UDMA on devices that cause trouble with this controller.
175 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400176
Alan Coxa76b62c2007-03-09 09:34:07 -0500177static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400178{
179 if (adev->class == ATA_DEV_ATA) {
180 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
181 mask &= ~ATA_MASK_UDMA;
182 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
183 mask &= ~(0x07 << ATA_SHIFT_UDMA);
184 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
185 mask &= ~(0x0F << ATA_SHIFT_UDMA);
186 }
Alan Coxa76b62c2007-03-09 09:34:07 -0500187 return ata_pci_default_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188}
189
190/**
191 * hpt36x_find_mode - reset the hpt36x bus
192 * @ap: ATA port
193 * @speed: transfer mode
194 *
195 * Return the 32bit register programming information for this channel
196 * that matches the speed provided.
197 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400198
Jeff Garzik669a5db2006-08-29 18:12:40 -0400199static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
200{
201 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400202
Jeff Garzik669a5db2006-08-29 18:12:40 -0400203 while(clocks->xfer_speed) {
204 if (clocks->xfer_speed == speed)
205 return clocks->timing;
206 clocks++;
207 }
208 BUG();
209 return 0xffffffffU; /* silence compiler warning */
210}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400211
Alan Coxfecfda52007-03-08 19:34:28 +0000212static int hpt36x_cable_detect(struct ata_port *ap)
213{
214 u8 ata66;
215 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
216
217 pci_read_config_byte(pdev, 0x5A, &ata66);
218 if (ata66 & (1 << ap->port_no))
219 return ATA_CBL_PATA40;
220 return ATA_CBL_PATA80;
221}
222
Jeff Garzik669a5db2006-08-29 18:12:40 -0400223/**
224 * hpt366_set_piomode - PIO setup
225 * @ap: ATA interface
226 * @adev: device on the interface
227 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400228 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400229 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400230
Jeff Garzik669a5db2006-08-29 18:12:40 -0400231static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
232{
233 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
234 u32 addr1, addr2;
235 u32 reg;
236 u32 mode;
237 u8 fast;
238
239 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
240 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400241
Jeff Garzik669a5db2006-08-29 18:12:40 -0400242 /* Fast interrupt prediction disable, hold off interrupt disable */
243 pci_read_config_byte(pdev, addr2, &fast);
244 if (fast & 0x80) {
245 fast &= ~0x80;
246 pci_write_config_byte(pdev, addr2, fast);
247 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400248
Jeff Garzik669a5db2006-08-29 18:12:40 -0400249 pci_read_config_dword(pdev, addr1, &reg);
250 mode = hpt36x_find_mode(ap, adev->pio_mode);
251 mode &= ~0x8000000; /* No FIFO in PIO */
252 mode &= ~0x30070000; /* Leave config bits alone */
253 reg &= 0x30070000; /* Strip timing bits */
254 pci_write_config_dword(pdev, addr1, reg | mode);
255}
256
257/**
258 * hpt366_set_dmamode - DMA timing setup
259 * @ap: ATA interface
260 * @adev: Device being configured
261 *
262 * Set up the channel for MWDMA or UDMA modes. Much the same as with
263 * PIO, load the mode number and then set MWDMA or UDMA flag.
264 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400265
Jeff Garzik669a5db2006-08-29 18:12:40 -0400266static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
267{
268 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
269 u32 addr1, addr2;
270 u32 reg;
271 u32 mode;
272 u8 fast;
273
274 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
275 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400276
Jeff Garzik669a5db2006-08-29 18:12:40 -0400277 /* Fast interrupt prediction disable, hold off interrupt disable */
278 pci_read_config_byte(pdev, addr2, &fast);
279 if (fast & 0x80) {
280 fast &= ~0x80;
281 pci_write_config_byte(pdev, addr2, fast);
282 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400283
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 pci_read_config_dword(pdev, addr1, &reg);
285 mode = hpt36x_find_mode(ap, adev->dma_mode);
286 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
287 mode &= ~0xC0000000; /* Leave config bits alone */
288 reg &= 0xC0000000; /* Strip timing bits */
289 pci_write_config_dword(pdev, addr1, reg | mode);
290}
291
292static struct scsi_host_template hpt36x_sht = {
293 .module = THIS_MODULE,
294 .name = DRV_NAME,
295 .ioctl = ata_scsi_ioctl,
296 .queuecommand = ata_scsi_queuecmd,
297 .can_queue = ATA_DEF_QUEUE,
298 .this_id = ATA_SHT_THIS_ID,
299 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400300 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
301 .emulated = ATA_SHT_EMULATED,
302 .use_clustering = ATA_SHT_USE_CLUSTERING,
303 .proc_name = DRV_NAME,
304 .dma_boundary = ATA_DMA_BOUNDARY,
305 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900306 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307 .bios_param = ata_std_bios_param,
308};
309
310/*
311 * Configuration for HPT366/68
312 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400313
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314static struct ata_port_operations hpt366_port_ops = {
315 .port_disable = ata_port_disable,
316 .set_piomode = hpt366_set_piomode,
317 .set_dmamode = hpt366_set_dmamode,
318 .mode_filter = hpt366_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400319
Jeff Garzik669a5db2006-08-29 18:12:40 -0400320 .tf_load = ata_tf_load,
321 .tf_read = ata_tf_read,
322 .check_status = ata_check_status,
323 .exec_command = ata_exec_command,
324 .dev_select = ata_std_dev_select,
325
326 .freeze = ata_bmdma_freeze,
327 .thaw = ata_bmdma_thaw,
Alan Cox4349eeb2007-05-21 14:52:49 +0100328 .error_handler = ata_bmdma_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400329 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Coxfecfda52007-03-08 19:34:28 +0000330 .cable_detect = hpt36x_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400331
332 .bmdma_setup = ata_bmdma_setup,
333 .bmdma_start = ata_bmdma_start,
334 .bmdma_stop = ata_bmdma_stop,
335 .bmdma_status = ata_bmdma_status,
336
337 .qc_prep = ata_qc_prep,
338 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400339
Tejun Heo0d5ff562007-02-01 15:06:36 +0900340 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400341
342 .irq_handler = ata_interrupt,
343 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900344 .irq_on = ata_irq_on,
345 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400346
347 .port_start = ata_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400348};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400349
350/**
Alanaa54ab12006-11-27 16:24:15 +0000351 * hpt36x_init_chipset - common chip setup
352 * @dev: PCI device
353 *
354 * Perform the chip setup work that must be done at both init and
355 * resume time
356 */
357
358static void hpt36x_init_chipset(struct pci_dev *dev)
359{
360 u8 drive_fast;
361 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
362 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
363 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
364 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
365
366 pci_read_config_byte(dev, 0x51, &drive_fast);
367 if (drive_fast & 0x80)
368 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
369}
370
371/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400372 * hpt36x_init_one - Initialise an HPT366/368
373 * @dev: PCI device
374 * @id: Entry in match table
375 *
376 * Initialise an HPT36x device. There are some interesting complications
377 * here. Firstly the chip may report 366 and be one of several variants.
378 * Secondly all the timings depend on the clock for the chip which we must
379 * detect and look up
380 *
381 * This is the known chip mappings. It may be missing a couple of later
382 * releases.
383 *
384 * Chip version PCI Rev Notes
385 * HPT366 4 (HPT366) 0 UDMA66
386 * HPT366 4 (HPT366) 1 UDMA66
387 * HPT368 4 (HPT366) 2 UDMA66
388 * HPT37x/30x 4 (HPT366) 3+ Other driver
389 *
390 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400391
Jeff Garzik669a5db2006-08-29 18:12:40 -0400392static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
393{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200394 static const struct ata_port_info info_hpt366 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400395 .sht = &hpt36x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400396 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400397 .pio_mask = 0x1f,
398 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400399 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400400 .port_ops = &hpt366_port_ops
401 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200402 struct ata_port_info info = info_hpt366;
403 const struct ata_port_info *ppi[] = { &info, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400404
405 u32 class_rev;
406 u32 reg1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400407
408 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
409 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400410
Jeff Garzik669a5db2006-08-29 18:12:40 -0400411 /* May be a later chip in disguise. Check */
412 /* Newer chips are not in the HPT36x driver. Ignore them */
413 if (class_rev > 2)
414 return -ENODEV;
415
Alanaa54ab12006-11-27 16:24:15 +0000416 hpt36x_init_chipset(dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400417
418 pci_read_config_dword(dev, 0x40, &reg1);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400419
Jeff Garzik669a5db2006-08-29 18:12:40 -0400420 /* PCI clocking determines the ATA timing values to use */
421 /* info_hpt366 is safe against re-entry so we can scribble on it */
OGAWA Hirofumi2c136ef2006-10-03 01:14:03 -0700422 switch((reg1 & 0x700) >> 8) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400423 case 5:
Tejun Heo1626aeb2007-05-04 12:43:58 +0200424 info.private_data = &hpt366_40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400425 break;
426 case 9:
Tejun Heo1626aeb2007-05-04 12:43:58 +0200427 info.private_data = &hpt366_25;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400428 break;
429 default:
Tejun Heo1626aeb2007-05-04 12:43:58 +0200430 info.private_data = &hpt366_33;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400431 break;
432 }
433 /* Now kick off ATA set up */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200434 return ata_pci_init_one(dev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400435}
436
Tejun Heo438ac6d2007-03-02 17:31:26 +0900437#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000438static int hpt36x_reinit_one(struct pci_dev *dev)
439{
440 hpt36x_init_chipset(dev);
441 return ata_pci_device_resume(dev);
442}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900443#endif
Alanaa54ab12006-11-27 16:24:15 +0000444
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400445static const struct pci_device_id hpt36x[] = {
446 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400447 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400448};
449
450static struct pci_driver hpt36x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400451 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400452 .id_table = hpt36x,
453 .probe = hpt36x_init_one,
Alanaa54ab12006-11-27 16:24:15 +0000454 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900455#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000456 .suspend = ata_pci_device_suspend,
457 .resume = hpt36x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900458#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400459};
460
461static int __init hpt36x_init(void)
462{
463 return pci_register_driver(&hpt36x_pci_driver);
464}
465
Jeff Garzik669a5db2006-08-29 18:12:40 -0400466static void __exit hpt36x_exit(void)
467{
468 pci_unregister_driver(&hpt36x_pci_driver);
469}
470
Jeff Garzik669a5db2006-08-29 18:12:40 -0400471MODULE_AUTHOR("Alan Cox");
472MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
473MODULE_LICENSE("GPL");
474MODULE_DEVICE_TABLE(pci, hpt36x);
475MODULE_VERSION(DRV_VERSION);
476
477module_init(hpt36x_init);
478module_exit(hpt36x_exit);