blob: ac764d0fda4b753a1af3d33efde5e2063c0e47b8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
34
Jesse Barnes585fb112008-07-29 11:54:06 -070035#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080037#include "intel_ringbuffer.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070038#include "i915_gem_gtt.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070039#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070040#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010041#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020042#include <drm/intel-gtt.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020043#include <linux/backlight.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070044#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020045#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010046#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070047
Linus Torvalds1da177e2005-04-16 15:20:36 -070048/* General customization:
49 */
50
51#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52
53#define DRIVER_NAME "i915"
54#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070055#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Jesse Barnes317c35d2008-08-25 15:11:06 -070057enum pipe {
Jesse Barnes752aa882013-10-31 18:55:49 +020058 INVALID_PIPE = -1,
Jesse Barnes317c35d2008-08-25 15:11:06 -070059 PIPE_A = 0,
60 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080061 PIPE_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020062 _PIPE_EDP,
63 I915_MAX_PIPES = _PIPE_EDP
Jesse Barnes317c35d2008-08-25 15:11:06 -070064};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080065#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -070066
Paulo Zanonia5c961d2012-10-24 15:59:34 -020067enum transcoder {
68 TRANSCODER_A = 0,
69 TRANSCODER_B,
70 TRANSCODER_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020071 TRANSCODER_EDP,
72 I915_MAX_TRANSCODERS
Paulo Zanonia5c961d2012-10-24 15:59:34 -020073};
74#define transcoder_name(t) ((t) + 'A')
75
Jesse Barnes80824002009-09-10 15:28:06 -070076enum plane {
77 PLANE_A = 0,
78 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080079 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -070080};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080081#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -080082
Damien Lespiaud615a162014-03-03 17:31:48 +000083#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +030084
Eugeni Dodonov2b139522012-03-29 12:32:22 -030085enum port {
86 PORT_A = 0,
87 PORT_B,
88 PORT_C,
89 PORT_D,
90 PORT_E,
91 I915_MAX_PORTS
92};
93#define port_name(p) ((p) + 'A')
94
Chon Ming Leee4607fc2013-11-06 14:36:35 +080095#define I915_NUM_PHYS_VLV 1
96
97enum dpio_channel {
98 DPIO_CH0,
99 DPIO_CH1
100};
101
102enum dpio_phy {
103 DPIO_PHY0,
104 DPIO_PHY1
105};
106
Paulo Zanonib97186f2013-05-03 12:15:36 -0300107enum intel_display_power_domain {
108 POWER_DOMAIN_PIPE_A,
109 POWER_DOMAIN_PIPE_B,
110 POWER_DOMAIN_PIPE_C,
111 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
114 POWER_DOMAIN_TRANSCODER_A,
115 POWER_DOMAIN_TRANSCODER_B,
116 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300117 POWER_DOMAIN_TRANSCODER_EDP,
Imre Deak319be8a2014-03-04 19:22:57 +0200118 POWER_DOMAIN_PORT_DDI_A_2_LANES,
119 POWER_DOMAIN_PORT_DDI_A_4_LANES,
120 POWER_DOMAIN_PORT_DDI_B_2_LANES,
121 POWER_DOMAIN_PORT_DDI_B_4_LANES,
122 POWER_DOMAIN_PORT_DDI_C_2_LANES,
123 POWER_DOMAIN_PORT_DDI_C_4_LANES,
124 POWER_DOMAIN_PORT_DDI_D_2_LANES,
125 POWER_DOMAIN_PORT_DDI_D_4_LANES,
126 POWER_DOMAIN_PORT_DSI,
127 POWER_DOMAIN_PORT_CRT,
128 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300129 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200130 POWER_DOMAIN_AUDIO,
Imre Deakbaa70702013-10-25 17:36:48 +0300131 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300132
133 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300134};
135
136#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
137#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
138 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300139#define POWER_DOMAIN_TRANSCODER(tran) \
140 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
141 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300142
Egbert Eich1d843f92013-02-25 12:06:49 -0500143enum hpd_pin {
144 HPD_NONE = 0,
145 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
146 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
147 HPD_CRT,
148 HPD_SDVO_B,
149 HPD_SDVO_C,
150 HPD_PORT_B,
151 HPD_PORT_C,
152 HPD_PORT_D,
153 HPD_NUM_PINS
154};
155
Chris Wilson2a2d5482012-12-03 11:49:06 +0000156#define I915_GEM_GPU_DOMAINS \
157 (I915_GEM_DOMAIN_RENDER | \
158 I915_GEM_DOMAIN_SAMPLER | \
159 I915_GEM_DOMAIN_COMMAND | \
160 I915_GEM_DOMAIN_INSTRUCTION | \
161 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700162
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700163#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
Damien Lespiaud615a162014-03-03 17:31:48 +0000164#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800165
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200166#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
167 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
168 if ((intel_encoder)->base.crtc == (__crtc))
169
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800170#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
171 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
172 if ((intel_connector)->base.encoder == (__encoder))
173
Daniel Vettere7b903d2013-06-05 13:34:14 +0200174struct drm_i915_private;
175
Daniel Vettere2b78262013-06-07 23:10:03 +0200176enum intel_dpll_id {
177 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
178 /* real shared dpll ids must be >= 0 */
179 DPLL_ID_PCH_PLL_A,
180 DPLL_ID_PCH_PLL_B,
181};
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100182#define I915_NUM_PLLS 2
183
Daniel Vetter53589012013-06-05 13:34:16 +0200184struct intel_dpll_hw_state {
Daniel Vetter66e985c2013-06-05 13:34:20 +0200185 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200186 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200187 uint32_t fp0;
188 uint32_t fp1;
Daniel Vetter53589012013-06-05 13:34:16 +0200189};
190
Daniel Vetter46edb022013-06-05 13:34:12 +0200191struct intel_shared_dpll {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 int refcount; /* count of number of CRTCs sharing this PLL */
193 int active; /* count of number of active CRTCs (i.e. DPMS on) */
194 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200195 const char *name;
196 /* should match the index in the dev_priv->shared_dplls array */
197 enum intel_dpll_id id;
Daniel Vetter53589012013-06-05 13:34:16 +0200198 struct intel_dpll_hw_state hw_state;
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200199 void (*mode_set)(struct drm_i915_private *dev_priv,
200 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200201 void (*enable)(struct drm_i915_private *dev_priv,
202 struct intel_shared_dpll *pll);
203 void (*disable)(struct drm_i915_private *dev_priv,
204 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200205 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
206 struct intel_shared_dpll *pll,
207 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100210/* Used by dp and fdi links */
211struct intel_link_m_n {
212 uint32_t tu;
213 uint32_t gmch_m;
214 uint32_t gmch_n;
215 uint32_t link_m;
216 uint32_t link_n;
217};
218
219void intel_link_compute_m_n(int bpp, int nlanes,
220 int pixel_clock, int link_clock,
221 struct intel_link_m_n *m_n);
222
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300223struct intel_ddi_plls {
224 int spll_refcount;
225 int wrpll1_refcount;
226 int wrpll2_refcount;
227};
228
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229/* Interface history:
230 *
231 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100232 * 1.2: Add Power Management
233 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100234 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000235 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000236 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
237 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 */
239#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000240#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241#define DRIVER_PATCHLEVEL 0
242
Chris Wilson23bc5982010-09-29 16:10:57 +0100243#define WATCH_LISTS 0
Chris Wilson42d6ab42012-07-26 11:49:32 +0100244#define WATCH_GTT 0
Eric Anholt673a3942008-07-30 12:06:12 -0700245
Dave Airlie71acb5e2008-12-30 20:31:46 +1000246#define I915_GEM_PHYS_CURSOR_0 1
247#define I915_GEM_PHYS_CURSOR_1 2
248#define I915_GEM_PHYS_OVERLAY_REGS 3
249#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
250
251struct drm_i915_gem_phys_object {
252 int id;
253 struct page **page_list;
254 drm_dma_handle_t *handle;
Chris Wilson05394f32010-11-08 19:18:58 +0000255 struct drm_i915_gem_object *cur_obj;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000256};
257
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700258struct opregion_header;
259struct opregion_acpi;
260struct opregion_swsci;
261struct opregion_asle;
262
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100263struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700264 struct opregion_header __iomem *header;
265 struct opregion_acpi __iomem *acpi;
266 struct opregion_swsci __iomem *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300267 u32 swsci_gbda_sub_functions;
268 u32 swsci_sbcb_sub_functions;
Ben Widawsky5bc44182012-04-16 14:07:42 -0700269 struct opregion_asle __iomem *asle;
270 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000271 u32 __iomem *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200272 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100273};
Chris Wilson44834a62010-08-19 16:09:23 +0100274#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100275
Chris Wilson6ef3d422010-08-04 20:26:07 +0100276struct intel_overlay;
277struct intel_overlay_error_state;
278
Dave Airlie7c1c2872008-11-28 14:22:24 +1000279struct drm_i915_master_private {
280 drm_local_map_t *sarea;
281 struct _drm_i915_sarea *sarea_priv;
282};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800283#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300284#define I915_MAX_NUM_FENCES 32
285/* 32 fences + sign bit for FENCE_REG_NONE */
286#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800287
288struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200289 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000290 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100291 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800292};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000293
yakui_zhao9b9d1722009-05-31 17:17:17 +0800294struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100295 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800296 u8 dvo_port;
297 u8 slave_addr;
298 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100299 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400300 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800301};
302
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000303struct intel_display_error_state;
304
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700305struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200306 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800307 struct timeval time;
308
Mika Kuoppalacb383002014-02-25 17:11:25 +0200309 char error_msg[128];
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200310 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200311 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200312
Ben Widawsky585b0282014-01-30 00:19:37 -0800313 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700314 u32 eir;
315 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700316 u32 ier;
Ben Widawskyb9a39062012-06-04 14:42:52 -0700317 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000318 u32 derrmr;
319 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800320 u32 error; /* gen6+ */
321 u32 err_int; /* gen7 */
322 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800323 u32 gac_eco;
324 u32 gam_ecochk;
325 u32 gab_ctl;
326 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800327 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800328 u32 pipestat[I915_MAX_PIPES];
Ben Widawsky585b0282014-01-30 00:19:37 -0800329 u64 fence[I915_MAX_NUM_FENCES];
330 struct intel_overlay_error_state *overlay;
331 struct intel_display_error_state *display;
332
Chris Wilson52d39a22012-02-15 11:25:37 +0000333 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000334 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800335 /* Software tracked state */
336 bool waiting;
337 int hangcheck_score;
338 enum intel_ring_hangcheck_action hangcheck_action;
339 int num_requests;
340
341 /* our own tracking of ring head and tail */
342 u32 cpu_ring_head;
343 u32 cpu_ring_tail;
344
345 u32 semaphore_seqno[I915_NUM_RINGS - 1];
346
347 /* Register state */
348 u32 tail;
349 u32 head;
350 u32 ctl;
351 u32 hws;
352 u32 ipeir;
353 u32 ipehr;
354 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800355 u32 bbstate;
356 u32 instpm;
357 u32 instps;
358 u32 seqno;
359 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000360 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800361 u32 fault_reg;
362 u32 faddr;
363 u32 rc_psmi; /* sleep state */
364 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
365
Chris Wilson52d39a22012-02-15 11:25:37 +0000366 struct drm_i915_error_object {
367 int page_count;
368 u32 gtt_offset;
369 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200370 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800371
Chris Wilson52d39a22012-02-15 11:25:37 +0000372 struct drm_i915_error_request {
373 long jiffies;
374 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000375 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000376 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800377
378 struct {
379 u32 gfx_mode;
380 union {
381 u64 pdp[4];
382 u32 pp_dir_base;
383 };
384 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200385
386 pid_t pid;
387 char comm[TASK_COMM_LEN];
Chris Wilson52d39a22012-02-15 11:25:37 +0000388 } ring[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000389 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000390 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000391 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100392 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000393 u32 gtt_offset;
394 u32 read_domains;
395 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200396 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000397 s32 pinned:2;
398 u32 tiling:2;
399 u32 dirty:1;
400 u32 purgeable:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100401 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100402 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700403 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800404
Ben Widawsky95f53012013-07-31 17:00:15 -0700405 u32 *active_bo_count, *pinned_bo_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700406};
407
Jani Nikula7bd688c2013-11-08 16:48:56 +0200408struct intel_connector;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100409struct intel_crtc_config;
Jesse Barnes46f297f2014-03-07 08:57:48 -0800410struct intel_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100411struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200412struct intel_limit;
413struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100414
Jesse Barnese70236a2009-09-21 10:42:27 -0700415struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400416 bool (*fbc_enabled)(struct drm_device *dev);
Ville Syrjälä993495a2013-12-12 17:27:40 +0200417 void (*enable_fbc)(struct drm_crtc *crtc);
Jesse Barnese70236a2009-09-21 10:42:27 -0700418 void (*disable_fbc)(struct drm_device *dev);
419 int (*get_display_clock_speed)(struct drm_device *dev);
420 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200421 /**
422 * find_dpll() - Find the best values for the PLL
423 * @limit: limits for the PLL
424 * @crtc: current CRTC
425 * @target: target frequency in kHz
426 * @refclk: reference clock frequency in kHz
427 * @match_clock: if provided, @best_clock P divider must
428 * match the P divider from @match_clock
429 * used for LVDS downclocking
430 * @best_clock: best PLL values found
431 *
432 * Returns true on success, false on failure.
433 */
434 bool (*find_dpll)(const struct intel_limit *limit,
435 struct drm_crtc *crtc,
436 int target, int refclk,
437 struct dpll *match_clock,
438 struct dpll *best_clock);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300439 void (*update_wm)(struct drm_crtc *crtc);
Ville Syrjäläadf3d352013-08-06 22:24:11 +0300440 void (*update_sprite_wm)(struct drm_plane *plane,
441 struct drm_crtc *crtc,
Paulo Zanoni4c4ff432013-05-24 11:59:17 -0300442 uint32_t sprite_width, int pixel_size,
Ville Syrjäläbdd57d02013-07-05 11:57:13 +0300443 bool enable, bool scaled);
Daniel Vetter47fab732012-10-26 10:58:18 +0200444 void (*modeset_global_resources)(struct drm_device *dev);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100445 /* Returns the active state of the crtc, and if the crtc is active,
446 * fills out the pipe-config with the hw state. */
447 bool (*get_pipe_config)(struct intel_crtc *,
448 struct intel_crtc_config *);
Jesse Barnes46f297f2014-03-07 08:57:48 -0800449 void (*get_plane_config)(struct intel_crtc *,
450 struct intel_plane_config *);
Eric Anholtf564048e2011-03-30 13:01:02 -0700451 int (*crtc_mode_set)(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -0700452 int x, int y,
453 struct drm_framebuffer *old_fb);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200454 void (*crtc_enable)(struct drm_crtc *crtc);
455 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100456 void (*off)(struct drm_crtc *crtc);
Wu Fengguange0dac652011-09-05 14:25:34 +0800457 void (*write_eld)(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +0300458 struct drm_crtc *crtc,
459 struct drm_display_mode *mode);
Jesse Barnes674cf962011-04-28 14:27:04 -0700460 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700461 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700462 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
463 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700464 struct drm_i915_gem_object *obj,
465 uint32_t flags);
Matt Roper262ca2b2014-03-18 17:22:55 -0700466 int (*update_primary_plane)(struct drm_crtc *crtc,
467 struct drm_framebuffer *fb,
468 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100469 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700470 /* clock updates for mode set */
471 /* cursor updates */
472 /* render clock increase/decrease */
473 /* display clock increase/decrease */
474 /* pll clock increase/decrease */
Jani Nikula7bd688c2013-11-08 16:48:56 +0200475
476 int (*setup_backlight)(struct intel_connector *connector);
Jani Nikula7bd688c2013-11-08 16:48:56 +0200477 uint32_t (*get_backlight)(struct intel_connector *connector);
478 void (*set_backlight)(struct intel_connector *connector,
479 uint32_t level);
480 void (*disable_backlight)(struct intel_connector *connector);
481 void (*enable_backlight)(struct intel_connector *connector);
Jesse Barnese70236a2009-09-21 10:42:27 -0700482};
483
Chris Wilson907b28c2013-07-19 20:36:52 +0100484struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530485 void (*force_wake_get)(struct drm_i915_private *dev_priv,
486 int fw_engine);
487 void (*force_wake_put)(struct drm_i915_private *dev_priv,
488 int fw_engine);
Ben Widawsky0b274482013-10-04 21:22:51 -0700489
490 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
491 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
492 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
493 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
494
495 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
496 uint8_t val, bool trace);
497 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
498 uint16_t val, bool trace);
499 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
500 uint32_t val, bool trace);
501 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
502 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300503};
504
Chris Wilson907b28c2013-07-19 20:36:52 +0100505struct intel_uncore {
506 spinlock_t lock; /** lock is also taken in irq contexts. */
507
508 struct intel_uncore_funcs funcs;
509
510 unsigned fifo_count;
511 unsigned forcewake_count;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100512
Deepak S940aece2013-11-23 14:55:43 +0530513 unsigned fw_rendercount;
514 unsigned fw_mediacount;
515
Chris Wilson82326442014-03-05 12:00:39 +0000516 struct timer_list force_wake_timer;
Chris Wilson907b28c2013-07-19 20:36:52 +0100517};
518
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100519#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
520 func(is_mobile) sep \
521 func(is_i85x) sep \
522 func(is_i915g) sep \
523 func(is_i945gm) sep \
524 func(is_g33) sep \
525 func(need_gfx_hws) sep \
526 func(is_g4x) sep \
527 func(is_pineview) sep \
528 func(is_broadwater) sep \
529 func(is_crestline) sep \
530 func(is_ivybridge) sep \
531 func(is_valleyview) sep \
532 func(is_haswell) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700533 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100534 func(has_fbc) sep \
535 func(has_pipe_cxsr) sep \
536 func(has_hotplug) sep \
537 func(cursor_needs_physical) sep \
538 func(has_overlay) sep \
539 func(overlay_needs_physical) sep \
540 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100541 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100542 func(has_ddi) sep \
543 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200544
Damien Lespiaua587f772013-04-22 18:40:38 +0100545#define DEFINE_FLAG(name) u8 name:1
546#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200547
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500548struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200549 u32 display_mmio_offset;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700550 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000551 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000552 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700553 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100554 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200555 /* Register offsets for the various display pipes and transcoders */
556 int pipe_offsets[I915_MAX_TRANSCODERS];
557 int trans_offsets[I915_MAX_TRANSCODERS];
558 int dpll_offsets[I915_MAX_PIPES];
559 int dpll_md_offsets[I915_MAX_PIPES];
560 int palette_offsets[I915_MAX_PIPES];
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500561};
562
Damien Lespiaua587f772013-04-22 18:40:38 +0100563#undef DEFINE_FLAG
564#undef SEP_SEMICOLON
565
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800566enum i915_cache_level {
567 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100568 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
569 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
570 caches, eg sampler/render caches, and the
571 large Last-Level-Cache. LLC is coherent with
572 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100573 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800574};
575
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300576struct i915_ctx_hang_stats {
577 /* This context had batch pending when hang was declared */
578 unsigned batch_pending;
579
580 /* This context had batch active when hang was declared */
581 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300582
583 /* Time when this context was last blamed for a GPU reset */
584 unsigned long guilty_ts;
585
586 /* This context is banned to submit more work */
587 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300588};
Ben Widawsky40521052012-06-04 14:42:43 -0700589
590/* This must match up with the value previously used for execbuf2.rsvd1. */
591#define DEFAULT_CONTEXT_ID 0
592struct i915_hw_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300593 struct kref ref;
Ben Widawsky40521052012-06-04 14:42:43 -0700594 int id;
Ben Widawskye0556842012-06-04 14:42:46 -0700595 bool is_initialized;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700596 uint8_t remap_slice;
Ben Widawsky40521052012-06-04 14:42:43 -0700597 struct drm_i915_file_private *file_priv;
Ben Widawsky0009e462013-12-06 14:11:02 -0800598 struct intel_ring_buffer *last_ring;
Ben Widawsky40521052012-06-04 14:42:43 -0700599 struct drm_i915_gem_object *obj;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300600 struct i915_ctx_hang_stats hang_stats;
Ben Widawskyc7c48df2013-12-06 14:11:15 -0800601 struct i915_address_space *vm;
Ben Widawskya33afea2013-09-17 21:12:45 -0700602
603 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700604};
605
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700606struct i915_fbc {
607 unsigned long size;
608 unsigned int fb_id;
609 enum plane plane;
610 int y;
611
612 struct drm_mm_node *compressed_fb;
613 struct drm_mm_node *compressed_llb;
614
615 struct intel_fbc_work {
616 struct delayed_work work;
617 struct drm_crtc *crtc;
618 struct drm_framebuffer *fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700619 } *fbc_work;
620
Chris Wilson29ebf902013-07-27 17:23:55 +0100621 enum no_fbc_reason {
622 FBC_OK, /* FBC is enabled */
623 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700624 FBC_NO_OUTPUT, /* no outputs enabled to compress */
625 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
626 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
627 FBC_MODE_TOO_LARGE, /* mode too large for compression */
628 FBC_BAD_PLANE, /* fbc not supported on plane */
629 FBC_NOT_TILED, /* buffer not tiled */
630 FBC_MULTIPLE_PIPES, /* more than one pipe active */
631 FBC_MODULE_PARAM,
632 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
633 } no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800634};
635
Rodrigo Vivia031d702013-10-03 16:15:06 -0300636struct i915_psr {
637 bool sink_support;
638 bool source_ok;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300639};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700640
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800641enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300642 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800643 PCH_IBX, /* Ibexpeak PCH */
644 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300645 PCH_LPT, /* Lynxpoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700646 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800647};
648
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200649enum intel_sbi_destination {
650 SBI_ICLK,
651 SBI_MPHY,
652};
653
Jesse Barnesb690e962010-07-19 13:53:12 -0700654#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700655#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100656#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Jesse Barnesb690e962010-07-19 13:53:12 -0700657
Dave Airlie8be48d92010-03-30 05:34:14 +0000658struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100659struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000660
Daniel Vetterc2b91522012-02-14 22:37:19 +0100661struct intel_gmbus {
662 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000663 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100664 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100665 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100666 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100667 struct drm_i915_private *dev_priv;
668};
669
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100670struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000671 u8 saveLBB;
672 u32 saveDSPACNTR;
673 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000674 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000675 u32 savePIPEACONF;
676 u32 savePIPEBCONF;
677 u32 savePIPEASRC;
678 u32 savePIPEBSRC;
679 u32 saveFPA0;
680 u32 saveFPA1;
681 u32 saveDPLL_A;
682 u32 saveDPLL_A_MD;
683 u32 saveHTOTAL_A;
684 u32 saveHBLANK_A;
685 u32 saveHSYNC_A;
686 u32 saveVTOTAL_A;
687 u32 saveVBLANK_A;
688 u32 saveVSYNC_A;
689 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000690 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800691 u32 saveTRANS_HTOTAL_A;
692 u32 saveTRANS_HBLANK_A;
693 u32 saveTRANS_HSYNC_A;
694 u32 saveTRANS_VTOTAL_A;
695 u32 saveTRANS_VBLANK_A;
696 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000697 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000698 u32 saveDSPASTRIDE;
699 u32 saveDSPASIZE;
700 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700701 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000702 u32 saveDSPASURF;
703 u32 saveDSPATILEOFF;
704 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700705 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000706 u32 saveBLC_PWM_CTL;
707 u32 saveBLC_PWM_CTL2;
Jesse Barnes07bf1392013-10-31 18:55:50 +0200708 u32 saveBLC_HIST_CTL_B;
Zhenyu Wang42048782009-10-21 15:27:01 +0800709 u32 saveBLC_CPU_PWM_CTL;
710 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000711 u32 saveFPB0;
712 u32 saveFPB1;
713 u32 saveDPLL_B;
714 u32 saveDPLL_B_MD;
715 u32 saveHTOTAL_B;
716 u32 saveHBLANK_B;
717 u32 saveHSYNC_B;
718 u32 saveVTOTAL_B;
719 u32 saveVBLANK_B;
720 u32 saveVSYNC_B;
721 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000722 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800723 u32 saveTRANS_HTOTAL_B;
724 u32 saveTRANS_HBLANK_B;
725 u32 saveTRANS_HSYNC_B;
726 u32 saveTRANS_VTOTAL_B;
727 u32 saveTRANS_VBLANK_B;
728 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000729 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000730 u32 saveDSPBSTRIDE;
731 u32 saveDSPBSIZE;
732 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700733 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000734 u32 saveDSPBSURF;
735 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700736 u32 saveVGA0;
737 u32 saveVGA1;
738 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000739 u32 saveVGACNTRL;
740 u32 saveADPA;
741 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700742 u32 savePP_ON_DELAYS;
743 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000744 u32 saveDVOA;
745 u32 saveDVOB;
746 u32 saveDVOC;
747 u32 savePP_ON;
748 u32 savePP_OFF;
749 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700750 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000751 u32 savePFIT_CONTROL;
752 u32 save_palette_a[256];
753 u32 save_palette_b[256];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000754 u32 saveFBC_CONTROL;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000755 u32 saveIER;
756 u32 saveIIR;
757 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800758 u32 saveDEIER;
759 u32 saveDEIMR;
760 u32 saveGTIER;
761 u32 saveGTIMR;
762 u32 saveFDI_RXA_IMR;
763 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800764 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800765 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000766 u32 saveSWF0[16];
767 u32 saveSWF1[16];
768 u32 saveSWF2[3];
769 u8 saveMSR;
770 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800771 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000772 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000773 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000774 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000775 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200776 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000777 u32 saveCURACNTR;
778 u32 saveCURAPOS;
779 u32 saveCURABASE;
780 u32 saveCURBCNTR;
781 u32 saveCURBPOS;
782 u32 saveCURBBASE;
783 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700784 u32 saveDP_B;
785 u32 saveDP_C;
786 u32 saveDP_D;
787 u32 savePIPEA_GMCH_DATA_M;
788 u32 savePIPEB_GMCH_DATA_M;
789 u32 savePIPEA_GMCH_DATA_N;
790 u32 savePIPEB_GMCH_DATA_N;
791 u32 savePIPEA_DP_LINK_M;
792 u32 savePIPEB_DP_LINK_M;
793 u32 savePIPEA_DP_LINK_N;
794 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800795 u32 saveFDI_RXA_CTL;
796 u32 saveFDI_TXA_CTL;
797 u32 saveFDI_RXB_CTL;
798 u32 saveFDI_TXB_CTL;
799 u32 savePFA_CTL_1;
800 u32 savePFB_CTL_1;
801 u32 savePFA_WIN_SZ;
802 u32 savePFB_WIN_SZ;
803 u32 savePFA_WIN_POS;
804 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000805 u32 savePCH_DREF_CONTROL;
806 u32 saveDISP_ARB_CTL;
807 u32 savePIPEA_DATA_M1;
808 u32 savePIPEA_DATA_N1;
809 u32 savePIPEA_LINK_M1;
810 u32 savePIPEA_LINK_N1;
811 u32 savePIPEB_DATA_M1;
812 u32 savePIPEB_DATA_N1;
813 u32 savePIPEB_LINK_M1;
814 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000815 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400816 u32 savePCH_PORT_HOTPLUG;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100817};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100818
819struct intel_gen6_power_mgmt {
Daniel Vetter59cdb632013-07-04 23:35:28 +0200820 /* work and pm_iir are protected by dev_priv->irq_lock */
Daniel Vetterc85aa882012-11-02 19:55:03 +0100821 struct work_struct work;
822 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +0200823
Ben Widawskyb39fb292014-03-19 18:31:11 -0700824 /* Frequencies are stored in potentially platform dependent multiples.
825 * In other words, *_freq needs to be multiplied by X to be interesting.
826 * Soft limits are those which are used for the dynamic reclocking done
827 * by the driver (raise frequencies under heavy loads, and lower for
828 * lighter loads). Hard limits are those imposed by the hardware.
829 *
830 * A distinction is made for overclocking, which is never enabled by
831 * default, and is considered to be above the hard limit if it's
832 * possible at all.
833 */
834 u8 cur_freq; /* Current frequency (cached, may not == HW) */
835 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
836 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
837 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
838 u8 min_freq; /* AKA RPn. Minimum frequency */
839 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
840 u8 rp1_freq; /* "less than" RP0 power/freqency */
841 u8 rp0_freq; /* Non-overclocked max frequency. */
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700842
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100843 int last_adj;
844 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
845
Chris Wilsonc0951f02013-10-10 21:58:50 +0100846 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700847 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700848
849 /*
850 * Protects RPS/RC6 register access and PCU communication.
851 * Must be taken after struct_mutex if nested.
852 */
853 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100854};
855
Daniel Vetter1a240d42012-11-29 22:18:51 +0100856/* defined intel_pm.c */
857extern spinlock_t mchdev_lock;
858
Daniel Vetterc85aa882012-11-02 19:55:03 +0100859struct intel_ilk_power_mgmt {
860 u8 cur_delay;
861 u8 min_delay;
862 u8 max_delay;
863 u8 fmax;
864 u8 fstart;
865
866 u64 last_count1;
867 unsigned long last_time1;
868 unsigned long chipset_power;
869 u64 last_count2;
870 struct timespec last_time2;
871 unsigned long gfx_power;
872 u8 corr;
873
874 int c_m;
875 int r_t;
Daniel Vetter3e373942012-11-02 19:55:04 +0100876
877 struct drm_i915_gem_object *pwrctx;
878 struct drm_i915_gem_object *renderctx;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100879};
880
Imre Deakc6cb5822014-03-04 19:22:55 +0200881struct drm_i915_private;
882struct i915_power_well;
883
884struct i915_power_well_ops {
885 /*
886 * Synchronize the well's hw state to match the current sw state, for
887 * example enable/disable it based on the current refcount. Called
888 * during driver init and resume time, possibly after first calling
889 * the enable/disable handlers.
890 */
891 void (*sync_hw)(struct drm_i915_private *dev_priv,
892 struct i915_power_well *power_well);
893 /*
894 * Enable the well and resources that depend on it (for example
895 * interrupts located on the well). Called after the 0->1 refcount
896 * transition.
897 */
898 void (*enable)(struct drm_i915_private *dev_priv,
899 struct i915_power_well *power_well);
900 /*
901 * Disable the well and resources that depend on it. Called after
902 * the 1->0 refcount transition.
903 */
904 void (*disable)(struct drm_i915_private *dev_priv,
905 struct i915_power_well *power_well);
906 /* Returns the hw enabled state. */
907 bool (*is_enabled)(struct drm_i915_private *dev_priv,
908 struct i915_power_well *power_well);
909};
910
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800911/* Power well structure for haswell */
912struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +0200913 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +0200914 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800915 /* power well enable/disable usage count */
916 int count;
Imre Deakc1ca7272013-11-25 17:15:29 +0200917 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +0200918 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +0200919 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800920};
921
Imre Deak83c00f552013-10-25 17:36:47 +0300922struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +0300923 /*
924 * Power wells needed for initialization at driver init and suspend
925 * time are on. They are kept on until after the first modeset.
926 */
927 bool init_power_on;
Imre Deakc1ca7272013-11-25 17:15:29 +0200928 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +0300929
Imre Deak83c00f552013-10-25 17:36:47 +0300930 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +0200931 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +0200932 struct i915_power_well *power_wells;
Imre Deak83c00f552013-10-25 17:36:47 +0300933};
934
Daniel Vetter231f42a2012-11-02 19:55:05 +0100935struct i915_dri1_state {
936 unsigned allow_batchbuffer : 1;
937 u32 __iomem *gfx_hws_cpu_addr;
938
939 unsigned int cpp;
940 int back_offset;
941 int front_offset;
942 int current_page;
943 int page_flipping;
944
945 uint32_t counter;
946};
947
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200948struct i915_ums_state {
949 /**
950 * Flag if the X Server, and thus DRM, is not currently in
951 * control of the device.
952 *
953 * This is set between LeaveVT and EnterVT. It needs to be
954 * replaced with a semaphore. It also needs to be
955 * transitioned away from for kernel modesetting.
956 */
957 int mm_suspended;
958};
959
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700960#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100961struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700962 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100963 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700964 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100965};
966
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100967struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100968 /** Memory allocator for GTT stolen memory */
969 struct drm_mm stolen;
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100970 /** List of all objects in gtt_space. Used to restore gtt
971 * mappings on resume */
972 struct list_head bound_list;
973 /**
974 * List of objects which are not bound to the GTT (thus
975 * are idle and not used by the GPU) but still have
976 * (presumably uncached) pages still attached.
977 */
978 struct list_head unbound_list;
979
980 /** Usable portion of the GTT for GEM */
981 unsigned long stolen_base; /* limited to low memory (32-bit) */
982
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100983 /** PPGTT used for aliasing the PPGTT with the GTT */
984 struct i915_hw_ppgtt *aliasing_ppgtt;
985
986 struct shrinker inactive_shrinker;
987 bool shrinker_no_lock_stealing;
988
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100989 /** LRU list of objects with fence regs on them. */
990 struct list_head fence_list;
991
992 /**
993 * We leave the user IRQ off as much as possible,
994 * but this means that requests will finish and never
995 * be retired once the system goes idle. Set a timer to
996 * fire periodically while the ring is running. When it
997 * fires, go retire requests.
998 */
999 struct delayed_work retire_work;
1000
1001 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001002 * When we detect an idle GPU, we want to turn on
1003 * powersaving features. So once we see that there
1004 * are no more requests outstanding and no more
1005 * arrive within a small period of time, we fire
1006 * off the idle_work.
1007 */
1008 struct delayed_work idle_work;
1009
1010 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001011 * Are we in a non-interruptible section of code like
1012 * modesetting?
1013 */
1014 bool interruptible;
1015
Chris Wilsonf62a0072014-02-21 17:55:39 +00001016 /**
1017 * Is the GPU currently considered idle, or busy executing userspace
1018 * requests? Whilst idle, we attempt to power down the hardware and
1019 * display clocks. In order to reduce the effect on performance, there
1020 * is a slight delay before we do so.
1021 */
1022 bool busy;
1023
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001024 /** Bit 6 swizzling required for X tiling */
1025 uint32_t bit_6_swizzle_x;
1026 /** Bit 6 swizzling required for Y tiling */
1027 uint32_t bit_6_swizzle_y;
1028
1029 /* storage for physical objects */
1030 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1031
1032 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001033 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001034 size_t object_memory;
1035 u32 object_count;
1036};
1037
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001038struct drm_i915_error_state_buf {
1039 unsigned bytes;
1040 unsigned size;
1041 int err;
1042 u8 *buf;
1043 loff_t start;
1044 loff_t pos;
1045};
1046
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001047struct i915_error_state_file_priv {
1048 struct drm_device *dev;
1049 struct drm_i915_error_state *error;
1050};
1051
Daniel Vetter99584db2012-11-14 17:14:04 +01001052struct i915_gpu_error {
1053 /* For hangcheck timer */
1054#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1055#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001056 /* Hang gpu twice in this window and your context gets banned */
1057#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1058
Daniel Vetter99584db2012-11-14 17:14:04 +01001059 struct timer_list hangcheck_timer;
Daniel Vetter99584db2012-11-14 17:14:04 +01001060
1061 /* For reset and error_state handling. */
1062 spinlock_t lock;
1063 /* Protected by the above dev->gpu_error.lock. */
1064 struct drm_i915_error_state *first_error;
1065 struct work_struct work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001066
Chris Wilson094f9a52013-09-25 17:34:55 +01001067
1068 unsigned long missed_irq_rings;
1069
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001070 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001071 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001072 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001073 * This is a counter which gets incremented when reset is triggered,
1074 * and again when reset has been handled. So odd values (lowest bit set)
1075 * means that reset is in progress and even values that
1076 * (reset_counter >> 1):th reset was successfully completed.
1077 *
1078 * If reset is not completed succesfully, the I915_WEDGE bit is
1079 * set meaning that hardware is terminally sour and there is no
1080 * recovery. All waiters on the reset_queue will be woken when
1081 * that happens.
1082 *
1083 * This counter is used by the wait_seqno code to notice that reset
1084 * event happened and it needs to restart the entire ioctl (since most
1085 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001086 *
1087 * This is important for lock-free wait paths, where no contended lock
1088 * naturally enforces the correct ordering between the bail-out of the
1089 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001090 */
1091 atomic_t reset_counter;
1092
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001093#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001094#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001095
1096 /**
1097 * Waitqueue to signal when the reset has completed. Used by clients
1098 * that wait for dev_priv->mm.wedged to settle.
1099 */
1100 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001101
Daniel Vetter99584db2012-11-14 17:14:04 +01001102 /* For gpu hang simulation. */
1103 unsigned int stop_rings;
Chris Wilson094f9a52013-09-25 17:34:55 +01001104
1105 /* For missed irq/seqno simulation. */
1106 unsigned int test_irq_rings;
Daniel Vetter99584db2012-11-14 17:14:04 +01001107};
1108
Zhang Ruib8efb172013-02-05 15:41:53 +08001109enum modeset_restore {
1110 MODESET_ON_LID_OPEN,
1111 MODESET_DONE,
1112 MODESET_SUSPENDED,
1113};
1114
Paulo Zanoni6acab152013-09-12 17:06:24 -03001115struct ddi_vbt_port_info {
1116 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001117
1118 uint8_t supports_dvi:1;
1119 uint8_t supports_hdmi:1;
1120 uint8_t supports_dp:1;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001121};
1122
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001123struct intel_vbt_data {
1124 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1125 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1126
1127 /* Feature bits */
1128 unsigned int int_tv_support:1;
1129 unsigned int lvds_dither:1;
1130 unsigned int lvds_vbt:1;
1131 unsigned int int_crt_support:1;
1132 unsigned int lvds_use_ssc:1;
1133 unsigned int display_clock_mode:1;
1134 unsigned int fdi_rx_polarity_inverted:1;
1135 int lvds_ssc_freq;
1136 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1137
1138 /* eDP */
1139 int edp_rate;
1140 int edp_lanes;
1141 int edp_preemphasis;
1142 int edp_vswing;
1143 bool edp_initialized;
1144 bool edp_support;
1145 int edp_bpp;
1146 struct edp_power_seq edp_pps;
1147
Jani Nikulaf00076d2013-12-14 20:38:29 -02001148 struct {
1149 u16 pwm_freq_hz;
1150 bool active_low_pwm;
1151 } backlight;
1152
Shobhit Kumard17c5442013-08-27 15:12:25 +03001153 /* MIPI DSI */
1154 struct {
1155 u16 panel_id;
1156 } dsi;
1157
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001158 int crt_ddc_pin;
1159
1160 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001161 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001162
1163 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001164};
1165
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001166enum intel_ddb_partitioning {
1167 INTEL_DDB_PART_1_2,
1168 INTEL_DDB_PART_5_6, /* IVB+ */
1169};
1170
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001171struct intel_wm_level {
1172 bool enable;
1173 uint32_t pri_val;
1174 uint32_t spr_val;
1175 uint32_t cur_val;
1176 uint32_t fbc_val;
1177};
1178
Imre Deak820c1982013-12-17 14:46:36 +02001179struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001180 uint32_t wm_pipe[3];
1181 uint32_t wm_lp[3];
1182 uint32_t wm_lp_spr[3];
1183 uint32_t wm_linetime[3];
1184 bool enable_fbc_wm;
1185 enum intel_ddb_partitioning partitioning;
1186};
1187
Paulo Zanonic67a4702013-08-19 13:18:09 -03001188/*
Paulo Zanoni765dab62014-03-07 20:08:18 -03001189 * This struct helps tracking the state needed for runtime PM, which puts the
1190 * device in PCI D3 state. Notice that when this happens, nothing on the
1191 * graphics device works, even register access, so we don't get interrupts nor
1192 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001193 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001194 * Every piece of our code that needs to actually touch the hardware needs to
1195 * either call intel_runtime_pm_get or call intel_display_power_get with the
1196 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001197 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001198 * Our driver uses the autosuspend delay feature, which means we'll only really
1199 * suspend if we stay with zero refcount for a certain amount of time. The
1200 * default value is currently very conservative (see intel_init_runtime_pm), but
1201 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001202 *
1203 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1204 * goes back to false exactly before we reenable the IRQs. We use this variable
1205 * to check if someone is trying to enable/disable IRQs while they're supposed
1206 * to be disabled. This shouldn't happen and we'll print some error messages in
1207 * case it happens, but if it actually happens we'll also update the variables
1208 * inside struct regsave so when we restore the IRQs they will contain the
1209 * latest expected values.
1210 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001211 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001212 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001213struct i915_runtime_pm {
1214 bool suspended;
1215 bool irqs_disabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001216
1217 struct {
1218 uint32_t deimr;
1219 uint32_t sdeimr;
1220 uint32_t gtimr;
1221 uint32_t gtier;
1222 uint32_t gen6_pmimr;
1223 } regsave;
1224};
1225
Daniel Vetter926321d2013-10-16 13:30:34 +02001226enum intel_pipe_crc_source {
1227 INTEL_PIPE_CRC_SOURCE_NONE,
1228 INTEL_PIPE_CRC_SOURCE_PLANE1,
1229 INTEL_PIPE_CRC_SOURCE_PLANE2,
1230 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001231 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001232 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1233 INTEL_PIPE_CRC_SOURCE_TV,
1234 INTEL_PIPE_CRC_SOURCE_DP_B,
1235 INTEL_PIPE_CRC_SOURCE_DP_C,
1236 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001237 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001238 INTEL_PIPE_CRC_SOURCE_MAX,
1239};
1240
Shuang He8bf1e9f2013-10-15 18:55:27 +01001241struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001242 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001243 uint32_t crc[5];
1244};
1245
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001246#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001247struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001248 spinlock_t lock;
1249 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001250 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001251 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001252 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001253 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001254};
1255
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001256typedef struct drm_i915_private {
1257 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +00001258 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001259
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001260 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001261
1262 int relative_constants_mode;
1263
1264 void __iomem *regs;
1265
Chris Wilson907b28c2013-07-19 20:36:52 +01001266 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001267
1268 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1269
Daniel Vetter28c70f12012-12-01 13:53:45 +01001270
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001271 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1272 * controller on different i2c buses. */
1273 struct mutex gmbus_mutex;
1274
1275 /**
1276 * Base address of the gmbus and gpio block.
1277 */
1278 uint32_t gpio_mmio_base;
1279
Daniel Vetter28c70f12012-12-01 13:53:45 +01001280 wait_queue_head_t gmbus_wait_queue;
1281
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001282 struct pci_dev *bridge_dev;
1283 struct intel_ring_buffer ring[I915_NUM_RINGS];
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001284 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001285
1286 drm_dma_handle_t *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001287 struct resource mch_res;
1288
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001289 /* protects the irq masks */
1290 spinlock_t irq_lock;
1291
Imre Deakf8b79e52014-03-04 19:23:07 +02001292 bool display_irqs_enabled;
1293
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001294 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1295 struct pm_qos_request pm_qos;
1296
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001297 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +01001298 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001299
1300 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001301 union {
1302 u32 irq_mask;
1303 u32 de_irq_mask[I915_MAX_PIPES];
1304 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001305 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001306 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301307 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001308 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001309
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001310 struct work_struct hotplug_work;
Daniel Vetter52d7ece2012-12-01 21:03:22 +01001311 bool enable_hotplug_processing;
Egbert Eichb543fb02013-04-16 13:36:54 +02001312 struct {
1313 unsigned long hpd_last_jiffies;
1314 int hpd_cnt;
1315 enum {
1316 HPD_ENABLED = 0,
1317 HPD_DISABLED = 1,
1318 HPD_MARK_DISABLED = 2
1319 } hpd_mark;
1320 } hpd_stats[HPD_NUM_PINS];
Egbert Eich142e2392013-04-11 15:57:57 +02001321 u32 hpd_event_bits;
Egbert Eichac4c16c2013-04-16 13:36:58 +02001322 struct timer_list hotplug_reenable_timer;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001323
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001324 struct i915_fbc fbc;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001325 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001326 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001327
1328 /* overlay */
1329 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001330
Jani Nikula58c68772013-11-08 16:48:54 +02001331 /* backlight registers and fields in struct intel_panel */
1332 spinlock_t backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001333
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001334 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001335 bool no_aux_handshake;
1336
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001337 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1338 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1339 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1340
1341 unsigned int fsb_freq, mem_freq, is_ddr3;
1342
Daniel Vetter645416f2013-09-02 16:22:25 +02001343 /**
1344 * wq - Driver workqueue for GEM.
1345 *
1346 * NOTE: Work items scheduled here are not allowed to grab any modeset
1347 * locks, for otherwise the flushing done in the pageflip code will
1348 * result in deadlocks.
1349 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001350 struct workqueue_struct *wq;
1351
1352 /* Display functions */
1353 struct drm_i915_display_funcs display;
1354
1355 /* PCH chipset type */
1356 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001357 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001358
1359 unsigned long quirks;
1360
Zhang Ruib8efb172013-02-05 15:41:53 +08001361 enum modeset_restore modeset_restore;
1362 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001363
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001364 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001365 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001366
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001367 struct i915_gem_mm mm;
Daniel Vetter87813422012-05-02 11:49:32 +02001368
Daniel Vetter87813422012-05-02 11:49:32 +02001369 /* Kernel Modesetting */
1370
yakui_zhao9b9d1722009-05-31 17:17:17 +08001371 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001372
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001373 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1374 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001375 wait_queue_head_t pending_flip_queue;
1376
Daniel Vetterc4597872013-10-21 21:04:07 +02001377#ifdef CONFIG_DEBUG_FS
1378 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1379#endif
1380
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001381 int num_shared_dpll;
1382 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001383 struct intel_ddi_plls ddi_plls;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001384 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001385
Jesse Barnes652c3932009-08-17 13:31:43 -07001386 /* Reclocking support */
1387 bool render_reclock_avail;
1388 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001389 /* indicates the reduced downclock for LVDS*/
1390 int lvds_downclock;
Jesse Barnes652c3932009-08-17 13:31:43 -07001391 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001392
Zhenyu Wangc48044112009-12-17 14:48:43 +08001393 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001394
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001395 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001396
Ben Widawsky59124502013-07-04 11:02:05 -07001397 /* Cannot be determined by PCIID. You must always read a register. */
1398 size_t ellc_size;
1399
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001400 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001401 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001402
Daniel Vetter20e4d402012-08-08 23:35:39 +02001403 /* ilk-only ips/rps state. Everything in here is protected by the global
1404 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001405 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001406
Imre Deak83c00f552013-10-25 17:36:47 +03001407 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001408
Rodrigo Vivia031d702013-10-03 16:15:06 -03001409 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001410
Daniel Vetter99584db2012-11-14 17:14:04 +01001411 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001412
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001413 struct drm_i915_gem_object *vlv_pctx;
1414
Daniel Vetter4520f532013-10-09 09:18:51 +02001415#ifdef CONFIG_DRM_I915_FBDEV
Dave Airlie8be48d92010-03-30 05:34:14 +00001416 /* list of fbdev register on this device */
1417 struct intel_fbdev *fbdev;
Daniel Vetter4520f532013-10-09 09:18:51 +02001418#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001419
Jesse Barnes073f34d2012-11-02 11:13:59 -07001420 /*
1421 * The console may be contended at resume, but we don't
1422 * want it to block on it.
1423 */
1424 struct work_struct console_resume_work;
1425
Chris Wilsone953fd72011-02-21 22:23:52 +00001426 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001427 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001428
Ben Widawsky254f9652012-06-04 14:42:42 -07001429 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001430 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001431
Damien Lespiau3e683202012-12-11 18:48:29 +00001432 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001433
Daniel Vetter842f1c82014-03-10 10:01:44 +01001434 u32 suspend_count;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001435 struct i915_suspend_saved_registers regfile;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001436
Ville Syrjälä53615a52013-08-01 16:18:50 +03001437 struct {
1438 /*
1439 * Raw watermark latency values:
1440 * in 0.1us units for WM0,
1441 * in 0.5us units for WM1+.
1442 */
1443 /* primary */
1444 uint16_t pri_latency[5];
1445 /* sprite */
1446 uint16_t spr_latency[5];
1447 /* cursor */
1448 uint16_t cur_latency[5];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001449
1450 /* current hardware state */
Imre Deak820c1982013-12-17 14:46:36 +02001451 struct ilk_wm_values hw;
Ville Syrjälä53615a52013-08-01 16:18:50 +03001452 } wm;
1453
Paulo Zanoni8a187452013-12-06 20:32:13 -02001454 struct i915_runtime_pm pm;
1455
Daniel Vetter231f42a2012-11-02 19:55:05 +01001456 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1457 * here! */
1458 struct i915_dri1_state dri1;
Daniel Vetterdb1b76c2013-07-09 16:51:37 +02001459 /* Old ums support infrastructure, same warning applies. */
1460 struct i915_ums_state ums;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461} drm_i915_private_t;
1462
Chris Wilson2c1792a2013-08-01 18:39:55 +01001463static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1464{
1465 return dev->dev_private;
1466}
1467
Chris Wilsonb4519512012-05-11 14:29:30 +01001468/* Iterate over initialised rings */
1469#define for_each_ring(ring__, dev_priv__, i__) \
1470 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1471 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1472
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001473enum hdmi_force_audio {
1474 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1475 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1476 HDMI_AUDIO_AUTO, /* trust EDID */
1477 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1478};
1479
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001480#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001481
Chris Wilson37e680a2012-06-07 15:38:42 +01001482struct drm_i915_gem_object_ops {
1483 /* Interface between the GEM object and its backing storage.
1484 * get_pages() is called once prior to the use of the associated set
1485 * of pages before to binding them into the GTT, and put_pages() is
1486 * called after we no longer need them. As we expect there to be
1487 * associated cost with migrating pages between the backing storage
1488 * and making them available for the GPU (e.g. clflush), we may hold
1489 * onto the pages after they are no longer referenced by the GPU
1490 * in case they may be used again shortly (for example migrating the
1491 * pages to a different memory domain within the GTT). put_pages()
1492 * will therefore most likely be called when the object itself is
1493 * being released or under memory pressure (where we attempt to
1494 * reap pages for the shrinker).
1495 */
1496 int (*get_pages)(struct drm_i915_gem_object *);
1497 void (*put_pages)(struct drm_i915_gem_object *);
1498};
1499
Eric Anholt673a3942008-07-30 12:06:12 -07001500struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001501 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001502
Chris Wilson37e680a2012-06-07 15:38:42 +01001503 const struct drm_i915_gem_object_ops *ops;
1504
Ben Widawsky2f633152013-07-17 12:19:03 -07001505 /** List of VMAs backed by this object */
1506 struct list_head vma_list;
1507
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001508 /** Stolen memory for this object, instead of being backed by shmem. */
1509 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07001510 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001511
Chris Wilson69dc4982010-10-19 10:36:51 +01001512 struct list_head ring_list;
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02001513 /** Used in execbuf to temporarily hold a ref */
1514 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07001515
1516 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001517 * This is set if the object is on the active lists (has pending
1518 * rendering and so a non-zero seqno), and is not set if it i s on
1519 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001520 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001521 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001522
1523 /**
1524 * This is set if the object has been written to since last bound
1525 * to the GTT
1526 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001527 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001528
1529 /**
1530 * Fence register bits (if any) for this object. Will be set
1531 * as needed when mapped into the GTT.
1532 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001533 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001534 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001535
1536 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001537 * Advice: are the backing pages purgeable?
1538 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001539 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001540
1541 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001542 * Current tiling mode for the object.
1543 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001544 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001545 /**
1546 * Whether the tiling parameters for the currently associated fence
1547 * register have changed. Note that for the purposes of tracking
1548 * tiling changes we also treat the unfenced register, the register
1549 * slot that the object occupies whilst it executes a fenced
1550 * command (such as BLT on gen2/3), as a "fence".
1551 */
1552 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001553
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001554 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001555 * Is the object at the current location in the gtt mappable and
1556 * fenceable? Used to avoid costly recalculations.
1557 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001558 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001559
1560 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001561 * Whether the current gtt mapping needs to be mappable (and isn't just
1562 * mappable by accident). Track pin and fault separate for a more
1563 * accurate mappable working set.
1564 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001565 unsigned int fault_mappable:1;
1566 unsigned int pin_mappable:1;
Chris Wilsoncc98b412013-08-09 12:25:09 +01001567 unsigned int pin_display:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001568
Chris Wilsoncaea7472010-11-12 13:53:37 +00001569 /*
1570 * Is the GPU currently using a fence to access this buffer,
1571 */
1572 unsigned int pending_fenced_gpu_access:1;
1573 unsigned int fenced_gpu_access:1;
1574
Chris Wilson651d7942013-08-08 14:41:10 +01001575 unsigned int cache_level:3;
Chris Wilson93dfb402011-03-29 16:59:50 -07001576
Daniel Vetter7bddb012012-02-09 17:15:47 +01001577 unsigned int has_aliasing_ppgtt_mapping:1;
Daniel Vetter74898d72012-02-15 23:50:22 +01001578 unsigned int has_global_gtt_mapping:1;
Chris Wilson9da3da62012-06-01 15:20:22 +01001579 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001580
Chris Wilson9da3da62012-06-01 15:20:22 +01001581 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001582 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001583
Daniel Vetter1286ff72012-05-10 15:25:09 +02001584 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001585 void *dma_buf_vmapping;
1586 int vmapping_count;
1587
Chris Wilsoncaea7472010-11-12 13:53:37 +00001588 struct intel_ring_buffer *ring;
1589
Chris Wilson1c293ea2012-04-17 15:31:27 +01001590 /** Breadcrumb of last rendering to the buffer. */
Chris Wilson0201f1e2012-07-20 12:41:01 +01001591 uint32_t last_read_seqno;
1592 uint32_t last_write_seqno;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001593 /** Breadcrumb of last fenced GPU access to the buffer. */
1594 uint32_t last_fenced_seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001595
Daniel Vetter778c3542010-05-13 11:49:44 +02001596 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08001597 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07001598
Daniel Vetter80075d42013-10-09 21:23:52 +02001599 /** References from framebuffers, locks out tiling changes. */
1600 unsigned long framebuffer_references;
1601
Eric Anholt280b7132009-03-12 16:56:27 -07001602 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01001603 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07001604
Jesse Barnes79e53942008-11-07 14:24:08 -08001605 /** User space pin count and filp owning the pin */
Daniel Vetteraa5f8022013-10-10 14:46:37 +02001606 unsigned long user_pin_count;
Jesse Barnes79e53942008-11-07 14:24:08 -08001607 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001608
1609 /** for phy allocated objects */
1610 struct drm_i915_gem_phys_object *phys_obj;
Eric Anholt673a3942008-07-30 12:06:12 -07001611};
1612
Daniel Vetter62b8b212010-04-09 19:05:08 +00001613#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01001614
Eric Anholt673a3942008-07-30 12:06:12 -07001615/**
1616 * Request queue structure.
1617 *
1618 * The request queue allows us to note sequence numbers that have been emitted
1619 * and may be associated with active buffers to be retired.
1620 *
1621 * By keeping this list, we can avoid having to do questionable
1622 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1623 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1624 */
1625struct drm_i915_gem_request {
Zou Nan hai852835f2010-05-21 09:08:56 +08001626 /** On Which ring this request was generated */
1627 struct intel_ring_buffer *ring;
1628
Eric Anholt673a3942008-07-30 12:06:12 -07001629 /** GEM sequence number associated with this request. */
1630 uint32_t seqno;
1631
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001632 /** Position in the ringbuffer of the start of the request */
1633 u32 head;
1634
1635 /** Position in the ringbuffer of the end of the request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00001636 u32 tail;
1637
Mika Kuoppala0e50e962013-05-02 16:48:08 +03001638 /** Context related to this request */
1639 struct i915_hw_context *ctx;
1640
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001641 /** Batch buffer related to this request if any */
1642 struct drm_i915_gem_object *batch_obj;
1643
Eric Anholt673a3942008-07-30 12:06:12 -07001644 /** Time at which this request was emitted, in jiffies. */
1645 unsigned long emitted_jiffies;
1646
Eric Anholtb9624422009-06-03 07:27:35 +00001647 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07001648 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00001649
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001650 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00001651 /** file_priv list entry for this request */
1652 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001653};
1654
1655struct drm_i915_file_private {
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001656 struct drm_i915_private *dev_priv;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +02001657 struct drm_file *file;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001658
Eric Anholt673a3942008-07-30 12:06:12 -07001659 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08001660 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00001661 struct list_head request_list;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001662 struct delayed_work idle_work;
Eric Anholt673a3942008-07-30 12:06:12 -07001663 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07001664 struct idr context_idr;
Mika Kuoppalae59ec132013-06-12 12:35:28 +03001665
Ben Widawsky0eea67e2013-12-06 14:11:19 -08001666 struct i915_hw_context *private_default_ctx;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001667 atomic_t rps_wait_boost;
Eric Anholt673a3942008-07-30 12:06:12 -07001668};
1669
Brad Volkin351e3db2014-02-18 10:15:46 -08001670/*
1671 * A command that requires special handling by the command parser.
1672 */
1673struct drm_i915_cmd_descriptor {
1674 /*
1675 * Flags describing how the command parser processes the command.
1676 *
1677 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1678 * a length mask if not set
1679 * CMD_DESC_SKIP: The command is allowed but does not follow the
1680 * standard length encoding for the opcode range in
1681 * which it falls
1682 * CMD_DESC_REJECT: The command is never allowed
1683 * CMD_DESC_REGISTER: The command should be checked against the
1684 * register whitelist for the appropriate ring
1685 * CMD_DESC_MASTER: The command is allowed if the submitting process
1686 * is the DRM master
1687 */
1688 u32 flags;
1689#define CMD_DESC_FIXED (1<<0)
1690#define CMD_DESC_SKIP (1<<1)
1691#define CMD_DESC_REJECT (1<<2)
1692#define CMD_DESC_REGISTER (1<<3)
1693#define CMD_DESC_BITMASK (1<<4)
1694#define CMD_DESC_MASTER (1<<5)
1695
1696 /*
1697 * The command's unique identification bits and the bitmask to get them.
1698 * This isn't strictly the opcode field as defined in the spec and may
1699 * also include type, subtype, and/or subop fields.
1700 */
1701 struct {
1702 u32 value;
1703 u32 mask;
1704 } cmd;
1705
1706 /*
1707 * The command's length. The command is either fixed length (i.e. does
1708 * not include a length field) or has a length field mask. The flag
1709 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1710 * a length mask. All command entries in a command table must include
1711 * length information.
1712 */
1713 union {
1714 u32 fixed;
1715 u32 mask;
1716 } length;
1717
1718 /*
1719 * Describes where to find a register address in the command to check
1720 * against the ring's register whitelist. Only valid if flags has the
1721 * CMD_DESC_REGISTER bit set.
1722 */
1723 struct {
1724 u32 offset;
1725 u32 mask;
1726 } reg;
1727
1728#define MAX_CMD_DESC_BITMASKS 3
1729 /*
1730 * Describes command checks where a particular dword is masked and
1731 * compared against an expected value. If the command does not match
1732 * the expected value, the parser rejects it. Only valid if flags has
1733 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1734 * are valid.
1735 */
1736 struct {
1737 u32 offset;
1738 u32 mask;
1739 u32 expected;
1740 } bits[MAX_CMD_DESC_BITMASKS];
1741};
1742
1743/*
1744 * A table of commands requiring special handling by the command parser.
1745 *
1746 * Each ring has an array of tables. Each table consists of an array of command
1747 * descriptors, which must be sorted with command opcodes in ascending order.
1748 */
1749struct drm_i915_cmd_table {
1750 const struct drm_i915_cmd_descriptor *table;
1751 int count;
1752};
1753
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001754#define INTEL_INFO(dev) (&to_i915(dev)->info)
Zou Nan haicae58522010-11-09 17:17:32 +08001755
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001756#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1757#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08001758#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001759#define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08001760#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001761#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1762#define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08001763#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1764#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1765#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001766#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08001767#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001768#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1769#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08001770#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1771#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001772#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07001773#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001774#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1775 (dev)->pdev->device == 0x0152 || \
1776 (dev)->pdev->device == 0x015a)
1777#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1778 (dev)->pdev->device == 0x0106 || \
1779 (dev)->pdev->device == 0x010A)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07001780#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03001781#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Paulo Zanoni4e8058a2013-11-02 21:07:31 -07001782#define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
Zou Nan haicae58522010-11-09 17:17:32 +08001783#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03001784#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001785 ((dev)->pdev->device & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08001786#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1787 (((dev)->pdev->device & 0xf) == 0x2 || \
1788 ((dev)->pdev->device & 0xf) == 0x6 || \
1789 ((dev)->pdev->device & 0xf) == 0xe))
1790#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001791 ((dev)->pdev->device & 0xFF00) == 0x0A00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08001792#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Rodrigo Vivi94353732013-08-28 16:45:46 -03001793#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001794 ((dev)->pdev->device & 0x00F0) == 0x0020)
Ben Widawskyb833d682013-08-23 16:00:07 -07001795#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08001796
Jesse Barnes85436692011-04-06 12:11:14 -07001797/*
1798 * The genX designation typically refers to the render engine, so render
1799 * capability related checks should use IS_GEN, while display and other checks
1800 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1801 * chips, etc.).
1802 */
Zou Nan haicae58522010-11-09 17:17:32 +08001803#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1804#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1805#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1806#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1807#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07001808#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07001809#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Zou Nan haicae58522010-11-09 17:17:32 +08001810
Ben Widawsky73ae4782013-10-15 10:02:57 -07001811#define RENDER_RING (1<<RCS)
1812#define BSD_RING (1<<VCS)
1813#define BLT_RING (1<<BCS)
1814#define VEBOX_RING (1<<VECS)
1815#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1816#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1817#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
Eugeni Dodonov3d29b842012-01-17 14:43:53 -02001818#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Chris Wilson651d7942013-08-08 14:41:10 +01001819#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08001820#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1821
Ben Widawsky254f9652012-06-04 14:42:42 -07001822#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Ben Widawsky246cbfb2013-12-06 14:11:14 -08001823#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
Ben Widawskyc5dc5ce2014-01-27 23:07:00 -08001824#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1825 && !IS_BROADWELL(dev))
1826#define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08001827#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001828
Chris Wilson05394f32010-11-08 19:18:58 +00001829#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08001830#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1831
Daniel Vetterb45305f2012-12-17 16:21:27 +01001832/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1833#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01001834/*
1835 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1836 * even when in MSI mode. This results in spurious interrupt warnings if the
1837 * legacy irq no. is shared with another device. The kernel then disables that
1838 * interrupt source and so prevents the other device from working properly.
1839 */
1840#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1841#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01001842
Zou Nan haicae58522010-11-09 17:17:32 +08001843/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1844 * rows, which changed the alignment requirements and fence programming.
1845 */
1846#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1847 IS_I915GM(dev)))
1848#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1849#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1850#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08001851#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1852#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08001853
1854#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1855#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01001856#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08001857
Ben Widawsky2a114cc2013-11-02 21:07:47 -07001858#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01001859
Damien Lespiaudd93be52013-04-22 18:40:39 +01001860#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01001861#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Ben Widawskyed8546a2013-11-04 22:45:05 -08001862#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
Chris Wilson7c6c2652013-11-18 18:32:37 -08001863#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
Paulo Zanonidf4547d2013-12-13 15:22:32 -02001864#define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001865
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001866#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1867#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1868#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1869#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1870#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1871#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1872
Chris Wilson2c1792a2013-08-01 18:39:55 +01001873#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03001874#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08001875#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1876#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07001877#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03001878#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08001879
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001880/* DPF == dynamic parity feature */
1881#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1882#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07001883
Ben Widawskyc8735b02012-09-07 19:43:39 -07001884#define GT_FREQUENCY_MULTIPLIER 50
1885
Chris Wilson05394f32010-11-08 19:18:58 +00001886#include "i915_trace.h"
1887
Rob Clarkbaa70942013-08-02 13:27:49 -04001888extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10001889extern int i915_max_ioctl;
1890
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001891extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1892extern int i915_resume(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001893extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1894extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1895
Jani Nikulad330a952014-01-21 11:24:25 +02001896/* i915_params.c */
1897struct i915_params {
1898 int modeset;
1899 int panel_ignore_lid;
1900 unsigned int powersave;
1901 int semaphores;
1902 unsigned int lvds_downclock;
1903 int lvds_channel_mode;
1904 int panel_use_ssc;
1905 int vbt_sdvo_panel_type;
1906 int enable_rc6;
1907 int enable_fbc;
Jani Nikulad330a952014-01-21 11:24:25 +02001908 int enable_ppgtt;
1909 int enable_psr;
1910 unsigned int preliminary_hw_support;
1911 int disable_power_well;
1912 int enable_ips;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00001913 int invert_brightness;
Brad Volkin351e3db2014-02-18 10:15:46 -08001914 int enable_cmd_parser;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00001915 /* leave bools at the end to not create holes */
1916 bool enable_hangcheck;
1917 bool fastboot;
Jani Nikulad330a952014-01-21 11:24:25 +02001918 bool prefault_disable;
1919 bool reset;
Damien Lespiaua0bae572014-02-10 17:20:55 +00001920 bool disable_display;
Jani Nikulad330a952014-01-21 11:24:25 +02001921};
1922extern struct i915_params i915 __read_mostly;
1923
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924 /* i915_dma.c */
Daniel Vetterd05c6172012-04-26 23:28:09 +02001925void i915_update_dri1_breadcrumb(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001926extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +11001927extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001928extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -07001929extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001930extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10001931extern void i915_driver_preclose(struct drm_device *dev,
1932 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001933extern void i915_driver_postclose(struct drm_device *dev,
1934 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001935extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001936#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11001937extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1938 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001939#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001940extern int i915_emit_box(struct drm_device *dev,
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001941 struct drm_clip_rect *box,
1942 int DR1, int DR4);
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07001943extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02001944extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001945extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1946extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1947extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1948extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1949
Jesse Barnes073f34d2012-11-02 11:13:59 -07001950extern void intel_console_resume(struct work_struct *work);
Dave Airlieaf6061a2008-05-07 12:15:39 +10001951
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03001953void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02001954__printf(3, 4)
1955void i915_handle_error(struct drm_device *dev, bool wedged,
1956 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001957
Deepak S76c3552f2014-01-30 23:08:16 +05301958void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
1959 int new_delay);
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001960extern void intel_irq_init(struct drm_device *dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01001961extern void intel_hpd_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01001962
1963extern void intel_uncore_sanitize(struct drm_device *dev);
1964extern void intel_uncore_early_sanitize(struct drm_device *dev);
1965extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01001966extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01001967extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001968
Keith Packard7c463582008-11-04 02:03:27 -08001969void
Jani Nikula50227e12014-03-31 14:27:21 +03001970i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02001971 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08001972
1973void
Jani Nikula50227e12014-03-31 14:27:21 +03001974i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02001975 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08001976
Imre Deakf8b79e52014-03-04 19:23:07 +02001977void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
1978void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
1979
Eric Anholt673a3942008-07-30 12:06:12 -07001980/* i915_gem.c */
1981int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1982 struct drm_file *file_priv);
1983int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1984 struct drm_file *file_priv);
1985int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1986 struct drm_file *file_priv);
1987int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1988 struct drm_file *file_priv);
1989int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1990 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001991int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1992 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001993int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1994 struct drm_file *file_priv);
1995int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1996 struct drm_file *file_priv);
1997int i915_gem_execbuffer(struct drm_device *dev, void *data,
1998 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05001999int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2000 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002001int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2002 struct drm_file *file_priv);
2003int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2004 struct drm_file *file_priv);
2005int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2006 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002007int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2008 struct drm_file *file);
2009int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2010 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002011int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2012 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002013int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2014 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002015int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2016 struct drm_file *file_priv);
2017int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2018 struct drm_file *file_priv);
2019int i915_gem_set_tiling(struct drm_device *dev, void *data,
2020 struct drm_file *file_priv);
2021int i915_gem_get_tiling(struct drm_device *dev, void *data,
2022 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -07002023int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002025int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002027void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002028void *i915_gem_object_alloc(struct drm_device *dev);
2029void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002030void i915_gem_object_init(struct drm_i915_gem_object *obj,
2031 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002032struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2033 size_t size);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08002034void i915_init_vm(struct drm_i915_private *dev_priv,
2035 struct i915_address_space *vm);
Eric Anholt673a3942008-07-30 12:06:12 -07002036void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002037void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002038
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002039#define PIN_MAPPABLE 0x1
2040#define PIN_NONBLOCK 0x2
Daniel Vetterbf3d1492014-02-14 14:01:12 +01002041#define PIN_GLOBAL 0x4
Chris Wilson20217462010-11-23 15:26:33 +00002042int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
Ben Widawskyc37e2202013-07-31 16:59:58 -07002043 struct i915_address_space *vm,
Chris Wilson20217462010-11-23 15:26:33 +00002044 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002045 unsigned flags);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002046int __must_check i915_vma_unbind(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002047int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002048void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002049void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002050void i915_gem_lastclose(struct drm_device *dev);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002051
Brad Volkin4c914c02014-02-18 10:15:45 -08002052int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2053 int *needs_clflush);
2054
Chris Wilson37e680a2012-06-07 15:38:42 +01002055int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01002056static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2057{
Imre Deak67d5a502013-02-18 19:28:02 +02002058 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01002059
Imre Deak67d5a502013-02-18 19:28:02 +02002060 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02002061 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02002062
2063 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01002064}
Chris Wilsona5570172012-09-04 21:02:54 +01002065static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2066{
2067 BUG_ON(obj->pages == NULL);
2068 obj->pages_pin_count++;
2069}
2070static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2071{
2072 BUG_ON(obj->pages_pin_count == 0);
2073 obj->pages_pin_count--;
2074}
2075
Chris Wilson54cf91d2010-11-25 18:00:26 +00002076int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002077int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2078 struct intel_ring_buffer *to);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002079void i915_vma_move_to_active(struct i915_vma *vma,
2080 struct intel_ring_buffer *ring);
Dave Airlieff72145b2011-02-07 12:16:14 +10002081int i915_gem_dumb_create(struct drm_file *file_priv,
2082 struct drm_device *dev,
2083 struct drm_mode_create_dumb *args);
2084int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2085 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002086/**
2087 * Returns true if seq1 is later than seq2.
2088 */
2089static inline bool
2090i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2091{
2092 return (int32_t)(seq1 - seq2) >= 0;
2093}
2094
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002095int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2096int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01002097int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00002098int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00002099
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002100static inline bool
Chris Wilson1690e1e2011-12-14 13:57:08 +01002101i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2102{
2103 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2104 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2105 dev_priv->fence_regs[obj->fence_reg].pin_count++;
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002106 return true;
2107 } else
2108 return false;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002109}
2110
2111static inline void
2112i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2113{
2114 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2115 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsonb8c3af72013-06-12 11:29:47 +01002116 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002117 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2118 }
2119}
2120
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002121struct drm_i915_gem_request *
2122i915_gem_find_active_request(struct intel_ring_buffer *ring);
2123
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002124bool i915_gem_retire_requests(struct drm_device *dev);
Daniel Vetter33196de2012-11-14 17:14:05 +01002125int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002126 bool interruptible);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002127static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2128{
2129 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002130 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002131}
2132
2133static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2134{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002135 return atomic_read(&error->reset_counter) & I915_WEDGED;
2136}
2137
2138static inline u32 i915_reset_count(struct i915_gpu_error *error)
2139{
2140 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002141}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002142
Chris Wilson069efc12010-09-30 16:53:18 +01002143void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002144bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilsona8198ee2011-04-13 22:04:09 +01002145int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01002146int __must_check i915_gem_init(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002147int __must_check i915_gem_init_hw(struct drm_device *dev);
Ben Widawskyc3787e22013-09-17 21:12:44 -07002148int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002149void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002150void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002151int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002152int __must_check i915_gem_suspend(struct drm_device *dev);
Mika Kuoppala0025c072013-06-12 12:35:30 +03002153int __i915_add_request(struct intel_ring_buffer *ring,
2154 struct drm_file *file,
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002155 struct drm_i915_gem_object *batch_obj,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002156 u32 *seqno);
2157#define i915_add_request(ring, seqno) \
Dan Carpenter854c94a2013-06-18 10:29:58 +03002158 __i915_add_request(ring, NULL, NULL, seqno)
Ben Widawsky199b2bc2012-05-24 15:03:11 -07002159int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2160 uint32_t seqno);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002161int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002162int __must_check
2163i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2164 bool write);
2165int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002166i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2167int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002168i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2169 u32 alignment,
Chris Wilson20217462010-11-23 15:26:33 +00002170 struct intel_ring_buffer *pipelined);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002171void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002172int i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002173 struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01002174 int id,
2175 int align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002176void i915_gem_detach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002177 struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002178void i915_gem_free_all_phys_object(struct drm_device *dev);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002179int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00002180void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002181
Chris Wilson467cffb2011-03-07 10:42:03 +00002182uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02002183i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2184uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02002185i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2186 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00002187
Chris Wilsone4ffd172011-04-04 09:44:39 +01002188int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2189 enum i915_cache_level cache_level);
2190
Daniel Vetter1286ff72012-05-10 15:25:09 +02002191struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2192 struct dma_buf *dma_buf);
2193
2194struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2195 struct drm_gem_object *gem_obj, int flags);
2196
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002197void i915_gem_restore_fences(struct drm_device *dev);
2198
Ben Widawskya70a3142013-07-31 16:59:56 -07002199unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2200 struct i915_address_space *vm);
2201bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2202bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2203 struct i915_address_space *vm);
2204unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2205 struct i915_address_space *vm);
2206struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2207 struct i915_address_space *vm);
Ben Widawskyaccfef22013-08-14 11:38:35 +02002208struct i915_vma *
2209i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2210 struct i915_address_space *vm);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002211
2212struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08002213static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2214 struct i915_vma *vma;
2215 list_for_each_entry(vma, &obj->vma_list, vma_link)
2216 if (vma->pin_count > 0)
2217 return true;
2218 return false;
2219}
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002220
Ben Widawskya70a3142013-07-31 16:59:56 -07002221/* Some GGTT VM helpers */
2222#define obj_to_ggtt(obj) \
2223 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2224static inline bool i915_is_ggtt(struct i915_address_space *vm)
2225{
2226 struct i915_address_space *ggtt =
2227 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2228 return vm == ggtt;
2229}
2230
2231static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2232{
2233 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2234}
2235
2236static inline unsigned long
2237i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2238{
2239 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2240}
2241
2242static inline unsigned long
2243i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2244{
2245 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2246}
Ben Widawskyc37e2202013-07-31 16:59:58 -07002247
2248static inline int __must_check
2249i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2250 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002251 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07002252{
Daniel Vetterbf3d1492014-02-14 14:01:12 +01002253 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07002254}
Ben Widawskya70a3142013-07-31 16:59:56 -07002255
Daniel Vetterb2871102014-02-14 14:01:19 +01002256static inline int
2257i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2258{
2259 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2260}
2261
2262void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2263
Ben Widawsky254f9652012-06-04 14:42:42 -07002264/* i915_gem_context.c */
Ben Widawsky0eea67e2013-12-06 14:11:19 -08002265#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
Ben Widawsky8245be32013-11-06 13:56:29 -02002266int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07002267void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08002268void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08002269int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
Ben Widawsky2fa48d82013-12-06 14:11:04 -08002270int i915_gem_context_enable(struct drm_i915_private *dev_priv);
Ben Widawsky254f9652012-06-04 14:42:42 -07002271void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Ben Widawskye0556842012-06-04 14:42:46 -07002272int i915_switch_context(struct intel_ring_buffer *ring,
Ben Widawsky41bde552013-12-06 14:11:21 -08002273 struct drm_file *file, struct i915_hw_context *to);
2274struct i915_hw_context *
2275i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002276void i915_gem_context_free(struct kref *ctx_ref);
2277static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2278{
Ben Widawskyc4829722013-12-06 14:11:20 -08002279 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2280 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002281}
2282
2283static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2284{
Ben Widawskyc4829722013-12-06 14:11:20 -08002285 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2286 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002287}
2288
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002289static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2290{
2291 return c->id == DEFAULT_CONTEXT_ID;
2292}
2293
Ben Widawsky84624812012-06-04 14:42:54 -07002294int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2295 struct drm_file *file);
2296int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2297 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02002298
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002299/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07002300int __must_check i915_gem_evict_something(struct drm_device *dev,
2301 struct i915_address_space *vm,
2302 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01002303 unsigned alignment,
2304 unsigned cache_level,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002305 unsigned flags);
Ben Widawsky68c8c172013-09-11 14:57:50 -07002306int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilson6c085a72012-08-20 11:40:46 +02002307int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002308
Ben Widawsky0260c422014-03-22 22:47:21 -07002309/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07002310static inline void i915_gem_chipset_flush(struct drm_device *dev)
2311{
Chris Wilson05394f32010-11-08 19:18:58 +00002312 if (INTEL_INFO(dev)->gen < 6)
2313 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01002314}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08002315
Chris Wilson9797fbf2012-04-24 15:47:39 +01002316/* i915_gem_stolen.c */
2317int i915_gem_init_stolen(struct drm_device *dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00002318int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2319void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002320void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002321struct drm_i915_gem_object *
2322i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08002323struct drm_i915_gem_object *
2324i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2325 u32 stolen_offset,
2326 u32 gtt_offset,
2327 u32 size);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002328void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002329
Eric Anholt673a3942008-07-30 12:06:12 -07002330/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01002331static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00002332{
Jani Nikula50227e12014-03-31 14:27:21 +03002333 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00002334
2335 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2336 obj->tiling_mode != I915_TILING_NONE;
2337}
2338
Eric Anholt673a3942008-07-30 12:06:12 -07002339void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -07002340void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2341void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002342
2343/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01002344#if WATCH_LISTS
2345int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002346#else
Chris Wilson23bc5982010-09-29 16:10:57 +01002347#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07002348#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002349
Ben Gamari20172632009-02-17 20:08:50 -05002350/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04002351int i915_debugfs_init(struct drm_minor *minor);
2352void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002353#ifdef CONFIG_DEBUG_FS
Damien Lespiau07144422013-10-15 18:55:40 +01002354void intel_display_crc_init(struct drm_device *dev);
2355#else
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002356static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01002357#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03002358
2359/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002360__printf(2, 3)
2361void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03002362int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2363 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03002364int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2365 size_t count, loff_t pos);
2366static inline void i915_error_state_buf_release(
2367 struct drm_i915_error_state_buf *eb)
2368{
2369 kfree(eb->buf);
2370}
Mika Kuoppala58174462014-02-25 17:11:26 +02002371void i915_capture_error_state(struct drm_device *dev, bool wedge,
2372 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03002373void i915_error_state_get(struct drm_device *dev,
2374 struct i915_error_state_file_priv *error_priv);
2375void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2376void i915_destroy_error_state(struct drm_device *dev);
2377
2378void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2379const char *i915_cache_level_str(int type);
Ben Gamari20172632009-02-17 20:08:50 -05002380
Brad Volkin351e3db2014-02-18 10:15:46 -08002381/* i915_cmd_parser.c */
2382void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2383bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2384int i915_parse_cmds(struct intel_ring_buffer *ring,
2385 struct drm_i915_gem_object *batch_obj,
2386 u32 batch_start_offset,
2387 bool is_master);
2388
Jesse Barnes317c35d2008-08-25 15:11:06 -07002389/* i915_suspend.c */
2390extern int i915_save_state(struct drm_device *dev);
2391extern int i915_restore_state(struct drm_device *dev);
2392
Daniel Vetterd8157a32013-01-25 17:53:20 +01002393/* i915_ums.c */
2394void i915_save_display_reg(struct drm_device *dev);
2395void i915_restore_display_reg(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002396
Ben Widawsky0136db582012-04-10 21:17:01 -07002397/* i915_sysfs.c */
2398void i915_setup_sysfs(struct drm_device *dev_priv);
2399void i915_teardown_sysfs(struct drm_device *dev_priv);
2400
Chris Wilsonf899fc62010-07-20 15:44:45 -07002401/* intel_i2c.c */
2402extern int intel_setup_gmbus(struct drm_device *dev);
2403extern void intel_teardown_gmbus(struct drm_device *dev);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02002404static inline bool intel_gmbus_is_port_valid(unsigned port)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08002405{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08002406 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08002407}
2408
2409extern struct i2c_adapter *intel_gmbus_get_adapter(
2410 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01002411extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2412extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02002413static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01002414{
2415 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2416}
Chris Wilsonf899fc62010-07-20 15:44:45 -07002417extern void intel_i2c_reset(struct drm_device *dev);
2418
Chris Wilson3b617962010-08-24 09:02:58 +01002419/* intel_opregion.c */
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002420struct intel_encoder;
Chris Wilson44834a62010-08-19 16:09:23 +01002421#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08002422extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01002423extern void intel_opregion_init(struct drm_device *dev);
2424extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01002425extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002426extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2427 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03002428extern int intel_opregion_notify_adapter(struct drm_device *dev,
2429 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04002430#else
Lv Zheng27d50c82013-12-06 16:52:05 +08002431static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01002432static inline void intel_opregion_init(struct drm_device *dev) { return; }
2433static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01002434static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002435static inline int
2436intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2437{
2438 return 0;
2439}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03002440static inline int
2441intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2442{
2443 return 0;
2444}
Len Brown65e082c2008-10-24 17:18:10 -04002445#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01002446
Jesse Barnes723bfd72010-10-07 16:01:13 -07002447/* intel_acpi.c */
2448#ifdef CONFIG_ACPI
2449extern void intel_register_dsm_handler(void);
2450extern void intel_unregister_dsm_handler(void);
2451#else
2452static inline void intel_register_dsm_handler(void) { return; }
2453static inline void intel_unregister_dsm_handler(void) { return; }
2454#endif /* CONFIG_ACPI */
2455
Jesse Barnes79e53942008-11-07 14:24:08 -08002456/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02002457extern void intel_modeset_init_hw(struct drm_device *dev);
Imre Deak7d708ee2013-04-17 14:04:50 +03002458extern void intel_modeset_suspend_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002459extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01002460extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002461extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02002462extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10002463extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01002464extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2465 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01002466extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02002467extern void i915_redisable_vga_power_on(struct drm_device *dev);
Adam Jacksonee5382a2010-04-23 11:17:39 -04002468extern bool intel_fbc_enabled(struct drm_device *dev);
Chris Wilson43a95392011-07-08 12:22:36 +01002469extern void intel_disable_fbc(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002470extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02002471extern void intel_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002472extern void gen6_set_rps(struct drm_device *dev, u8 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002473extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2474extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2475extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
Akshay Joshi0206e352011-08-16 15:34:10 -04002476extern void intel_detect_pch(struct drm_device *dev);
2477extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07002478extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08002479
Ben Widawsky2911a352012-04-05 14:47:36 -07002480extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07002481int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2482 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02002483int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2484 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07002485
Chris Wilson6ef3d422010-08-04 20:26:07 +01002486/* overlay */
2487extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002488extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2489 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002490
2491extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002492extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002493 struct drm_device *dev,
2494 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01002495
Ben Widawskyb7287d82011-04-25 11:22:22 -07002496/* On SNB platform, before reading ring registers forcewake bit
2497 * must be set to prevent GT core from power down and stale values being
2498 * returned.
2499 */
Deepak Sc8d9a592013-11-23 14:55:42 +05302500void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2501void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
Paulo Zanonie998c402014-02-21 13:52:26 -03002502void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07002503
Ben Widawsky42c05262012-09-26 10:34:00 -07002504int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2505int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002506
2507/* intel_sideband.c */
Jani Nikula64936252013-05-22 15:36:20 +03002508u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2509void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2510u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03002511u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2512void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2513u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2514void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2515u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2516void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08002517u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2518void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03002519u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2520void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002521u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2522void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002523u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2524 enum intel_sbi_destination destination);
2525void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2526 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05302527u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2528void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002529
Ville Syrjälä2ec38152013-11-05 22:42:29 +02002530int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2531int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
Ben Widawsky42c05262012-09-26 10:34:00 -07002532
Deepak S940aece2013-11-23 14:55:43 +05302533void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2534void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2535
2536#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2537 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2538 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2539 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2540 ((reg) >= 0x2E000 && (reg) < 0x30000))
2541
2542#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2543 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2544 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2545 ((reg) >= 0x30000 && (reg) < 0x40000))
2546
Deepak Sc8d9a592013-11-23 14:55:42 +05302547#define FORCEWAKE_RENDER (1 << 0)
2548#define FORCEWAKE_MEDIA (1 << 1)
2549#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2550
2551
Ben Widawsky0b274482013-10-04 21:22:51 -07002552#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2553#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00002554
Ben Widawsky0b274482013-10-04 21:22:51 -07002555#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2556#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2557#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2558#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00002559
Ben Widawsky0b274482013-10-04 21:22:51 -07002560#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2561#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2562#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2563#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00002564
Chris Wilson698b3132014-03-21 13:16:43 +00002565/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2566 * will be implemented using 2 32-bit writes in an arbitrary order with
2567 * an arbitrary delay between them. This can cause the hardware to
2568 * act upon the intermediate value, possibly leading to corruption and
2569 * machine death. You have been warned.
2570 */
Ben Widawsky0b274482013-10-04 21:22:51 -07002571#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2572#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08002573
Chris Wilson50877442014-03-21 12:41:53 +00002574#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2575 u32 upper = I915_READ(upper_reg); \
2576 u32 lower = I915_READ(lower_reg); \
2577 u32 tmp = I915_READ(upper_reg); \
2578 if (upper != tmp) { \
2579 upper = tmp; \
2580 lower = I915_READ(lower_reg); \
2581 WARN_ON(I915_READ(upper_reg) != upper); \
2582 } \
2583 (u64)upper << 32 | lower; })
2584
Zou Nan haicae58522010-11-09 17:17:32 +08002585#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2586#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2587
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02002588/* "Broadcast RGB" property */
2589#define INTEL_BROADCAST_RGB_AUTO 0
2590#define INTEL_BROADCAST_RGB_FULL 1
2591#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08002592
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02002593static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2594{
2595 if (HAS_PCH_SPLIT(dev))
2596 return CPU_VGACNTRL;
2597 else if (IS_VALLEYVIEW(dev))
2598 return VLV_VGACNTRL;
2599 else
2600 return VGACNTRL;
2601}
2602
Ville Syrjälä2bb46292013-02-22 16:12:51 +02002603static inline void __user *to_user_ptr(u64 address)
2604{
2605 return (void __user *)(uintptr_t)address;
2606}
2607
Imre Deakdf977292013-05-21 20:03:17 +03002608static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2609{
2610 unsigned long j = msecs_to_jiffies(m);
2611
2612 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2613}
2614
2615static inline unsigned long
2616timespec_to_jiffies_timeout(const struct timespec *value)
2617{
2618 unsigned long j = timespec_to_jiffies(value);
2619
2620 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2621}
2622
Paulo Zanonidce56b32013-12-19 14:29:40 -02002623/*
2624 * If you need to wait X milliseconds between events A and B, but event B
2625 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2626 * when event A happened, then just before event B you call this function and
2627 * pass the timestamp as the first argument, and X as the second argument.
2628 */
2629static inline void
2630wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2631{
Imre Deakec5e0cf2014-01-29 13:25:40 +02002632 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02002633
2634 /*
2635 * Don't re-read the value of "jiffies" every time since it may change
2636 * behind our back and break the math.
2637 */
2638 tmp_jiffies = jiffies;
2639 target_jiffies = timestamp_jiffies +
2640 msecs_to_jiffies_timeout(to_wait_ms);
2641
2642 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02002643 remaining_jiffies = target_jiffies - tmp_jiffies;
2644 while (remaining_jiffies)
2645 remaining_jiffies =
2646 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02002647 }
2648}
2649
Linus Torvalds1da177e2005-04-16 15:20:36 -07002650#endif