Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c |
| 3 | * |
| 4 | * OMAP3 CPU IDLE Routines |
| 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Rajendra Nayak <rnayak@ti.com> |
| 8 | * |
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Karthik Dasu <karthik-dp@ti.com> |
| 11 | * |
| 12 | * Copyright (C) 2006 Nokia Corporation |
| 13 | * Tony Lindgren <tony@atomide.com> |
| 14 | * |
| 15 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 16 | * Richard Woodruff <r-woodruff2@ti.com> |
| 17 | * |
| 18 | * Based on pm.c for omap2 |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License version 2 as |
| 22 | * published by the Free Software Foundation. |
| 23 | */ |
| 24 | |
| 25 | #include <linux/cpuidle.h> |
| 26 | |
| 27 | #include <plat/prcm.h> |
| 28 | #include <plat/powerdomain.h> |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 29 | #include <plat/irqs.h> |
| 30 | #include <plat/control.h> |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 31 | #include <plat/serial.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 32 | |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 33 | #include "pm.h" |
| 34 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 35 | #ifdef CONFIG_CPU_IDLE |
| 36 | |
| 37 | #define OMAP3_MAX_STATES 7 |
| 38 | #define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ |
| 39 | #define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ |
| 40 | #define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ |
| 41 | #define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ |
| 42 | #define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ |
| 43 | #define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ |
| 44 | |
| 45 | struct omap3_processor_cx { |
| 46 | u8 valid; |
| 47 | u8 type; |
| 48 | u32 sleep_latency; |
| 49 | u32 wakeup_latency; |
| 50 | u32 mpu_state; |
| 51 | u32 core_state; |
| 52 | u32 threshold; |
| 53 | u32 flags; |
| 54 | }; |
| 55 | |
| 56 | struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; |
| 57 | struct omap3_processor_cx current_cx_state; |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 58 | struct powerdomain *mpu_pd, *core_pd; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 59 | |
| 60 | static int omap3_idle_bm_check(void) |
| 61 | { |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 62 | if (!omap3_can_sleep()) |
| 63 | return 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | /** |
| 68 | * omap3_enter_idle - Programs OMAP3 to enter the specified state |
| 69 | * @dev: cpuidle device |
| 70 | * @state: The target state to be programmed |
| 71 | * |
| 72 | * Called from the CPUidle framework to program the device to the |
| 73 | * specified target state selected by the governor. |
| 74 | */ |
| 75 | static int omap3_enter_idle(struct cpuidle_device *dev, |
| 76 | struct cpuidle_state *state) |
| 77 | { |
| 78 | struct omap3_processor_cx *cx = cpuidle_get_statedata(state); |
| 79 | struct timespec ts_preidle, ts_postidle, ts_idle; |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 80 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 81 | |
| 82 | current_cx_state = *cx; |
| 83 | |
| 84 | /* Used to keep track of the total time in idle */ |
| 85 | getnstimeofday(&ts_preidle); |
| 86 | |
| 87 | local_irq_disable(); |
| 88 | local_fiq_disable(); |
| 89 | |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 90 | if (!enable_off_mode) { |
| 91 | if (mpu_state < PWRDM_POWER_RET) |
| 92 | mpu_state = PWRDM_POWER_RET; |
| 93 | if (core_state < PWRDM_POWER_RET) |
| 94 | core_state = PWRDM_POWER_RET; |
| 95 | } |
| 96 | |
| 97 | set_pwrdm_state(mpu_pd, mpu_state); |
| 98 | set_pwrdm_state(core_pd, core_state); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 99 | |
| 100 | if (omap_irq_pending()) |
| 101 | goto return_sleep_time; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 102 | |
| 103 | /* Execute ARM wfi */ |
| 104 | omap_sram_idle(); |
| 105 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 106 | return_sleep_time: |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 107 | getnstimeofday(&ts_postidle); |
| 108 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
| 109 | |
| 110 | local_irq_enable(); |
| 111 | local_fiq_enable(); |
| 112 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 113 | return (u32)timespec_to_ns(&ts_idle)/1000; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | /** |
| 117 | * omap3_enter_idle_bm - Checks for any bus activity |
| 118 | * @dev: cpuidle device |
| 119 | * @state: The target state to be programmed |
| 120 | * |
| 121 | * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This |
| 122 | * function checks for any pending activity and then programs the |
| 123 | * device to the specified or a safer state. |
| 124 | */ |
| 125 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
| 126 | struct cpuidle_state *state) |
| 127 | { |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 128 | struct cpuidle_state *new_state = state; |
| 129 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 130 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 131 | BUG_ON(!dev->safe_state); |
| 132 | new_state = dev->safe_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 133 | } |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 134 | |
| 135 | dev->last_state = new_state; |
| 136 | return omap3_enter_idle(dev, new_state); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
| 140 | |
| 141 | /* omap3_init_power_states - Initialises the OMAP3 specific C states. |
| 142 | * |
| 143 | * Below is the desciption of each C state. |
| 144 | * C1 . MPU WFI + Core active |
| 145 | * C2 . MPU CSWR + Core active |
| 146 | * C3 . MPU OFF + Core active |
| 147 | * C4 . MPU CSWR + Core CSWR |
| 148 | * C5 . MPU OFF + Core CSWR |
| 149 | * C6 . MPU OFF + Core OFF |
| 150 | */ |
| 151 | void omap_init_power_states(void) |
| 152 | { |
| 153 | /* C1 . MPU WFI + Core active */ |
| 154 | omap3_power_states[OMAP3_STATE_C1].valid = 1; |
| 155 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; |
| 156 | omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10; |
| 157 | omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10; |
| 158 | omap3_power_states[OMAP3_STATE_C1].threshold = 30; |
| 159 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; |
| 160 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; |
| 161 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; |
| 162 | |
| 163 | /* C2 . MPU CSWR + Core active */ |
| 164 | omap3_power_states[OMAP3_STATE_C2].valid = 1; |
| 165 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; |
| 166 | omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50; |
| 167 | omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50; |
| 168 | omap3_power_states[OMAP3_STATE_C2].threshold = 300; |
| 169 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET; |
| 170 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 171 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | |
| 172 | CPUIDLE_FLAG_CHECK_BM; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 173 | |
| 174 | /* C3 . MPU OFF + Core active */ |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 175 | omap3_power_states[OMAP3_STATE_C3].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 176 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; |
| 177 | omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500; |
| 178 | omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800; |
| 179 | omap3_power_states[OMAP3_STATE_C3].threshold = 4000; |
| 180 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF; |
| 181 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 182 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | |
| 183 | CPUIDLE_FLAG_CHECK_BM; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 184 | |
| 185 | /* C4 . MPU CSWR + Core CSWR*/ |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 186 | omap3_power_states[OMAP3_STATE_C4].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 187 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; |
| 188 | omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500; |
| 189 | omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500; |
| 190 | omap3_power_states[OMAP3_STATE_C4].threshold = 12000; |
| 191 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET; |
| 192 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET; |
| 193 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | |
| 194 | CPUIDLE_FLAG_CHECK_BM; |
| 195 | |
| 196 | /* C5 . MPU OFF + Core CSWR */ |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 197 | omap3_power_states[OMAP3_STATE_C5].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 198 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; |
| 199 | omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000; |
| 200 | omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500; |
| 201 | omap3_power_states[OMAP3_STATE_C5].threshold = 15000; |
| 202 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF; |
| 203 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; |
| 204 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | |
| 205 | CPUIDLE_FLAG_CHECK_BM; |
| 206 | |
| 207 | /* C6 . MPU OFF + Core OFF */ |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 208 | omap3_power_states[OMAP3_STATE_C6].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 209 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; |
| 210 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000; |
| 211 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000; |
| 212 | omap3_power_states[OMAP3_STATE_C6].threshold = 300000; |
| 213 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; |
| 214 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF; |
| 215 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | |
| 216 | CPUIDLE_FLAG_CHECK_BM; |
| 217 | } |
| 218 | |
| 219 | struct cpuidle_driver omap3_idle_driver = { |
| 220 | .name = "omap3_idle", |
| 221 | .owner = THIS_MODULE, |
| 222 | }; |
| 223 | |
| 224 | /** |
| 225 | * omap3_idle_init - Init routine for OMAP3 idle |
| 226 | * |
| 227 | * Registers the OMAP3 specific cpuidle driver with the cpuidle |
| 228 | * framework with the valid set of states. |
| 229 | */ |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame^] | 230 | int __init omap3_idle_init(void) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 231 | { |
| 232 | int i, count = 0; |
| 233 | struct omap3_processor_cx *cx; |
| 234 | struct cpuidle_state *state; |
| 235 | struct cpuidle_device *dev; |
| 236 | |
| 237 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 238 | core_pd = pwrdm_lookup("core_pwrdm"); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 239 | |
| 240 | omap_init_power_states(); |
| 241 | cpuidle_register_driver(&omap3_idle_driver); |
| 242 | |
| 243 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
| 244 | |
| 245 | for (i = 1; i < OMAP3_MAX_STATES; i++) { |
| 246 | cx = &omap3_power_states[i]; |
| 247 | state = &dev->states[count]; |
| 248 | |
| 249 | if (!cx->valid) |
| 250 | continue; |
| 251 | cpuidle_set_statedata(state, cx); |
| 252 | state->exit_latency = cx->sleep_latency + cx->wakeup_latency; |
| 253 | state->target_residency = cx->threshold; |
| 254 | state->flags = cx->flags; |
| 255 | state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? |
| 256 | omap3_enter_idle_bm : omap3_enter_idle; |
| 257 | if (cx->type == OMAP3_STATE_C1) |
| 258 | dev->safe_state = state; |
| 259 | sprintf(state->name, "C%d", count+1); |
| 260 | count++; |
| 261 | } |
| 262 | |
| 263 | if (!count) |
| 264 | return -EINVAL; |
| 265 | dev->state_count = count; |
| 266 | |
| 267 | if (cpuidle_register_device(dev)) { |
| 268 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
| 269 | __func__); |
| 270 | return -EIO; |
| 271 | } |
| 272 | |
| 273 | return 0; |
| 274 | } |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame^] | 275 | #else |
| 276 | int __init omap3_idle_init(void) |
| 277 | { |
| 278 | return 0; |
| 279 | } |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 280 | #endif /* CONFIG_CPU_IDLE */ |