Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 1 | /* |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 2 | * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Due to massive hardware bugs, UltraDMA is only supported |
| 6 | * on the 646U2 and not on the 646U. |
| 7 | * |
| 8 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
| 9 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) |
| 10 | * |
| 11 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 12 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/hdreg.h> |
| 20 | #include <linux/ide.h> |
| 21 | #include <linux/init.h> |
| 22 | |
| 23 | #include <asm/io.h> |
| 24 | |
| 25 | #define DISPLAY_CMD64X_TIMINGS |
| 26 | |
| 27 | #define CMD_DEBUG 0 |
| 28 | |
| 29 | #if CMD_DEBUG |
| 30 | #define cmdprintk(x...) printk(x) |
| 31 | #else |
| 32 | #define cmdprintk(x...) |
| 33 | #endif |
| 34 | |
| 35 | /* |
| 36 | * CMD64x specific registers definition. |
| 37 | */ |
| 38 | #define CFR 0x50 |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 39 | #define CFR_INTR_CH0 0x04 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #define CNTRL 0x51 |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 41 | #define CNTRL_ENA_1ST 0x04 |
| 42 | #define CNTRL_ENA_2ND 0x08 |
| 43 | #define CNTRL_DIS_RA0 0x40 |
| 44 | #define CNTRL_DIS_RA1 0x80 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
| 46 | #define CMDTIM 0x52 |
| 47 | #define ARTTIM0 0x53 |
| 48 | #define DRWTIM0 0x54 |
| 49 | #define ARTTIM1 0x55 |
| 50 | #define DRWTIM1 0x56 |
| 51 | #define ARTTIM23 0x57 |
| 52 | #define ARTTIM23_DIS_RA2 0x04 |
| 53 | #define ARTTIM23_DIS_RA3 0x08 |
| 54 | #define ARTTIM23_INTR_CH1 0x10 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | #define DRWTIM2 0x58 |
| 56 | #define BRST 0x59 |
| 57 | #define DRWTIM3 0x5b |
| 58 | |
| 59 | #define BMIDECR0 0x70 |
| 60 | #define MRDMODE 0x71 |
| 61 | #define MRDMODE_INTR_CH0 0x04 |
| 62 | #define MRDMODE_INTR_CH1 0x08 |
| 63 | #define MRDMODE_BLK_CH0 0x10 |
| 64 | #define MRDMODE_BLK_CH1 0x20 |
| 65 | #define BMIDESR0 0x72 |
| 66 | #define UDIDETCR0 0x73 |
| 67 | #define DTPR0 0x74 |
| 68 | #define BMIDECR1 0x78 |
| 69 | #define BMIDECSR 0x79 |
| 70 | #define BMIDESR1 0x7A |
| 71 | #define UDIDETCR1 0x7B |
| 72 | #define DTPR1 0x7C |
| 73 | |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 74 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | #include <linux/stat.h> |
| 76 | #include <linux/proc_fs.h> |
| 77 | |
| 78 | static u8 cmd64x_proc = 0; |
| 79 | |
| 80 | #define CMD_MAX_DEVS 5 |
| 81 | |
| 82 | static struct pci_dev *cmd_devs[CMD_MAX_DEVS]; |
| 83 | static int n_cmd_devs; |
| 84 | |
| 85 | static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) |
| 86 | { |
| 87 | char *p = buf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | u8 reg72 = 0, reg73 = 0; /* primary */ |
| 89 | u8 reg7a = 0, reg7b = 0; /* secondary */ |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 90 | u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | |
| 92 | p += sprintf(p, "\nController: %d\n", index); |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 93 | p += sprintf(p, "PCI-%x Chipset.\n", dev->device); |
| 94 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | (void) pci_read_config_byte(dev, CFR, ®50); |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 96 | (void) pci_read_config_byte(dev, CNTRL, ®51); |
| 97 | (void) pci_read_config_byte(dev, ARTTIM23, ®57); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | (void) pci_read_config_byte(dev, MRDMODE, ®71); |
| 99 | (void) pci_read_config_byte(dev, BMIDESR0, ®72); |
| 100 | (void) pci_read_config_byte(dev, UDIDETCR0, ®73); |
| 101 | (void) pci_read_config_byte(dev, BMIDESR1, ®7a); |
| 102 | (void) pci_read_config_byte(dev, UDIDETCR1, ®7b); |
| 103 | |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 104 | /* PCI0643/6 originally didn't have the primary channel enable bit */ |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 105 | if ((dev->device == PCI_DEVICE_ID_CMD_643) || |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 106 | (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3)) |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 107 | reg51 |= CNTRL_ENA_1ST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 109 | p += sprintf(p, "---------------- Primary Channel " |
| 110 | "---------------- Secondary Channel ------------\n"); |
| 111 | p += sprintf(p, " %s %s\n", |
| 112 | (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled", |
| 113 | (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled"); |
| 114 | p += sprintf(p, "---------------- drive0 --------- drive1 " |
| 115 | "-------- drive0 --------- drive1 ------\n"); |
| 116 | p += sprintf(p, "DMA enabled: %s %s" |
| 117 | " %s %s\n", |
| 118 | (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ", |
| 119 | (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no "); |
| 120 | p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)", |
| 121 | ( reg73 & 0x01) ? " on" : "off", |
| 122 | ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') : |
| 123 | ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') : |
| 124 | ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') : |
| 125 | ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?', |
| 126 | ( reg73 & 0x02) ? " on" : "off", |
| 127 | ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') : |
| 128 | ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') : |
| 129 | ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') : |
| 130 | ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?'); |
| 131 | p += sprintf(p, " %s (%c) %s (%c)\n", |
| 132 | ( reg7b & 0x01) ? " on" : "off", |
| 133 | ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') : |
| 134 | ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') : |
| 135 | ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') : |
| 136 | ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?', |
| 137 | ( reg7b & 0x02) ? " on" : "off", |
| 138 | ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') : |
| 139 | ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') : |
| 140 | ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') : |
| 141 | ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?'); |
| 142 | p += sprintf(p, "Interrupt: %s, %s %s, %s\n", |
| 143 | (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled", |
| 144 | (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ", |
| 145 | (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled", |
| 146 | (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear "); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | |
| 148 | return (char *)p; |
| 149 | } |
| 150 | |
| 151 | static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) |
| 152 | { |
| 153 | char *p = buffer; |
| 154 | int i; |
| 155 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | for (i = 0; i < n_cmd_devs; i++) { |
| 157 | struct pci_dev *dev = cmd_devs[i]; |
| 158 | p = print_cmd64x_get_info(p, dev, i); |
| 159 | } |
| 160 | return p-buffer; /* => must be less than 4k! */ |
| 161 | } |
| 162 | |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 163 | #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | |
Sergei Shtylyov | e277a1a | 2007-03-17 21:57:24 +0100 | [diff] [blame] | 165 | static u8 quantize_timing(int timing, int quant) |
| 166 | { |
| 167 | return (timing + quant - 1) / quant; |
| 168 | } |
| 169 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | /* |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 171 | * This routine calculates active/recovery counts and then writes them into |
| 172 | * the chipset registers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | */ |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 174 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | { |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 176 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
| 177 | int clock_time = 1000 / system_bus_clock(); |
| 178 | u8 cycle_count, active_count, recovery_count, drwtim; |
| 179 | static const u8 recovery_values[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 181 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 183 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", |
| 184 | cycle_time, active_time); |
| 185 | |
| 186 | cycle_count = quantize_timing( cycle_time, clock_time); |
| 187 | active_count = quantize_timing(active_time, clock_time); |
| 188 | recovery_count = cycle_count - active_count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | |
| 190 | /* |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 191 | * In case we've got too long recovery phase, try to lengthen |
| 192 | * the active phase |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | if (recovery_count > 16) { |
| 195 | active_count += recovery_count - 16; |
| 196 | recovery_count = 16; |
| 197 | } |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 198 | if (active_count > 16) /* shouldn't actually happen... */ |
| 199 | active_count = 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 201 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", |
| 202 | cycle_count, active_count, recovery_count); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 204 | /* |
| 205 | * Convert values to internal chipset representation |
| 206 | */ |
| 207 | recovery_count = recovery_values[recovery_count]; |
| 208 | active_count &= 0x0f; |
| 209 | |
| 210 | /* Program the active/recovery counts into the DRWTIM register */ |
| 211 | drwtim = (active_count << 4) | recovery_count; |
| 212 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); |
| 213 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); |
| 214 | } |
| 215 | |
| 216 | /* |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 217 | * This routine writes into the chipset registers |
| 218 | * PIO setup/active/recovery timings. |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 219 | */ |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 220 | static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 221 | { |
| 222 | ide_hwif_t *hwif = HWIF(drive); |
| 223 | struct pci_dev *dev = hwif->pci_dev; |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 224 | unsigned int cycle_time; |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 225 | u8 setup_count, arttim = 0; |
| 226 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 227 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; |
| 228 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 229 | |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 230 | cycle_time = ide_pio_cycle_time(drive, pio); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 231 | |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 232 | program_cycle_times(drive, cycle_time, |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 233 | ide_pio_timings[pio].active_time); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 234 | |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 235 | setup_count = quantize_timing(ide_pio_timings[pio].setup_time, |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 236 | 1000 / system_bus_clock()); |
| 237 | |
| 238 | /* |
| 239 | * The primary channel has individual address setup timing registers |
| 240 | * for each drive and the hardware selects the slowest timing itself. |
| 241 | * The secondary channel has one common register and we have to select |
| 242 | * the slowest address setup timing ourselves. |
| 243 | */ |
| 244 | if (hwif->channel) { |
| 245 | ide_drive_t *drives = hwif->drives; |
| 246 | |
| 247 | drive->drive_data = setup_count; |
| 248 | setup_count = max(drives[0].drive_data, drives[1].drive_data); |
| 249 | } |
| 250 | |
| 251 | if (setup_count > 5) /* shouldn't actually happen... */ |
| 252 | setup_count = 5; |
| 253 | cmdprintk("Final address setup count: %d\n", setup_count); |
| 254 | |
| 255 | /* |
| 256 | * Program the address setup clocks into the ARTTIM registers. |
| 257 | * Avoid clearing the secondary channel's interrupt bit. |
| 258 | */ |
| 259 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); |
| 260 | if (hwif->channel) |
| 261 | arttim &= ~ARTTIM23_INTR_CH1; |
| 262 | arttim &= ~0xc0; |
| 263 | arttim |= setup_values[setup_count]; |
| 264 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); |
| 265 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | /* |
| 269 | * Attempts to set drive's PIO mode. |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 270 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked) |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 271 | */ |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 272 | |
| 273 | static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 274 | { |
| 275 | /* |
| 276 | * Filter out the prefetch control values |
| 277 | * to prevent PIO5 from being programmed |
| 278 | */ |
| 279 | if (pio == 8 || pio == 9) |
| 280 | return; |
| 281 | |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 282 | cmd64x_tune_pio(drive, pio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | } |
| 284 | |
Bartlomiej Zolnierkiewicz | 88b2b32 | 2007-10-13 17:47:51 +0200 | [diff] [blame] | 285 | static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | { |
| 287 | ide_hwif_t *hwif = HWIF(drive); |
| 288 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 289 | u8 unit = drive->dn & 0x01; |
| 290 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 292 | if (speed >= XFER_SW_DMA_0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | (void) pci_read_config_byte(dev, pciU, ®U); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | regU &= ~(unit ? 0xCA : 0x35); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | switch(speed) { |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 298 | case XFER_UDMA_5: |
| 299 | regU |= unit ? 0x0A : 0x05; |
| 300 | break; |
| 301 | case XFER_UDMA_4: |
| 302 | regU |= unit ? 0x4A : 0x15; |
| 303 | break; |
| 304 | case XFER_UDMA_3: |
| 305 | regU |= unit ? 0x8A : 0x25; |
| 306 | break; |
| 307 | case XFER_UDMA_2: |
| 308 | regU |= unit ? 0x42 : 0x11; |
| 309 | break; |
| 310 | case XFER_UDMA_1: |
| 311 | regU |= unit ? 0x82 : 0x21; |
| 312 | break; |
| 313 | case XFER_UDMA_0: |
| 314 | regU |= unit ? 0xC2 : 0x31; |
| 315 | break; |
| 316 | case XFER_MW_DMA_2: |
| 317 | program_cycle_times(drive, 120, 70); |
| 318 | break; |
| 319 | case XFER_MW_DMA_1: |
| 320 | program_cycle_times(drive, 150, 80); |
| 321 | break; |
| 322 | case XFER_MW_DMA_0: |
| 323 | program_cycle_times(drive, 480, 215); |
| 324 | break; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 325 | default: |
Bartlomiej Zolnierkiewicz | 88b2b32 | 2007-10-13 17:47:51 +0200 | [diff] [blame] | 326 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | } |
| 328 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 329 | if (speed >= XFER_SW_DMA_0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 330 | (void) pci_write_config_byte(dev, pciU, regU); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | } |
| 332 | |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 333 | static int cmd648_ide_dma_end (ide_drive_t *drive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | { |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 335 | ide_hwif_t *hwif = HWIF(drive); |
| 336 | int err = __ide_dma_end(drive); |
| 337 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
| 338 | MRDMODE_INTR_CH0; |
| 339 | u8 mrdmode = inb(hwif->dma_master + 0x01); |
| 340 | |
| 341 | /* clear the interrupt bit */ |
| 342 | outb(mrdmode | irq_mask, hwif->dma_master + 0x01); |
| 343 | |
| 344 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | static int cmd64x_ide_dma_end (ide_drive_t *drive) |
| 348 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | ide_hwif_t *hwif = HWIF(drive); |
| 350 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 351 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
| 352 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
| 353 | CFR_INTR_CH0; |
| 354 | u8 irq_stat = 0; |
| 355 | int err = __ide_dma_end(drive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 357 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
| 358 | /* clear the interrupt bit */ |
| 359 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); |
| 360 | |
| 361 | return err; |
| 362 | } |
| 363 | |
| 364 | static int cmd648_ide_dma_test_irq (ide_drive_t *drive) |
| 365 | { |
| 366 | ide_hwif_t *hwif = HWIF(drive); |
| 367 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
| 368 | MRDMODE_INTR_CH0; |
| 369 | u8 dma_stat = inb(hwif->dma_status); |
| 370 | u8 mrdmode = inb(hwif->dma_master + 0x01); |
| 371 | |
| 372 | #ifdef DEBUG |
| 373 | printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", |
| 374 | drive->name, dma_stat, mrdmode, irq_mask); |
| 375 | #endif |
| 376 | if (!(mrdmode & irq_mask)) |
| 377 | return 0; |
| 378 | |
| 379 | /* return 1 if INTR asserted */ |
| 380 | if (dma_stat & 4) |
| 381 | return 1; |
| 382 | |
| 383 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) |
| 387 | { |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 388 | ide_hwif_t *hwif = HWIF(drive); |
| 389 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 390 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
| 391 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
| 392 | CFR_INTR_CH0; |
| 393 | u8 dma_stat = inb(hwif->dma_status); |
| 394 | u8 irq_stat = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 396 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
| 397 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | #ifdef DEBUG |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 399 | printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n", |
| 400 | drive->name, dma_stat, irq_stat, irq_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | #endif |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 402 | if (!(irq_stat & irq_mask)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | return 0; |
| 404 | |
| 405 | /* return 1 if INTR asserted */ |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 406 | if (dma_stat & 4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | return 1; |
| 408 | |
| 409 | return 0; |
| 410 | } |
| 411 | |
| 412 | /* |
| 413 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old |
| 414 | * event order for DMA transfers. |
| 415 | */ |
| 416 | |
| 417 | static int cmd646_1_ide_dma_end (ide_drive_t *drive) |
| 418 | { |
| 419 | ide_hwif_t *hwif = HWIF(drive); |
| 420 | u8 dma_stat = 0, dma_cmd = 0; |
| 421 | |
| 422 | drive->waiting_for_dma = 0; |
| 423 | /* get DMA status */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 424 | dma_stat = inb(hwif->dma_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | /* read DMA command state */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 426 | dma_cmd = inb(hwif->dma_command); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | /* stop DMA */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 428 | outb(dma_cmd & ~1, hwif->dma_command); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | /* clear the INTR & ERROR bits */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 430 | outb(dma_stat | 6, hwif->dma_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | /* and free any DMA resources */ |
| 432 | ide_destroy_dmatable(drive); |
| 433 | /* verify good DMA status */ |
| 434 | return (dma_stat & 7) != 4; |
| 435 | } |
| 436 | |
| 437 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) |
| 438 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | u8 mrdmode = 0; |
| 440 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 441 | if (dev->device == PCI_DEVICE_ID_CMD_646) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | |
Auke Kok | 1afa655 | 2007-10-19 00:30:08 +0200 | [diff] [blame] | 443 | switch (dev->revision) { |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 444 | case 0x07: |
| 445 | case 0x05: |
Meelis Roos | b37c6b8 | 2007-08-01 23:46:44 +0200 | [diff] [blame] | 446 | printk("%s: UltraDMA capable\n", name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | break; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 448 | case 0x03: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | default: |
Meelis Roos | b37c6b8 | 2007-08-01 23:46:44 +0200 | [diff] [blame] | 450 | printk("%s: MultiWord DMA force limited\n", name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 451 | break; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 452 | case 0x01: |
| 453 | printk("%s: MultiWord DMA limited, " |
| 454 | "IRQ workaround enabled\n", name); |
| 455 | break; |
| 456 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | /* Set a good latency timer and cache line size value. */ |
| 460 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
| 461 | /* FIXME: pci_set_master() to ensure a good latency timer value */ |
| 462 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 463 | /* |
| 464 | * Enable interrupts, select MEMORY READ LINE for reads. |
| 465 | * |
| 466 | * NOTE: although not mentioned in the PCI0646U specs, |
| 467 | * bits 0-1 are write only and won't be read back as |
| 468 | * set or not -- PCI0646U2 specs clarify this point. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | */ |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 470 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); |
| 471 | mrdmode &= ~0x30; |
| 472 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 474 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | |
| 476 | cmd_devs[n_cmd_devs++] = dev; |
| 477 | |
| 478 | if (!cmd64x_proc) { |
| 479 | cmd64x_proc = 1; |
| 480 | ide_pci_create_host_proc("cmd64x", cmd64x_get_info); |
| 481 | } |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 482 | #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | |
| 484 | return 0; |
| 485 | } |
| 486 | |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 487 | static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | { |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 489 | struct pci_dev *dev = hwif->pci_dev; |
| 490 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 492 | switch (dev->device) { |
| 493 | case PCI_DEVICE_ID_CMD_648: |
| 494 | case PCI_DEVICE_ID_CMD_649: |
| 495 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 496 | return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 497 | default: |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 498 | return ATA_CBL_PATA40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | } |
| 501 | |
| 502 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) |
| 503 | { |
| 504 | struct pci_dev *dev = hwif->pci_dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 506 | hwif->set_pio_mode = &cmd64x_set_pio_mode; |
Bartlomiej Zolnierkiewicz | 88b2b32 | 2007-10-13 17:47:51 +0200 | [diff] [blame] | 507 | hwif->set_dma_mode = &cmd64x_set_dma_mode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 509 | if (!hwif->dma_base) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | |
Bartlomiej Zolnierkiewicz | 2d5eaa6 | 2007-05-10 00:01:08 +0200 | [diff] [blame] | 512 | /* |
| 513 | * UltraDMA only supported on PCI646U and PCI646U2, which |
| 514 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. |
| 515 | * Actually, although the CMD tech support people won't |
| 516 | * tell me the details, the 0x03 revision cannot support |
| 517 | * UDMA correctly without hardware modifications, and even |
| 518 | * then it only works with Quantum disks due to some |
| 519 | * hold time assumptions in the 646U part which are fixed |
| 520 | * in the 646U2. |
| 521 | * |
| 522 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. |
| 523 | */ |
Auke Kok | 1afa655 | 2007-10-19 00:30:08 +0200 | [diff] [blame] | 524 | if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5) |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 525 | hwif->ultra_mask = 0x00; |
| 526 | |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 527 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
| 528 | hwif->cbl = ata66_cmd64x(hwif); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 530 | switch (dev->device) { |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 531 | case PCI_DEVICE_ID_CMD_648: |
| 532 | case PCI_DEVICE_ID_CMD_649: |
| 533 | alt_irq_bits: |
| 534 | hwif->ide_dma_end = &cmd648_ide_dma_end; |
| 535 | hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq; |
| 536 | break; |
| 537 | case PCI_DEVICE_ID_CMD_646: |
Auke Kok | 1afa655 | 2007-10-19 00:30:08 +0200 | [diff] [blame] | 538 | if (dev->revision == 0x01) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 539 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 540 | break; |
Auke Kok | 1afa655 | 2007-10-19 00:30:08 +0200 | [diff] [blame] | 541 | } else if (dev->revision >= 0x03) |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 542 | goto alt_irq_bits; |
| 543 | /* fall thru */ |
| 544 | default: |
| 545 | hwif->ide_dma_end = &cmd64x_ide_dma_end; |
| 546 | hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; |
| 547 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { |
| 552 | { /* 0 */ |
| 553 | .name = "CMD643", |
| 554 | .init_chipset = init_chipset_cmd64x, |
| 555 | .init_hwif = init_hwif_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 556 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
Bartlomiej Zolnierkiewicz | 7cab14a | 2007-10-19 00:30:06 +0200 | [diff] [blame] | 557 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 558 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 559 | .mwdma_mask = ATA_MWDMA2, |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 560 | .udma_mask = 0x00, /* no udma */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 561 | },{ /* 1 */ |
| 562 | .name = "CMD646", |
| 563 | .init_chipset = init_chipset_cmd64x, |
| 564 | .init_hwif = init_hwif_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 565 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Bartlomiej Zolnierkiewicz | 7cab14a | 2007-10-19 00:30:06 +0200 | [diff] [blame] | 566 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 567 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 568 | .mwdma_mask = ATA_MWDMA2, |
| 569 | .udma_mask = ATA_UDMA2, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 570 | },{ /* 2 */ |
| 571 | .name = "CMD648", |
| 572 | .init_chipset = init_chipset_cmd64x, |
| 573 | .init_hwif = init_hwif_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 574 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Bartlomiej Zolnierkiewicz | 528a572 | 2007-10-20 00:32:30 +0200 | [diff] [blame] | 575 | .chipset = ide_cmd646, |
Bartlomiej Zolnierkiewicz | 7cab14a | 2007-10-19 00:30:06 +0200 | [diff] [blame] | 576 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 577 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 578 | .mwdma_mask = ATA_MWDMA2, |
| 579 | .udma_mask = ATA_UDMA4, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | },{ /* 3 */ |
| 581 | .name = "CMD649", |
| 582 | .init_chipset = init_chipset_cmd64x, |
| 583 | .init_hwif = init_hwif_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 584 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Bartlomiej Zolnierkiewicz | 7cab14a | 2007-10-19 00:30:06 +0200 | [diff] [blame] | 585 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 586 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 587 | .mwdma_mask = ATA_MWDMA2, |
| 588 | .udma_mask = ATA_UDMA5, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 589 | } |
| 590 | }; |
| 591 | |
| 592 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 593 | { |
Bartlomiej Zolnierkiewicz | bfd314a | 2007-10-19 00:30:09 +0200 | [diff] [blame] | 594 | ide_pci_device_t d; |
| 595 | u8 idx = id->driver_data; |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 596 | |
Bartlomiej Zolnierkiewicz | bfd314a | 2007-10-19 00:30:09 +0200 | [diff] [blame] | 597 | d = cmd64x_chipsets[idx]; |
| 598 | |
| 599 | /* |
| 600 | * The original PCI0646 didn't have the primary channel enable bit, |
| 601 | * it appeared starting with PCI0646U (i.e. revision ID 3). |
| 602 | */ |
| 603 | if (idx == 1 && dev->revision < 3) |
| 604 | d.enablebits[0].reg = 0; |
| 605 | |
| 606 | return ide_setup_pci_device(dev, &d); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | } |
| 608 | |
Bartlomiej Zolnierkiewicz | 9cbcc5e | 2007-10-16 22:29:56 +0200 | [diff] [blame] | 609 | static const struct pci_device_id cmd64x_pci_tbl[] = { |
| 610 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, |
| 611 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, |
| 612 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 }, |
| 613 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | { 0, }, |
| 615 | }; |
| 616 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); |
| 617 | |
| 618 | static struct pci_driver driver = { |
| 619 | .name = "CMD64x_IDE", |
| 620 | .id_table = cmd64x_pci_tbl, |
| 621 | .probe = cmd64x_init_one, |
| 622 | }; |
| 623 | |
Bartlomiej Zolnierkiewicz | 82ab1ee | 2007-01-27 13:46:56 +0100 | [diff] [blame] | 624 | static int __init cmd64x_ide_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | { |
| 626 | return ide_pci_register_driver(&driver); |
| 627 | } |
| 628 | |
| 629 | module_init(cmd64x_ide_init); |
| 630 | |
| 631 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); |
| 632 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); |
| 633 | MODULE_LICENSE("GPL"); |