Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/amdgpu_drm.h> |
| 28 | #include "amdgpu.h" |
| 29 | #include "amdgpu_i2c.h" |
| 30 | #include "atom.h" |
| 31 | #include "amdgpu_connectors.h" |
| 32 | #include <asm/div64.h> |
| 33 | |
| 34 | #include <linux/pm_runtime.h> |
| 35 | #include <drm/drm_crtc_helper.h> |
| 36 | #include <drm/drm_edid.h> |
| 37 | |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 38 | static void amdgpu_flip_wait_fence(struct amdgpu_device *adev, |
| 39 | struct fence **f) |
| 40 | { |
| 41 | struct amdgpu_fence *fence; |
| 42 | long r; |
| 43 | |
| 44 | if (*f == NULL) |
| 45 | return; |
| 46 | |
| 47 | fence = to_amdgpu_fence(*f); |
| 48 | if (fence) { |
| 49 | r = fence_wait(&fence->base, false); |
Christian König | 0c418f1 | 2015-09-01 15:13:53 +0200 | [diff] [blame] | 50 | if (r == -EDEADLK) |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 51 | r = amdgpu_gpu_reset(adev); |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 52 | } else |
| 53 | r = fence_wait(*f, false); |
| 54 | |
| 55 | if (r) |
| 56 | DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r); |
| 57 | |
| 58 | /* We continue with the page flip even if we failed to wait on |
| 59 | * the fence, otherwise the DRM core and userspace will be |
| 60 | * confused about which BO the CRTC is scanning out |
| 61 | */ |
| 62 | fence_put(*f); |
| 63 | *f = NULL; |
| 64 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 65 | |
| 66 | static void amdgpu_flip_work_func(struct work_struct *__work) |
| 67 | { |
| 68 | struct amdgpu_flip_work *work = |
| 69 | container_of(__work, struct amdgpu_flip_work, flip_work); |
| 70 | struct amdgpu_device *adev = work->adev; |
| 71 | struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; |
| 72 | |
| 73 | struct drm_crtc *crtc = &amdgpuCrtc->base; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 74 | unsigned long flags; |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 75 | unsigned i; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 76 | |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 77 | amdgpu_flip_wait_fence(adev, &work->excl); |
| 78 | for (i = 0; i < work->shared_count; ++i) |
| 79 | amdgpu_flip_wait_fence(adev, &work->shared[i]); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 80 | |
| 81 | /* We borrow the event spin lock for protecting flip_status */ |
| 82 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
| 83 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 84 | /* do the flip (mmio) */ |
| 85 | adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); |
| 86 | /* set the flip status */ |
| 87 | amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; |
| 88 | |
| 89 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Handle unpin events outside the interrupt handler proper. |
| 94 | */ |
| 95 | static void amdgpu_unpin_work_func(struct work_struct *__work) |
| 96 | { |
| 97 | struct amdgpu_flip_work *work = |
| 98 | container_of(__work, struct amdgpu_flip_work, unpin_work); |
| 99 | int r; |
| 100 | |
| 101 | /* unpin of the old buffer */ |
| 102 | r = amdgpu_bo_reserve(work->old_rbo, false); |
| 103 | if (likely(r == 0)) { |
| 104 | r = amdgpu_bo_unpin(work->old_rbo); |
| 105 | if (unlikely(r != 0)) { |
| 106 | DRM_ERROR("failed to unpin buffer after flip\n"); |
| 107 | } |
| 108 | amdgpu_bo_unreserve(work->old_rbo); |
| 109 | } else |
| 110 | DRM_ERROR("failed to reserve buffer after flip\n"); |
| 111 | |
| 112 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 113 | kfree(work->shared); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 114 | kfree(work); |
| 115 | } |
| 116 | |
| 117 | int amdgpu_crtc_page_flip(struct drm_crtc *crtc, |
| 118 | struct drm_framebuffer *fb, |
| 119 | struct drm_pending_vblank_event *event, |
| 120 | uint32_t page_flip_flags) |
| 121 | { |
| 122 | struct drm_device *dev = crtc->dev; |
| 123 | struct amdgpu_device *adev = dev->dev_private; |
| 124 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 125 | struct amdgpu_framebuffer *old_amdgpu_fb; |
| 126 | struct amdgpu_framebuffer *new_amdgpu_fb; |
| 127 | struct drm_gem_object *obj; |
| 128 | struct amdgpu_flip_work *work; |
| 129 | struct amdgpu_bo *new_rbo; |
| 130 | unsigned long flags; |
| 131 | u64 tiling_flags; |
| 132 | u64 base; |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 133 | int i, r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 134 | |
| 135 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 136 | if (work == NULL) |
| 137 | return -ENOMEM; |
| 138 | |
| 139 | INIT_WORK(&work->flip_work, amdgpu_flip_work_func); |
| 140 | INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); |
| 141 | |
| 142 | work->event = event; |
| 143 | work->adev = adev; |
| 144 | work->crtc_id = amdgpu_crtc->crtc_id; |
| 145 | |
| 146 | /* schedule unpin of the old buffer */ |
| 147 | old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); |
| 148 | obj = old_amdgpu_fb->obj; |
| 149 | |
| 150 | /* take a reference to the old object */ |
| 151 | drm_gem_object_reference(obj); |
| 152 | work->old_rbo = gem_to_amdgpu_bo(obj); |
| 153 | |
| 154 | new_amdgpu_fb = to_amdgpu_framebuffer(fb); |
| 155 | obj = new_amdgpu_fb->obj; |
| 156 | new_rbo = gem_to_amdgpu_bo(obj); |
| 157 | |
| 158 | /* pin the new buffer */ |
| 159 | r = amdgpu_bo_reserve(new_rbo, false); |
| 160 | if (unlikely(r != 0)) { |
| 161 | DRM_ERROR("failed to reserve new rbo buffer before flip\n"); |
| 162 | goto cleanup; |
| 163 | } |
| 164 | |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 165 | r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 166 | if (unlikely(r != 0)) { |
| 167 | amdgpu_bo_unreserve(new_rbo); |
| 168 | r = -EINVAL; |
| 169 | DRM_ERROR("failed to pin new rbo buffer before flip\n"); |
| 170 | goto cleanup; |
| 171 | } |
| 172 | |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 173 | r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, |
| 174 | &work->shared_count, |
| 175 | &work->shared); |
| 176 | if (unlikely(r != 0)) { |
| 177 | amdgpu_bo_unreserve(new_rbo); |
| 178 | DRM_ERROR("failed to get fences for buffer\n"); |
| 179 | goto cleanup; |
| 180 | } |
| 181 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 182 | amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); |
| 183 | amdgpu_bo_unreserve(new_rbo); |
| 184 | |
| 185 | work->base = base; |
| 186 | |
| 187 | r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); |
| 188 | if (r) { |
| 189 | DRM_ERROR("failed to get vblank before flip\n"); |
| 190 | goto pflip_cleanup; |
| 191 | } |
| 192 | |
| 193 | /* we borrow the event spin lock for protecting flip_wrok */ |
| 194 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
| 195 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { |
| 196 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
| 197 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
| 198 | r = -EBUSY; |
| 199 | goto vblank_cleanup; |
| 200 | } |
| 201 | |
| 202 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; |
| 203 | amdgpu_crtc->pflip_works = work; |
| 204 | |
| 205 | /* update crtc fb */ |
| 206 | crtc->primary->fb = fb; |
| 207 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
| 208 | queue_work(amdgpu_crtc->pflip_queue, &work->flip_work); |
| 209 | return 0; |
| 210 | |
| 211 | vblank_cleanup: |
| 212 | drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); |
| 213 | |
| 214 | pflip_cleanup: |
| 215 | if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { |
| 216 | DRM_ERROR("failed to reserve new rbo in error path\n"); |
| 217 | goto cleanup; |
| 218 | } |
| 219 | if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { |
| 220 | DRM_ERROR("failed to unpin new rbo in error path\n"); |
| 221 | } |
| 222 | amdgpu_bo_unreserve(new_rbo); |
| 223 | |
| 224 | cleanup: |
| 225 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 226 | fence_put(work->excl); |
| 227 | for (i = 0; i < work->shared_count; ++i) |
| 228 | fence_put(work->shared[i]); |
| 229 | kfree(work->shared); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 230 | kfree(work); |
| 231 | |
| 232 | return r; |
| 233 | } |
| 234 | |
| 235 | int amdgpu_crtc_set_config(struct drm_mode_set *set) |
| 236 | { |
| 237 | struct drm_device *dev; |
| 238 | struct amdgpu_device *adev; |
| 239 | struct drm_crtc *crtc; |
| 240 | bool active = false; |
| 241 | int ret; |
| 242 | |
| 243 | if (!set || !set->crtc) |
| 244 | return -EINVAL; |
| 245 | |
| 246 | dev = set->crtc->dev; |
| 247 | |
| 248 | ret = pm_runtime_get_sync(dev->dev); |
| 249 | if (ret < 0) |
| 250 | return ret; |
| 251 | |
| 252 | ret = drm_crtc_helper_set_config(set); |
| 253 | |
| 254 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 255 | if (crtc->enabled) |
| 256 | active = true; |
| 257 | |
| 258 | pm_runtime_mark_last_busy(dev->dev); |
| 259 | |
| 260 | adev = dev->dev_private; |
| 261 | /* if we have active crtcs and we don't have a power ref, |
| 262 | take the current one */ |
| 263 | if (active && !adev->have_disp_power_ref) { |
| 264 | adev->have_disp_power_ref = true; |
| 265 | return ret; |
| 266 | } |
| 267 | /* if we have no active crtcs, then drop the power ref |
| 268 | we got before */ |
| 269 | if (!active && adev->have_disp_power_ref) { |
| 270 | pm_runtime_put_autosuspend(dev->dev); |
| 271 | adev->have_disp_power_ref = false; |
| 272 | } |
| 273 | |
| 274 | /* drop the power reference we got coming in here */ |
| 275 | pm_runtime_put_autosuspend(dev->dev); |
| 276 | return ret; |
| 277 | } |
| 278 | |
| 279 | static const char *encoder_names[38] = { |
| 280 | "NONE", |
| 281 | "INTERNAL_LVDS", |
| 282 | "INTERNAL_TMDS1", |
| 283 | "INTERNAL_TMDS2", |
| 284 | "INTERNAL_DAC1", |
| 285 | "INTERNAL_DAC2", |
| 286 | "INTERNAL_SDVOA", |
| 287 | "INTERNAL_SDVOB", |
| 288 | "SI170B", |
| 289 | "CH7303", |
| 290 | "CH7301", |
| 291 | "INTERNAL_DVO1", |
| 292 | "EXTERNAL_SDVOA", |
| 293 | "EXTERNAL_SDVOB", |
| 294 | "TITFP513", |
| 295 | "INTERNAL_LVTM1", |
| 296 | "VT1623", |
| 297 | "HDMI_SI1930", |
| 298 | "HDMI_INTERNAL", |
| 299 | "INTERNAL_KLDSCP_TMDS1", |
| 300 | "INTERNAL_KLDSCP_DVO1", |
| 301 | "INTERNAL_KLDSCP_DAC1", |
| 302 | "INTERNAL_KLDSCP_DAC2", |
| 303 | "SI178", |
| 304 | "MVPU_FPGA", |
| 305 | "INTERNAL_DDI", |
| 306 | "VT1625", |
| 307 | "HDMI_SI1932", |
| 308 | "DP_AN9801", |
| 309 | "DP_DP501", |
| 310 | "INTERNAL_UNIPHY", |
| 311 | "INTERNAL_KLDSCP_LVTMA", |
| 312 | "INTERNAL_UNIPHY1", |
| 313 | "INTERNAL_UNIPHY2", |
| 314 | "NUTMEG", |
| 315 | "TRAVIS", |
| 316 | "INTERNAL_VCE", |
| 317 | "INTERNAL_UNIPHY3", |
| 318 | }; |
| 319 | |
| 320 | static const char *hpd_names[6] = { |
| 321 | "HPD1", |
| 322 | "HPD2", |
| 323 | "HPD3", |
| 324 | "HPD4", |
| 325 | "HPD5", |
| 326 | "HPD6", |
| 327 | }; |
| 328 | |
| 329 | void amdgpu_print_display_setup(struct drm_device *dev) |
| 330 | { |
| 331 | struct drm_connector *connector; |
| 332 | struct amdgpu_connector *amdgpu_connector; |
| 333 | struct drm_encoder *encoder; |
| 334 | struct amdgpu_encoder *amdgpu_encoder; |
| 335 | uint32_t devices; |
| 336 | int i = 0; |
| 337 | |
| 338 | DRM_INFO("AMDGPU Display Connectors\n"); |
| 339 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 340 | amdgpu_connector = to_amdgpu_connector(connector); |
| 341 | DRM_INFO("Connector %d:\n", i); |
| 342 | DRM_INFO(" %s\n", connector->name); |
| 343 | if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) |
| 344 | DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); |
| 345 | if (amdgpu_connector->ddc_bus) { |
| 346 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
| 347 | amdgpu_connector->ddc_bus->rec.mask_clk_reg, |
| 348 | amdgpu_connector->ddc_bus->rec.mask_data_reg, |
| 349 | amdgpu_connector->ddc_bus->rec.a_clk_reg, |
| 350 | amdgpu_connector->ddc_bus->rec.a_data_reg, |
| 351 | amdgpu_connector->ddc_bus->rec.en_clk_reg, |
| 352 | amdgpu_connector->ddc_bus->rec.en_data_reg, |
| 353 | amdgpu_connector->ddc_bus->rec.y_clk_reg, |
| 354 | amdgpu_connector->ddc_bus->rec.y_data_reg); |
| 355 | if (amdgpu_connector->router.ddc_valid) |
| 356 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
| 357 | amdgpu_connector->router.ddc_mux_control_pin, |
| 358 | amdgpu_connector->router.ddc_mux_state); |
| 359 | if (amdgpu_connector->router.cd_valid) |
| 360 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
| 361 | amdgpu_connector->router.cd_mux_control_pin, |
| 362 | amdgpu_connector->router.cd_mux_state); |
| 363 | } else { |
| 364 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
| 365 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
| 366 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
| 367 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
| 368 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
| 369 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
| 370 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
| 371 | } |
| 372 | DRM_INFO(" Encoders:\n"); |
| 373 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 374 | amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 375 | devices = amdgpu_encoder->devices & amdgpu_connector->devices; |
| 376 | if (devices) { |
| 377 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
| 378 | DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 379 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
| 380 | DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 381 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
| 382 | DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 383 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
| 384 | DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 385 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
| 386 | DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 387 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
| 388 | DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 389 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
| 390 | DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 391 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
| 392 | DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 393 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
| 394 | DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 395 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
| 396 | DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 397 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
| 398 | DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); |
| 399 | } |
| 400 | } |
| 401 | i++; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | /** |
| 406 | * amdgpu_ddc_probe |
| 407 | * |
| 408 | */ |
| 409 | bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, |
| 410 | bool use_aux) |
| 411 | { |
| 412 | u8 out = 0x0; |
| 413 | u8 buf[8]; |
| 414 | int ret; |
| 415 | struct i2c_msg msgs[] = { |
| 416 | { |
| 417 | .addr = DDC_ADDR, |
| 418 | .flags = 0, |
| 419 | .len = 1, |
| 420 | .buf = &out, |
| 421 | }, |
| 422 | { |
| 423 | .addr = DDC_ADDR, |
| 424 | .flags = I2C_M_RD, |
| 425 | .len = 8, |
| 426 | .buf = buf, |
| 427 | } |
| 428 | }; |
| 429 | |
| 430 | /* on hw with routers, select right port */ |
| 431 | if (amdgpu_connector->router.ddc_valid) |
| 432 | amdgpu_i2c_router_select_ddc_port(amdgpu_connector); |
| 433 | |
| 434 | if (use_aux) { |
| 435 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); |
| 436 | } else { |
| 437 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); |
| 438 | } |
| 439 | |
| 440 | if (ret != 2) |
| 441 | /* Couldn't find an accessible DDC on this connector */ |
| 442 | return false; |
| 443 | /* Probe also for valid EDID header |
| 444 | * EDID header starts with: |
| 445 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. |
| 446 | * Only the first 6 bytes must be valid as |
| 447 | * drm_edid_block_valid() can fix the last 2 bytes */ |
| 448 | if (drm_edid_header_is_valid(buf) < 6) { |
| 449 | /* Couldn't find an accessible EDID on this |
| 450 | * connector */ |
| 451 | return false; |
| 452 | } |
| 453 | return true; |
| 454 | } |
| 455 | |
| 456 | static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 457 | { |
| 458 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); |
| 459 | |
| 460 | if (amdgpu_fb->obj) { |
| 461 | drm_gem_object_unreference_unlocked(amdgpu_fb->obj); |
| 462 | } |
| 463 | drm_framebuffer_cleanup(fb); |
| 464 | kfree(amdgpu_fb); |
| 465 | } |
| 466 | |
| 467 | static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 468 | struct drm_file *file_priv, |
| 469 | unsigned int *handle) |
| 470 | { |
| 471 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); |
| 472 | |
| 473 | return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); |
| 474 | } |
| 475 | |
| 476 | static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { |
| 477 | .destroy = amdgpu_user_framebuffer_destroy, |
| 478 | .create_handle = amdgpu_user_framebuffer_create_handle, |
| 479 | }; |
| 480 | |
| 481 | int |
| 482 | amdgpu_framebuffer_init(struct drm_device *dev, |
| 483 | struct amdgpu_framebuffer *rfb, |
| 484 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 485 | struct drm_gem_object *obj) |
| 486 | { |
| 487 | int ret; |
| 488 | rfb->obj = obj; |
| 489 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
| 490 | ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); |
| 491 | if (ret) { |
| 492 | rfb->obj = NULL; |
| 493 | return ret; |
| 494 | } |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | static struct drm_framebuffer * |
| 499 | amdgpu_user_framebuffer_create(struct drm_device *dev, |
| 500 | struct drm_file *file_priv, |
| 501 | struct drm_mode_fb_cmd2 *mode_cmd) |
| 502 | { |
| 503 | struct drm_gem_object *obj; |
| 504 | struct amdgpu_framebuffer *amdgpu_fb; |
| 505 | int ret; |
| 506 | |
| 507 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); |
| 508 | if (obj == NULL) { |
| 509 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " |
| 510 | "can't create framebuffer\n", mode_cmd->handles[0]); |
| 511 | return ERR_PTR(-ENOENT); |
| 512 | } |
| 513 | |
| 514 | amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); |
| 515 | if (amdgpu_fb == NULL) { |
| 516 | drm_gem_object_unreference_unlocked(obj); |
| 517 | return ERR_PTR(-ENOMEM); |
| 518 | } |
| 519 | |
| 520 | ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); |
| 521 | if (ret) { |
| 522 | kfree(amdgpu_fb); |
| 523 | drm_gem_object_unreference_unlocked(obj); |
| 524 | return ERR_PTR(ret); |
| 525 | } |
| 526 | |
| 527 | return &amdgpu_fb->base; |
| 528 | } |
| 529 | |
| 530 | static void amdgpu_output_poll_changed(struct drm_device *dev) |
| 531 | { |
| 532 | struct amdgpu_device *adev = dev->dev_private; |
| 533 | amdgpu_fb_output_poll_changed(adev); |
| 534 | } |
| 535 | |
| 536 | const struct drm_mode_config_funcs amdgpu_mode_funcs = { |
| 537 | .fb_create = amdgpu_user_framebuffer_create, |
| 538 | .output_poll_changed = amdgpu_output_poll_changed |
| 539 | }; |
| 540 | |
| 541 | static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = |
| 542 | { { UNDERSCAN_OFF, "off" }, |
| 543 | { UNDERSCAN_ON, "on" }, |
| 544 | { UNDERSCAN_AUTO, "auto" }, |
| 545 | }; |
| 546 | |
| 547 | static struct drm_prop_enum_list amdgpu_audio_enum_list[] = |
| 548 | { { AMDGPU_AUDIO_DISABLE, "off" }, |
| 549 | { AMDGPU_AUDIO_ENABLE, "on" }, |
| 550 | { AMDGPU_AUDIO_AUTO, "auto" }, |
| 551 | }; |
| 552 | |
| 553 | /* XXX support different dither options? spatial, temporal, both, etc. */ |
| 554 | static struct drm_prop_enum_list amdgpu_dither_enum_list[] = |
| 555 | { { AMDGPU_FMT_DITHER_DISABLE, "off" }, |
| 556 | { AMDGPU_FMT_DITHER_ENABLE, "on" }, |
| 557 | }; |
| 558 | |
| 559 | int amdgpu_modeset_create_props(struct amdgpu_device *adev) |
| 560 | { |
| 561 | int sz; |
| 562 | |
| 563 | if (adev->is_atom_bios) { |
| 564 | adev->mode_info.coherent_mode_property = |
| 565 | drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); |
| 566 | if (!adev->mode_info.coherent_mode_property) |
| 567 | return -ENOMEM; |
| 568 | } |
| 569 | |
| 570 | adev->mode_info.load_detect_property = |
| 571 | drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); |
| 572 | if (!adev->mode_info.load_detect_property) |
| 573 | return -ENOMEM; |
| 574 | |
| 575 | drm_mode_create_scaling_mode_property(adev->ddev); |
| 576 | |
| 577 | sz = ARRAY_SIZE(amdgpu_underscan_enum_list); |
| 578 | adev->mode_info.underscan_property = |
| 579 | drm_property_create_enum(adev->ddev, 0, |
| 580 | "underscan", |
| 581 | amdgpu_underscan_enum_list, sz); |
| 582 | |
| 583 | adev->mode_info.underscan_hborder_property = |
| 584 | drm_property_create_range(adev->ddev, 0, |
| 585 | "underscan hborder", 0, 128); |
| 586 | if (!adev->mode_info.underscan_hborder_property) |
| 587 | return -ENOMEM; |
| 588 | |
| 589 | adev->mode_info.underscan_vborder_property = |
| 590 | drm_property_create_range(adev->ddev, 0, |
| 591 | "underscan vborder", 0, 128); |
| 592 | if (!adev->mode_info.underscan_vborder_property) |
| 593 | return -ENOMEM; |
| 594 | |
| 595 | sz = ARRAY_SIZE(amdgpu_audio_enum_list); |
| 596 | adev->mode_info.audio_property = |
| 597 | drm_property_create_enum(adev->ddev, 0, |
| 598 | "audio", |
| 599 | amdgpu_audio_enum_list, sz); |
| 600 | |
| 601 | sz = ARRAY_SIZE(amdgpu_dither_enum_list); |
| 602 | adev->mode_info.dither_property = |
| 603 | drm_property_create_enum(adev->ddev, 0, |
| 604 | "dither", |
| 605 | amdgpu_dither_enum_list, sz); |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | void amdgpu_update_display_priority(struct amdgpu_device *adev) |
| 611 | { |
| 612 | /* adjustment options for the display watermarks */ |
| 613 | if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) |
| 614 | adev->mode_info.disp_priority = 0; |
| 615 | else |
| 616 | adev->mode_info.disp_priority = amdgpu_disp_priority; |
| 617 | |
| 618 | } |
| 619 | |
| 620 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
| 621 | { |
| 622 | /* try and guess if this is a tv or a monitor */ |
| 623 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
| 624 | (mode->vdisplay == 576) || /* 576p */ |
| 625 | (mode->vdisplay == 720) || /* 720p */ |
| 626 | (mode->vdisplay == 1080)) /* 1080p */ |
| 627 | return true; |
| 628 | else |
| 629 | return false; |
| 630 | } |
| 631 | |
| 632 | bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
| 633 | const struct drm_display_mode *mode, |
| 634 | struct drm_display_mode *adjusted_mode) |
| 635 | { |
| 636 | struct drm_device *dev = crtc->dev; |
| 637 | struct drm_encoder *encoder; |
| 638 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 639 | struct amdgpu_encoder *amdgpu_encoder; |
| 640 | struct drm_connector *connector; |
| 641 | struct amdgpu_connector *amdgpu_connector; |
| 642 | u32 src_v = 1, dst_v = 1; |
| 643 | u32 src_h = 1, dst_h = 1; |
| 644 | |
| 645 | amdgpu_crtc->h_border = 0; |
| 646 | amdgpu_crtc->v_border = 0; |
| 647 | |
| 648 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 649 | if (encoder->crtc != crtc) |
| 650 | continue; |
| 651 | amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 652 | connector = amdgpu_get_connector_for_encoder(encoder); |
| 653 | amdgpu_connector = to_amdgpu_connector(connector); |
| 654 | |
| 655 | /* set scaling */ |
| 656 | if (amdgpu_encoder->rmx_type == RMX_OFF) |
| 657 | amdgpu_crtc->rmx_type = RMX_OFF; |
| 658 | else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || |
| 659 | mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) |
| 660 | amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; |
| 661 | else |
| 662 | amdgpu_crtc->rmx_type = RMX_OFF; |
| 663 | /* copy native mode */ |
| 664 | memcpy(&amdgpu_crtc->native_mode, |
| 665 | &amdgpu_encoder->native_mode, |
| 666 | sizeof(struct drm_display_mode)); |
| 667 | src_v = crtc->mode.vdisplay; |
| 668 | dst_v = amdgpu_crtc->native_mode.vdisplay; |
| 669 | src_h = crtc->mode.hdisplay; |
| 670 | dst_h = amdgpu_crtc->native_mode.hdisplay; |
| 671 | |
| 672 | /* fix up for overscan on hdmi */ |
| 673 | if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
| 674 | ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || |
| 675 | ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && |
| 676 | drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && |
| 677 | is_hdtv_mode(mode)))) { |
| 678 | if (amdgpu_encoder->underscan_hborder != 0) |
| 679 | amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; |
| 680 | else |
| 681 | amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; |
| 682 | if (amdgpu_encoder->underscan_vborder != 0) |
| 683 | amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; |
| 684 | else |
| 685 | amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; |
| 686 | amdgpu_crtc->rmx_type = RMX_FULL; |
| 687 | src_v = crtc->mode.vdisplay; |
| 688 | dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); |
| 689 | src_h = crtc->mode.hdisplay; |
| 690 | dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); |
| 691 | } |
| 692 | } |
| 693 | if (amdgpu_crtc->rmx_type != RMX_OFF) { |
| 694 | fixed20_12 a, b; |
| 695 | a.full = dfixed_const(src_v); |
| 696 | b.full = dfixed_const(dst_v); |
| 697 | amdgpu_crtc->vsc.full = dfixed_div(a, b); |
| 698 | a.full = dfixed_const(src_h); |
| 699 | b.full = dfixed_const(dst_h); |
| 700 | amdgpu_crtc->hsc.full = dfixed_div(a, b); |
| 701 | } else { |
| 702 | amdgpu_crtc->vsc.full = dfixed_const(1); |
| 703 | amdgpu_crtc->hsc.full = dfixed_const(1); |
| 704 | } |
| 705 | return true; |
| 706 | } |
| 707 | |
| 708 | /* |
| 709 | * Retrieve current video scanout position of crtc on a given gpu, and |
| 710 | * an optional accurate timestamp of when query happened. |
| 711 | * |
| 712 | * \param dev Device to query. |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 713 | * \param pipe Crtc to query. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 714 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
| 715 | * \param *vpos Location where vertical scanout position should be stored. |
| 716 | * \param *hpos Location where horizontal scanout position should go. |
| 717 | * \param *stime Target location for timestamp taken immediately before |
| 718 | * scanout position query. Can be NULL to skip timestamp. |
| 719 | * \param *etime Target location for timestamp taken immediately after |
| 720 | * scanout position query. Can be NULL to skip timestamp. |
| 721 | * |
| 722 | * Returns vpos as a positive number while in active scanout area. |
| 723 | * Returns vpos as a negative number inside vblank, counting the number |
| 724 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
| 725 | * until start of active scanout / end of vblank." |
| 726 | * |
| 727 | * \return Flags, or'ed together as follows: |
| 728 | * |
| 729 | * DRM_SCANOUTPOS_VALID = Query successful. |
| 730 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
| 731 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
| 732 | * this flag means that returned position may be offset by a constant but |
| 733 | * unknown small number of scanlines wrt. real scanout position. |
| 734 | * |
| 735 | */ |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 736 | int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
| 737 | unsigned int flags, int *vpos, int *hpos, |
| 738 | ktime_t *stime, ktime_t *etime, |
Ville Syrjälä | 3bb403b | 2015-09-14 22:43:44 +0300 | [diff] [blame] | 739 | const struct drm_display_mode *mode) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 740 | { |
| 741 | u32 vbl = 0, position = 0; |
| 742 | int vbl_start, vbl_end, vtotal, ret = 0; |
| 743 | bool in_vbl = true; |
| 744 | |
| 745 | struct amdgpu_device *adev = dev->dev_private; |
| 746 | |
| 747 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
| 748 | |
| 749 | /* Get optional system timestamp before query. */ |
| 750 | if (stime) |
| 751 | *stime = ktime_get(); |
| 752 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 753 | if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 754 | ret |= DRM_SCANOUTPOS_VALID; |
| 755 | |
| 756 | /* Get optional system timestamp after query. */ |
| 757 | if (etime) |
| 758 | *etime = ktime_get(); |
| 759 | |
| 760 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
| 761 | |
| 762 | /* Decode into vertical and horizontal scanout position. */ |
| 763 | *vpos = position & 0x1fff; |
| 764 | *hpos = (position >> 16) & 0x1fff; |
| 765 | |
| 766 | /* Valid vblank area boundaries from gpu retrieved? */ |
| 767 | if (vbl > 0) { |
| 768 | /* Yes: Decode. */ |
| 769 | ret |= DRM_SCANOUTPOS_ACCURATE; |
| 770 | vbl_start = vbl & 0x1fff; |
| 771 | vbl_end = (vbl >> 16) & 0x1fff; |
| 772 | } |
| 773 | else { |
| 774 | /* No: Fake something reasonable which gives at least ok results. */ |
Ville Syrjälä | 3bb403b | 2015-09-14 22:43:44 +0300 | [diff] [blame] | 775 | vbl_start = mode->crtc_vdisplay; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 776 | vbl_end = 0; |
| 777 | } |
| 778 | |
| 779 | /* Test scanout position against vblank region. */ |
| 780 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
| 781 | in_vbl = false; |
| 782 | |
| 783 | /* Check if inside vblank area and apply corrective offsets: |
| 784 | * vpos will then be >=0 in video scanout area, but negative |
| 785 | * within vblank area, counting down the number of lines until |
| 786 | * start of scanout. |
| 787 | */ |
| 788 | |
| 789 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
| 790 | if (in_vbl && (*vpos >= vbl_start)) { |
Ville Syrjälä | 3bb403b | 2015-09-14 22:43:44 +0300 | [diff] [blame] | 791 | vtotal = mode->crtc_vtotal; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 792 | *vpos = *vpos - vtotal; |
| 793 | } |
| 794 | |
| 795 | /* Correct for shifted end of vbl at vbl_end. */ |
| 796 | *vpos = *vpos - vbl_end; |
| 797 | |
| 798 | /* In vblank? */ |
| 799 | if (in_vbl) |
| 800 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
| 801 | |
| 802 | /* Is vpos outside nominal vblank area, but less than |
| 803 | * 1/100 of a frame height away from start of vblank? |
| 804 | * If so, assume this isn't a massively delayed vblank |
| 805 | * interrupt, but a vblank interrupt that fired a few |
| 806 | * microseconds before true start of vblank. Compensate |
| 807 | * by adding a full frame duration to the final timestamp. |
| 808 | * Happens, e.g., on ATI R500, R600. |
| 809 | * |
| 810 | * We only do this if DRM_CALLED_FROM_VBLIRQ. |
| 811 | */ |
| 812 | if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { |
Ville Syrjälä | 3bb403b | 2015-09-14 22:43:44 +0300 | [diff] [blame] | 813 | vbl_start = mode->crtc_vdisplay; |
| 814 | vtotal = mode->crtc_vtotal; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 815 | |
| 816 | if (vbl_start - *vpos < vtotal / 100) { |
| 817 | *vpos -= vtotal; |
| 818 | |
| 819 | /* Signal this correction as "applied". */ |
| 820 | ret |= 0x8; |
| 821 | } |
| 822 | } |
| 823 | |
| 824 | return ret; |
| 825 | } |
| 826 | |
| 827 | int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) |
| 828 | { |
| 829 | if (crtc < 0 || crtc >= adev->mode_info.num_crtc) |
| 830 | return AMDGPU_CRTC_IRQ_NONE; |
| 831 | |
| 832 | switch (crtc) { |
| 833 | case 0: |
| 834 | return AMDGPU_CRTC_IRQ_VBLANK1; |
| 835 | case 1: |
| 836 | return AMDGPU_CRTC_IRQ_VBLANK2; |
| 837 | case 2: |
| 838 | return AMDGPU_CRTC_IRQ_VBLANK3; |
| 839 | case 3: |
| 840 | return AMDGPU_CRTC_IRQ_VBLANK4; |
| 841 | case 4: |
| 842 | return AMDGPU_CRTC_IRQ_VBLANK5; |
| 843 | case 5: |
| 844 | return AMDGPU_CRTC_IRQ_VBLANK6; |
| 845 | default: |
| 846 | return AMDGPU_CRTC_IRQ_NONE; |
| 847 | } |
| 848 | } |