Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 31 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 33 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/drm_crtc.h> |
| 35 | #include <drm/drm_edid.h> |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 36 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "i915_drv.h" |
| 39 | #include "intel_sdvo_regs.h" |
| 40 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
Chris Wilson | a0b1c7a | 2011-09-30 22:56:41 +0100 | [diff] [blame] | 44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 45 | |
| 46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 47 | SDVO_TV_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 48 | |
| 49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 54 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 55 | |
Ville Syrjälä | 4d9194d | 2015-08-21 20:45:29 +0300 | [diff] [blame] | 56 | static const char * const tv_format_names[] = { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 58 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 59 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 60 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 63 | "SECAM_60" |
| 64 | }; |
| 65 | |
Ville Syrjälä | 53abb67 | 2015-08-21 20:45:28 +0300 | [diff] [blame] | 66 | #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 67 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 68 | struct intel_sdvo { |
| 69 | struct intel_encoder base; |
| 70 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 71 | struct i2c_adapter *i2c; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 72 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 73 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 74 | struct i2c_adapter ddc; |
| 75 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 77 | i915_reg_t sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 78 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 79 | /* Active outputs controlled by this SDVO output */ |
| 80 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 81 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 82 | /* |
| 83 | * Capabilities of the SDVO device returned by |
Damien Lespiau | 19d415a | 2013-06-10 13:28:42 +0100 | [diff] [blame] | 84 | * intel_sdvo_get_capabilities() |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 85 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 86 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 87 | |
| 88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 89 | int pixel_clock_min, pixel_clock_max; |
| 90 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 91 | /* |
| 92 | * For multiple function SDVO device, |
| 93 | * this is for current attached outputs. |
| 94 | */ |
| 95 | uint16_t attached_output; |
| 96 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 97 | /* |
| 98 | * Hotplug activation bits for this device |
| 99 | */ |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 100 | uint16_t hotplug_active; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 101 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 102 | /** |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 103 | * This is used to select the color range of RBG outputs in HDMI mode. |
| 104 | * It is only valid when using TMDS encoding and 8 bit per color mode. |
| 105 | */ |
| 106 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 107 | bool color_range_auto; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 108 | |
| 109 | /** |
Ville Syrjälä | 7949dd4 | 2015-09-25 16:39:30 +0300 | [diff] [blame] | 110 | * HDMI user specified aspect ratio |
| 111 | */ |
| 112 | enum hdmi_picture_aspect aspect_ratio; |
| 113 | |
| 114 | /** |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 115 | * This is set if we're going to treat the device as TV-out. |
| 116 | * |
| 117 | * While we have these nice friendly flags for output types that ought |
| 118 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 119 | * shows up as RGB1 (VGA). |
| 120 | */ |
| 121 | bool is_tv; |
| 122 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 123 | enum port port; |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 124 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 125 | /* This is for current tv format name */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 126 | int tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 127 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 128 | /** |
| 129 | * This is set if we treat the device as HDMI, instead of DVI. |
| 130 | */ |
| 131 | bool is_hdmi; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 132 | bool has_hdmi_monitor; |
| 133 | bool has_hdmi_audio; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 134 | bool rgb_quant_range_selectable; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 135 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 136 | /** |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 137 | * This is set if we detect output of sdvo device as LVDS and |
| 138 | * have a valid fixed mode to use with the panel. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 139 | */ |
| 140 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 141 | |
| 142 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 143 | * This is sdvo fixed pannel mode pointer |
| 144 | */ |
| 145 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 146 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 147 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 148 | uint8_t ddc_bus; |
Egbert Eich | e751823 | 2012-10-13 14:29:31 +0200 | [diff] [blame] | 149 | |
| 150 | /* |
| 151 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd |
| 152 | */ |
| 153 | uint8_t dtd_sdvo_flags; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | struct intel_sdvo_connector { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 157 | struct intel_connector base; |
| 158 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 159 | /* Mark the type of connector */ |
| 160 | uint16_t output_flag; |
| 161 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 162 | enum hdmi_force_audio force_audio; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 163 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 164 | /* This contains all current supported TV format */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 165 | u8 tv_format_supported[TV_FORMAT_NUM]; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 166 | int format_supported_num; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 167 | struct drm_property *tv_format; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 168 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 169 | /* add the property for the SDVO-TV */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 170 | struct drm_property *left; |
| 171 | struct drm_property *right; |
| 172 | struct drm_property *top; |
| 173 | struct drm_property *bottom; |
| 174 | struct drm_property *hpos; |
| 175 | struct drm_property *vpos; |
| 176 | struct drm_property *contrast; |
| 177 | struct drm_property *saturation; |
| 178 | struct drm_property *hue; |
| 179 | struct drm_property *sharpness; |
| 180 | struct drm_property *flicker_filter; |
| 181 | struct drm_property *flicker_filter_adaptive; |
| 182 | struct drm_property *flicker_filter_2d; |
| 183 | struct drm_property *tv_chroma_filter; |
| 184 | struct drm_property *tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 185 | struct drm_property *dot_crawl; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 186 | |
| 187 | /* add the property for the SDVO-TV/LVDS */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 188 | struct drm_property *brightness; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 189 | |
| 190 | /* Add variable to record current setting for the above property */ |
| 191 | u32 left_margin, right_margin, top_margin, bottom_margin; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 192 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 193 | /* this is to get the range of margin.*/ |
| 194 | u32 max_hscan, max_vscan; |
| 195 | u32 max_hpos, cur_hpos; |
| 196 | u32 max_vpos, cur_vpos; |
| 197 | u32 cur_brightness, max_brightness; |
| 198 | u32 cur_contrast, max_contrast; |
| 199 | u32 cur_saturation, max_saturation; |
| 200 | u32 cur_hue, max_hue; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 201 | u32 cur_sharpness, max_sharpness; |
| 202 | u32 cur_flicker_filter, max_flicker_filter; |
| 203 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
| 204 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
| 205 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
| 206 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 207 | u32 cur_dot_crawl, max_dot_crawl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 208 | }; |
| 209 | |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 210 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 211 | { |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 212 | return container_of(encoder, struct intel_sdvo, base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 213 | } |
| 214 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 215 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
| 216 | { |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 217 | return to_sdvo(intel_attached_encoder(connector)); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 218 | } |
| 219 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 220 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
| 221 | { |
| 222 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
| 223 | } |
| 224 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 225 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 226 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 227 | static bool |
| 228 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 229 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 230 | int type); |
| 231 | static bool |
| 232 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 233 | struct intel_sdvo_connector *intel_sdvo_connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 234 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 235 | /** |
| 236 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 237 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 238 | * comments in the BIOS). |
| 239 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 240 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 241 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 242 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 243 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 244 | u32 bval = val, cval = val; |
| 245 | int i; |
| 246 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 247 | if (HAS_PCH_SPLIT(dev_priv)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 248 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
Ville Syrjälä | abab631 | 2015-05-05 17:17:32 +0300 | [diff] [blame] | 249 | POSTING_READ(intel_sdvo->sdvo_reg); |
Ville Syrjälä | e8504ee | 2015-05-05 17:17:33 +0300 | [diff] [blame] | 250 | /* |
| 251 | * HW workaround, need to write this twice for issue |
| 252 | * that may result in first write getting masked. |
| 253 | */ |
| 254 | if (HAS_PCH_IBX(dev)) { |
| 255 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 256 | POSTING_READ(intel_sdvo->sdvo_reg); |
| 257 | } |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 258 | return; |
| 259 | } |
| 260 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 261 | if (intel_sdvo->port == PORT_B) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 262 | cval = I915_READ(GEN3_SDVOC); |
| 263 | else |
| 264 | bval = I915_READ(GEN3_SDVOB); |
| 265 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 266 | /* |
| 267 | * Write the registers twice for luck. Sometimes, |
| 268 | * writing them only once doesn't appear to 'stick'. |
| 269 | * The BIOS does this too. Yay, magic |
| 270 | */ |
| 271 | for (i = 0; i < 2; i++) |
| 272 | { |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 273 | I915_WRITE(GEN3_SDVOB, bval); |
Ville Syrjälä | abab631 | 2015-05-05 17:17:32 +0300 | [diff] [blame] | 274 | POSTING_READ(GEN3_SDVOB); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 275 | I915_WRITE(GEN3_SDVOC, cval); |
Ville Syrjälä | abab631 | 2015-05-05 17:17:32 +0300 | [diff] [blame] | 276 | POSTING_READ(GEN3_SDVOC); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 277 | } |
| 278 | } |
| 279 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 280 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 281 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 282 | struct i2c_msg msgs[] = { |
| 283 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 284 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 285 | .flags = 0, |
| 286 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 287 | .buf = &addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 288 | }, |
| 289 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 290 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 291 | .flags = I2C_M_RD, |
| 292 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 293 | .buf = ch, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 294 | } |
| 295 | }; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 296 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 297 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 298 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 299 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 300 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 301 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 302 | return false; |
| 303 | } |
| 304 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 305 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 306 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 307 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 308 | u8 cmd; |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 309 | const char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 310 | } sdvo_cmd_names[] = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
| 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 354 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 355 | /* Add the op code for SDVO enhancements */ |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
| 380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
| 381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
| 382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
| 383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
| 385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
| 386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
| 387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
| 388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
| 389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
| 390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
| 391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
| 392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
| 393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
| 394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
| 395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
| 396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
| 397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
| 398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
| 399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 400 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 401 | /* HDMI op code */ |
| 402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 410 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 411 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 412 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 413 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 414 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 415 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 416 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 417 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 418 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 419 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 420 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 421 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 422 | }; |
| 423 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 424 | #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 425 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 426 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 427 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 428 | { |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 429 | int i, pos = 0; |
| 430 | #define BUF_LEN 256 |
| 431 | char buffer[BUF_LEN]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 432 | |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 433 | #define BUF_PRINT(args...) \ |
| 434 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) |
| 435 | |
| 436 | |
| 437 | for (i = 0; i < args_len; i++) { |
| 438 | BUF_PRINT("%02X ", ((u8 *)args)[i]); |
| 439 | } |
| 440 | for (; i < 8; i++) { |
| 441 | BUF_PRINT(" "); |
| 442 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 443 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 444 | if (cmd == sdvo_cmd_names[i].cmd) { |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 445 | BUF_PRINT("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 446 | break; |
| 447 | } |
| 448 | } |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 449 | if (i == ARRAY_SIZE(sdvo_cmd_names)) { |
| 450 | BUF_PRINT("(%02X)", cmd); |
| 451 | } |
| 452 | BUG_ON(pos >= BUF_LEN - 1); |
| 453 | #undef BUF_PRINT |
| 454 | #undef BUF_LEN |
| 455 | |
| 456 | DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 457 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 458 | |
Ville Syrjälä | 4d9194d | 2015-08-21 20:45:29 +0300 | [diff] [blame] | 459 | static const char * const cmd_status_names[] = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 460 | "Power on", |
| 461 | "Success", |
| 462 | "Not supported", |
| 463 | "Invalid arg", |
| 464 | "Pending", |
| 465 | "Target not specified", |
| 466 | "Scaling not supported" |
| 467 | }; |
| 468 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 469 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 470 | const void *args, int args_len) |
| 471 | { |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 472 | u8 *buf, status; |
| 473 | struct i2c_msg *msgs; |
| 474 | int i, ret = true; |
| 475 | |
Alan Cox | 0274df3 | 2012-07-25 13:51:04 +0100 | [diff] [blame] | 476 | /* Would be simpler to allocate both in one go ? */ |
Mihnea Dobrescu-Balaur | 5c67eeb | 2013-03-10 14:22:48 +0200 | [diff] [blame] | 477 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 478 | if (!buf) |
| 479 | return false; |
| 480 | |
| 481 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); |
Alan Cox | 0274df3 | 2012-07-25 13:51:04 +0100 | [diff] [blame] | 482 | if (!msgs) { |
| 483 | kfree(buf); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 484 | return false; |
Alan Cox | 0274df3 | 2012-07-25 13:51:04 +0100 | [diff] [blame] | 485 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 486 | |
| 487 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
| 488 | |
| 489 | for (i = 0; i < args_len; i++) { |
| 490 | msgs[i].addr = intel_sdvo->slave_addr; |
| 491 | msgs[i].flags = 0; |
| 492 | msgs[i].len = 2; |
| 493 | msgs[i].buf = buf + 2 *i; |
| 494 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
| 495 | buf[2*i + 1] = ((u8*)args)[i]; |
| 496 | } |
| 497 | msgs[i].addr = intel_sdvo->slave_addr; |
| 498 | msgs[i].flags = 0; |
| 499 | msgs[i].len = 2; |
| 500 | msgs[i].buf = buf + 2*i; |
| 501 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
| 502 | buf[2*i + 1] = cmd; |
| 503 | |
| 504 | /* the following two are to read the response */ |
| 505 | status = SDVO_I2C_CMD_STATUS; |
| 506 | msgs[i+1].addr = intel_sdvo->slave_addr; |
| 507 | msgs[i+1].flags = 0; |
| 508 | msgs[i+1].len = 1; |
| 509 | msgs[i+1].buf = &status; |
| 510 | |
| 511 | msgs[i+2].addr = intel_sdvo->slave_addr; |
| 512 | msgs[i+2].flags = I2C_M_RD; |
| 513 | msgs[i+2].len = 1; |
| 514 | msgs[i+2].buf = &status; |
| 515 | |
| 516 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 517 | if (ret < 0) { |
| 518 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 519 | ret = false; |
| 520 | goto out; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 521 | } |
| 522 | if (ret != i+3) { |
| 523 | /* failure in I2C transfer */ |
| 524 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 525 | ret = false; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 526 | } |
| 527 | |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 528 | out: |
| 529 | kfree(msgs); |
| 530 | kfree(buf); |
| 531 | return ret; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 532 | } |
| 533 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 534 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 535 | void *response, int response_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 536 | { |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 537 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 538 | u8 status; |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 539 | int i, pos = 0; |
| 540 | #define BUF_LEN 256 |
| 541 | char buffer[BUF_LEN]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 542 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 543 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 544 | /* |
| 545 | * The documentation states that all commands will be |
| 546 | * processed within 15µs, and that we need only poll |
| 547 | * the status byte a maximum of 3 times in order for the |
| 548 | * command to be complete. |
| 549 | * |
| 550 | * Check 5 times in case the hardware failed to read the docs. |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 551 | * |
| 552 | * Also beware that the first response by many devices is to |
| 553 | * reply PENDING and stall for time. TVs are notorious for |
| 554 | * requiring longer than specified to complete their replies. |
| 555 | * Originally (in the DDX long ago), the delay was only ever 15ms |
| 556 | * with an additional delay of 30ms applied for TVs added later after |
| 557 | * many experiments. To accommodate both sets of delays, we do a |
| 558 | * sequence of slow checks if the device is falling behind and fails |
| 559 | * to reply within 5*15µs. |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 560 | */ |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 561 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 562 | SDVO_I2C_CMD_STATUS, |
| 563 | &status)) |
| 564 | goto log_fail; |
| 565 | |
Guillaume Clement | 1ad87e7 | 2013-08-10 21:57:57 +0200 | [diff] [blame] | 566 | while ((status == SDVO_CMD_STATUS_PENDING || |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 567 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 568 | if (retry < 10) |
| 569 | msleep(15); |
| 570 | else |
| 571 | udelay(15); |
| 572 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 573 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 574 | SDVO_I2C_CMD_STATUS, |
| 575 | &status)) |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 576 | goto log_fail; |
| 577 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 578 | |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 579 | #define BUF_PRINT(args...) \ |
| 580 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) |
| 581 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 582 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 583 | BUF_PRINT("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 584 | else |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 585 | BUF_PRINT("(??? %d)", status); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 586 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 587 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 588 | goto log_fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 589 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 590 | /* Read the command response */ |
| 591 | for (i = 0; i < response_len; i++) { |
| 592 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 593 | SDVO_I2C_RETURN_0 + i, |
| 594 | &((u8 *)response)[i])) |
| 595 | goto log_fail; |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 596 | BUF_PRINT(" %02X", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 597 | } |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 598 | BUG_ON(pos >= BUF_LEN - 1); |
| 599 | #undef BUF_PRINT |
| 600 | #undef BUF_LEN |
| 601 | |
| 602 | DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 603 | return true; |
| 604 | |
| 605 | log_fail: |
Daniel Vetter | 84fcb46 | 2013-11-27 16:03:01 +0100 | [diff] [blame] | 606 | DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 607 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 608 | } |
| 609 | |
Ville Syrjälä | 5e7234c | 2015-09-25 16:37:43 +0300 | [diff] [blame] | 610 | static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 611 | { |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 612 | if (adjusted_mode->crtc_clock >= 100000) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 613 | return 1; |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 614 | else if (adjusted_mode->crtc_clock >= 50000) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 615 | return 2; |
| 616 | else |
| 617 | return 4; |
| 618 | } |
| 619 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 620 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 621 | u8 ddc_bus) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 622 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 623 | /* This must be the immediately preceding write before the i2c xfer */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 624 | return intel_sdvo_write_cmd(intel_sdvo, |
| 625 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
| 626 | &ddc_bus, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 627 | } |
| 628 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 629 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 630 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 631 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
| 632 | return false; |
| 633 | |
| 634 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static bool |
| 638 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 639 | { |
| 640 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
| 641 | return false; |
| 642 | |
| 643 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 644 | } |
| 645 | |
| 646 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 647 | { |
| 648 | struct intel_sdvo_set_target_input_args targets = {0}; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 649 | return intel_sdvo_set_value(intel_sdvo, |
| 650 | SDVO_CMD_SET_TARGET_INPUT, |
| 651 | &targets, sizeof(targets)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | /** |
| 655 | * Return whether each input is trained. |
| 656 | * |
| 657 | * This function is making an assumption about the layout of the response, |
| 658 | * which should be checked against the docs. |
| 659 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 660 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | { |
| 662 | struct intel_sdvo_get_trained_inputs_response response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 663 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 664 | BUILD_BUG_ON(sizeof(response) != 1); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 665 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
| 666 | &response, sizeof(response))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 667 | return false; |
| 668 | |
| 669 | *input_1 = response.input0_trained; |
| 670 | *input_2 = response.input1_trained; |
| 671 | return true; |
| 672 | } |
| 673 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 674 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 675 | u16 outputs) |
| 676 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 677 | return intel_sdvo_set_value(intel_sdvo, |
| 678 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
| 679 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 680 | } |
| 681 | |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 682 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
| 683 | u16 *outputs) |
| 684 | { |
| 685 | return intel_sdvo_get_value(intel_sdvo, |
| 686 | SDVO_CMD_GET_ACTIVE_OUTPUTS, |
| 687 | outputs, sizeof(*outputs)); |
| 688 | } |
| 689 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 690 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 691 | int mode) |
| 692 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 693 | u8 state = SDVO_ENCODER_STATE_ON; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 694 | |
| 695 | switch (mode) { |
| 696 | case DRM_MODE_DPMS_ON: |
| 697 | state = SDVO_ENCODER_STATE_ON; |
| 698 | break; |
| 699 | case DRM_MODE_DPMS_STANDBY: |
| 700 | state = SDVO_ENCODER_STATE_STANDBY; |
| 701 | break; |
| 702 | case DRM_MODE_DPMS_SUSPEND: |
| 703 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 704 | break; |
| 705 | case DRM_MODE_DPMS_OFF: |
| 706 | state = SDVO_ENCODER_STATE_OFF; |
| 707 | break; |
| 708 | } |
| 709 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 710 | return intel_sdvo_set_value(intel_sdvo, |
| 711 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 712 | } |
| 713 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 714 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 715 | int *clock_min, |
| 716 | int *clock_max) |
| 717 | { |
| 718 | struct intel_sdvo_pixel_clock_range clocks; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 719 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 720 | BUILD_BUG_ON(sizeof(clocks) != 4); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 721 | if (!intel_sdvo_get_value(intel_sdvo, |
| 722 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
| 723 | &clocks, sizeof(clocks))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 724 | return false; |
| 725 | |
| 726 | /* Convert the values from units of 10 kHz to kHz. */ |
| 727 | *clock_min = clocks.min * 10; |
| 728 | *clock_max = clocks.max * 10; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 729 | return true; |
| 730 | } |
| 731 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 732 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 733 | u16 outputs) |
| 734 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 735 | return intel_sdvo_set_value(intel_sdvo, |
| 736 | SDVO_CMD_SET_TARGET_OUTPUT, |
| 737 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 738 | } |
| 739 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 740 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | struct intel_sdvo_dtd *dtd) |
| 742 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 743 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 744 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 745 | } |
| 746 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 747 | static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 748 | struct intel_sdvo_dtd *dtd) |
| 749 | { |
| 750 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 751 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
| 752 | } |
| 753 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 754 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 755 | struct intel_sdvo_dtd *dtd) |
| 756 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 757 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 758 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 759 | } |
| 760 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 761 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 762 | struct intel_sdvo_dtd *dtd) |
| 763 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 764 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 765 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 766 | } |
| 767 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 768 | static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
| 769 | struct intel_sdvo_dtd *dtd) |
| 770 | { |
| 771 | return intel_sdvo_get_timing(intel_sdvo, |
| 772 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); |
| 773 | } |
| 774 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 775 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 776 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 777 | uint16_t clock, |
| 778 | uint16_t width, |
| 779 | uint16_t height) |
| 780 | { |
| 781 | struct intel_sdvo_preferred_input_timing_args args; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 782 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 783 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 784 | args.clock = clock; |
| 785 | args.width = width; |
| 786 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 787 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 788 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 789 | if (intel_sdvo->is_lvds && |
| 790 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 791 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 792 | args.scaled = 1; |
| 793 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 794 | return intel_sdvo_set_value(intel_sdvo, |
| 795 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
| 796 | &args, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 797 | } |
| 798 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 799 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 800 | struct intel_sdvo_dtd *dtd) |
| 801 | { |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 802 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
| 803 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 804 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
| 805 | &dtd->part1, sizeof(dtd->part1)) && |
| 806 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
| 807 | &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 808 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 809 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 810 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 811 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 812 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 813 | } |
| 814 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 815 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 816 | const struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 817 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 818 | uint16_t width, height; |
| 819 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 820 | uint16_t h_sync_offset, v_sync_offset; |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 821 | int mode_clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 822 | |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 823 | memset(dtd, 0, sizeof(*dtd)); |
| 824 | |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 825 | width = mode->hdisplay; |
| 826 | height = mode->vdisplay; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 827 | |
| 828 | /* do some mode translations */ |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 829 | h_blank_len = mode->htotal - mode->hdisplay; |
| 830 | h_sync_len = mode->hsync_end - mode->hsync_start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 831 | |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 832 | v_blank_len = mode->vtotal - mode->vdisplay; |
| 833 | v_sync_len = mode->vsync_end - mode->vsync_start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 834 | |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 835 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
| 836 | v_sync_offset = mode->vsync_start - mode->vdisplay; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 837 | |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 838 | mode_clock = mode->clock; |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 839 | mode_clock /= 10; |
| 840 | dtd->part1.clock = mode_clock; |
| 841 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 842 | dtd->part1.h_active = width & 0xff; |
| 843 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 844 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 845 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 846 | dtd->part1.v_active = height & 0xff; |
| 847 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 848 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 849 | ((v_blank_len >> 8) & 0xf); |
| 850 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 851 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 852 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 853 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 854 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 855 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 856 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 857 | ((v_sync_len & 0x30) >> 4); |
| 858 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 859 | dtd->part2.dtd_flags = 0x18; |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 860 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 861 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 862 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 863 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 864 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 865 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 866 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 867 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 868 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 869 | |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 870 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 871 | const struct intel_sdvo_dtd *dtd) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 872 | { |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 873 | struct drm_display_mode mode = {}; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 874 | |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 875 | mode.hdisplay = dtd->part1.h_active; |
| 876 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 877 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; |
| 878 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
| 879 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; |
| 880 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 881 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; |
| 882 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; |
| 883 | |
| 884 | mode.vdisplay = dtd->part1.v_active; |
| 885 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 886 | mode.vsync_start = mode.vdisplay; |
| 887 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
| 888 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
| 889 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 890 | mode.vsync_end = mode.vsync_start + |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 891 | (dtd->part2.v_sync_off_width & 0xf); |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 892 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 893 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; |
| 894 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 895 | |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 896 | mode.clock = dtd->part1.clock * 10; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 897 | |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 898 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 899 | mode.flags |= DRM_MODE_FLAG_INTERLACE; |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 900 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 901 | mode.flags |= DRM_MODE_FLAG_PHSYNC; |
Daniel Vetter | 3cea210 | 2013-09-10 10:02:48 +0200 | [diff] [blame] | 902 | else |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 903 | mode.flags |= DRM_MODE_FLAG_NHSYNC; |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 904 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 905 | mode.flags |= DRM_MODE_FLAG_PVSYNC; |
Daniel Vetter | 3cea210 | 2013-09-10 10:02:48 +0200 | [diff] [blame] | 906 | else |
Daniel Vetter | 1c4a814 | 2013-09-11 09:58:49 +0200 | [diff] [blame] | 907 | mode.flags |= DRM_MODE_FLAG_NVSYNC; |
| 908 | |
| 909 | drm_mode_set_crtcinfo(&mode, 0); |
| 910 | |
| 911 | drm_mode_copy(pmode, &mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 912 | } |
| 913 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 914 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 915 | { |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 916 | struct intel_sdvo_encode encode; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 917 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 918 | BUILD_BUG_ON(sizeof(encode) != 2); |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 919 | return intel_sdvo_get_value(intel_sdvo, |
| 920 | SDVO_CMD_GET_SUPP_ENCODE, |
| 921 | &encode, sizeof(encode)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 922 | } |
| 923 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 924 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 925 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 926 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 927 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 928 | } |
| 929 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 930 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 931 | uint8_t mode) |
| 932 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 933 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 934 | } |
| 935 | |
| 936 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 937 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 938 | { |
| 939 | int i, j; |
| 940 | uint8_t set_buf_index[2]; |
| 941 | uint8_t av_split; |
| 942 | uint8_t buf_size; |
| 943 | uint8_t buf[48]; |
| 944 | uint8_t *pos; |
| 945 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 946 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 947 | |
| 948 | for (i = 0; i <= av_split; i++) { |
| 949 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 950 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 951 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 952 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 953 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 954 | |
| 955 | pos = buf; |
| 956 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 957 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 958 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 959 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 960 | pos += 8; |
| 961 | } |
| 962 | } |
| 963 | } |
| 964 | #endif |
| 965 | |
Daniel Vetter | b6e0e54 | 2012-10-21 12:52:39 +0200 | [diff] [blame] | 966 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
| 967 | unsigned if_index, uint8_t tx_rate, |
Ville Syrjälä | fff6386 | 2013-12-10 15:19:08 +0200 | [diff] [blame] | 968 | const uint8_t *data, unsigned length) |
Daniel Vetter | b6e0e54 | 2012-10-21 12:52:39 +0200 | [diff] [blame] | 969 | { |
| 970 | uint8_t set_buf_index[2] = { if_index, 0 }; |
| 971 | uint8_t hbuf_size, tmp[8]; |
| 972 | int i; |
| 973 | |
| 974 | if (!intel_sdvo_set_value(intel_sdvo, |
| 975 | SDVO_CMD_SET_HBUF_INDEX, |
| 976 | set_buf_index, 2)) |
| 977 | return false; |
| 978 | |
| 979 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, |
| 980 | &hbuf_size, 1)) |
| 981 | return false; |
| 982 | |
| 983 | /* Buffer size is 0 based, hooray! */ |
| 984 | hbuf_size++; |
| 985 | |
| 986 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", |
| 987 | if_index, length, hbuf_size); |
| 988 | |
| 989 | for (i = 0; i < hbuf_size; i += 8) { |
| 990 | memset(tmp, 0, 8); |
| 991 | if (i < length) |
| 992 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); |
| 993 | |
| 994 | if (!intel_sdvo_set_value(intel_sdvo, |
| 995 | SDVO_CMD_SET_HBUF_DATA, |
| 996 | tmp, 8)) |
| 997 | return false; |
| 998 | } |
| 999 | |
| 1000 | return intel_sdvo_set_value(intel_sdvo, |
| 1001 | SDVO_CMD_SET_HBUF_TXRATE, |
| 1002 | &tx_rate, 1); |
| 1003 | } |
| 1004 | |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1005 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
| 1006 | const struct drm_display_mode *adjusted_mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1007 | { |
Damien Lespiau | 15dcd35 | 2013-08-06 20:32:20 +0100 | [diff] [blame] | 1008 | uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; |
| 1009 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; |
| 1010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1011 | union hdmi_infoframe frame; |
| 1012 | int ret; |
| 1013 | ssize_t len; |
| 1014 | |
| 1015 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
| 1016 | adjusted_mode); |
| 1017 | if (ret < 0) { |
| 1018 | DRM_ERROR("couldn't fill AVI infoframe\n"); |
| 1019 | return false; |
| 1020 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1021 | |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1022 | if (intel_sdvo->rgb_quant_range_selectable) { |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1023 | if (intel_crtc->config->limited_color_range) |
Damien Lespiau | 15dcd35 | 2013-08-06 20:32:20 +0100 | [diff] [blame] | 1024 | frame.avi.quantization_range = |
| 1025 | HDMI_QUANTIZATION_RANGE_LIMITED; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1026 | else |
Damien Lespiau | 15dcd35 | 2013-08-06 20:32:20 +0100 | [diff] [blame] | 1027 | frame.avi.quantization_range = |
| 1028 | HDMI_QUANTIZATION_RANGE_FULL; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1029 | } |
| 1030 | |
Damien Lespiau | 15dcd35 | 2013-08-06 20:32:20 +0100 | [diff] [blame] | 1031 | len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); |
| 1032 | if (len < 0) |
| 1033 | return false; |
Daniel Vetter | 81014b9 | 2012-05-12 20:22:00 +0200 | [diff] [blame] | 1034 | |
Daniel Vetter | b6e0e54 | 2012-10-21 12:52:39 +0200 | [diff] [blame] | 1035 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
| 1036 | SDVO_HBUF_TX_VSYNC, |
| 1037 | sdvo_data, sizeof(sdvo_data)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1038 | } |
| 1039 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1040 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1041 | { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1042 | struct intel_sdvo_tv_format format; |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1043 | uint32_t format_map; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1044 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1045 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1046 | memset(&format, 0, sizeof(format)); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1047 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1048 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1049 | BUILD_BUG_ON(sizeof(format) != 6); |
| 1050 | return intel_sdvo_set_value(intel_sdvo, |
| 1051 | SDVO_CMD_SET_TV_FORMAT, |
| 1052 | &format, sizeof(format)); |
| 1053 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1054 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1055 | static bool |
| 1056 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1057 | const struct drm_display_mode *mode) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1058 | { |
| 1059 | struct intel_sdvo_dtd output_dtd; |
| 1060 | |
| 1061 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1062 | intel_sdvo->attached_output)) |
| 1063 | return false; |
| 1064 | |
| 1065 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 1066 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1067 | return false; |
| 1068 | |
| 1069 | return true; |
| 1070 | } |
| 1071 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1072 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
| 1073 | * Unfortunately we have to set up the full output mode to do that. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1074 | static bool |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1075 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1076 | const struct drm_display_mode *mode, |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1077 | struct drm_display_mode *adjusted_mode) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1078 | { |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1079 | struct intel_sdvo_dtd input_dtd; |
| 1080 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1081 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 1082 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1083 | return false; |
| 1084 | |
| 1085 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 1086 | mode->clock / 10, |
| 1087 | mode->hdisplay, |
| 1088 | mode->vdisplay)) |
| 1089 | return false; |
| 1090 | |
| 1091 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1092 | &input_dtd)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1093 | return false; |
| 1094 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1095 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
Egbert Eich | e751823 | 2012-10-13 14:29:31 +0200 | [diff] [blame] | 1096 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1097 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1098 | return true; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1099 | } |
| 1100 | |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1101 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) |
Daniel Vetter | 7048455 | 2013-04-30 14:01:41 +0200 | [diff] [blame] | 1102 | { |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 1103 | unsigned dotclock = pipe_config->port_clock; |
Daniel Vetter | 7048455 | 2013-04-30 14:01:41 +0200 | [diff] [blame] | 1104 | struct dpll *clock = &pipe_config->dpll; |
| 1105 | |
| 1106 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 1107 | this mirrors vbios setting. */ |
| 1108 | if (dotclock >= 100000 && dotclock < 140500) { |
| 1109 | clock->p1 = 2; |
| 1110 | clock->p2 = 10; |
| 1111 | clock->n = 3; |
| 1112 | clock->m1 = 16; |
| 1113 | clock->m2 = 8; |
| 1114 | } else if (dotclock >= 140500 && dotclock <= 200000) { |
| 1115 | clock->p1 = 1; |
| 1116 | clock->p2 = 10; |
| 1117 | clock->n = 6; |
| 1118 | clock->m1 = 12; |
| 1119 | clock->m2 = 8; |
| 1120 | } else { |
| 1121 | WARN(1, "SDVO TV clock out of range: %i\n", dotclock); |
| 1122 | } |
| 1123 | |
| 1124 | pipe_config->clock_set = true; |
| 1125 | } |
| 1126 | |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 1127 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1128 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1129 | { |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1130 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1131 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| 1132 | struct drm_display_mode *mode = &pipe_config->base.mode; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1133 | |
Daniel Vetter | 5d2d38d | 2013-03-27 00:45:01 +0100 | [diff] [blame] | 1134 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); |
| 1135 | pipe_config->pipe_bpp = 8*3; |
| 1136 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1137 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
| 1138 | pipe_config->has_pch_encoder = true; |
| 1139 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1140 | /* We need to construct preferred input timings based on our |
| 1141 | * output timings. To do that, we have to set the output |
| 1142 | * timings, even though this isn't really the right place in |
| 1143 | * the sequence to do it. Oh well. |
| 1144 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1145 | if (intel_sdvo->is_tv) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1146 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1147 | return false; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1148 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1149 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1150 | mode, |
| 1151 | adjusted_mode); |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 1152 | pipe_config->sdvo_tv_clock = true; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1153 | } else if (intel_sdvo->is_lvds) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1154 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1155 | intel_sdvo->sdvo_lvds_fixed_mode)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1156 | return false; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1157 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1158 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1159 | mode, |
| 1160 | adjusted_mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1161 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1162 | |
| 1163 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1164 | * SDVO device will factor out the multiplier during mode_set. |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1165 | */ |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 1166 | pipe_config->pixel_multiplier = |
| 1167 | intel_sdvo_get_pixel_multiplier(adjusted_mode); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1168 | |
Daniel Vetter | 9f04003 | 2014-04-24 23:54:50 +0200 | [diff] [blame] | 1169 | pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; |
| 1170 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1171 | if (intel_sdvo->color_range_auto) { |
| 1172 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
Paulo Zanoni | 4f3a8bc | 2013-02-19 16:21:47 -0300 | [diff] [blame] | 1173 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
| 1174 | * bit per color mode. */ |
Daniel Vetter | 9f04003 | 2014-04-24 23:54:50 +0200 | [diff] [blame] | 1175 | if (pipe_config->has_hdmi_sink && |
Thierry Reding | 18316c8 | 2012-12-20 15:41:44 +0100 | [diff] [blame] | 1176 | drm_match_cea_mode(adjusted_mode) > 1) |
Daniel Vetter | 69f5acc | 2014-04-24 23:54:48 +0200 | [diff] [blame] | 1177 | pipe_config->limited_color_range = true; |
| 1178 | } else { |
Daniel Vetter | 9f04003 | 2014-04-24 23:54:50 +0200 | [diff] [blame] | 1179 | if (pipe_config->has_hdmi_sink && |
Daniel Vetter | 69f5acc | 2014-04-24 23:54:48 +0200 | [diff] [blame] | 1180 | intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) |
| 1181 | pipe_config->limited_color_range = true; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1182 | } |
| 1183 | |
Daniel Vetter | 7048455 | 2013-04-30 14:01:41 +0200 | [diff] [blame] | 1184 | /* Clock computation needs to happen after pixel multiplier. */ |
| 1185 | if (intel_sdvo->is_tv) |
| 1186 | i9xx_adjust_sdvo_tv_clock(pipe_config); |
| 1187 | |
Ville Syrjälä | 7949dd4 | 2015-09-25 16:39:30 +0300 | [diff] [blame] | 1188 | /* Set user selected PAR to incoming mode's member */ |
| 1189 | if (intel_sdvo->is_hdmi) |
| 1190 | adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; |
| 1191 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1192 | return true; |
| 1193 | } |
| 1194 | |
Daniel Vetter | 192d47a | 2014-04-24 23:54:45 +0200 | [diff] [blame] | 1195 | static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1196 | { |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 1197 | struct drm_device *dev = intel_encoder->base.dev; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1198 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eeb4793 | 2013-09-03 20:40:36 +0200 | [diff] [blame] | 1199 | struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 1200 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1201 | struct drm_display_mode *mode = &crtc->config->base.mode; |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1202 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1203 | u32 sdvox; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1204 | struct intel_sdvo_in_out_map in_out; |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 1205 | struct intel_sdvo_dtd input_dtd, output_dtd; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1206 | int rate; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1207 | |
| 1208 | if (!mode) |
| 1209 | return; |
| 1210 | |
| 1211 | /* First, set the input mapping for the first input to our controlled |
| 1212 | * output. This is only correct if we're a single-input device, in |
| 1213 | * which case the first input is the output from the appropriate SDVO |
| 1214 | * channel on the motherboard. In a two-input device, the first input |
| 1215 | * will be SDVOB and the second SDVOC. |
| 1216 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1217 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1218 | in_out.in1 = 0; |
| 1219 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1220 | intel_sdvo_set_value(intel_sdvo, |
| 1221 | SDVO_CMD_SET_IN_OUT_MAP, |
| 1222 | &in_out, sizeof(in_out)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1223 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1224 | /* Set the output timings to the screen */ |
| 1225 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1226 | intel_sdvo->attached_output)) |
| 1227 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1228 | |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 1229 | /* lvds has a special fixed output timing. */ |
| 1230 | if (intel_sdvo->is_lvds) |
| 1231 | intel_sdvo_get_dtd_from_mode(&output_dtd, |
| 1232 | intel_sdvo->sdvo_lvds_fixed_mode); |
| 1233 | else |
| 1234 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
Daniel Vetter | c8d4bb5 | 2012-04-10 13:55:48 +0200 | [diff] [blame] | 1235 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1236 | DRM_INFO("Setting output timings on %s failed\n", |
| 1237 | SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1238 | |
| 1239 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1240 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1241 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1242 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1243 | if (crtc->config->has_hdmi_sink) { |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1244 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 1245 | intel_sdvo_set_colorimetry(intel_sdvo, |
| 1246 | SDVO_COLORIMETRY_RGB256); |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1247 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1248 | } else |
| 1249 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1250 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1251 | if (intel_sdvo->is_tv && |
| 1252 | !intel_sdvo_set_tv_format(intel_sdvo)) |
| 1253 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1254 | |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 1255 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Daniel Vetter | eeb4793 | 2013-09-03 20:40:36 +0200 | [diff] [blame] | 1256 | |
Egbert Eich | e751823 | 2012-10-13 14:29:31 +0200 | [diff] [blame] | 1257 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
| 1258 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; |
Daniel Vetter | c8d4bb5 | 2012-04-10 13:55:48 +0200 | [diff] [blame] | 1259 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
| 1260 | DRM_INFO("Setting input timings on %s failed\n", |
| 1261 | SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1262 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1263 | switch (crtc->config->pixel_multiplier) { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1264 | default: |
Yannick Guerrini | fd0753c | 2015-02-28 17:20:41 +0100 | [diff] [blame] | 1265 | WARN(1, "unknown pixel multiplier specified\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1266 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
| 1267 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
| 1268 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1269 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1270 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1271 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1272 | |
| 1273 | /* Set the SDVO control regs. */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1274 | if (INTEL_INFO(dev)->gen >= 4) { |
Paulo Zanoni | ba68e08 | 2012-01-06 19:45:34 -0200 | [diff] [blame] | 1275 | /* The real mode polarity is set by the SDVO commands, using |
| 1276 | * struct intel_sdvo_dtd. */ |
| 1277 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1278 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
Daniel Vetter | 69f5acc | 2014-04-24 23:54:48 +0200 | [diff] [blame] | 1279 | sdvox |= HDMI_COLOR_RANGE_16_235; |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1280 | if (INTEL_INFO(dev)->gen < 5) |
| 1281 | sdvox |= SDVO_BORDER_ENABLE; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1282 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1283 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 1284 | if (intel_sdvo->port == PORT_B) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1285 | sdvox &= SDVOB_PRESERVE_MASK; |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 1286 | else |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1287 | sdvox &= SDVOC_PRESERVE_MASK; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1288 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1289 | } |
Paulo Zanoni | 3573c41 | 2011-10-14 18:16:22 -0300 | [diff] [blame] | 1290 | |
| 1291 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) |
Daniel Vetter | eeb4793 | 2013-09-03 20:40:36 +0200 | [diff] [blame] | 1292 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
Paulo Zanoni | 3573c41 | 2011-10-14 18:16:22 -0300 | [diff] [blame] | 1293 | else |
Daniel Vetter | eeb4793 | 2013-09-03 20:40:36 +0200 | [diff] [blame] | 1294 | sdvox |= SDVO_PIPE_SEL(crtc->pipe); |
Paulo Zanoni | 3573c41 | 2011-10-14 18:16:22 -0300 | [diff] [blame] | 1295 | |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1296 | if (intel_sdvo->has_hdmi_audio) |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1297 | sdvox |= SDVO_AUDIO_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1298 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1299 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1300 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1301 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1302 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1303 | } else { |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1304 | sdvox |= (crtc->config->pixel_multiplier - 1) |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 1305 | << SDVO_PORT_MULTIPLY_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1306 | } |
| 1307 | |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1308 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
| 1309 | INTEL_INFO(dev)->gen < 5) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1310 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1311 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1312 | } |
| 1313 | |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1314 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1315 | { |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1316 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 1317 | to_intel_sdvo_connector(&connector->base); |
| 1318 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); |
Damien Lespiau | 2f28c50 | 2013-06-10 13:49:25 +0100 | [diff] [blame] | 1319 | u16 active_outputs = 0; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1320 | |
| 1321 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
| 1322 | |
| 1323 | if (active_outputs & intel_sdvo_connector->output_flag) |
| 1324 | return true; |
| 1325 | else |
| 1326 | return false; |
| 1327 | } |
| 1328 | |
| 1329 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, |
| 1330 | enum pipe *pipe) |
| 1331 | { |
| 1332 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1333 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1334 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
Damien Lespiau | 2f28c50 | 2013-06-10 13:49:25 +0100 | [diff] [blame] | 1335 | u16 active_outputs = 0; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1336 | u32 tmp; |
| 1337 | |
| 1338 | tmp = I915_READ(intel_sdvo->sdvo_reg); |
Egbert Eich | 7a7d1fb | 2013-04-04 16:04:02 -0400 | [diff] [blame] | 1339 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1340 | |
Egbert Eich | 7a7d1fb | 2013-04-04 16:04:02 -0400 | [diff] [blame] | 1341 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1342 | return false; |
| 1343 | |
| 1344 | if (HAS_PCH_CPT(dev)) |
| 1345 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 1346 | else |
| 1347 | *pipe = PORT_TO_PIPE(tmp); |
| 1348 | |
| 1349 | return true; |
| 1350 | } |
| 1351 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1352 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1353 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1354 | { |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1355 | struct drm_device *dev = encoder->base.dev; |
| 1356 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1357 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1358 | struct intel_sdvo_dtd dtd; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1359 | int encoder_pixel_multiplier = 0; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1360 | int dotclock; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1361 | u32 flags = 0, sdvox; |
| 1362 | u8 val; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1363 | bool ret; |
| 1364 | |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 1365 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
| 1366 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1367 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); |
| 1368 | if (!ret) { |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 1369 | /* Some sdvo encoders are not spec compliant and don't |
| 1370 | * implement the mandatory get_timings function. */ |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1371 | DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 1372 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; |
| 1373 | } else { |
| 1374 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
| 1375 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1376 | else |
| 1377 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 1378 | |
| 1379 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
| 1380 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1381 | else |
| 1382 | flags |= DRM_MODE_FLAG_NVSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1383 | } |
| 1384 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1385 | pipe_config->base.adjusted_mode.flags |= flags; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1386 | |
Daniel Vetter | fdafa9e | 2013-06-12 11:47:24 +0200 | [diff] [blame] | 1387 | /* |
| 1388 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in |
| 1389 | * the sdvo port register, on all other platforms it is part of the dpll |
| 1390 | * state. Since the general pipe state readout happens before the |
| 1391 | * encoder->get_config we so already have a valid pixel multplier on all |
| 1392 | * other platfroms. |
| 1393 | */ |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1394 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1395 | pipe_config->pixel_multiplier = |
| 1396 | ((sdvox & SDVO_PORT_MULTIPLY_MASK) |
| 1397 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; |
| 1398 | } |
| 1399 | |
Ville Syrjälä | 2b85886 | 2014-06-09 16:20:46 +0300 | [diff] [blame] | 1400 | dotclock = pipe_config->port_clock; |
| 1401 | if (pipe_config->pixel_multiplier) |
| 1402 | dotclock /= pipe_config->pixel_multiplier; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1403 | |
| 1404 | if (HAS_PCH_SPLIT(dev)) |
| 1405 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
| 1406 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1407 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1408 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1409 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
Damien Lespiau | 53b9140 | 2013-07-12 16:24:40 +0100 | [diff] [blame] | 1410 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, |
| 1411 | &val, 1)) { |
| 1412 | switch (val) { |
| 1413 | case SDVO_CLOCK_RATE_MULT_1X: |
| 1414 | encoder_pixel_multiplier = 1; |
| 1415 | break; |
| 1416 | case SDVO_CLOCK_RATE_MULT_2X: |
| 1417 | encoder_pixel_multiplier = 2; |
| 1418 | break; |
| 1419 | case SDVO_CLOCK_RATE_MULT_4X: |
| 1420 | encoder_pixel_multiplier = 4; |
| 1421 | break; |
| 1422 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1423 | } |
Daniel Vetter | fdafa9e | 2013-06-12 11:47:24 +0200 | [diff] [blame] | 1424 | |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 1425 | if (sdvox & HDMI_COLOR_RANGE_16_235) |
| 1426 | pipe_config->limited_color_range = true; |
| 1427 | |
Daniel Vetter | 9f04003 | 2014-04-24 23:54:50 +0200 | [diff] [blame] | 1428 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, |
| 1429 | &val, 1)) { |
| 1430 | if (val == SDVO_ENCODE_HDMI) |
| 1431 | pipe_config->has_hdmi_sink = true; |
| 1432 | } |
| 1433 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 1434 | WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, |
| 1435 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", |
| 1436 | pipe_config->pixel_multiplier, encoder_pixel_multiplier); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1437 | } |
| 1438 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1439 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
| 1440 | { |
| 1441 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1442 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 1443 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1444 | u32 temp; |
| 1445 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1446 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
| 1447 | if (0) |
| 1448 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
| 1449 | DRM_MODE_DPMS_OFF); |
| 1450 | |
| 1451 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1452 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 1453 | temp &= ~SDVO_ENABLE; |
| 1454 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1455 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 1456 | /* |
| 1457 | * HW workaround for IBX, we need to move the port |
| 1458 | * to transcoder A after disabling it to allow the |
| 1459 | * matching DP port to be enabled on transcoder A. |
| 1460 | */ |
| 1461 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 1462 | /* |
| 1463 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 1464 | * doing the workaround. Sweep them under the rug. |
| 1465 | */ |
| 1466 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 1467 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 1468 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 1469 | temp &= ~SDVO_PIPE_B_SELECT; |
| 1470 | temp |= SDVO_ENABLE; |
| 1471 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1472 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 1473 | temp &= ~SDVO_ENABLE; |
| 1474 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 1475 | |
| 1476 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
| 1477 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 1478 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1479 | } |
| 1480 | } |
| 1481 | |
Ville Syrjälä | 3c65d1d | 2015-05-05 17:17:36 +0300 | [diff] [blame] | 1482 | static void pch_disable_sdvo(struct intel_encoder *encoder) |
| 1483 | { |
| 1484 | } |
| 1485 | |
| 1486 | static void pch_post_disable_sdvo(struct intel_encoder *encoder) |
| 1487 | { |
| 1488 | intel_disable_sdvo(encoder); |
| 1489 | } |
| 1490 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1491 | static void intel_enable_sdvo(struct intel_encoder *encoder) |
| 1492 | { |
| 1493 | struct drm_device *dev = encoder->base.dev; |
| 1494 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1495 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1496 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 1497 | u32 temp; |
| 1498 | bool input1, input2; |
| 1499 | int i; |
Jani Nikula | d0a7b6d | 2014-03-21 14:56:32 +0200 | [diff] [blame] | 1500 | bool success; |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1501 | |
| 1502 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Ville Syrjälä | 3c65d1d | 2015-05-05 17:17:36 +0300 | [diff] [blame] | 1503 | temp |= SDVO_ENABLE; |
| 1504 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1505 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1506 | for (i = 0; i < 2; i++) |
| 1507 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 1508 | |
Jani Nikula | d0a7b6d | 2014-03-21 14:56:32 +0200 | [diff] [blame] | 1509 | success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1510 | /* Warn if the device reported failure to sync. |
| 1511 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1512 | * a given it the status is a success, we succeeded. |
| 1513 | */ |
Jani Nikula | d0a7b6d | 2014-03-21 14:56:32 +0200 | [diff] [blame] | 1514 | if (success && !input1) { |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1515 | DRM_DEBUG_KMS("First %s output reported failure to " |
| 1516 | "sync\n", SDVO_NAME(intel_sdvo)); |
| 1517 | } |
| 1518 | |
| 1519 | if (0) |
| 1520 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
| 1521 | DRM_MODE_DPMS_ON); |
| 1522 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
| 1523 | } |
| 1524 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 1525 | static enum drm_mode_status |
| 1526 | intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1527 | struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1528 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1529 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1530 | |
| 1531 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1532 | return MODE_NO_DBLESCAN; |
| 1533 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1534 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1535 | return MODE_CLOCK_LOW; |
| 1536 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1537 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1538 | return MODE_CLOCK_HIGH; |
| 1539 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1540 | if (intel_sdvo->is_lvds) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1541 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1542 | return MODE_PANEL; |
| 1543 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1544 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1545 | return MODE_PANEL; |
| 1546 | } |
| 1547 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1548 | return MODE_OK; |
| 1549 | } |
| 1550 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1551 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1552 | { |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 1553 | BUILD_BUG_ON(sizeof(*caps) != 8); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1554 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1555 | SDVO_CMD_GET_DEVICE_CAPS, |
| 1556 | caps, sizeof(*caps))) |
| 1557 | return false; |
| 1558 | |
| 1559 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
| 1560 | " vendor_id: %d\n" |
| 1561 | " device_id: %d\n" |
| 1562 | " device_rev_id: %d\n" |
| 1563 | " sdvo_version_major: %d\n" |
| 1564 | " sdvo_version_minor: %d\n" |
| 1565 | " sdvo_inputs_mask: %d\n" |
| 1566 | " smooth_scaling: %d\n" |
| 1567 | " sharp_scaling: %d\n" |
| 1568 | " up_scaling: %d\n" |
| 1569 | " down_scaling: %d\n" |
| 1570 | " stall_support: %d\n" |
| 1571 | " output_flags: %d\n", |
| 1572 | caps->vendor_id, |
| 1573 | caps->device_id, |
| 1574 | caps->device_rev_id, |
| 1575 | caps->sdvo_version_major, |
| 1576 | caps->sdvo_version_minor, |
| 1577 | caps->sdvo_inputs_mask, |
| 1578 | caps->smooth_scaling, |
| 1579 | caps->sharp_scaling, |
| 1580 | caps->up_scaling, |
| 1581 | caps->down_scaling, |
| 1582 | caps->stall_support, |
| 1583 | caps->output_flags); |
| 1584 | |
| 1585 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1586 | } |
| 1587 | |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1588 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1589 | { |
Daniel Vetter | 768b107 | 2012-05-04 11:29:56 +0200 | [diff] [blame] | 1590 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1591 | uint16_t hotplug; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1592 | |
Ville Syrjälä | 1d83d95 | 2015-01-09 14:21:15 +0200 | [diff] [blame] | 1593 | if (!I915_HAS_HOTPLUG(dev)) |
| 1594 | return 0; |
| 1595 | |
Daniel Vetter | 768b107 | 2012-05-04 11:29:56 +0200 | [diff] [blame] | 1596 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
| 1597 | * on the line. */ |
| 1598 | if (IS_I945G(dev) || IS_I945GM(dev)) |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1599 | return 0; |
Daniel Vetter | 768b107 | 2012-05-04 11:29:56 +0200 | [diff] [blame] | 1600 | |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1601 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
| 1602 | &hotplug, sizeof(hotplug))) |
| 1603 | return 0; |
| 1604 | |
| 1605 | return hotplug; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1606 | } |
| 1607 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1608 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1609 | { |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 1610 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1611 | |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1612 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
| 1613 | &intel_sdvo->hotplug_active, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1614 | } |
| 1615 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1616 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1617 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1618 | { |
Chris Wilson | bc65212 | 2011-01-25 13:28:29 +0000 | [diff] [blame] | 1619 | /* Is there more than one type of output? */ |
Adam Jackson | 2294488 | 2011-06-16 16:36:24 -0400 | [diff] [blame] | 1620 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1621 | } |
| 1622 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1623 | static struct edid * |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1624 | intel_sdvo_get_edid(struct drm_connector *connector) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1625 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1626 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
| 1627 | return drm_get_edid(connector, &sdvo->ddc); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1628 | } |
| 1629 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1630 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 1631 | static struct edid * |
| 1632 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 1633 | { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1634 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1635 | |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1636 | return drm_get_edid(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 1637 | intel_gmbus_get_adapter(dev_priv, |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1638 | dev_priv->vbt.crt_ddc_pin)); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1639 | } |
| 1640 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1641 | static enum drm_connector_status |
Adam Jackson | 8bf3848 | 2011-06-16 16:36:25 -0400 | [diff] [blame] | 1642 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1643 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1644 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1645 | enum drm_connector_status status; |
| 1646 | struct edid *edid; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1647 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1648 | edid = intel_sdvo_get_edid(connector); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1649 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1650 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1651 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1652 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1653 | /* |
| 1654 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1655 | * the EDID. It is used for SDVO SPD ROM. |
| 1656 | */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1657 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1658 | intel_sdvo->ddc_bus = ddc; |
| 1659 | edid = intel_sdvo_get_edid(connector); |
| 1660 | if (edid) |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1661 | break; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1662 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1663 | /* |
| 1664 | * If we found the EDID on the other bus, |
| 1665 | * assume that is the correct DDC bus. |
| 1666 | */ |
| 1667 | if (edid == NULL) |
| 1668 | intel_sdvo->ddc_bus = saved_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1669 | } |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1670 | |
| 1671 | /* |
| 1672 | * When there is no edid and no monitor is connected with VGA |
| 1673 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1674 | */ |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1675 | if (edid == NULL) |
| 1676 | edid = intel_sdvo_get_analog_edid(connector); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1677 | |
Chris Wilson | 2f551c8 | 2010-09-15 10:42:50 +0100 | [diff] [blame] | 1678 | status = connector_status_unknown; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1679 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1680 | /* DDC bus is shared, match EDID to connector type */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1681 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 1682 | status = connector_status_connected; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1683 | if (intel_sdvo->is_hdmi) { |
| 1684 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
| 1685 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1686 | intel_sdvo->rgb_quant_range_selectable = |
| 1687 | drm_rgb_quant_range_selectable(edid); |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1688 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1689 | } else |
| 1690 | status = connector_status_disconnected; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1691 | kfree(edid); |
| 1692 | } |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1693 | |
| 1694 | if (status == connector_status_connected) { |
| 1695 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 1696 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
| 1697 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1698 | } |
| 1699 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1700 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1701 | } |
| 1702 | |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1703 | static bool |
| 1704 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, |
| 1705 | struct edid *edid) |
| 1706 | { |
| 1707 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
| 1708 | bool connector_is_digital = !!IS_DIGITAL(sdvo); |
| 1709 | |
| 1710 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", |
| 1711 | connector_is_digital, monitor_is_digital); |
| 1712 | return connector_is_digital == monitor_is_digital; |
| 1713 | } |
| 1714 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 1715 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1716 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1717 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1718 | uint16_t response; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1719 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1720 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1721 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1722 | |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 1723 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1724 | connector->base.id, connector->name); |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 1725 | |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 1726 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1727 | SDVO_CMD_GET_ATTACHED_DISPLAYS, |
| 1728 | &response, 2)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1729 | return connector_status_unknown; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1730 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1731 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
| 1732 | response & 0xff, response >> 8, |
| 1733 | intel_sdvo_connector->output_flag); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1734 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1735 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1736 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1737 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1738 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1739 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1740 | intel_sdvo->has_hdmi_monitor = false; |
| 1741 | intel_sdvo->has_hdmi_audio = false; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1742 | intel_sdvo->rgb_quant_range_selectable = false; |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1743 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1744 | if ((intel_sdvo_connector->output_flag & response) == 0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1745 | ret = connector_status_disconnected; |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1746 | else if (IS_TMDS(intel_sdvo_connector)) |
Adam Jackson | 8bf3848 | 2011-06-16 16:36:25 -0400 | [diff] [blame] | 1747 | ret = intel_sdvo_tmds_sink_detect(connector); |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1748 | else { |
| 1749 | struct edid *edid; |
| 1750 | |
| 1751 | /* if we have an edid check it matches the connection */ |
| 1752 | edid = intel_sdvo_get_edid(connector); |
| 1753 | if (edid == NULL) |
| 1754 | edid = intel_sdvo_get_analog_edid(connector); |
| 1755 | if (edid != NULL) { |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1756 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
| 1757 | edid)) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1758 | ret = connector_status_connected; |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1759 | else |
| 1760 | ret = connector_status_disconnected; |
| 1761 | |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1762 | kfree(edid); |
| 1763 | } else |
| 1764 | ret = connector_status_connected; |
| 1765 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1766 | |
| 1767 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1768 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1769 | intel_sdvo->is_tv = false; |
| 1770 | intel_sdvo->is_lvds = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1771 | |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 1772 | if (response & SDVO_TV_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1773 | intel_sdvo->is_tv = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1774 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1775 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1776 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1777 | |
| 1778 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1779 | } |
| 1780 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1781 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1782 | { |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1783 | struct edid *edid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1784 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 1785 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1786 | connector->base.id, connector->name); |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 1787 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1788 | /* set the bus switch and get the modes */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1789 | edid = intel_sdvo_get_edid(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1790 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1791 | /* |
| 1792 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1793 | * link between analog and digital outputs. So, if the regular SDVO |
| 1794 | * DDC fails, check to see if the analog output is disconnected, in |
| 1795 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1796 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1797 | if (edid == NULL) |
| 1798 | edid = intel_sdvo_get_analog_edid(connector); |
| 1799 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1800 | if (edid != NULL) { |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1801 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
| 1802 | edid)) { |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1803 | drm_mode_connector_update_edid_property(connector, edid); |
| 1804 | drm_add_edid_modes(connector, edid); |
| 1805 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1806 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1807 | kfree(edid); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1808 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1809 | } |
| 1810 | |
| 1811 | /* |
| 1812 | * Set of SDVO TV modes. |
| 1813 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1814 | * XXX: all 60Hz refresh? |
| 1815 | */ |
Chris Wilson | b1f559e | 2011-01-26 09:49:47 +0000 | [diff] [blame] | 1816 | static const struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1817 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1818 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1819 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1820 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1821 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1822 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1823 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1824 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1825 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1826 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1827 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1828 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1829 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1830 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1831 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1832 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1833 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1834 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1835 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1836 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1837 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1838 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1839 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1840 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1841 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1842 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1843 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1844 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1845 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1846 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1847 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1848 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1849 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1850 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1851 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1852 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1853 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1854 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1855 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1856 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1857 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1858 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1859 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1860 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1861 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1862 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1863 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1864 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1865 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1866 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1867 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1868 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1869 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1870 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1871 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1872 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1873 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1874 | }; |
| 1875 | |
| 1876 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1877 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1878 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1879 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1880 | uint32_t reply = 0, format_map = 0; |
| 1881 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1882 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 1883 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1884 | connector->base.id, connector->name); |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 1885 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1886 | /* Read the list of supported input resolutions for the selected TV |
| 1887 | * format. |
| 1888 | */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1889 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1890 | memcpy(&tv_res, &format_map, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1891 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1892 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1893 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 1894 | return; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1895 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1896 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1897 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 1898 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1899 | &tv_res, sizeof(tv_res))) |
| 1900 | return; |
| 1901 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1902 | return; |
| 1903 | |
| 1904 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1905 | if (reply & (1 << i)) { |
| 1906 | struct drm_display_mode *nmode; |
| 1907 | nmode = drm_mode_duplicate(connector->dev, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1908 | &sdvo_tv_modes[i]); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1909 | if (nmode) |
| 1910 | drm_mode_probed_add(connector, nmode); |
| 1911 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1912 | } |
| 1913 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1914 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1915 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1916 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1917 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1918 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1919 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 1920 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1921 | connector->base.id, connector->name); |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 1922 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1923 | /* |
Daniel Vetter | c3456fb | 2013-06-10 09:47:58 +0200 | [diff] [blame] | 1924 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
Dave Airlie | 4300a0f | 2013-06-27 20:40:44 +1000 | [diff] [blame] | 1925 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1926 | */ |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1927 | if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1928 | newmode = drm_mode_duplicate(connector->dev, |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1929 | dev_priv->vbt.sdvo_lvds_vbt_mode); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1930 | if (newmode != NULL) { |
| 1931 | /* Guarantee the mode is preferred */ |
| 1932 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1933 | DRM_MODE_TYPE_DRIVER); |
| 1934 | drm_mode_probed_add(connector, newmode); |
| 1935 | } |
| 1936 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1937 | |
Dave Airlie | 4300a0f | 2013-06-27 20:40:44 +1000 | [diff] [blame] | 1938 | /* |
| 1939 | * Attempt to get the mode list from DDC. |
| 1940 | * Assume that the preferred modes are |
| 1941 | * arranged in priority order. |
| 1942 | */ |
| 1943 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); |
| 1944 | |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1945 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1946 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1947 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1948 | drm_mode_duplicate(connector->dev, newmode); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1949 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1950 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1951 | break; |
| 1952 | } |
| 1953 | } |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1954 | } |
| 1955 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1956 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1957 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1958 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1959 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1960 | if (IS_TV(intel_sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1961 | intel_sdvo_get_tv_modes(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1962 | else if (IS_LVDS(intel_sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1963 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1964 | else |
| 1965 | intel_sdvo_get_ddc_modes(connector); |
| 1966 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1967 | return !list_empty(&connector->probed_modes); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1968 | } |
| 1969 | |
| 1970 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1971 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1972 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1973 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1974 | drm_connector_cleanup(connector); |
Jani Nikula | 4b745b1 | 2012-11-12 18:31:36 +0200 | [diff] [blame] | 1975 | kfree(intel_sdvo_connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1976 | } |
| 1977 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1978 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
| 1979 | { |
| 1980 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
| 1981 | struct edid *edid; |
| 1982 | bool has_audio = false; |
| 1983 | |
| 1984 | if (!intel_sdvo->is_hdmi) |
| 1985 | return false; |
| 1986 | |
| 1987 | edid = intel_sdvo_get_edid(connector); |
| 1988 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) |
| 1989 | has_audio = drm_detect_monitor_audio(edid); |
Jani Nikula | 38ab8a2 | 2012-08-15 12:32:36 +0300 | [diff] [blame] | 1990 | kfree(edid); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1991 | |
| 1992 | return has_audio; |
| 1993 | } |
| 1994 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1995 | static int |
| 1996 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1997 | struct drm_property *property, |
| 1998 | uint64_t val) |
| 1999 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2000 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2001 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2002 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2003 | uint16_t temp_value; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2004 | uint8_t cmd; |
| 2005 | int ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2006 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2007 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2008 | if (ret) |
| 2009 | return ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2010 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2011 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2012 | int i = val; |
| 2013 | bool has_audio; |
| 2014 | |
| 2015 | if (i == intel_sdvo_connector->force_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2016 | return 0; |
| 2017 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2018 | intel_sdvo_connector->force_audio = i; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2019 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2020 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2021 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
| 2022 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2023 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2024 | |
| 2025 | if (has_audio == intel_sdvo->has_hdmi_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2026 | return 0; |
| 2027 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2028 | intel_sdvo->has_hdmi_audio = has_audio; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2029 | goto done; |
| 2030 | } |
| 2031 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2032 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 2033 | bool old_auto = intel_sdvo->color_range_auto; |
| 2034 | uint32_t old_range = intel_sdvo->color_range; |
| 2035 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2036 | switch (val) { |
| 2037 | case INTEL_BROADCAST_RGB_AUTO: |
| 2038 | intel_sdvo->color_range_auto = true; |
| 2039 | break; |
| 2040 | case INTEL_BROADCAST_RGB_FULL: |
| 2041 | intel_sdvo->color_range_auto = false; |
| 2042 | intel_sdvo->color_range = 0; |
| 2043 | break; |
| 2044 | case INTEL_BROADCAST_RGB_LIMITED: |
| 2045 | intel_sdvo->color_range_auto = false; |
Paulo Zanoni | 4f3a8bc | 2013-02-19 16:21:47 -0300 | [diff] [blame] | 2046 | /* FIXME: this bit is only valid when using TMDS |
| 2047 | * encoding and 8 bit per color mode. */ |
| 2048 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2049 | break; |
| 2050 | default: |
| 2051 | return -EINVAL; |
| 2052 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 2053 | |
| 2054 | if (old_auto == intel_sdvo->color_range_auto && |
| 2055 | old_range == intel_sdvo->color_range) |
| 2056 | return 0; |
| 2057 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2058 | goto done; |
| 2059 | } |
| 2060 | |
Ville Syrjälä | 7949dd4 | 2015-09-25 16:39:30 +0300 | [diff] [blame] | 2061 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
| 2062 | switch (val) { |
| 2063 | case DRM_MODE_PICTURE_ASPECT_NONE: |
| 2064 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
| 2065 | break; |
| 2066 | case DRM_MODE_PICTURE_ASPECT_4_3: |
| 2067 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; |
| 2068 | break; |
| 2069 | case DRM_MODE_PICTURE_ASPECT_16_9: |
| 2070 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; |
| 2071 | break; |
| 2072 | default: |
| 2073 | return -EINVAL; |
| 2074 | } |
| 2075 | goto done; |
| 2076 | } |
| 2077 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2078 | #define CHECK_PROPERTY(name, NAME) \ |
| 2079 | if (intel_sdvo_connector->name == property) { \ |
| 2080 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
| 2081 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
| 2082 | cmd = SDVO_CMD_SET_##NAME; \ |
| 2083 | intel_sdvo_connector->cur_##name = temp_value; \ |
| 2084 | goto set_value; \ |
| 2085 | } |
| 2086 | |
| 2087 | if (property == intel_sdvo_connector->tv_format) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2088 | if (val >= TV_FORMAT_NUM) |
| 2089 | return -EINVAL; |
| 2090 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2091 | if (intel_sdvo->tv_format_index == |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2092 | intel_sdvo_connector->tv_format_supported[val]) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2093 | return 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2094 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2095 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2096 | goto done; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2097 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2098 | temp_value = val; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2099 | if (intel_sdvo_connector->left == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2100 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2101 | intel_sdvo_connector->right, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2102 | if (intel_sdvo_connector->left_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2103 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2104 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2105 | intel_sdvo_connector->left_margin = temp_value; |
| 2106 | intel_sdvo_connector->right_margin = temp_value; |
| 2107 | temp_value = intel_sdvo_connector->max_hscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2108 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2109 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2110 | goto set_value; |
| 2111 | } else if (intel_sdvo_connector->right == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2112 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2113 | intel_sdvo_connector->left, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2114 | if (intel_sdvo_connector->right_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2115 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2116 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2117 | intel_sdvo_connector->left_margin = temp_value; |
| 2118 | intel_sdvo_connector->right_margin = temp_value; |
| 2119 | temp_value = intel_sdvo_connector->max_hscan - |
| 2120 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2121 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2122 | goto set_value; |
| 2123 | } else if (intel_sdvo_connector->top == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2124 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2125 | intel_sdvo_connector->bottom, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2126 | if (intel_sdvo_connector->top_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2127 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2128 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2129 | intel_sdvo_connector->top_margin = temp_value; |
| 2130 | intel_sdvo_connector->bottom_margin = temp_value; |
| 2131 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2132 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2133 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2134 | goto set_value; |
| 2135 | } else if (intel_sdvo_connector->bottom == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2136 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2137 | intel_sdvo_connector->top, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2138 | if (intel_sdvo_connector->bottom_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2139 | return 0; |
| 2140 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2141 | intel_sdvo_connector->top_margin = temp_value; |
| 2142 | intel_sdvo_connector->bottom_margin = temp_value; |
| 2143 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2144 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2145 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2146 | goto set_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2147 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2148 | CHECK_PROPERTY(hpos, HPOS) |
| 2149 | CHECK_PROPERTY(vpos, VPOS) |
| 2150 | CHECK_PROPERTY(saturation, SATURATION) |
| 2151 | CHECK_PROPERTY(contrast, CONTRAST) |
| 2152 | CHECK_PROPERTY(hue, HUE) |
| 2153 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
| 2154 | CHECK_PROPERTY(sharpness, SHARPNESS) |
| 2155 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
| 2156 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
| 2157 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
| 2158 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
| 2159 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2160 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2161 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2162 | |
| 2163 | return -EINVAL; /* unknown property */ |
| 2164 | |
| 2165 | set_value: |
| 2166 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
| 2167 | return -EIO; |
| 2168 | |
| 2169 | |
| 2170 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 2171 | if (intel_sdvo->base.base.crtc) |
| 2172 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2173 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2174 | return 0; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2175 | #undef CHECK_PROPERTY |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2176 | } |
| 2177 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2178 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 2179 | .dpms = drm_atomic_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2180 | .detect = intel_sdvo_detect, |
| 2181 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2182 | .set_property = intel_sdvo_set_property, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 2183 | .atomic_get_property = intel_connector_atomic_get_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2184 | .destroy = intel_sdvo_destroy, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 2185 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 2186 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2187 | }; |
| 2188 | |
| 2189 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 2190 | .get_modes = intel_sdvo_get_modes, |
| 2191 | .mode_valid = intel_sdvo_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2192 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2193 | }; |
| 2194 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 2195 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2196 | { |
Daniel Vetter | 8aca63a | 2013-07-21 21:37:01 +0200 | [diff] [blame] | 2197 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2198 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2199 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2200 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2201 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2202 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2203 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2204 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2205 | } |
| 2206 | |
| 2207 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 2208 | .destroy = intel_sdvo_enc_destroy, |
| 2209 | }; |
| 2210 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 2211 | static void |
| 2212 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 2213 | { |
| 2214 | uint16_t mask = 0; |
| 2215 | unsigned int num_bits; |
| 2216 | |
| 2217 | /* Make a mask of outputs less than or equal to our own priority in the |
| 2218 | * list. |
| 2219 | */ |
| 2220 | switch (sdvo->controlled_output) { |
| 2221 | case SDVO_OUTPUT_LVDS1: |
| 2222 | mask |= SDVO_OUTPUT_LVDS1; |
| 2223 | case SDVO_OUTPUT_LVDS0: |
| 2224 | mask |= SDVO_OUTPUT_LVDS0; |
| 2225 | case SDVO_OUTPUT_TMDS1: |
| 2226 | mask |= SDVO_OUTPUT_TMDS1; |
| 2227 | case SDVO_OUTPUT_TMDS0: |
| 2228 | mask |= SDVO_OUTPUT_TMDS0; |
| 2229 | case SDVO_OUTPUT_RGB1: |
| 2230 | mask |= SDVO_OUTPUT_RGB1; |
| 2231 | case SDVO_OUTPUT_RGB0: |
| 2232 | mask |= SDVO_OUTPUT_RGB0; |
| 2233 | break; |
| 2234 | } |
| 2235 | |
| 2236 | /* Count bits to find what number we are in the priority list. */ |
| 2237 | mask &= sdvo->caps.output_flags; |
| 2238 | num_bits = hweight16(mask); |
| 2239 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 2240 | if (num_bits > 3) |
| 2241 | num_bits = 3; |
| 2242 | |
| 2243 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 2244 | sdvo->ddc_bus = 1 << num_bits; |
| 2245 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2246 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2247 | /** |
| 2248 | * Choose the appropriate DDC bus for control bus switch command for this |
| 2249 | * SDVO output based on the controlled output. |
| 2250 | * |
| 2251 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 2252 | * outputs, then LVDS outputs. |
| 2253 | */ |
| 2254 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2255 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 8bd864b | 2015-09-18 20:03:14 +0300 | [diff] [blame] | 2256 | struct intel_sdvo *sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2257 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2258 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2259 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2260 | if (sdvo->port == PORT_B) |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2261 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 2262 | else |
| 2263 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2264 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 2265 | if (mapping->initialized) |
| 2266 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 2267 | else |
| 2268 | intel_sdvo_guess_ddc_bus(sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2269 | } |
| 2270 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2271 | static void |
| 2272 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 8bd864b | 2015-09-18 20:03:14 +0300 | [diff] [blame] | 2273 | struct intel_sdvo *sdvo) |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2274 | { |
| 2275 | struct sdvo_device_mapping *mapping; |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 2276 | u8 pin; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2277 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2278 | if (sdvo->port == PORT_B) |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2279 | mapping = &dev_priv->sdvo_mappings[0]; |
| 2280 | else |
| 2281 | mapping = &dev_priv->sdvo_mappings[1]; |
| 2282 | |
Jani Nikula | 88ac793 | 2015-03-27 00:20:22 +0200 | [diff] [blame] | 2283 | if (mapping->initialized && |
| 2284 | intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2285 | pin = mapping->i2c_pin; |
Jani Nikula | 6cb1612 | 2012-10-22 16:12:17 +0300 | [diff] [blame] | 2286 | else |
Jani Nikula | 988c701 | 2015-03-27 00:20:19 +0200 | [diff] [blame] | 2287 | pin = GMBUS_PIN_DPB; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2288 | |
Jani Nikula | 6cb1612 | 2012-10-22 16:12:17 +0300 | [diff] [blame] | 2289 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
| 2290 | |
| 2291 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow |
| 2292 | * our code totally fails once we start using gmbus. Hence fall back to |
| 2293 | * bit banging for now. */ |
| 2294 | intel_gmbus_force_bit(sdvo->i2c, true); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2295 | } |
| 2296 | |
Jani Nikula | fbfcc4f | 2012-10-22 16:12:18 +0300 | [diff] [blame] | 2297 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
| 2298 | static void |
| 2299 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) |
| 2300 | { |
| 2301 | intel_gmbus_force_bit(sdvo->i2c, false); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2302 | } |
| 2303 | |
| 2304 | static bool |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2305 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2306 | { |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 2307 | return intel_sdvo_check_supp_encode(intel_sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2308 | } |
| 2309 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2310 | static u8 |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2311 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2312 | { |
| 2313 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2314 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2315 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2316 | if (sdvo->port == PORT_B) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2317 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 2318 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 2319 | } else { |
| 2320 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 2321 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 2322 | } |
| 2323 | |
| 2324 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2325 | if (my_mapping->slave_addr) |
| 2326 | return my_mapping->slave_addr; |
| 2327 | |
| 2328 | /* If the BIOS only described a different SDVO device, use the |
| 2329 | * address that it isn't using. |
| 2330 | */ |
| 2331 | if (other_mapping->slave_addr) { |
| 2332 | if (other_mapping->slave_addr == 0x70) |
| 2333 | return 0x72; |
| 2334 | else |
| 2335 | return 0x70; |
| 2336 | } |
| 2337 | |
| 2338 | /* No SDVO device info is found for another DVO port, |
| 2339 | * so use mapping assumption we had before BIOS parsing. |
| 2340 | */ |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2341 | if (sdvo->port == PORT_B) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2342 | return 0x70; |
| 2343 | else |
| 2344 | return 0x72; |
| 2345 | } |
| 2346 | |
Imre Deak | 931c1c2 | 2014-02-11 17:12:51 +0200 | [diff] [blame] | 2347 | static void |
| 2348 | intel_sdvo_connector_unregister(struct intel_connector *intel_connector) |
| 2349 | { |
| 2350 | struct drm_connector *drm_connector; |
| 2351 | struct intel_sdvo *sdvo_encoder; |
| 2352 | |
| 2353 | drm_connector = &intel_connector->base; |
| 2354 | sdvo_encoder = intel_attached_sdvo(&intel_connector->base); |
| 2355 | |
| 2356 | sysfs_remove_link(&drm_connector->kdev->kobj, |
| 2357 | sdvo_encoder->ddc.dev.kobj.name); |
| 2358 | intel_connector_unregister(intel_connector); |
| 2359 | } |
| 2360 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2361 | static int |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2362 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 2363 | struct intel_sdvo *encoder) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2364 | { |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2365 | struct drm_connector *drm_connector; |
| 2366 | int ret; |
| 2367 | |
| 2368 | drm_connector = &connector->base.base; |
| 2369 | ret = drm_connector_init(encoder->base.base.dev, |
| 2370 | drm_connector, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2371 | &intel_sdvo_connector_funcs, |
| 2372 | connector->base.base.connector_type); |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2373 | if (ret < 0) |
| 2374 | return ret; |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2375 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2376 | drm_connector_helper_add(drm_connector, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2377 | &intel_sdvo_connector_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2378 | |
Peter Ross | 8f4839e | 2012-01-28 14:49:25 +0100 | [diff] [blame] | 2379 | connector->base.base.interlace_allowed = 1; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2380 | connector->base.base.doublescan_allowed = 0; |
| 2381 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 2382 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
Imre Deak | 931c1c2 | 2014-02-11 17:12:51 +0200 | [diff] [blame] | 2383 | connector->base.unregister = intel_sdvo_connector_unregister; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2384 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2385 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 2386 | ret = drm_connector_register(drm_connector); |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2387 | if (ret < 0) |
| 2388 | goto err1; |
| 2389 | |
Egbert Eich | 4d43e9b | 2014-04-11 19:07:44 +0200 | [diff] [blame] | 2390 | ret = sysfs_create_link(&drm_connector->kdev->kobj, |
| 2391 | &encoder->ddc.dev.kobj, |
Imre Deak | 931c1c2 | 2014-02-11 17:12:51 +0200 | [diff] [blame] | 2392 | encoder->ddc.dev.kobj.name); |
| 2393 | if (ret < 0) |
| 2394 | goto err2; |
| 2395 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2396 | return 0; |
| 2397 | |
Imre Deak | 931c1c2 | 2014-02-11 17:12:51 +0200 | [diff] [blame] | 2398 | err2: |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 2399 | drm_connector_unregister(drm_connector); |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2400 | err1: |
| 2401 | drm_connector_cleanup(drm_connector); |
| 2402 | |
| 2403 | return ret; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2404 | } |
| 2405 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2406 | static void |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2407 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
| 2408 | struct intel_sdvo_connector *connector) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2409 | { |
| 2410 | struct drm_device *dev = connector->base.base.dev; |
| 2411 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2412 | intel_attach_force_audio_property(&connector->base.base); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2413 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2414 | intel_attach_broadcast_rgb_property(&connector->base.base); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2415 | intel_sdvo->color_range_auto = true; |
| 2416 | } |
Ville Syrjälä | 7949dd4 | 2015-09-25 16:39:30 +0300 | [diff] [blame] | 2417 | intel_attach_aspect_ratio_property(&connector->base.base); |
| 2418 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2419 | } |
| 2420 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 2421 | static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) |
| 2422 | { |
| 2423 | struct intel_sdvo_connector *sdvo_connector; |
| 2424 | |
| 2425 | sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); |
| 2426 | if (!sdvo_connector) |
| 2427 | return NULL; |
| 2428 | |
| 2429 | if (intel_connector_init(&sdvo_connector->base) < 0) { |
| 2430 | kfree(sdvo_connector); |
| 2431 | return NULL; |
| 2432 | } |
| 2433 | |
| 2434 | return sdvo_connector; |
| 2435 | } |
| 2436 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2437 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2438 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2439 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2440 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2441 | struct drm_connector *connector; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2442 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2443 | struct intel_connector *intel_connector; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2444 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2445 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 2446 | DRM_DEBUG_KMS("initialising DVI device %d\n", device); |
| 2447 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 2448 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2449 | if (!intel_sdvo_connector) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2450 | return false; |
| 2451 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2452 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2453 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2454 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2455 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2456 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2457 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2458 | } |
| 2459 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2460 | intel_connector = &intel_sdvo_connector->base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2461 | connector = &intel_connector->base; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2462 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
| 2463 | intel_sdvo_connector->output_flag) { |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2464 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2465 | /* Some SDVO devices have one-shot hotplug interrupts. |
| 2466 | * Ensure that they get re-enabled when an interrupt happens. |
| 2467 | */ |
| 2468 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; |
Daniel Vetter | 3a2fb2c | 2015-10-08 21:51:57 +0200 | [diff] [blame] | 2469 | intel_sdvo_enable_hotplug(intel_encoder); |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2470 | } else { |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 2471 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2472 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2473 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2474 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2475 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2476 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2477 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2478 | intel_sdvo->is_hdmi = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2479 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2480 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2481 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2482 | kfree(intel_sdvo_connector); |
| 2483 | return false; |
| 2484 | } |
| 2485 | |
Chris Wilson | f797d22 | 2010-12-23 09:43:48 +0000 | [diff] [blame] | 2486 | if (intel_sdvo->is_hdmi) |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2487 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2488 | |
| 2489 | return true; |
| 2490 | } |
| 2491 | |
| 2492 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2493 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2494 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2495 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2496 | struct drm_connector *connector; |
| 2497 | struct intel_connector *intel_connector; |
| 2498 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2499 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 2500 | DRM_DEBUG_KMS("initialising TV type %d\n", type); |
| 2501 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 2502 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2503 | if (!intel_sdvo_connector) |
| 2504 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2505 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2506 | intel_connector = &intel_sdvo_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2507 | connector = &intel_connector->base; |
| 2508 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2509 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2510 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2511 | intel_sdvo->controlled_output |= type; |
| 2512 | intel_sdvo_connector->output_flag = type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2513 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2514 | intel_sdvo->is_tv = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2515 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2516 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2517 | kfree(intel_sdvo_connector); |
| 2518 | return false; |
| 2519 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2520 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2521 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2522 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2523 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2524 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2525 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2526 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2527 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2528 | |
| 2529 | err: |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 2530 | drm_connector_unregister(connector); |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2531 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2532 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2533 | } |
| 2534 | |
| 2535 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2536 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2537 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2538 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2539 | struct drm_connector *connector; |
| 2540 | struct intel_connector *intel_connector; |
| 2541 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2542 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 2543 | DRM_DEBUG_KMS("initialising analog device %d\n", device); |
| 2544 | |
Ander Conselvan de Oliveira | 8ce7da4 | 2015-06-08 11:26:30 +0300 | [diff] [blame] | 2545 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2546 | if (!intel_sdvo_connector) |
| 2547 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2548 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2549 | intel_connector = &intel_sdvo_connector->base; |
| 2550 | connector = &intel_connector->base; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 2551 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2552 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2553 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2554 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2555 | if (device == 0) { |
| 2556 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2557 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2558 | } else if (device == 1) { |
| 2559 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2560 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2561 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2562 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2563 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2564 | kfree(intel_sdvo_connector); |
| 2565 | return false; |
| 2566 | } |
| 2567 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2568 | return true; |
| 2569 | } |
| 2570 | |
| 2571 | static bool |
| 2572 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2573 | { |
| 2574 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2575 | struct drm_connector *connector; |
| 2576 | struct intel_connector *intel_connector; |
| 2577 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2578 | |
Chris Wilson | 46a3f4a | 2013-09-24 12:55:40 +0100 | [diff] [blame] | 2579 | DRM_DEBUG_KMS("initialising LVDS device %d\n", device); |
| 2580 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 2581 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2582 | if (!intel_sdvo_connector) |
| 2583 | return false; |
| 2584 | |
| 2585 | intel_connector = &intel_sdvo_connector->base; |
| 2586 | connector = &intel_connector->base; |
| 2587 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2588 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2589 | |
| 2590 | if (device == 0) { |
| 2591 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2592 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2593 | } else if (device == 1) { |
| 2594 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2595 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2596 | } |
| 2597 | |
Imre Deak | c393454 | 2014-02-11 17:12:50 +0200 | [diff] [blame] | 2598 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2599 | kfree(intel_sdvo_connector); |
| 2600 | return false; |
| 2601 | } |
| 2602 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2603 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2604 | goto err; |
| 2605 | |
| 2606 | return true; |
| 2607 | |
| 2608 | err: |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 2609 | drm_connector_unregister(connector); |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2610 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2611 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2612 | } |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2613 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2614 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2615 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2616 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2617 | intel_sdvo->is_tv = false; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2618 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2619 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2620 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2621 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2622 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2623 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2624 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2625 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2626 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2627 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2628 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2629 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2630 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2631 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2632 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2633 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2634 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2635 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2636 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2637 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2638 | |
Chris Wilson | a0b1c7a | 2011-09-30 22:56:41 +0100 | [diff] [blame] | 2639 | if (flags & SDVO_OUTPUT_YPRPB0) |
| 2640 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) |
| 2641 | return false; |
| 2642 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2643 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2644 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2645 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2646 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2647 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2648 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2649 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2650 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2651 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2652 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2653 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2654 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2655 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2656 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2657 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2658 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2659 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2660 | unsigned char bytes[2]; |
| 2661 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2662 | intel_sdvo->controlled_output = 0; |
| 2663 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2664 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2665 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2666 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2667 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2668 | } |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2669 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2670 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2671 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2672 | } |
| 2673 | |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2674 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
| 2675 | { |
| 2676 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 2677 | struct drm_connector *connector, *tmp; |
| 2678 | |
| 2679 | list_for_each_entry_safe(connector, tmp, |
| 2680 | &dev->mode_config.connector_list, head) { |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 2681 | if (intel_attached_encoder(connector) == &intel_sdvo->base) { |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 2682 | drm_connector_unregister(connector); |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2683 | intel_sdvo_destroy(connector); |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 2684 | } |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2685 | } |
| 2686 | } |
| 2687 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2688 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 2689 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2690 | int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2691 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2692 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2693 | struct intel_sdvo_tv_format format; |
| 2694 | uint32_t format_map, i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2695 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2696 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 2697 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2698 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 2699 | BUILD_BUG_ON(sizeof(format) != 6); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2700 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2701 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
| 2702 | &format, sizeof(format))) |
| 2703 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2704 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2705 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2706 | |
| 2707 | if (format_map == 0) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2708 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2709 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2710 | intel_sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2711 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2712 | if (format_map & (1 << i)) |
| 2713 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2714 | |
| 2715 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2716 | intel_sdvo_connector->tv_format = |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2717 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
| 2718 | "mode", intel_sdvo_connector->format_supported_num); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2719 | if (!intel_sdvo_connector->tv_format) |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2720 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2721 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2722 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2723 | drm_property_add_enum( |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2724 | intel_sdvo_connector->tv_format, i, |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2725 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2726 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2727 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2728 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2729 | intel_sdvo_connector->tv_format, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2730 | return true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2731 | |
| 2732 | } |
| 2733 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2734 | #define ENHANCEMENT(name, NAME) do { \ |
| 2735 | if (enhancements.name) { \ |
| 2736 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 2737 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 2738 | return false; \ |
| 2739 | intel_sdvo_connector->max_##name = data_value[0]; \ |
| 2740 | intel_sdvo_connector->cur_##name = response; \ |
| 2741 | intel_sdvo_connector->name = \ |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2742 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2743 | if (!intel_sdvo_connector->name) return false; \ |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2744 | drm_object_attach_property(&connector->base, \ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2745 | intel_sdvo_connector->name, \ |
| 2746 | intel_sdvo_connector->cur_##name); \ |
| 2747 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
| 2748 | data_value[0], data_value[1], response); \ |
| 2749 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2750 | } while (0) |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2751 | |
| 2752 | static bool |
| 2753 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 2754 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2755 | struct intel_sdvo_enhancements_reply enhancements) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2756 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2757 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2758 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2759 | uint16_t response, data_value[2]; |
| 2760 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2761 | /* when horizontal overscan is supported, Add the left/right property */ |
| 2762 | if (enhancements.overscan_h) { |
| 2763 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2764 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
| 2765 | &data_value, 4)) |
| 2766 | return false; |
| 2767 | |
| 2768 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2769 | SDVO_CMD_GET_OVERSCAN_H, |
| 2770 | &response, 2)) |
| 2771 | return false; |
| 2772 | |
| 2773 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2774 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2775 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2776 | intel_sdvo_connector->left = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2777 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2778 | if (!intel_sdvo_connector->left) |
| 2779 | return false; |
| 2780 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2781 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2782 | intel_sdvo_connector->left, |
| 2783 | intel_sdvo_connector->left_margin); |
| 2784 | |
| 2785 | intel_sdvo_connector->right = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2786 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2787 | if (!intel_sdvo_connector->right) |
| 2788 | return false; |
| 2789 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2790 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2791 | intel_sdvo_connector->right, |
| 2792 | intel_sdvo_connector->right_margin); |
| 2793 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2794 | "default %d, current %d\n", |
| 2795 | data_value[0], data_value[1], response); |
| 2796 | } |
| 2797 | |
| 2798 | if (enhancements.overscan_v) { |
| 2799 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2800 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
| 2801 | &data_value, 4)) |
| 2802 | return false; |
| 2803 | |
| 2804 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2805 | SDVO_CMD_GET_OVERSCAN_V, |
| 2806 | &response, 2)) |
| 2807 | return false; |
| 2808 | |
| 2809 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2810 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2811 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2812 | intel_sdvo_connector->top = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2813 | drm_property_create_range(dev, 0, |
| 2814 | "top_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2815 | if (!intel_sdvo_connector->top) |
| 2816 | return false; |
| 2817 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2818 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2819 | intel_sdvo_connector->top, |
| 2820 | intel_sdvo_connector->top_margin); |
| 2821 | |
| 2822 | intel_sdvo_connector->bottom = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2823 | drm_property_create_range(dev, 0, |
| 2824 | "bottom_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2825 | if (!intel_sdvo_connector->bottom) |
| 2826 | return false; |
| 2827 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2828 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2829 | intel_sdvo_connector->bottom, |
| 2830 | intel_sdvo_connector->bottom_margin); |
| 2831 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2832 | "default %d, current %d\n", |
| 2833 | data_value[0], data_value[1], response); |
| 2834 | } |
| 2835 | |
| 2836 | ENHANCEMENT(hpos, HPOS); |
| 2837 | ENHANCEMENT(vpos, VPOS); |
| 2838 | ENHANCEMENT(saturation, SATURATION); |
| 2839 | ENHANCEMENT(contrast, CONTRAST); |
| 2840 | ENHANCEMENT(hue, HUE); |
| 2841 | ENHANCEMENT(sharpness, SHARPNESS); |
| 2842 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2843 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
| 2844 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 2845 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
| 2846 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
| 2847 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
| 2848 | |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2849 | if (enhancements.dot_crawl) { |
| 2850 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
| 2851 | return false; |
| 2852 | |
| 2853 | intel_sdvo_connector->max_dot_crawl = 1; |
| 2854 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
| 2855 | intel_sdvo_connector->dot_crawl = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2856 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2857 | if (!intel_sdvo_connector->dot_crawl) |
| 2858 | return false; |
| 2859 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2860 | drm_object_attach_property(&connector->base, |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2861 | intel_sdvo_connector->dot_crawl, |
| 2862 | intel_sdvo_connector->cur_dot_crawl); |
| 2863 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
| 2864 | } |
| 2865 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2866 | return true; |
| 2867 | } |
| 2868 | |
| 2869 | static bool |
| 2870 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 2871 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2872 | struct intel_sdvo_enhancements_reply enhancements) |
| 2873 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2874 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2875 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 2876 | uint16_t response, data_value[2]; |
| 2877 | |
| 2878 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2879 | |
| 2880 | return true; |
| 2881 | } |
| 2882 | #undef ENHANCEMENT |
| 2883 | |
| 2884 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 2885 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 2886 | { |
| 2887 | union { |
| 2888 | struct intel_sdvo_enhancements_reply reply; |
| 2889 | uint16_t response; |
| 2890 | } enhancements; |
| 2891 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 2892 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
| 2893 | |
Chris Wilson | cf9a2f3 | 2010-09-23 16:17:33 +0100 | [diff] [blame] | 2894 | enhancements.response = 0; |
| 2895 | intel_sdvo_get_value(intel_sdvo, |
| 2896 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
| 2897 | &enhancements, sizeof(enhancements)); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2898 | if (enhancements.response == 0) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2899 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2900 | return true; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2901 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2902 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2903 | if (IS_TV(intel_sdvo_connector)) |
| 2904 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2905 | else if (IS_LVDS(intel_sdvo_connector)) |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2906 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2907 | else |
| 2908 | return true; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2909 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2910 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2911 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
| 2912 | struct i2c_msg *msgs, |
| 2913 | int num) |
| 2914 | { |
| 2915 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2916 | |
| 2917 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
| 2918 | return -EIO; |
| 2919 | |
| 2920 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
| 2921 | } |
| 2922 | |
| 2923 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
| 2924 | { |
| 2925 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2926 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
| 2927 | } |
| 2928 | |
| 2929 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
| 2930 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
| 2931 | .functionality = intel_sdvo_ddc_proxy_func |
| 2932 | }; |
| 2933 | |
| 2934 | static bool |
| 2935 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
| 2936 | struct drm_device *dev) |
| 2937 | { |
| 2938 | sdvo->ddc.owner = THIS_MODULE; |
| 2939 | sdvo->ddc.class = I2C_CLASS_DDC; |
| 2940 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); |
| 2941 | sdvo->ddc.dev.parent = &dev->pdev->dev; |
| 2942 | sdvo->ddc.algo_data = sdvo; |
| 2943 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
| 2944 | |
| 2945 | return i2c_add_adapter(&sdvo->ddc) == 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2946 | } |
| 2947 | |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2948 | static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, |
| 2949 | enum port port) |
| 2950 | { |
| 2951 | if (HAS_PCH_SPLIT(dev_priv)) |
| 2952 | WARN_ON(port != PORT_B); |
| 2953 | else |
| 2954 | WARN_ON(port != PORT_B && port != PORT_C); |
| 2955 | } |
| 2956 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2957 | bool intel_sdvo_init(struct drm_device *dev, |
| 2958 | i915_reg_t sdvo_reg, enum port port) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2959 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2961 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2962 | struct intel_sdvo *intel_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2963 | int i; |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2964 | |
| 2965 | assert_sdvo_port_valid(dev_priv, port); |
| 2966 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 2967 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2968 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2969 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2970 | |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2971 | intel_sdvo->sdvo_reg = sdvo_reg; |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 2972 | intel_sdvo->port = port; |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2973 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; |
Ville Syrjälä | 8bd864b | 2015-09-18 20:03:14 +0300 | [diff] [blame] | 2974 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); |
Jani Nikula | fbfcc4f | 2012-10-22 16:12:18 +0300 | [diff] [blame] | 2975 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
| 2976 | goto err_i2c_bus; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2977 | |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2978 | /* encoder type will be decided later */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2979 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2980 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2981 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2982 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2983 | /* Read the regs to test if we can talk to the device */ |
| 2984 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2985 | u8 byte; |
| 2986 | |
| 2987 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2988 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
| 2989 | SDVO_NAME(intel_sdvo)); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2990 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2991 | } |
| 2992 | } |
| 2993 | |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 2994 | intel_encoder->compute_config = intel_sdvo_compute_config; |
Ville Syrjälä | 3c65d1d | 2015-05-05 17:17:36 +0300 | [diff] [blame] | 2995 | if (HAS_PCH_SPLIT(dev)) { |
| 2996 | intel_encoder->disable = pch_disable_sdvo; |
| 2997 | intel_encoder->post_disable = pch_post_disable_sdvo; |
| 2998 | } else { |
| 2999 | intel_encoder->disable = intel_disable_sdvo; |
| 3000 | } |
Daniel Vetter | 192d47a | 2014-04-24 23:54:45 +0200 | [diff] [blame] | 3001 | intel_encoder->pre_enable = intel_sdvo_pre_enable; |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 3002 | intel_encoder->enable = intel_enable_sdvo; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 3003 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 3004 | intel_encoder->get_config = intel_sdvo_get_config; |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 3005 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 3006 | /* In default case sdvo lvds is false */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 3007 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 3008 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3009 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3010 | if (intel_sdvo_output_setup(intel_sdvo, |
| 3011 | intel_sdvo->caps.output_flags) != true) { |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 3012 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
| 3013 | SDVO_NAME(intel_sdvo)); |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 3014 | /* Output_setup can leave behind connectors! */ |
| 3015 | goto err_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3016 | } |
| 3017 | |
Chris Wilson | 7ba220c | 2013-06-09 16:02:04 +0100 | [diff] [blame] | 3018 | /* Only enable the hotplug irq if we need it, to work around noisy |
| 3019 | * hotplug lines. |
| 3020 | */ |
| 3021 | if (intel_sdvo->hotplug_active) { |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 3022 | if (intel_sdvo->port == PORT_B) |
| 3023 | intel_encoder->hpd_pin = HPD_SDVO_B; |
| 3024 | else |
| 3025 | intel_encoder->hpd_pin = HPD_SDVO_C; |
Chris Wilson | 7ba220c | 2013-06-09 16:02:04 +0100 | [diff] [blame] | 3026 | } |
| 3027 | |
Daniel Vetter | e506d6f | 2012-11-13 17:24:43 +0100 | [diff] [blame] | 3028 | /* |
| 3029 | * Cloning SDVO with anything is often impossible, since the SDVO |
| 3030 | * encoder can request a special input timing mode. And even if that's |
| 3031 | * not the case we have evidence that cloning a plain unscaled mode with |
| 3032 | * VGA doesn't really work. Furthermore the cloning flags are way too |
| 3033 | * simplistic anyway to express such constraints, so just give up on |
| 3034 | * cloning for SDVO encoders. |
| 3035 | */ |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 3036 | intel_sdvo->base.cloneable = 0; |
Daniel Vetter | e506d6f | 2012-11-13 17:24:43 +0100 | [diff] [blame] | 3037 | |
Ville Syrjälä | 8bd864b | 2015-09-18 20:03:14 +0300 | [diff] [blame] | 3038 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 3039 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3040 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 3041 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 3042 | goto err_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3043 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 3044 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 3045 | &intel_sdvo->pixel_clock_min, |
| 3046 | &intel_sdvo->pixel_clock_max)) |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 3047 | goto err_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3048 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 3049 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 3050 | "clock range %dMHz - %dMHz, " |
| 3051 | "input 1: %c, input 2: %c, " |
| 3052 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3053 | SDVO_NAME(intel_sdvo), |
| 3054 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 3055 | intel_sdvo->caps.device_rev_id, |
| 3056 | intel_sdvo->pixel_clock_min / 1000, |
| 3057 | intel_sdvo->pixel_clock_max / 1000, |
| 3058 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 3059 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 3060 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3061 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3062 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3063 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3064 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 3065 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3066 | |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 3067 | err_output: |
| 3068 | intel_sdvo_output_cleanup(intel_sdvo); |
| 3069 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 3070 | err: |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 3071 | drm_encoder_cleanup(&intel_encoder->base); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 3072 | i2c_del_adapter(&intel_sdvo->ddc); |
Jani Nikula | fbfcc4f | 2012-10-22 16:12:18 +0300 | [diff] [blame] | 3073 | err_i2c_bus: |
| 3074 | intel_sdvo_unselect_i2c_bus(intel_sdvo); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3075 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3076 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 3077 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3078 | } |