Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | STMMAC Ethernet Driver -- MDIO bus implementation |
| 3 | Provides Bus interface for MII registers |
| 4 | |
| 5 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify it |
| 8 | under the terms and conditions of the GNU General Public License, |
| 9 | version 2, as published by the Free Software Foundation. |
| 10 | |
| 11 | This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License along with |
| 17 | this program; if not, write to the Free Software Foundation, Inc., |
| 18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 19 | |
| 20 | The full GNU General Public License is included in this distribution in |
| 21 | the file called "COPYING". |
| 22 | |
| 23 | Author: Carl Shaw <carl.shaw@st.com> |
| 24 | Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 25 | *******************************************************************************/ |
| 26 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 27 | #include <linux/mii.h> |
| 28 | #include <linux/phy.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 30 | #include <linux/of.h> |
| 31 | #include <linux/of_gpio.h> |
| 32 | |
Alexey Dobriyan | b7f080c | 2011-06-16 11:01:34 +0000 | [diff] [blame] | 33 | #include <asm/io.h> |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 34 | |
| 35 | #include "stmmac.h" |
| 36 | |
| 37 | #define MII_BUSY 0x00000001 |
| 38 | #define MII_WRITE 0x00000002 |
| 39 | |
Deepak SIKRI | 39b401d | 2012-04-04 04:33:24 +0000 | [diff] [blame] | 40 | static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr) |
| 41 | { |
| 42 | unsigned long curr; |
| 43 | unsigned long finish = jiffies + 3 * HZ; |
| 44 | |
| 45 | do { |
| 46 | curr = jiffies; |
| 47 | if (readl(ioaddr + mii_addr) & MII_BUSY) |
| 48 | cpu_relax(); |
| 49 | else |
| 50 | return 0; |
| 51 | } while (!time_after_eq(curr, finish)); |
| 52 | |
| 53 | return -EBUSY; |
| 54 | } |
| 55 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 56 | /** |
| 57 | * stmmac_mdio_read |
| 58 | * @bus: points to the mii_bus structure |
| 59 | * @phyaddr: MII addr reg bits 15-11 |
| 60 | * @phyreg: MII addr reg bits 10-6 |
| 61 | * Description: it reads data from the MII register from within the phy device. |
| 62 | * For the 7111 GMAC, we must set the bit 0 in the MII address register while |
| 63 | * accessing the PHY registers. |
| 64 | * Fortunately, it seems this has no drawback for the 7109 MAC. |
| 65 | */ |
| 66 | static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) |
| 67 | { |
| 68 | struct net_device *ndev = bus->priv; |
| 69 | struct stmmac_priv *priv = netdev_priv(ndev); |
Giuseppe CAVALLARO | db98a0b | 2010-01-06 23:07:17 +0000 | [diff] [blame] | 70 | unsigned int mii_address = priv->hw->mii.addr; |
| 71 | unsigned int mii_data = priv->hw->mii.data; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 72 | |
| 73 | int data; |
| 74 | u16 regValue = (((phyaddr << 11) & (0x0000F800)) | |
| 75 | ((phyreg << 6) & (0x000007C0))); |
Giuseppe CAVALLARO | cd7201f | 2012-04-04 04:33:27 +0000 | [diff] [blame] | 76 | regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 77 | |
Deepak SIKRI | 39b401d | 2012-04-04 04:33:24 +0000 | [diff] [blame] | 78 | if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) |
| 79 | return -EBUSY; |
| 80 | |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 81 | writel(regValue, priv->ioaddr + mii_address); |
Deepak SIKRI | 39b401d | 2012-04-04 04:33:24 +0000 | [diff] [blame] | 82 | |
| 83 | if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) |
| 84 | return -EBUSY; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 85 | |
| 86 | /* Read the data from the MII data register */ |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 87 | data = (int)readl(priv->ioaddr + mii_data); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 88 | |
| 89 | return data; |
| 90 | } |
| 91 | |
| 92 | /** |
| 93 | * stmmac_mdio_write |
| 94 | * @bus: points to the mii_bus structure |
| 95 | * @phyaddr: MII addr reg bits 15-11 |
| 96 | * @phyreg: MII addr reg bits 10-6 |
| 97 | * @phydata: phy data |
| 98 | * Description: it writes the data into the MII register from within the device. |
| 99 | */ |
| 100 | static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, |
| 101 | u16 phydata) |
| 102 | { |
| 103 | struct net_device *ndev = bus->priv; |
| 104 | struct stmmac_priv *priv = netdev_priv(ndev); |
Giuseppe CAVALLARO | db98a0b | 2010-01-06 23:07:17 +0000 | [diff] [blame] | 105 | unsigned int mii_address = priv->hw->mii.addr; |
| 106 | unsigned int mii_data = priv->hw->mii.data; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 107 | |
| 108 | u16 value = |
| 109 | (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) |
| 110 | | MII_WRITE; |
| 111 | |
Giuseppe CAVALLARO | cd7201f | 2012-04-04 04:33:27 +0000 | [diff] [blame] | 112 | value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); |
Giuseppe CAVALLARO | dfb8fb9 | 2010-09-17 03:23:39 +0000 | [diff] [blame] | 113 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 114 | /* Wait until any existing MII operation is complete */ |
Deepak SIKRI | 39b401d | 2012-04-04 04:33:24 +0000 | [diff] [blame] | 115 | if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) |
| 116 | return -EBUSY; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 117 | |
| 118 | /* Set the MII address register to write */ |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 119 | writel(phydata, priv->ioaddr + mii_data); |
| 120 | writel(value, priv->ioaddr + mii_address); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 121 | |
| 122 | /* Wait until any existing MII operation is complete */ |
Deepak SIKRI | 39b401d | 2012-04-04 04:33:24 +0000 | [diff] [blame] | 123 | return stmmac_mdio_busy_wait(priv->ioaddr, mii_address); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | /** |
| 127 | * stmmac_mdio_reset |
| 128 | * @bus: points to the mii_bus structure |
| 129 | * Description: reset the MII bus |
| 130 | */ |
Srinivas Kandagatla | 073752a | 2014-01-16 10:52:27 +0000 | [diff] [blame] | 131 | int stmmac_mdio_reset(struct mii_bus *bus) |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 132 | { |
Giuseppe CAVALLARO | bfab27a | 2011-12-21 03:58:19 +0000 | [diff] [blame] | 133 | #if defined(CONFIG_STMMAC_PLATFORM) |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 134 | struct net_device *ndev = bus->priv; |
| 135 | struct stmmac_priv *priv = netdev_priv(ndev); |
Giuseppe CAVALLARO | db98a0b | 2010-01-06 23:07:17 +0000 | [diff] [blame] | 136 | unsigned int mii_address = priv->hw->mii.addr; |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 137 | struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 138 | |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 139 | #ifdef CONFIG_OF |
| 140 | if (priv->device->of_node) { |
| 141 | int reset_gpio, active_low; |
| 142 | |
| 143 | if (data->reset_gpio < 0) { |
| 144 | struct device_node *np = priv->device->of_node; |
| 145 | if (!np) |
| 146 | return 0; |
| 147 | |
| 148 | data->reset_gpio = of_get_named_gpio(np, |
| 149 | "snps,reset-gpio", 0); |
| 150 | if (data->reset_gpio < 0) |
| 151 | return 0; |
| 152 | |
| 153 | data->active_low = of_property_read_bool(np, |
| 154 | "snps,reset-active-low"); |
| 155 | of_property_read_u32_array(np, |
| 156 | "snps,reset-delays-us", data->delays, 3); |
| 157 | } |
| 158 | |
| 159 | reset_gpio = data->reset_gpio; |
| 160 | active_low = data->active_low; |
| 161 | |
| 162 | if (!gpio_request(reset_gpio, "mdio-reset")) { |
| 163 | gpio_direction_output(reset_gpio, active_low ? 1 : 0); |
Sjoerd Simons | 892aa01 | 2015-09-11 22:25:48 +0200 | [diff] [blame] | 164 | if (data->delays[0]) |
| 165 | msleep(DIV_ROUND_UP(data->delays[0], 1000)); |
| 166 | |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 167 | gpio_set_value(reset_gpio, active_low ? 0 : 1); |
Sjoerd Simons | 892aa01 | 2015-09-11 22:25:48 +0200 | [diff] [blame] | 168 | if (data->delays[1]) |
| 169 | msleep(DIV_ROUND_UP(data->delays[1], 1000)); |
| 170 | |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 171 | gpio_set_value(reset_gpio, active_low ? 1 : 0); |
Sjoerd Simons | 892aa01 | 2015-09-11 22:25:48 +0200 | [diff] [blame] | 172 | if (data->delays[2]) |
| 173 | msleep(DIV_ROUND_UP(data->delays[2], 1000)); |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 174 | } |
| 175 | } |
| 176 | #endif |
| 177 | |
| 178 | if (data->phy_reset) { |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 179 | pr_debug("stmmac_mdio_reset: calling phy_reset\n"); |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 180 | data->phy_reset(priv->plat->bsp_priv); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | /* This is a workaround for problems with the STE101P PHY. |
| 184 | * It doesn't complete its reset until at least one clock cycle |
| 185 | * on MDC, so perform a dummy mdio read. |
| 186 | */ |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 187 | writel(0, priv->ioaddr + mii_address); |
Giuseppe CAVALLARO | bfab27a | 2011-12-21 03:58:19 +0000 | [diff] [blame] | 188 | #endif |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | /** |
| 193 | * stmmac_mdio_register |
| 194 | * @ndev: net device structure |
| 195 | * Description: it registers the MII bus |
| 196 | */ |
| 197 | int stmmac_mdio_register(struct net_device *ndev) |
| 198 | { |
| 199 | int err = 0; |
| 200 | struct mii_bus *new_bus; |
| 201 | int *irqlist; |
| 202 | struct stmmac_priv *priv = netdev_priv(ndev); |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 203 | struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 204 | int addr, found; |
| 205 | |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 206 | if (!mdio_bus_data) |
| 207 | return 0; |
| 208 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 209 | new_bus = mdiobus_alloc(); |
| 210 | if (new_bus == NULL) |
| 211 | return -ENOMEM; |
| 212 | |
Dinh Nguyen | cc80ee1 | 2014-04-29 12:56:21 -0500 | [diff] [blame] | 213 | if (mdio_bus_data->irqs) { |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 214 | irqlist = mdio_bus_data->irqs; |
Dinh Nguyen | cc80ee1 | 2014-04-29 12:56:21 -0500 | [diff] [blame] | 215 | } else { |
| 216 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) |
| 217 | priv->mii_irq[addr] = PHY_POLL; |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 218 | irqlist = priv->mii_irq; |
Dinh Nguyen | cc80ee1 | 2014-04-29 12:56:21 -0500 | [diff] [blame] | 219 | } |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 220 | |
Srinivas Kandagatla | 0e07647 | 2013-07-04 10:35:48 +0100 | [diff] [blame] | 221 | #ifdef CONFIG_OF |
| 222 | if (priv->device->of_node) |
| 223 | mdio_bus_data->reset_gpio = -1; |
| 224 | #endif |
| 225 | |
Alessandro Rubini | 90b9a545 | 2012-01-23 23:26:48 +0000 | [diff] [blame] | 226 | new_bus->name = "stmmac"; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 227 | new_bus->read = &stmmac_mdio_read; |
| 228 | new_bus->write = &stmmac_mdio_write; |
| 229 | new_bus->reset = &stmmac_mdio_reset; |
Florian Fainelli | db8857b | 2012-01-09 23:59:20 +0000 | [diff] [blame] | 230 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 231 | new_bus->name, priv->plat->bus_id); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 232 | new_bus->priv = ndev; |
| 233 | new_bus->irq = irqlist; |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 234 | new_bus->phy_mask = mdio_bus_data->phy_mask; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 235 | new_bus->parent = priv->device; |
| 236 | err = mdiobus_register(new_bus); |
| 237 | if (err != 0) { |
| 238 | pr_err("%s: Cannot register as MDIO bus\n", new_bus->name); |
| 239 | goto bus_register_fail; |
| 240 | } |
| 241 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 242 | found = 0; |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 243 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 244 | struct phy_device *phydev = new_bus->phy_map[addr]; |
| 245 | if (phydev) { |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 246 | int act = 0; |
| 247 | char irq_num[4]; |
| 248 | char *irq_str; |
| 249 | |
| 250 | /* |
| 251 | * If an IRQ was provided to be assigned after |
| 252 | * the bus probe, do it here. |
| 253 | */ |
| 254 | if ((mdio_bus_data->irqs == NULL) && |
| 255 | (mdio_bus_data->probed_phy_irq > 0)) { |
| 256 | irqlist[addr] = mdio_bus_data->probed_phy_irq; |
| 257 | phydev->irq = mdio_bus_data->probed_phy_irq; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 258 | } |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 259 | |
| 260 | /* |
Pavel Machek | a77e4ac | 2014-08-25 13:31:16 +0200 | [diff] [blame] | 261 | * If we're going to bind the MAC to this PHY bus, |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 262 | * and no PHY number was provided to the MAC, |
| 263 | * use the one probed here. |
| 264 | */ |
Srinivas Kandagatla | d56631a | 2012-08-30 05:50:43 +0000 | [diff] [blame] | 265 | if (priv->plat->phy_addr == -1) |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 266 | priv->plat->phy_addr = addr; |
| 267 | |
Srinivas Kandagatla | d56631a | 2012-08-30 05:50:43 +0000 | [diff] [blame] | 268 | act = (priv->plat->phy_addr == addr); |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 269 | switch (phydev->irq) { |
| 270 | case PHY_POLL: |
| 271 | irq_str = "POLL"; |
| 272 | break; |
| 273 | case PHY_IGNORE_INTERRUPT: |
| 274 | irq_str = "IGNORE"; |
| 275 | break; |
| 276 | default: |
| 277 | sprintf(irq_num, "%d", phydev->irq); |
| 278 | irq_str = irq_num; |
| 279 | break; |
| 280 | } |
| 281 | pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n", |
| 282 | ndev->name, phydev->phy_id, addr, |
| 283 | irq_str, dev_name(&phydev->dev), |
| 284 | act ? " active" : ""); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 285 | found = 1; |
| 286 | } |
| 287 | } |
| 288 | |
Giuseppe CAVALLARO | 3955b22b | 2013-02-06 20:47:52 +0000 | [diff] [blame] | 289 | if (!found) { |
Joe Perches | fe3881c | 2014-09-09 20:27:44 -0700 | [diff] [blame] | 290 | pr_warn("%s: No PHY found\n", ndev->name); |
Giuseppe CAVALLARO | 3955b22b | 2013-02-06 20:47:52 +0000 | [diff] [blame] | 291 | mdiobus_unregister(new_bus); |
| 292 | mdiobus_free(new_bus); |
| 293 | return -ENODEV; |
| 294 | } |
| 295 | |
| 296 | priv->mii = new_bus; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 297 | |
| 298 | return 0; |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 299 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 300 | bus_register_fail: |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 301 | mdiobus_free(new_bus); |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 302 | return err; |
| 303 | } |
| 304 | |
| 305 | /** |
| 306 | * stmmac_mdio_unregister |
| 307 | * @ndev: net device structure |
| 308 | * Description: it unregisters the MII bus |
| 309 | */ |
| 310 | int stmmac_mdio_unregister(struct net_device *ndev) |
| 311 | { |
| 312 | struct stmmac_priv *priv = netdev_priv(ndev); |
| 313 | |
Srinivas Kandagatla | a5cf5ce | 2012-08-30 05:49:58 +0000 | [diff] [blame] | 314 | if (!priv->mii) |
| 315 | return 0; |
| 316 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 317 | mdiobus_unregister(priv->mii); |
| 318 | priv->mii->priv = NULL; |
Giuseppe CAVALLARO | 36bcfe7 | 2011-07-20 00:05:23 +0000 | [diff] [blame] | 319 | mdiobus_free(priv->mii); |
| 320 | priv->mii = NULL; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 321 | |
| 322 | return 0; |
| 323 | } |