blob: 2832576d8b12ee7c99e24896c3fe333dd8cffadc [file] [log] [blame]
Mathias Nymana5d811b2013-06-18 14:33:02 +03001/*
2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/bitops.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/gpio.h>
30#include <linux/irqdomain.h>
31#include <linux/acpi.h>
32#include <linux/acpi_gpio.h>
33#include <linux/platform_device.h>
34#include <linux/seq_file.h>
35#include <linux/io.h>
36#include <linux/pm_runtime.h>
37#include <linux/pinctrl/pinctrl.h>
38
39/* memory mapped register offsets */
40#define BYT_CONF0_REG 0x000
41#define BYT_CONF1_REG 0x004
42#define BYT_VAL_REG 0x008
43#define BYT_DFT_REG 0x00c
44#define BYT_INT_STAT_REG 0x800
45
46/* BYT_CONF0_REG register bits */
47#define BYT_TRIG_NEG BIT(26)
48#define BYT_TRIG_POS BIT(25)
49#define BYT_TRIG_LVL BIT(24)
50#define BYT_PIN_MUX 0x07
51
52/* BYT_VAL_REG register bits */
53#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
54#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
55#define BYT_LEVEL BIT(0)
56
57#define BYT_DIR_MASK (BIT(1) | BIT(2))
58#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
59
60#define BYT_NGPIO_SCORE 102
61#define BYT_NGPIO_NCORE 28
62#define BYT_NGPIO_SUS 44
63
64/*
65 * Baytrail gpio controller consist of three separate sub-controllers called
66 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
67 *
68 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
69 * _not_ correspond to the first gpio register at controller's gpio base.
70 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
71 * each sub-controller needs to have its own mapping table
72 */
73
74/* score_pins[gpio_nr] = pad_nr */
75
76static unsigned const score_pins[BYT_NGPIO_SCORE] = {
77 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
78 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
79 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
80 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
81 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
82 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
83 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
84 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
85 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
86 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
87 97, 100,
88};
89
90static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
91 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
92 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
93 3, 6, 10, 13, 2, 5, 9, 7,
94};
95
96static unsigned const sus_pins[BYT_NGPIO_SUS] = {
97 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
98 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
99 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
100 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
101 52, 53, 59, 40,
102};
103
104static struct pinctrl_gpio_range byt_ranges[] = {
105 {
106 .name = "1", /* match with acpi _UID in probe */
107 .npins = BYT_NGPIO_SCORE,
108 .pins = score_pins,
109 },
110 {
111 .name = "2",
112 .npins = BYT_NGPIO_NCORE,
113 .pins = ncore_pins,
114 },
115 {
116 .name = "3",
117 .npins = BYT_NGPIO_SUS,
118 .pins = sus_pins,
119 },
120 {
121 },
122};
123
124struct byt_gpio {
125 struct gpio_chip chip;
126 struct irq_domain *domain;
127 struct platform_device *pdev;
128 spinlock_t lock;
129 void __iomem *reg_base;
130 struct pinctrl_gpio_range *range;
131};
132
Andy Shevchenko17e52462013-07-10 14:55:39 +0300133#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
134
Mathias Nymana5d811b2013-06-18 14:33:02 +0300135static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
136 int reg)
137{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300138 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300139 u32 reg_offset;
Mathias Nymana5d811b2013-06-18 14:33:02 +0300140
141 if (reg == BYT_INT_STAT_REG)
142 reg_offset = (offset / 32) * 4;
143 else
144 reg_offset = vg->range->pins[offset] * 16;
145
Andy Shevchenko9c5b6552013-07-10 14:55:38 +0300146 return vg->reg_base + reg_offset + reg;
Mathias Nymana5d811b2013-06-18 14:33:02 +0300147}
148
149static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
150{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300151 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300152
153 pm_runtime_get(&vg->pdev->dev);
154
155 return 0;
156}
157
158static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
159{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300160 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300161 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
162 u32 value;
163
164 /* clear interrupt triggering */
165 value = readl(reg);
166 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
167 writel(value, reg);
168
169 pm_runtime_put(&vg->pdev->dev);
170}
171
172static int byt_irq_type(struct irq_data *d, unsigned type)
173{
174 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
175 u32 offset = irqd_to_hwirq(d);
176 u32 value;
177 unsigned long flags;
178 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
179
180 if (offset >= vg->chip.ngpio)
181 return -EINVAL;
182
183 spin_lock_irqsave(&vg->lock, flags);
184 value = readl(reg);
185
186 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
187 * are used to indicate high and low level triggering
188 */
189 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
190
191 switch (type) {
192 case IRQ_TYPE_LEVEL_HIGH:
193 value |= BYT_TRIG_LVL;
194 case IRQ_TYPE_EDGE_RISING:
195 value |= BYT_TRIG_POS;
196 break;
197 case IRQ_TYPE_LEVEL_LOW:
198 value |= BYT_TRIG_LVL;
199 case IRQ_TYPE_EDGE_FALLING:
200 value |= BYT_TRIG_NEG;
201 break;
202 case IRQ_TYPE_EDGE_BOTH:
203 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
204 break;
205 }
206 writel(value, reg);
207
208 spin_unlock_irqrestore(&vg->lock, flags);
209
210 return 0;
211}
212
213static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
214{
215 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
216 return readl(reg) & BYT_LEVEL;
217}
218
219static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
220{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300221 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300222 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
223 unsigned long flags;
224 u32 old_val;
225
226 spin_lock_irqsave(&vg->lock, flags);
227
228 old_val = readl(reg);
229
230 if (value)
231 writel(old_val | BYT_LEVEL, reg);
232 else
233 writel(old_val & ~BYT_LEVEL, reg);
234
235 spin_unlock_irqrestore(&vg->lock, flags);
236}
237
238static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
239{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300240 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300241 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
242 unsigned long flags;
243 u32 value;
244
245 spin_lock_irqsave(&vg->lock, flags);
246
247 value = readl(reg) | BYT_DIR_MASK;
Andy Shevchenko496940c2013-07-10 14:55:40 +0300248 value &= ~BYT_INPUT_EN; /* active low */
Mathias Nymana5d811b2013-06-18 14:33:02 +0300249 writel(value, reg);
250
251 spin_unlock_irqrestore(&vg->lock, flags);
252
253 return 0;
254}
255
256static int byt_gpio_direction_output(struct gpio_chip *chip,
257 unsigned gpio, int value)
258{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300259 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300260 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
261 unsigned long flags;
262 u32 reg_val;
263
264 spin_lock_irqsave(&vg->lock, flags);
265
Andy Shevchenko496940c2013-07-10 14:55:40 +0300266 reg_val = readl(reg) | BYT_DIR_MASK;
267 reg_val &= ~BYT_OUTPUT_EN;
268
269 if (value)
270 writel(reg_val | BYT_LEVEL, reg);
271 else
272 writel(reg_val & ~BYT_LEVEL, reg);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300273
274 spin_unlock_irqrestore(&vg->lock, flags);
275
276 return 0;
277}
278
279static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
280{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300281 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300282 int i;
283 unsigned long flags;
284 u32 conf0, val, offs;
285
286 spin_lock_irqsave(&vg->lock, flags);
287
288 for (i = 0; i < vg->chip.ngpio; i++) {
289 offs = vg->range->pins[i] * 16;
290 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
291 val = readl(vg->reg_base + offs + BYT_VAL_REG);
292
293 seq_printf(s,
294 " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
295 i,
296 val & BYT_INPUT_EN ? " " : "in",
297 val & BYT_OUTPUT_EN ? " " : "out",
298 val & BYT_LEVEL ? "hi" : "lo",
299 vg->range->pins[i], offs,
300 conf0 & 0x7,
Andy Shevchenko15834492013-07-10 16:42:14 +0300301 conf0 & BYT_TRIG_NEG ? " fall" : "",
302 conf0 & BYT_TRIG_POS ? " rise" : "",
303 conf0 & BYT_TRIG_LVL ? " level" : "");
Mathias Nymana5d811b2013-06-18 14:33:02 +0300304 }
305 spin_unlock_irqrestore(&vg->lock, flags);
306}
307
308static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
309{
Andy Shevchenko17e52462013-07-10 14:55:39 +0300310 struct byt_gpio *vg = to_byt_gpio(chip);
Mathias Nymana5d811b2013-06-18 14:33:02 +0300311 return irq_create_mapping(vg->domain, offset);
312}
313
314static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
315{
316 struct irq_data *data = irq_desc_get_irq_data(desc);
317 struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
318 struct irq_chip *chip = irq_data_get_irq_chip(data);
319 u32 base, pin, mask;
320 void __iomem *reg;
321 u32 pending;
322 unsigned virq;
323 int looplimit = 0;
324
325 /* check from GPIO controller which pin triggered the interrupt */
326 for (base = 0; base < vg->chip.ngpio; base += 32) {
327
328 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
329
330 while ((pending = readl(reg))) {
331 pin = __ffs(pending);
332 mask = BIT(pin);
333 /* Clear before handling so we can't lose an edge */
334 writel(mask, reg);
335
336 virq = irq_find_mapping(vg->domain, base + pin);
337 generic_handle_irq(virq);
338
339 /* In case bios or user sets triggering incorretly a pin
340 * might remain in "interrupt triggered" state.
341 */
342 if (looplimit++ > 32) {
343 dev_err(&vg->pdev->dev,
344 "Gpio %d interrupt flood, disabling\n",
345 base + pin);
346
347 reg = byt_gpio_reg(&vg->chip, base + pin,
348 BYT_CONF0_REG);
349 mask = readl(reg);
350 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
351 BYT_TRIG_LVL);
352 writel(mask, reg);
353 mask = readl(reg); /* flush */
354 break;
355 }
356 }
357 }
358 chip->irq_eoi(data);
359}
360
361static void byt_irq_unmask(struct irq_data *d)
362{
363}
364
365static void byt_irq_mask(struct irq_data *d)
366{
367}
368
369static struct irq_chip byt_irqchip = {
370 .name = "BYT-GPIO",
371 .irq_mask = byt_irq_mask,
372 .irq_unmask = byt_irq_unmask,
373 .irq_set_type = byt_irq_type,
374};
375
376static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
377{
378 void __iomem *reg;
379 u32 base, value;
380
381 /* clear interrupt status trigger registers */
382 for (base = 0; base < vg->chip.ngpio; base += 32) {
383 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
384 writel(0xffffffff, reg);
385 /* make sure trigger bits are cleared, if not then a pin
386 might be misconfigured in bios */
387 value = readl(reg);
388 if (value)
389 dev_err(&vg->pdev->dev,
390 "GPIO interrupt error, pins misconfigured\n");
391 }
392}
393
394static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
395 irq_hw_number_t hw)
396{
397 struct byt_gpio *vg = d->host_data;
398
399 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
400 "demux");
401 irq_set_chip_data(virq, vg);
402 irq_set_irq_type(virq, IRQ_TYPE_NONE);
403
404 return 0;
405}
406
407static const struct irq_domain_ops byt_gpio_irq_ops = {
408 .map = byt_gpio_irq_map,
409};
410
411static int byt_gpio_probe(struct platform_device *pdev)
412{
413 struct byt_gpio *vg;
414 struct gpio_chip *gc;
415 struct resource *mem_rc, *irq_rc;
416 struct device *dev = &pdev->dev;
417 struct acpi_device *acpi_dev;
418 struct pinctrl_gpio_range *range;
419 acpi_handle handle = ACPI_HANDLE(dev);
420 unsigned hwirq;
421 int ret;
422
423 if (acpi_bus_get_device(handle, &acpi_dev))
424 return -ENODEV;
425
426 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
427 if (!vg) {
428 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
429 return -ENOMEM;
430 }
431
432 for (range = byt_ranges; range->name; range++) {
433 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
434 vg->chip.ngpio = range->npins;
435 vg->range = range;
436 break;
437 }
438 }
439
440 if (!vg->chip.ngpio || !vg->range)
441 return -ENODEV;
442
443 vg->pdev = pdev;
444 platform_set_drvdata(pdev, vg);
445
446 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
447 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
448 if (IS_ERR(vg->reg_base))
449 return PTR_ERR(vg->reg_base);
450
451 spin_lock_init(&vg->lock);
452
453 gc = &vg->chip;
454 gc->label = dev_name(&pdev->dev);
455 gc->owner = THIS_MODULE;
456 gc->request = byt_gpio_request;
457 gc->free = byt_gpio_free;
458 gc->direction_input = byt_gpio_direction_input;
459 gc->direction_output = byt_gpio_direction_output;
460 gc->get = byt_gpio_get;
461 gc->set = byt_gpio_set;
462 gc->dbg_show = byt_gpio_dbg_show;
463 gc->base = -1;
464 gc->can_sleep = 0;
465 gc->dev = dev;
466
467 ret = gpiochip_add(gc);
468 if (ret) {
469 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
470 return ret;
471 }
472
473 /* set up interrupts */
474 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
475 if (irq_rc && irq_rc->start) {
476 hwirq = irq_rc->start;
477 gc->to_irq = byt_gpio_to_irq;
478
479 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
480 &byt_gpio_irq_ops, vg);
481 if (!vg->domain)
482 return -ENXIO;
483
484 byt_gpio_irq_init_hw(vg);
485
486 irq_set_handler_data(hwirq, vg);
487 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
488
489 /* Register interrupt handlers for gpio signaled acpi events */
490 acpi_gpiochip_request_interrupts(gc);
491 }
492
493 pm_runtime_enable(dev);
494
495 return 0;
496}
497
498static int byt_gpio_runtime_suspend(struct device *dev)
499{
500 return 0;
501}
502
503static int byt_gpio_runtime_resume(struct device *dev)
504{
505 return 0;
506}
507
508static const struct dev_pm_ops byt_gpio_pm_ops = {
509 .runtime_suspend = byt_gpio_runtime_suspend,
510 .runtime_resume = byt_gpio_runtime_resume,
511};
512
513static const struct acpi_device_id byt_gpio_acpi_match[] = {
514 { "INT33B2", 0 },
515 { }
516};
517MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
518
519static int byt_gpio_remove(struct platform_device *pdev)
520{
521 struct byt_gpio *vg = platform_get_drvdata(pdev);
522 int err;
Andy Shevchenkoec243322013-07-10 14:55:36 +0300523
Mathias Nymana5d811b2013-06-18 14:33:02 +0300524 pm_runtime_disable(&pdev->dev);
525 err = gpiochip_remove(&vg->chip);
526 if (err)
527 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
528
529 return 0;
530}
531
532static struct platform_driver byt_gpio_driver = {
533 .probe = byt_gpio_probe,
534 .remove = byt_gpio_remove,
535 .driver = {
536 .name = "byt_gpio",
537 .owner = THIS_MODULE,
538 .pm = &byt_gpio_pm_ops,
539 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
540 },
541};
542
543static int __init byt_gpio_init(void)
544{
545 return platform_driver_register(&byt_gpio_driver);
546}
547
548subsys_initcall(byt_gpio_init);