Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 24 | #include "priv.h" |
| 25 | #include "acpi.h" |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 26 | |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 27 | #include <core/notify.h> |
Ben Skeggs | a1bfb29 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 28 | #include <core/option.h> |
Ben Skeggs | d01c309 | 2014-08-10 04:10:21 +1000 | [diff] [blame] | 29 | |
Ben Skeggs | a1bfb29 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 30 | #include <subdev/bios.h> |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 31 | |
| 32 | static DEFINE_MUTEX(nv_devices_mutex); |
| 33 | static LIST_HEAD(nv_devices); |
| 34 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 35 | static struct nvkm_device * |
| 36 | nvkm_device_find_locked(u64 handle) |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 37 | { |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 38 | struct nvkm_device *device; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 39 | list_for_each_entry(device, &nv_devices, head) { |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 40 | if (device->handle == handle) |
| 41 | return device; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 42 | } |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 43 | return NULL; |
| 44 | } |
| 45 | |
| 46 | struct nvkm_device * |
| 47 | nvkm_device_find(u64 handle) |
| 48 | { |
| 49 | struct nvkm_device *device; |
| 50 | mutex_lock(&nv_devices_mutex); |
| 51 | device = nvkm_device_find_locked(handle); |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 52 | mutex_unlock(&nv_devices_mutex); |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 53 | return device; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 54 | } |
| 55 | |
Ben Skeggs | 803c178 | 2014-08-10 04:10:21 +1000 | [diff] [blame] | 56 | int |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 57 | nvkm_device_list(u64 *name, int size) |
Ben Skeggs | 803c178 | 2014-08-10 04:10:21 +1000 | [diff] [blame] | 58 | { |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 59 | struct nvkm_device *device; |
Ben Skeggs | 803c178 | 2014-08-10 04:10:21 +1000 | [diff] [blame] | 60 | int nr = 0; |
| 61 | mutex_lock(&nv_devices_mutex); |
| 62 | list_for_each_entry(device, &nv_devices, head) { |
| 63 | if (nr++ < size) |
| 64 | name[nr - 1] = device->handle; |
| 65 | } |
| 66 | mutex_unlock(&nv_devices_mutex); |
| 67 | return nr; |
| 68 | } |
| 69 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 70 | static const struct nvkm_device_chip |
| 71 | null_chipset = { |
| 72 | .name = "NULL", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 73 | .bios = nvkm_bios_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | static const struct nvkm_device_chip |
| 77 | nv4_chipset = { |
| 78 | .name = "NV04", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 79 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 80 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 81 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 82 | .devinit = nv04_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 83 | .fb = nv04_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 84 | // .i2c = nv04_i2c_new, |
| 85 | // .imem = nv04_instmem_new, |
| 86 | // .mc = nv04_mc_new, |
| 87 | // .mmu = nv04_mmu_new, |
| 88 | // .timer = nv04_timer_new, |
| 89 | // .disp = nv04_disp_new, |
| 90 | // .dma = nv04_dma_new, |
| 91 | // .fifo = nv04_fifo_new, |
| 92 | // .gr = nv04_gr_new, |
| 93 | // .sw = nv04_sw_new, |
| 94 | }; |
| 95 | |
| 96 | static const struct nvkm_device_chip |
| 97 | nv5_chipset = { |
| 98 | .name = "NV05", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 99 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 100 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 101 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 102 | .devinit = nv05_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 103 | .fb = nv04_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 104 | // .i2c = nv04_i2c_new, |
| 105 | // .imem = nv04_instmem_new, |
| 106 | // .mc = nv04_mc_new, |
| 107 | // .mmu = nv04_mmu_new, |
| 108 | // .timer = nv04_timer_new, |
| 109 | // .disp = nv04_disp_new, |
| 110 | // .dma = nv04_dma_new, |
| 111 | // .fifo = nv04_fifo_new, |
| 112 | // .gr = nv04_gr_new, |
| 113 | // .sw = nv04_sw_new, |
| 114 | }; |
| 115 | |
| 116 | static const struct nvkm_device_chip |
| 117 | nv10_chipset = { |
| 118 | .name = "NV10", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 119 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 120 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 121 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 122 | .devinit = nv10_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 123 | .fb = nv10_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 124 | // .gpio = nv10_gpio_new, |
| 125 | // .i2c = nv04_i2c_new, |
| 126 | // .imem = nv04_instmem_new, |
| 127 | // .mc = nv04_mc_new, |
| 128 | // .mmu = nv04_mmu_new, |
| 129 | // .timer = nv04_timer_new, |
| 130 | // .disp = nv04_disp_new, |
| 131 | // .dma = nv04_dma_new, |
| 132 | // .gr = nv10_gr_new, |
| 133 | }; |
| 134 | |
| 135 | static const struct nvkm_device_chip |
| 136 | nv11_chipset = { |
| 137 | .name = "NV11", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 138 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 139 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 140 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 141 | .devinit = nv10_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 142 | .fb = nv10_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 143 | // .gpio = nv10_gpio_new, |
| 144 | // .i2c = nv04_i2c_new, |
| 145 | // .imem = nv04_instmem_new, |
| 146 | // .mc = nv04_mc_new, |
| 147 | // .mmu = nv04_mmu_new, |
| 148 | // .timer = nv04_timer_new, |
| 149 | // .disp = nv04_disp_new, |
| 150 | // .dma = nv04_dma_new, |
| 151 | // .fifo = nv10_fifo_new, |
| 152 | // .gr = nv10_gr_new, |
| 153 | // .sw = nv10_sw_new, |
| 154 | }; |
| 155 | |
| 156 | static const struct nvkm_device_chip |
| 157 | nv15_chipset = { |
| 158 | .name = "NV15", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 159 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 160 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 161 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 162 | .devinit = nv10_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 163 | .fb = nv10_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 164 | // .gpio = nv10_gpio_new, |
| 165 | // .i2c = nv04_i2c_new, |
| 166 | // .imem = nv04_instmem_new, |
| 167 | // .mc = nv04_mc_new, |
| 168 | // .mmu = nv04_mmu_new, |
| 169 | // .timer = nv04_timer_new, |
| 170 | // .disp = nv04_disp_new, |
| 171 | // .dma = nv04_dma_new, |
| 172 | // .fifo = nv10_fifo_new, |
| 173 | // .gr = nv10_gr_new, |
| 174 | // .sw = nv10_sw_new, |
| 175 | }; |
| 176 | |
| 177 | static const struct nvkm_device_chip |
| 178 | nv17_chipset = { |
| 179 | .name = "NV17", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 180 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 181 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 182 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 183 | .devinit = nv10_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 184 | .fb = nv10_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 185 | // .gpio = nv10_gpio_new, |
| 186 | // .i2c = nv04_i2c_new, |
| 187 | // .imem = nv04_instmem_new, |
| 188 | // .mc = nv04_mc_new, |
| 189 | // .mmu = nv04_mmu_new, |
| 190 | // .timer = nv04_timer_new, |
| 191 | // .disp = nv04_disp_new, |
| 192 | // .dma = nv04_dma_new, |
| 193 | // .fifo = nv17_fifo_new, |
| 194 | // .gr = nv10_gr_new, |
| 195 | // .sw = nv10_sw_new, |
| 196 | }; |
| 197 | |
| 198 | static const struct nvkm_device_chip |
| 199 | nv18_chipset = { |
| 200 | .name = "NV18", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 201 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 202 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 203 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 204 | .devinit = nv10_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 205 | .fb = nv10_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 206 | // .gpio = nv10_gpio_new, |
| 207 | // .i2c = nv04_i2c_new, |
| 208 | // .imem = nv04_instmem_new, |
| 209 | // .mc = nv04_mc_new, |
| 210 | // .mmu = nv04_mmu_new, |
| 211 | // .timer = nv04_timer_new, |
| 212 | // .disp = nv04_disp_new, |
| 213 | // .dma = nv04_dma_new, |
| 214 | // .fifo = nv17_fifo_new, |
| 215 | // .gr = nv10_gr_new, |
| 216 | // .sw = nv10_sw_new, |
| 217 | }; |
| 218 | |
| 219 | static const struct nvkm_device_chip |
| 220 | nv1a_chipset = { |
| 221 | .name = "nForce", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 222 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 223 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 224 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 225 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 226 | .fb = nv1a_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 227 | // .gpio = nv10_gpio_new, |
| 228 | // .i2c = nv04_i2c_new, |
| 229 | // .imem = nv04_instmem_new, |
| 230 | // .mc = nv04_mc_new, |
| 231 | // .mmu = nv04_mmu_new, |
| 232 | // .timer = nv04_timer_new, |
| 233 | // .disp = nv04_disp_new, |
| 234 | // .dma = nv04_dma_new, |
| 235 | // .fifo = nv10_fifo_new, |
| 236 | // .gr = nv10_gr_new, |
| 237 | // .sw = nv10_sw_new, |
| 238 | }; |
| 239 | |
| 240 | static const struct nvkm_device_chip |
| 241 | nv1f_chipset = { |
| 242 | .name = "nForce2", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 243 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 244 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 245 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 246 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 247 | .fb = nv1a_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 248 | // .gpio = nv10_gpio_new, |
| 249 | // .i2c = nv04_i2c_new, |
| 250 | // .imem = nv04_instmem_new, |
| 251 | // .mc = nv04_mc_new, |
| 252 | // .mmu = nv04_mmu_new, |
| 253 | // .timer = nv04_timer_new, |
| 254 | // .disp = nv04_disp_new, |
| 255 | // .dma = nv04_dma_new, |
| 256 | // .fifo = nv17_fifo_new, |
| 257 | // .gr = nv10_gr_new, |
| 258 | // .sw = nv10_sw_new, |
| 259 | }; |
| 260 | |
| 261 | static const struct nvkm_device_chip |
| 262 | nv20_chipset = { |
| 263 | .name = "NV20", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 264 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 265 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 266 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 267 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 268 | .fb = nv20_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 269 | // .gpio = nv10_gpio_new, |
| 270 | // .i2c = nv04_i2c_new, |
| 271 | // .imem = nv04_instmem_new, |
| 272 | // .mc = nv04_mc_new, |
| 273 | // .mmu = nv04_mmu_new, |
| 274 | // .timer = nv04_timer_new, |
| 275 | // .disp = nv04_disp_new, |
| 276 | // .dma = nv04_dma_new, |
| 277 | // .fifo = nv17_fifo_new, |
| 278 | // .gr = nv20_gr_new, |
| 279 | // .sw = nv10_sw_new, |
| 280 | }; |
| 281 | |
| 282 | static const struct nvkm_device_chip |
| 283 | nv25_chipset = { |
| 284 | .name = "NV25", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 285 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 286 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 287 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 288 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 289 | .fb = nv25_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 290 | // .gpio = nv10_gpio_new, |
| 291 | // .i2c = nv04_i2c_new, |
| 292 | // .imem = nv04_instmem_new, |
| 293 | // .mc = nv04_mc_new, |
| 294 | // .mmu = nv04_mmu_new, |
| 295 | // .timer = nv04_timer_new, |
| 296 | // .disp = nv04_disp_new, |
| 297 | // .dma = nv04_dma_new, |
| 298 | // .fifo = nv17_fifo_new, |
| 299 | // .gr = nv25_gr_new, |
| 300 | // .sw = nv10_sw_new, |
| 301 | }; |
| 302 | |
| 303 | static const struct nvkm_device_chip |
| 304 | nv28_chipset = { |
| 305 | .name = "NV28", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 306 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 307 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 308 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 309 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 310 | .fb = nv25_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 311 | // .gpio = nv10_gpio_new, |
| 312 | // .i2c = nv04_i2c_new, |
| 313 | // .imem = nv04_instmem_new, |
| 314 | // .mc = nv04_mc_new, |
| 315 | // .mmu = nv04_mmu_new, |
| 316 | // .timer = nv04_timer_new, |
| 317 | // .disp = nv04_disp_new, |
| 318 | // .dma = nv04_dma_new, |
| 319 | // .fifo = nv17_fifo_new, |
| 320 | // .gr = nv25_gr_new, |
| 321 | // .sw = nv10_sw_new, |
| 322 | }; |
| 323 | |
| 324 | static const struct nvkm_device_chip |
| 325 | nv2a_chipset = { |
| 326 | .name = "NV2A", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 327 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 328 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 329 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 330 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 331 | .fb = nv25_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 332 | // .gpio = nv10_gpio_new, |
| 333 | // .i2c = nv04_i2c_new, |
| 334 | // .imem = nv04_instmem_new, |
| 335 | // .mc = nv04_mc_new, |
| 336 | // .mmu = nv04_mmu_new, |
| 337 | // .timer = nv04_timer_new, |
| 338 | // .disp = nv04_disp_new, |
| 339 | // .dma = nv04_dma_new, |
| 340 | // .fifo = nv17_fifo_new, |
| 341 | // .gr = nv2a_gr_new, |
| 342 | // .sw = nv10_sw_new, |
| 343 | }; |
| 344 | |
| 345 | static const struct nvkm_device_chip |
| 346 | nv30_chipset = { |
| 347 | .name = "NV30", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 348 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 349 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 350 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 351 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 352 | .fb = nv30_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 353 | // .gpio = nv10_gpio_new, |
| 354 | // .i2c = nv04_i2c_new, |
| 355 | // .imem = nv04_instmem_new, |
| 356 | // .mc = nv04_mc_new, |
| 357 | // .mmu = nv04_mmu_new, |
| 358 | // .timer = nv04_timer_new, |
| 359 | // .disp = nv04_disp_new, |
| 360 | // .dma = nv04_dma_new, |
| 361 | // .fifo = nv17_fifo_new, |
| 362 | // .gr = nv30_gr_new, |
| 363 | // .sw = nv10_sw_new, |
| 364 | }; |
| 365 | |
| 366 | static const struct nvkm_device_chip |
| 367 | nv31_chipset = { |
| 368 | .name = "NV31", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 369 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 370 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 371 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 372 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 373 | .fb = nv30_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 374 | // .gpio = nv10_gpio_new, |
| 375 | // .i2c = nv04_i2c_new, |
| 376 | // .imem = nv04_instmem_new, |
| 377 | // .mc = nv04_mc_new, |
| 378 | // .mmu = nv04_mmu_new, |
| 379 | // .timer = nv04_timer_new, |
| 380 | // .disp = nv04_disp_new, |
| 381 | // .dma = nv04_dma_new, |
| 382 | // .fifo = nv17_fifo_new, |
| 383 | // .gr = nv30_gr_new, |
| 384 | // .mpeg = nv31_mpeg_new, |
| 385 | // .sw = nv10_sw_new, |
| 386 | }; |
| 387 | |
| 388 | static const struct nvkm_device_chip |
| 389 | nv34_chipset = { |
| 390 | .name = "NV34", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 391 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 392 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 393 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 394 | .devinit = nv10_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 395 | .fb = nv10_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 396 | // .gpio = nv10_gpio_new, |
| 397 | // .i2c = nv04_i2c_new, |
| 398 | // .imem = nv04_instmem_new, |
| 399 | // .mc = nv04_mc_new, |
| 400 | // .mmu = nv04_mmu_new, |
| 401 | // .timer = nv04_timer_new, |
| 402 | // .disp = nv04_disp_new, |
| 403 | // .dma = nv04_dma_new, |
| 404 | // .fifo = nv17_fifo_new, |
| 405 | // .gr = nv34_gr_new, |
| 406 | // .mpeg = nv31_mpeg_new, |
| 407 | // .sw = nv10_sw_new, |
| 408 | }; |
| 409 | |
| 410 | static const struct nvkm_device_chip |
| 411 | nv35_chipset = { |
| 412 | .name = "NV35", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 413 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 414 | .bus = nv04_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 415 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 416 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 417 | .fb = nv35_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 418 | // .gpio = nv10_gpio_new, |
| 419 | // .i2c = nv04_i2c_new, |
| 420 | // .imem = nv04_instmem_new, |
| 421 | // .mc = nv04_mc_new, |
| 422 | // .mmu = nv04_mmu_new, |
| 423 | // .timer = nv04_timer_new, |
| 424 | // .disp = nv04_disp_new, |
| 425 | // .dma = nv04_dma_new, |
| 426 | // .fifo = nv17_fifo_new, |
| 427 | // .gr = nv35_gr_new, |
| 428 | // .sw = nv10_sw_new, |
| 429 | }; |
| 430 | |
| 431 | static const struct nvkm_device_chip |
| 432 | nv36_chipset = { |
| 433 | .name = "NV36", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 434 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 435 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 436 | .clk = nv04_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 437 | .devinit = nv20_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 438 | .fb = nv36_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 439 | // .gpio = nv10_gpio_new, |
| 440 | // .i2c = nv04_i2c_new, |
| 441 | // .imem = nv04_instmem_new, |
| 442 | // .mc = nv04_mc_new, |
| 443 | // .mmu = nv04_mmu_new, |
| 444 | // .timer = nv04_timer_new, |
| 445 | // .disp = nv04_disp_new, |
| 446 | // .dma = nv04_dma_new, |
| 447 | // .fifo = nv17_fifo_new, |
| 448 | // .gr = nv35_gr_new, |
| 449 | // .mpeg = nv31_mpeg_new, |
| 450 | // .sw = nv10_sw_new, |
| 451 | }; |
| 452 | |
| 453 | static const struct nvkm_device_chip |
| 454 | nv40_chipset = { |
| 455 | .name = "NV40", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 456 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 457 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 458 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 459 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 460 | .fb = nv40_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 461 | // .gpio = nv10_gpio_new, |
| 462 | // .i2c = nv04_i2c_new, |
| 463 | // .imem = nv40_instmem_new, |
| 464 | // .mc = nv40_mc_new, |
| 465 | // .mmu = nv04_mmu_new, |
| 466 | // .therm = nv40_therm_new, |
| 467 | // .timer = nv04_timer_new, |
| 468 | // .volt = nv40_volt_new, |
| 469 | // .disp = nv04_disp_new, |
| 470 | // .dma = nv04_dma_new, |
| 471 | // .fifo = nv40_fifo_new, |
| 472 | // .gr = nv40_gr_new, |
| 473 | // .mpeg = nv40_mpeg_new, |
| 474 | // .pm = nv40_pm_new, |
| 475 | // .sw = nv10_sw_new, |
| 476 | }; |
| 477 | |
| 478 | static const struct nvkm_device_chip |
| 479 | nv41_chipset = { |
| 480 | .name = "NV41", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 481 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 482 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 483 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 484 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 485 | .fb = nv41_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 486 | // .gpio = nv10_gpio_new, |
| 487 | // .i2c = nv04_i2c_new, |
| 488 | // .imem = nv40_instmem_new, |
| 489 | // .mc = nv40_mc_new, |
| 490 | // .mmu = nv41_mmu_new, |
| 491 | // .therm = nv40_therm_new, |
| 492 | // .timer = nv04_timer_new, |
| 493 | // .volt = nv40_volt_new, |
| 494 | // .disp = nv04_disp_new, |
| 495 | // .dma = nv04_dma_new, |
| 496 | // .fifo = nv40_fifo_new, |
| 497 | // .gr = nv40_gr_new, |
| 498 | // .mpeg = nv40_mpeg_new, |
| 499 | // .pm = nv40_pm_new, |
| 500 | // .sw = nv10_sw_new, |
| 501 | }; |
| 502 | |
| 503 | static const struct nvkm_device_chip |
| 504 | nv42_chipset = { |
| 505 | .name = "NV42", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 506 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 507 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 508 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 509 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 510 | .fb = nv41_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 511 | // .gpio = nv10_gpio_new, |
| 512 | // .i2c = nv04_i2c_new, |
| 513 | // .imem = nv40_instmem_new, |
| 514 | // .mc = nv40_mc_new, |
| 515 | // .mmu = nv41_mmu_new, |
| 516 | // .therm = nv40_therm_new, |
| 517 | // .timer = nv04_timer_new, |
| 518 | // .volt = nv40_volt_new, |
| 519 | // .disp = nv04_disp_new, |
| 520 | // .dma = nv04_dma_new, |
| 521 | // .fifo = nv40_fifo_new, |
| 522 | // .gr = nv40_gr_new, |
| 523 | // .mpeg = nv40_mpeg_new, |
| 524 | // .pm = nv40_pm_new, |
| 525 | // .sw = nv10_sw_new, |
| 526 | }; |
| 527 | |
| 528 | static const struct nvkm_device_chip |
| 529 | nv43_chipset = { |
| 530 | .name = "NV43", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 531 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 532 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 533 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 534 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 535 | .fb = nv41_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 536 | // .gpio = nv10_gpio_new, |
| 537 | // .i2c = nv04_i2c_new, |
| 538 | // .imem = nv40_instmem_new, |
| 539 | // .mc = nv40_mc_new, |
| 540 | // .mmu = nv41_mmu_new, |
| 541 | // .therm = nv40_therm_new, |
| 542 | // .timer = nv04_timer_new, |
| 543 | // .volt = nv40_volt_new, |
| 544 | // .disp = nv04_disp_new, |
| 545 | // .dma = nv04_dma_new, |
| 546 | // .fifo = nv40_fifo_new, |
| 547 | // .gr = nv40_gr_new, |
| 548 | // .mpeg = nv40_mpeg_new, |
| 549 | // .pm = nv40_pm_new, |
| 550 | // .sw = nv10_sw_new, |
| 551 | }; |
| 552 | |
| 553 | static const struct nvkm_device_chip |
| 554 | nv44_chipset = { |
| 555 | .name = "NV44", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 556 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 557 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 558 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 559 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 560 | .fb = nv44_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 561 | // .gpio = nv10_gpio_new, |
| 562 | // .i2c = nv04_i2c_new, |
| 563 | // .imem = nv40_instmem_new, |
| 564 | // .mc = nv44_mc_new, |
| 565 | // .mmu = nv44_mmu_new, |
| 566 | // .therm = nv40_therm_new, |
| 567 | // .timer = nv04_timer_new, |
| 568 | // .volt = nv40_volt_new, |
| 569 | // .disp = nv04_disp_new, |
| 570 | // .dma = nv04_dma_new, |
| 571 | // .fifo = nv40_fifo_new, |
| 572 | // .gr = nv40_gr_new, |
| 573 | // .mpeg = nv44_mpeg_new, |
| 574 | // .pm = nv40_pm_new, |
| 575 | // .sw = nv10_sw_new, |
| 576 | }; |
| 577 | |
| 578 | static const struct nvkm_device_chip |
| 579 | nv45_chipset = { |
| 580 | .name = "NV45", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 581 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 582 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 583 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 584 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 585 | .fb = nv40_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 586 | // .gpio = nv10_gpio_new, |
| 587 | // .i2c = nv04_i2c_new, |
| 588 | // .imem = nv40_instmem_new, |
| 589 | // .mc = nv40_mc_new, |
| 590 | // .mmu = nv04_mmu_new, |
| 591 | // .therm = nv40_therm_new, |
| 592 | // .timer = nv04_timer_new, |
| 593 | // .volt = nv40_volt_new, |
| 594 | // .disp = nv04_disp_new, |
| 595 | // .dma = nv04_dma_new, |
| 596 | // .fifo = nv40_fifo_new, |
| 597 | // .gr = nv40_gr_new, |
| 598 | // .mpeg = nv44_mpeg_new, |
| 599 | // .pm = nv40_pm_new, |
| 600 | // .sw = nv10_sw_new, |
| 601 | }; |
| 602 | |
| 603 | static const struct nvkm_device_chip |
| 604 | nv46_chipset = { |
| 605 | .name = "G72", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 606 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 607 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 608 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 609 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 610 | .fb = nv46_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 611 | // .gpio = nv10_gpio_new, |
| 612 | // .i2c = nv04_i2c_new, |
| 613 | // .imem = nv40_instmem_new, |
| 614 | // .mc = nv44_mc_new, |
| 615 | // .mmu = nv44_mmu_new, |
| 616 | // .therm = nv40_therm_new, |
| 617 | // .timer = nv04_timer_new, |
| 618 | // .volt = nv40_volt_new, |
| 619 | // .disp = nv04_disp_new, |
| 620 | // .dma = nv04_dma_new, |
| 621 | // .fifo = nv40_fifo_new, |
| 622 | // .gr = nv40_gr_new, |
| 623 | // .mpeg = nv44_mpeg_new, |
| 624 | // .pm = nv40_pm_new, |
| 625 | // .sw = nv10_sw_new, |
| 626 | }; |
| 627 | |
| 628 | static const struct nvkm_device_chip |
| 629 | nv47_chipset = { |
| 630 | .name = "G70", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 631 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 632 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 633 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 634 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 635 | .fb = nv47_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 636 | // .gpio = nv10_gpio_new, |
| 637 | // .i2c = nv04_i2c_new, |
| 638 | // .imem = nv40_instmem_new, |
| 639 | // .mc = nv40_mc_new, |
| 640 | // .mmu = nv41_mmu_new, |
| 641 | // .therm = nv40_therm_new, |
| 642 | // .timer = nv04_timer_new, |
| 643 | // .volt = nv40_volt_new, |
| 644 | // .disp = nv04_disp_new, |
| 645 | // .dma = nv04_dma_new, |
| 646 | // .fifo = nv40_fifo_new, |
| 647 | // .gr = nv40_gr_new, |
| 648 | // .mpeg = nv44_mpeg_new, |
| 649 | // .pm = nv40_pm_new, |
| 650 | // .sw = nv10_sw_new, |
| 651 | }; |
| 652 | |
| 653 | static const struct nvkm_device_chip |
| 654 | nv49_chipset = { |
| 655 | .name = "G71", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 656 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 657 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 658 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 659 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 660 | .fb = nv49_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 661 | // .gpio = nv10_gpio_new, |
| 662 | // .i2c = nv04_i2c_new, |
| 663 | // .imem = nv40_instmem_new, |
| 664 | // .mc = nv40_mc_new, |
| 665 | // .mmu = nv41_mmu_new, |
| 666 | // .therm = nv40_therm_new, |
| 667 | // .timer = nv04_timer_new, |
| 668 | // .volt = nv40_volt_new, |
| 669 | // .disp = nv04_disp_new, |
| 670 | // .dma = nv04_dma_new, |
| 671 | // .fifo = nv40_fifo_new, |
| 672 | // .gr = nv40_gr_new, |
| 673 | // .mpeg = nv44_mpeg_new, |
| 674 | // .pm = nv40_pm_new, |
| 675 | // .sw = nv10_sw_new, |
| 676 | }; |
| 677 | |
| 678 | static const struct nvkm_device_chip |
| 679 | nv4a_chipset = { |
| 680 | .name = "NV44A", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 681 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 682 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 683 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 684 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 685 | .fb = nv44_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 686 | // .gpio = nv10_gpio_new, |
| 687 | // .i2c = nv04_i2c_new, |
| 688 | // .imem = nv40_instmem_new, |
| 689 | // .mc = nv44_mc_new, |
| 690 | // .mmu = nv44_mmu_new, |
| 691 | // .therm = nv40_therm_new, |
| 692 | // .timer = nv04_timer_new, |
| 693 | // .volt = nv40_volt_new, |
| 694 | // .disp = nv04_disp_new, |
| 695 | // .dma = nv04_dma_new, |
| 696 | // .fifo = nv40_fifo_new, |
| 697 | // .gr = nv40_gr_new, |
| 698 | // .mpeg = nv44_mpeg_new, |
| 699 | // .pm = nv40_pm_new, |
| 700 | // .sw = nv10_sw_new, |
| 701 | }; |
| 702 | |
| 703 | static const struct nvkm_device_chip |
| 704 | nv4b_chipset = { |
| 705 | .name = "G73", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 706 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 707 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 708 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 709 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 710 | .fb = nv49_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 711 | // .gpio = nv10_gpio_new, |
| 712 | // .i2c = nv04_i2c_new, |
| 713 | // .imem = nv40_instmem_new, |
| 714 | // .mc = nv40_mc_new, |
| 715 | // .mmu = nv41_mmu_new, |
| 716 | // .therm = nv40_therm_new, |
| 717 | // .timer = nv04_timer_new, |
| 718 | // .volt = nv40_volt_new, |
| 719 | // .disp = nv04_disp_new, |
| 720 | // .dma = nv04_dma_new, |
| 721 | // .fifo = nv40_fifo_new, |
| 722 | // .gr = nv40_gr_new, |
| 723 | // .mpeg = nv44_mpeg_new, |
| 724 | // .pm = nv40_pm_new, |
| 725 | // .sw = nv10_sw_new, |
| 726 | }; |
| 727 | |
| 728 | static const struct nvkm_device_chip |
| 729 | nv4c_chipset = { |
| 730 | .name = "C61", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 731 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 732 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 733 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 734 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 735 | .fb = nv46_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 736 | // .gpio = nv10_gpio_new, |
| 737 | // .i2c = nv04_i2c_new, |
| 738 | // .imem = nv40_instmem_new, |
| 739 | // .mc = nv4c_mc_new, |
| 740 | // .mmu = nv44_mmu_new, |
| 741 | // .therm = nv40_therm_new, |
| 742 | // .timer = nv04_timer_new, |
| 743 | // .volt = nv40_volt_new, |
| 744 | // .disp = nv04_disp_new, |
| 745 | // .dma = nv04_dma_new, |
| 746 | // .fifo = nv40_fifo_new, |
| 747 | // .gr = nv40_gr_new, |
| 748 | // .mpeg = nv44_mpeg_new, |
| 749 | // .pm = nv40_pm_new, |
| 750 | // .sw = nv10_sw_new, |
| 751 | }; |
| 752 | |
| 753 | static const struct nvkm_device_chip |
| 754 | nv4e_chipset = { |
| 755 | .name = "C51", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 756 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 757 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 758 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 759 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 760 | .fb = nv4e_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 761 | // .gpio = nv10_gpio_new, |
| 762 | // .i2c = nv4e_i2c_new, |
| 763 | // .imem = nv40_instmem_new, |
| 764 | // .mc = nv4c_mc_new, |
| 765 | // .mmu = nv44_mmu_new, |
| 766 | // .therm = nv40_therm_new, |
| 767 | // .timer = nv04_timer_new, |
| 768 | // .volt = nv40_volt_new, |
| 769 | // .disp = nv04_disp_new, |
| 770 | // .dma = nv04_dma_new, |
| 771 | // .fifo = nv40_fifo_new, |
| 772 | // .gr = nv40_gr_new, |
| 773 | // .mpeg = nv44_mpeg_new, |
| 774 | // .pm = nv40_pm_new, |
| 775 | // .sw = nv10_sw_new, |
| 776 | }; |
| 777 | |
| 778 | static const struct nvkm_device_chip |
| 779 | nv50_chipset = { |
| 780 | .name = "G80", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 781 | .bar = nv50_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 782 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 783 | .bus = nv50_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 784 | .clk = nv50_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 785 | .devinit = nv50_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 786 | .fb = nv50_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 787 | // .fuse = nv50_fuse_new, |
| 788 | // .gpio = nv50_gpio_new, |
| 789 | // .i2c = nv50_i2c_new, |
| 790 | // .imem = nv50_instmem_new, |
| 791 | // .mc = nv50_mc_new, |
| 792 | // .mmu = nv50_mmu_new, |
| 793 | // .mxm = nv50_mxm_new, |
| 794 | // .therm = nv50_therm_new, |
| 795 | // .timer = nv04_timer_new, |
| 796 | // .volt = nv40_volt_new, |
| 797 | // .disp = nv50_disp_new, |
| 798 | // .dma = nv50_dma_new, |
| 799 | // .fifo = nv50_fifo_new, |
| 800 | // .gr = nv50_gr_new, |
| 801 | // .mpeg = nv50_mpeg_new, |
| 802 | // .pm = nv50_pm_new, |
| 803 | // .sw = nv50_sw_new, |
| 804 | }; |
| 805 | |
| 806 | static const struct nvkm_device_chip |
| 807 | nv63_chipset = { |
| 808 | .name = "C73", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 809 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 810 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 811 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 812 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 813 | .fb = nv46_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 814 | // .gpio = nv10_gpio_new, |
| 815 | // .i2c = nv04_i2c_new, |
| 816 | // .imem = nv40_instmem_new, |
| 817 | // .mc = nv4c_mc_new, |
| 818 | // .mmu = nv44_mmu_new, |
| 819 | // .therm = nv40_therm_new, |
| 820 | // .timer = nv04_timer_new, |
| 821 | // .volt = nv40_volt_new, |
| 822 | // .disp = nv04_disp_new, |
| 823 | // .dma = nv04_dma_new, |
| 824 | // .fifo = nv40_fifo_new, |
| 825 | // .gr = nv40_gr_new, |
| 826 | // .mpeg = nv44_mpeg_new, |
| 827 | // .pm = nv40_pm_new, |
| 828 | // .sw = nv10_sw_new, |
| 829 | }; |
| 830 | |
| 831 | static const struct nvkm_device_chip |
| 832 | nv67_chipset = { |
| 833 | .name = "C67", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 834 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 835 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 836 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 837 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 838 | .fb = nv46_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 839 | // .gpio = nv10_gpio_new, |
| 840 | // .i2c = nv04_i2c_new, |
| 841 | // .imem = nv40_instmem_new, |
| 842 | // .mc = nv4c_mc_new, |
| 843 | // .mmu = nv44_mmu_new, |
| 844 | // .therm = nv40_therm_new, |
| 845 | // .timer = nv04_timer_new, |
| 846 | // .volt = nv40_volt_new, |
| 847 | // .disp = nv04_disp_new, |
| 848 | // .dma = nv04_dma_new, |
| 849 | // .fifo = nv40_fifo_new, |
| 850 | // .gr = nv40_gr_new, |
| 851 | // .mpeg = nv44_mpeg_new, |
| 852 | // .pm = nv40_pm_new, |
| 853 | // .sw = nv10_sw_new, |
| 854 | }; |
| 855 | |
| 856 | static const struct nvkm_device_chip |
| 857 | nv68_chipset = { |
| 858 | .name = "C68", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 859 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 860 | .bus = nv31_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 861 | .clk = nv40_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 862 | .devinit = nv1a_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 863 | .fb = nv46_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 864 | // .gpio = nv10_gpio_new, |
| 865 | // .i2c = nv04_i2c_new, |
| 866 | // .imem = nv40_instmem_new, |
| 867 | // .mc = nv4c_mc_new, |
| 868 | // .mmu = nv44_mmu_new, |
| 869 | // .therm = nv40_therm_new, |
| 870 | // .timer = nv04_timer_new, |
| 871 | // .volt = nv40_volt_new, |
| 872 | // .disp = nv04_disp_new, |
| 873 | // .dma = nv04_dma_new, |
| 874 | // .fifo = nv40_fifo_new, |
| 875 | // .gr = nv40_gr_new, |
| 876 | // .mpeg = nv44_mpeg_new, |
| 877 | // .pm = nv40_pm_new, |
| 878 | // .sw = nv10_sw_new, |
| 879 | }; |
| 880 | |
| 881 | static const struct nvkm_device_chip |
| 882 | nv84_chipset = { |
| 883 | .name = "G84", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 884 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 885 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 886 | .bus = nv50_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 887 | .clk = g84_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 888 | .devinit = g84_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 889 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 890 | // .fuse = nv50_fuse_new, |
| 891 | // .gpio = nv50_gpio_new, |
| 892 | // .i2c = nv50_i2c_new, |
| 893 | // .imem = nv50_instmem_new, |
| 894 | // .mc = nv50_mc_new, |
| 895 | // .mmu = nv50_mmu_new, |
| 896 | // .mxm = nv50_mxm_new, |
| 897 | // .therm = g84_therm_new, |
| 898 | // .timer = nv04_timer_new, |
| 899 | // .volt = nv40_volt_new, |
| 900 | // .bsp = g84_bsp_new, |
| 901 | // .cipher = g84_cipher_new, |
| 902 | // .disp = g84_disp_new, |
| 903 | // .dma = nv50_dma_new, |
| 904 | // .fifo = g84_fifo_new, |
| 905 | // .gr = nv50_gr_new, |
| 906 | // .mpeg = g84_mpeg_new, |
| 907 | // .pm = g84_pm_new, |
| 908 | // .sw = nv50_sw_new, |
| 909 | // .vp = g84_vp_new, |
| 910 | }; |
| 911 | |
| 912 | static const struct nvkm_device_chip |
| 913 | nv86_chipset = { |
| 914 | .name = "G86", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 915 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 916 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 917 | .bus = nv50_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 918 | .clk = g84_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 919 | .devinit = g84_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 920 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 921 | // .fuse = nv50_fuse_new, |
| 922 | // .gpio = nv50_gpio_new, |
| 923 | // .i2c = nv50_i2c_new, |
| 924 | // .imem = nv50_instmem_new, |
| 925 | // .mc = nv50_mc_new, |
| 926 | // .mmu = nv50_mmu_new, |
| 927 | // .mxm = nv50_mxm_new, |
| 928 | // .therm = g84_therm_new, |
| 929 | // .timer = nv04_timer_new, |
| 930 | // .volt = nv40_volt_new, |
| 931 | // .bsp = g84_bsp_new, |
| 932 | // .cipher = g84_cipher_new, |
| 933 | // .disp = g84_disp_new, |
| 934 | // .dma = nv50_dma_new, |
| 935 | // .fifo = g84_fifo_new, |
| 936 | // .gr = nv50_gr_new, |
| 937 | // .mpeg = g84_mpeg_new, |
| 938 | // .pm = g84_pm_new, |
| 939 | // .sw = nv50_sw_new, |
| 940 | // .vp = g84_vp_new, |
| 941 | }; |
| 942 | |
| 943 | static const struct nvkm_device_chip |
| 944 | nv92_chipset = { |
| 945 | .name = "G92", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 946 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 947 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 948 | .bus = nv50_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 949 | .clk = g84_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 950 | .devinit = g84_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 951 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 952 | // .fuse = nv50_fuse_new, |
| 953 | // .gpio = nv50_gpio_new, |
| 954 | // .i2c = nv50_i2c_new, |
| 955 | // .imem = nv50_instmem_new, |
| 956 | // .mc = nv50_mc_new, |
| 957 | // .mmu = nv50_mmu_new, |
| 958 | // .mxm = nv50_mxm_new, |
| 959 | // .therm = g84_therm_new, |
| 960 | // .timer = nv04_timer_new, |
| 961 | // .volt = nv40_volt_new, |
| 962 | // .bsp = g84_bsp_new, |
| 963 | // .cipher = g84_cipher_new, |
| 964 | // .disp = g84_disp_new, |
| 965 | // .dma = nv50_dma_new, |
| 966 | // .fifo = g84_fifo_new, |
| 967 | // .gr = nv50_gr_new, |
| 968 | // .mpeg = g84_mpeg_new, |
| 969 | // .pm = g84_pm_new, |
| 970 | // .sw = nv50_sw_new, |
| 971 | // .vp = g84_vp_new, |
| 972 | }; |
| 973 | |
| 974 | static const struct nvkm_device_chip |
| 975 | nv94_chipset = { |
| 976 | .name = "G94", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 977 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 978 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 979 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 980 | .clk = g84_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 981 | .devinit = g84_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 982 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 983 | // .fuse = nv50_fuse_new, |
| 984 | // .gpio = g94_gpio_new, |
| 985 | // .i2c = g94_i2c_new, |
| 986 | // .imem = nv50_instmem_new, |
| 987 | // .mc = g94_mc_new, |
| 988 | // .mmu = nv50_mmu_new, |
| 989 | // .mxm = nv50_mxm_new, |
| 990 | // .therm = g84_therm_new, |
| 991 | // .timer = nv04_timer_new, |
| 992 | // .volt = nv40_volt_new, |
| 993 | // .bsp = g84_bsp_new, |
| 994 | // .cipher = g84_cipher_new, |
| 995 | // .disp = g94_disp_new, |
| 996 | // .dma = nv50_dma_new, |
| 997 | // .fifo = g84_fifo_new, |
| 998 | // .gr = nv50_gr_new, |
| 999 | // .mpeg = g84_mpeg_new, |
| 1000 | // .pm = g84_pm_new, |
| 1001 | // .sw = nv50_sw_new, |
| 1002 | // .vp = g84_vp_new, |
| 1003 | }; |
| 1004 | |
| 1005 | static const struct nvkm_device_chip |
| 1006 | nv96_chipset = { |
| 1007 | .name = "G96", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1008 | .bios = nvkm_bios_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1009 | // .gpio = g94_gpio_new, |
| 1010 | // .i2c = g94_i2c_new, |
| 1011 | // .fuse = nv50_fuse_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1012 | .clk = g84_clk_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1013 | // .therm = g84_therm_new, |
| 1014 | // .mxm = nv50_mxm_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1015 | .devinit = g84_devinit_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1016 | // .mc = g94_mc_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1017 | .bus = g94_bus_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1018 | // .timer = nv04_timer_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1019 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1020 | // .imem = nv50_instmem_new, |
| 1021 | // .mmu = nv50_mmu_new, |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1022 | .bar = g84_bar_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1023 | // .volt = nv40_volt_new, |
| 1024 | // .dma = nv50_dma_new, |
| 1025 | // .fifo = g84_fifo_new, |
| 1026 | // .sw = nv50_sw_new, |
| 1027 | // .gr = nv50_gr_new, |
| 1028 | // .mpeg = g84_mpeg_new, |
| 1029 | // .vp = g84_vp_new, |
| 1030 | // .cipher = g84_cipher_new, |
| 1031 | // .bsp = g84_bsp_new, |
| 1032 | // .disp = g94_disp_new, |
| 1033 | // .pm = g84_pm_new, |
| 1034 | }; |
| 1035 | |
| 1036 | static const struct nvkm_device_chip |
| 1037 | nv98_chipset = { |
| 1038 | .name = "G98", |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1039 | .bios = nvkm_bios_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1040 | // .gpio = g94_gpio_new, |
| 1041 | // .i2c = g94_i2c_new, |
| 1042 | // .fuse = nv50_fuse_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1043 | .clk = g84_clk_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1044 | // .therm = g84_therm_new, |
| 1045 | // .mxm = nv50_mxm_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1046 | .devinit = g98_devinit_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1047 | // .mc = g98_mc_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1048 | .bus = g94_bus_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1049 | // .timer = nv04_timer_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1050 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1051 | // .imem = nv50_instmem_new, |
| 1052 | // .mmu = nv50_mmu_new, |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1053 | .bar = g84_bar_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1054 | // .volt = nv40_volt_new, |
| 1055 | // .dma = nv50_dma_new, |
| 1056 | // .fifo = g84_fifo_new, |
| 1057 | // .sw = nv50_sw_new, |
| 1058 | // .gr = nv50_gr_new, |
| 1059 | // .mspdec = g98_mspdec_new, |
| 1060 | // .sec = g98_sec_new, |
| 1061 | // .msvld = g98_msvld_new, |
| 1062 | // .msppp = g98_msppp_new, |
| 1063 | // .disp = g94_disp_new, |
| 1064 | // .pm = g84_pm_new, |
| 1065 | }; |
| 1066 | |
| 1067 | static const struct nvkm_device_chip |
| 1068 | nva0_chipset = { |
| 1069 | .name = "GT200", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1070 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1071 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1072 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1073 | .clk = g84_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1074 | .devinit = g84_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1075 | .fb = g84_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1076 | // .fuse = nv50_fuse_new, |
| 1077 | // .gpio = g94_gpio_new, |
| 1078 | // .i2c = nv50_i2c_new, |
| 1079 | // .imem = nv50_instmem_new, |
| 1080 | // .mc = g98_mc_new, |
| 1081 | // .mmu = nv50_mmu_new, |
| 1082 | // .mxm = nv50_mxm_new, |
| 1083 | // .therm = g84_therm_new, |
| 1084 | // .timer = nv04_timer_new, |
| 1085 | // .volt = nv40_volt_new, |
| 1086 | // .bsp = g84_bsp_new, |
| 1087 | // .cipher = g84_cipher_new, |
| 1088 | // .disp = gt200_disp_new, |
| 1089 | // .dma = nv50_dma_new, |
| 1090 | // .fifo = g84_fifo_new, |
| 1091 | // .gr = nv50_gr_new, |
| 1092 | // .mpeg = g84_mpeg_new, |
| 1093 | // .pm = gt200_pm_new, |
| 1094 | // .sw = nv50_sw_new, |
| 1095 | // .vp = g84_vp_new, |
| 1096 | }; |
| 1097 | |
| 1098 | static const struct nvkm_device_chip |
| 1099 | nva3_chipset = { |
| 1100 | .name = "GT215", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1101 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1102 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1103 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1104 | .clk = gt215_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1105 | .devinit = gt215_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1106 | .fb = gt215_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1107 | // .fuse = nv50_fuse_new, |
| 1108 | // .gpio = g94_gpio_new, |
| 1109 | // .i2c = g94_i2c_new, |
| 1110 | // .imem = nv50_instmem_new, |
| 1111 | // .mc = g98_mc_new, |
| 1112 | // .mmu = nv50_mmu_new, |
| 1113 | // .mxm = nv50_mxm_new, |
| 1114 | // .pmu = gt215_pmu_new, |
| 1115 | // .therm = gt215_therm_new, |
| 1116 | // .timer = nv04_timer_new, |
| 1117 | // .volt = nv40_volt_new, |
| 1118 | // .ce[0] = gt215_ce_new, |
| 1119 | // .disp = gt215_disp_new, |
| 1120 | // .dma = nv50_dma_new, |
| 1121 | // .fifo = g84_fifo_new, |
| 1122 | // .gr = nv50_gr_new, |
| 1123 | // .mpeg = g84_mpeg_new, |
| 1124 | // .mspdec = g98_mspdec_new, |
| 1125 | // .msppp = g98_msppp_new, |
| 1126 | // .msvld = g98_msvld_new, |
| 1127 | // .pm = gt215_pm_new, |
| 1128 | // .sw = nv50_sw_new, |
| 1129 | }; |
| 1130 | |
| 1131 | static const struct nvkm_device_chip |
| 1132 | nva5_chipset = { |
| 1133 | .name = "GT216", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1134 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1135 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1136 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1137 | .clk = gt215_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1138 | .devinit = gt215_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1139 | .fb = gt215_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1140 | // .fuse = nv50_fuse_new, |
| 1141 | // .gpio = g94_gpio_new, |
| 1142 | // .i2c = g94_i2c_new, |
| 1143 | // .imem = nv50_instmem_new, |
| 1144 | // .mc = g98_mc_new, |
| 1145 | // .mmu = nv50_mmu_new, |
| 1146 | // .mxm = nv50_mxm_new, |
| 1147 | // .pmu = gt215_pmu_new, |
| 1148 | // .therm = gt215_therm_new, |
| 1149 | // .timer = nv04_timer_new, |
| 1150 | // .volt = nv40_volt_new, |
| 1151 | // .ce[0] = gt215_ce_new, |
| 1152 | // .disp = gt215_disp_new, |
| 1153 | // .dma = nv50_dma_new, |
| 1154 | // .fifo = g84_fifo_new, |
| 1155 | // .gr = nv50_gr_new, |
| 1156 | // .mspdec = g98_mspdec_new, |
| 1157 | // .msppp = g98_msppp_new, |
| 1158 | // .msvld = g98_msvld_new, |
| 1159 | // .pm = gt215_pm_new, |
| 1160 | // .sw = nv50_sw_new, |
| 1161 | }; |
| 1162 | |
| 1163 | static const struct nvkm_device_chip |
| 1164 | nva8_chipset = { |
| 1165 | .name = "GT218", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1166 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1167 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1168 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1169 | .clk = gt215_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1170 | .devinit = gt215_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1171 | .fb = gt215_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1172 | // .fuse = nv50_fuse_new, |
| 1173 | // .gpio = g94_gpio_new, |
| 1174 | // .i2c = g94_i2c_new, |
| 1175 | // .imem = nv50_instmem_new, |
| 1176 | // .mc = g98_mc_new, |
| 1177 | // .mmu = nv50_mmu_new, |
| 1178 | // .mxm = nv50_mxm_new, |
| 1179 | // .pmu = gt215_pmu_new, |
| 1180 | // .therm = gt215_therm_new, |
| 1181 | // .timer = nv04_timer_new, |
| 1182 | // .volt = nv40_volt_new, |
| 1183 | // .ce[0] = gt215_ce_new, |
| 1184 | // .disp = gt215_disp_new, |
| 1185 | // .dma = nv50_dma_new, |
| 1186 | // .fifo = g84_fifo_new, |
| 1187 | // .gr = nv50_gr_new, |
| 1188 | // .mspdec = g98_mspdec_new, |
| 1189 | // .msppp = g98_msppp_new, |
| 1190 | // .msvld = g98_msvld_new, |
| 1191 | // .pm = gt215_pm_new, |
| 1192 | // .sw = nv50_sw_new, |
| 1193 | }; |
| 1194 | |
| 1195 | static const struct nvkm_device_chip |
| 1196 | nvaa_chipset = { |
| 1197 | .name = "MCP77/MCP78", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1198 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1199 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1200 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1201 | .clk = mcp77_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1202 | .devinit = g98_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1203 | .fb = mcp77_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1204 | // .fuse = nv50_fuse_new, |
| 1205 | // .gpio = g94_gpio_new, |
| 1206 | // .i2c = g94_i2c_new, |
| 1207 | // .imem = nv50_instmem_new, |
| 1208 | // .mc = g98_mc_new, |
| 1209 | // .mmu = nv50_mmu_new, |
| 1210 | // .mxm = nv50_mxm_new, |
| 1211 | // .therm = g84_therm_new, |
| 1212 | // .timer = nv04_timer_new, |
| 1213 | // .volt = nv40_volt_new, |
| 1214 | // .disp = g94_disp_new, |
| 1215 | // .dma = nv50_dma_new, |
| 1216 | // .fifo = g84_fifo_new, |
| 1217 | // .gr = nv50_gr_new, |
| 1218 | // .mspdec = g98_mspdec_new, |
| 1219 | // .msppp = g98_msppp_new, |
| 1220 | // .msvld = g98_msvld_new, |
| 1221 | // .pm = g84_pm_new, |
| 1222 | // .sec = g98_sec_new, |
| 1223 | // .sw = nv50_sw_new, |
| 1224 | }; |
| 1225 | |
| 1226 | static const struct nvkm_device_chip |
| 1227 | nvac_chipset = { |
| 1228 | .name = "MCP79/MCP7A", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1229 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1230 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1231 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1232 | .clk = mcp77_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1233 | .devinit = g98_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1234 | .fb = mcp77_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1235 | // .fuse = nv50_fuse_new, |
| 1236 | // .gpio = g94_gpio_new, |
| 1237 | // .i2c = g94_i2c_new, |
| 1238 | // .imem = nv50_instmem_new, |
| 1239 | // .mc = g98_mc_new, |
| 1240 | // .mmu = nv50_mmu_new, |
| 1241 | // .mxm = nv50_mxm_new, |
| 1242 | // .therm = g84_therm_new, |
| 1243 | // .timer = nv04_timer_new, |
| 1244 | // .volt = nv40_volt_new, |
| 1245 | // .disp = g94_disp_new, |
| 1246 | // .dma = nv50_dma_new, |
| 1247 | // .fifo = g84_fifo_new, |
| 1248 | // .gr = nv50_gr_new, |
| 1249 | // .mspdec = g98_mspdec_new, |
| 1250 | // .msppp = g98_msppp_new, |
| 1251 | // .msvld = g98_msvld_new, |
| 1252 | // .pm = g84_pm_new, |
| 1253 | // .sec = g98_sec_new, |
| 1254 | // .sw = nv50_sw_new, |
| 1255 | }; |
| 1256 | |
| 1257 | static const struct nvkm_device_chip |
| 1258 | nvaf_chipset = { |
| 1259 | .name = "MCP89", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1260 | .bar = g84_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1261 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1262 | .bus = g94_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1263 | .clk = gt215_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1264 | .devinit = mcp89_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1265 | .fb = mcp89_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1266 | // .fuse = nv50_fuse_new, |
| 1267 | // .gpio = g94_gpio_new, |
| 1268 | // .i2c = g94_i2c_new, |
| 1269 | // .imem = nv50_instmem_new, |
| 1270 | // .mc = g98_mc_new, |
| 1271 | // .mmu = nv50_mmu_new, |
| 1272 | // .mxm = nv50_mxm_new, |
| 1273 | // .pmu = gt215_pmu_new, |
| 1274 | // .therm = gt215_therm_new, |
| 1275 | // .timer = nv04_timer_new, |
| 1276 | // .volt = nv40_volt_new, |
| 1277 | // .ce[0] = gt215_ce_new, |
| 1278 | // .disp = gt215_disp_new, |
| 1279 | // .dma = nv50_dma_new, |
| 1280 | // .fifo = g84_fifo_new, |
| 1281 | // .gr = nv50_gr_new, |
| 1282 | // .mspdec = g98_mspdec_new, |
| 1283 | // .msppp = g98_msppp_new, |
| 1284 | // .msvld = g98_msvld_new, |
| 1285 | // .pm = gt215_pm_new, |
| 1286 | // .sw = nv50_sw_new, |
| 1287 | }; |
| 1288 | |
| 1289 | static const struct nvkm_device_chip |
| 1290 | nvc0_chipset = { |
| 1291 | .name = "GF100", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1292 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1293 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1294 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1295 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1296 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1297 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1298 | // .fuse = gf100_fuse_new, |
| 1299 | // .gpio = g94_gpio_new, |
| 1300 | // .i2c = g94_i2c_new, |
| 1301 | // .ibus = gf100_ibus_new, |
| 1302 | // .imem = nv50_instmem_new, |
| 1303 | // .ltc = gf100_ltc_new, |
| 1304 | // .mc = gf100_mc_new, |
| 1305 | // .mmu = gf100_mmu_new, |
| 1306 | // .mxm = nv50_mxm_new, |
| 1307 | // .pmu = gf100_pmu_new, |
| 1308 | // .therm = gt215_therm_new, |
| 1309 | // .timer = nv04_timer_new, |
| 1310 | // .volt = nv40_volt_new, |
| 1311 | // .ce[0] = gf100_ce0_new, |
| 1312 | // .ce[1] = gf100_ce1_new, |
| 1313 | // .disp = gt215_disp_new, |
| 1314 | // .dma = gf100_dma_new, |
| 1315 | // .fifo = gf100_fifo_new, |
| 1316 | // .gr = gf100_gr_new, |
| 1317 | // .mspdec = gf100_mspdec_new, |
| 1318 | // .msppp = gf100_msppp_new, |
| 1319 | // .msvld = gf100_msvld_new, |
| 1320 | // .pm = gf100_pm_new, |
| 1321 | // .sw = gf100_sw_new, |
| 1322 | }; |
| 1323 | |
| 1324 | static const struct nvkm_device_chip |
| 1325 | nvc1_chipset = { |
| 1326 | .name = "GF108", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1327 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1328 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1329 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1330 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1331 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1332 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1333 | // .fuse = gf100_fuse_new, |
| 1334 | // .gpio = g94_gpio_new, |
| 1335 | // .i2c = g94_i2c_new, |
| 1336 | // .ibus = gf100_ibus_new, |
| 1337 | // .imem = nv50_instmem_new, |
| 1338 | // .ltc = gf100_ltc_new, |
| 1339 | // .mc = gf106_mc_new, |
| 1340 | // .mmu = gf100_mmu_new, |
| 1341 | // .mxm = nv50_mxm_new, |
| 1342 | // .pmu = gf100_pmu_new, |
| 1343 | // .therm = gt215_therm_new, |
| 1344 | // .timer = nv04_timer_new, |
| 1345 | // .volt = nv40_volt_new, |
| 1346 | // .ce[0] = gf100_ce0_new, |
| 1347 | // .disp = gt215_disp_new, |
| 1348 | // .dma = gf100_dma_new, |
| 1349 | // .fifo = gf100_fifo_new, |
| 1350 | // .gr = gf108_gr_new, |
| 1351 | // .mspdec = gf100_mspdec_new, |
| 1352 | // .msppp = gf100_msppp_new, |
| 1353 | // .msvld = gf100_msvld_new, |
| 1354 | // .pm = gf108_pm_new, |
| 1355 | // .sw = gf100_sw_new, |
| 1356 | }; |
| 1357 | |
| 1358 | static const struct nvkm_device_chip |
| 1359 | nvc3_chipset = { |
| 1360 | .name = "GF106", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1361 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1362 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1363 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1364 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1365 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1366 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1367 | // .fuse = gf100_fuse_new, |
| 1368 | // .gpio = g94_gpio_new, |
| 1369 | // .i2c = g94_i2c_new, |
| 1370 | // .ibus = gf100_ibus_new, |
| 1371 | // .imem = nv50_instmem_new, |
| 1372 | // .ltc = gf100_ltc_new, |
| 1373 | // .mc = gf106_mc_new, |
| 1374 | // .mmu = gf100_mmu_new, |
| 1375 | // .mxm = nv50_mxm_new, |
| 1376 | // .pmu = gf100_pmu_new, |
| 1377 | // .therm = gt215_therm_new, |
| 1378 | // .timer = nv04_timer_new, |
| 1379 | // .volt = nv40_volt_new, |
| 1380 | // .ce[0] = gf100_ce0_new, |
| 1381 | // .disp = gt215_disp_new, |
| 1382 | // .dma = gf100_dma_new, |
| 1383 | // .fifo = gf100_fifo_new, |
| 1384 | // .gr = gf104_gr_new, |
| 1385 | // .mspdec = gf100_mspdec_new, |
| 1386 | // .msppp = gf100_msppp_new, |
| 1387 | // .msvld = gf100_msvld_new, |
| 1388 | // .pm = gf100_pm_new, |
| 1389 | // .sw = gf100_sw_new, |
| 1390 | }; |
| 1391 | |
| 1392 | static const struct nvkm_device_chip |
| 1393 | nvc4_chipset = { |
| 1394 | .name = "GF104", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1395 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1396 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1397 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1398 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1399 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1400 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1401 | // .fuse = gf100_fuse_new, |
| 1402 | // .gpio = g94_gpio_new, |
| 1403 | // .i2c = g94_i2c_new, |
| 1404 | // .ibus = gf100_ibus_new, |
| 1405 | // .imem = nv50_instmem_new, |
| 1406 | // .ltc = gf100_ltc_new, |
| 1407 | // .mc = gf100_mc_new, |
| 1408 | // .mmu = gf100_mmu_new, |
| 1409 | // .mxm = nv50_mxm_new, |
| 1410 | // .pmu = gf100_pmu_new, |
| 1411 | // .therm = gt215_therm_new, |
| 1412 | // .timer = nv04_timer_new, |
| 1413 | // .volt = nv40_volt_new, |
| 1414 | // .ce[0] = gf100_ce0_new, |
| 1415 | // .ce[1] = gf100_ce1_new, |
| 1416 | // .disp = gt215_disp_new, |
| 1417 | // .dma = gf100_dma_new, |
| 1418 | // .fifo = gf100_fifo_new, |
| 1419 | // .gr = gf104_gr_new, |
| 1420 | // .mspdec = gf100_mspdec_new, |
| 1421 | // .msppp = gf100_msppp_new, |
| 1422 | // .msvld = gf100_msvld_new, |
| 1423 | // .pm = gf100_pm_new, |
| 1424 | // .sw = gf100_sw_new, |
| 1425 | }; |
| 1426 | |
| 1427 | static const struct nvkm_device_chip |
| 1428 | nvc8_chipset = { |
| 1429 | .name = "GF110", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1430 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1431 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1432 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1433 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1434 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1435 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1436 | // .fuse = gf100_fuse_new, |
| 1437 | // .gpio = g94_gpio_new, |
| 1438 | // .i2c = g94_i2c_new, |
| 1439 | // .ibus = gf100_ibus_new, |
| 1440 | // .imem = nv50_instmem_new, |
| 1441 | // .ltc = gf100_ltc_new, |
| 1442 | // .mc = gf100_mc_new, |
| 1443 | // .mmu = gf100_mmu_new, |
| 1444 | // .mxm = nv50_mxm_new, |
| 1445 | // .pmu = gf100_pmu_new, |
| 1446 | // .therm = gt215_therm_new, |
| 1447 | // .timer = nv04_timer_new, |
| 1448 | // .volt = nv40_volt_new, |
| 1449 | // .ce[0] = gf100_ce0_new, |
| 1450 | // .ce[1] = gf100_ce1_new, |
| 1451 | // .disp = gt215_disp_new, |
| 1452 | // .dma = gf100_dma_new, |
| 1453 | // .fifo = gf100_fifo_new, |
| 1454 | // .gr = gf110_gr_new, |
| 1455 | // .mspdec = gf100_mspdec_new, |
| 1456 | // .msppp = gf100_msppp_new, |
| 1457 | // .msvld = gf100_msvld_new, |
| 1458 | // .pm = gf100_pm_new, |
| 1459 | // .sw = gf100_sw_new, |
| 1460 | }; |
| 1461 | |
| 1462 | static const struct nvkm_device_chip |
| 1463 | nvce_chipset = { |
| 1464 | .name = "GF114", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1465 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1466 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1467 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1468 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1469 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1470 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1471 | // .fuse = gf100_fuse_new, |
| 1472 | // .gpio = g94_gpio_new, |
| 1473 | // .i2c = g94_i2c_new, |
| 1474 | // .ibus = gf100_ibus_new, |
| 1475 | // .imem = nv50_instmem_new, |
| 1476 | // .ltc = gf100_ltc_new, |
| 1477 | // .mc = gf100_mc_new, |
| 1478 | // .mmu = gf100_mmu_new, |
| 1479 | // .mxm = nv50_mxm_new, |
| 1480 | // .pmu = gf100_pmu_new, |
| 1481 | // .therm = gt215_therm_new, |
| 1482 | // .timer = nv04_timer_new, |
| 1483 | // .volt = nv40_volt_new, |
| 1484 | // .ce[0] = gf100_ce0_new, |
| 1485 | // .ce[1] = gf100_ce1_new, |
| 1486 | // .disp = gt215_disp_new, |
| 1487 | // .dma = gf100_dma_new, |
| 1488 | // .fifo = gf100_fifo_new, |
| 1489 | // .gr = gf104_gr_new, |
| 1490 | // .mspdec = gf100_mspdec_new, |
| 1491 | // .msppp = gf100_msppp_new, |
| 1492 | // .msvld = gf100_msvld_new, |
| 1493 | // .pm = gf100_pm_new, |
| 1494 | // .sw = gf100_sw_new, |
| 1495 | }; |
| 1496 | |
| 1497 | static const struct nvkm_device_chip |
| 1498 | nvcf_chipset = { |
| 1499 | .name = "GF116", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1500 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1501 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1502 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1503 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1504 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1505 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1506 | // .fuse = gf100_fuse_new, |
| 1507 | // .gpio = g94_gpio_new, |
| 1508 | // .i2c = g94_i2c_new, |
| 1509 | // .ibus = gf100_ibus_new, |
| 1510 | // .imem = nv50_instmem_new, |
| 1511 | // .ltc = gf100_ltc_new, |
| 1512 | // .mc = gf106_mc_new, |
| 1513 | // .mmu = gf100_mmu_new, |
| 1514 | // .mxm = nv50_mxm_new, |
| 1515 | // .pmu = gf100_pmu_new, |
| 1516 | // .therm = gt215_therm_new, |
| 1517 | // .timer = nv04_timer_new, |
| 1518 | // .volt = nv40_volt_new, |
| 1519 | // .ce[0] = gf100_ce0_new, |
| 1520 | // .disp = gt215_disp_new, |
| 1521 | // .dma = gf100_dma_new, |
| 1522 | // .fifo = gf100_fifo_new, |
| 1523 | // .gr = gf104_gr_new, |
| 1524 | // .mspdec = gf100_mspdec_new, |
| 1525 | // .msppp = gf100_msppp_new, |
| 1526 | // .msvld = gf100_msvld_new, |
| 1527 | // .pm = gf100_pm_new, |
| 1528 | // .sw = gf100_sw_new, |
| 1529 | }; |
| 1530 | |
| 1531 | static const struct nvkm_device_chip |
| 1532 | nvd7_chipset = { |
| 1533 | .name = "GF117", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1534 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1535 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1536 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1537 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1538 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1539 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1540 | // .fuse = gf100_fuse_new, |
| 1541 | // .gpio = gf110_gpio_new, |
| 1542 | // .i2c = gf117_i2c_new, |
| 1543 | // .ibus = gf100_ibus_new, |
| 1544 | // .imem = nv50_instmem_new, |
| 1545 | // .ltc = gf100_ltc_new, |
| 1546 | // .mc = gf106_mc_new, |
| 1547 | // .mmu = gf100_mmu_new, |
| 1548 | // .mxm = nv50_mxm_new, |
| 1549 | // .therm = gf110_therm_new, |
| 1550 | // .timer = nv04_timer_new, |
| 1551 | // .ce[0] = gf100_ce0_new, |
| 1552 | // .disp = gf119_disp_new, |
| 1553 | // .dma = gf119_dma_new, |
| 1554 | // .fifo = gf100_fifo_new, |
| 1555 | // .gr = gf117_gr_new, |
| 1556 | // .mspdec = gf100_mspdec_new, |
| 1557 | // .msppp = gf100_msppp_new, |
| 1558 | // .msvld = gf100_msvld_new, |
| 1559 | // .pm = gf117_pm_new, |
| 1560 | // .sw = gf100_sw_new, |
| 1561 | }; |
| 1562 | |
| 1563 | static const struct nvkm_device_chip |
| 1564 | nvd9_chipset = { |
| 1565 | .name = "GF119", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1566 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1567 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1568 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1569 | .clk = gf100_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1570 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1571 | .fb = gf100_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1572 | // .fuse = gf100_fuse_new, |
| 1573 | // .gpio = gf110_gpio_new, |
| 1574 | // .i2c = gf110_i2c_new, |
| 1575 | // .ibus = gf100_ibus_new, |
| 1576 | // .imem = nv50_instmem_new, |
| 1577 | // .ltc = gf100_ltc_new, |
| 1578 | // .mc = gf106_mc_new, |
| 1579 | // .mmu = gf100_mmu_new, |
| 1580 | // .mxm = nv50_mxm_new, |
| 1581 | // .pmu = gf110_pmu_new, |
| 1582 | // .therm = gf110_therm_new, |
| 1583 | // .timer = nv04_timer_new, |
| 1584 | // .volt = nv40_volt_new, |
| 1585 | // .ce[0] = gf100_ce0_new, |
| 1586 | // .disp = gf119_disp_new, |
| 1587 | // .dma = gf119_dma_new, |
| 1588 | // .fifo = gf100_fifo_new, |
| 1589 | // .gr = gf119_gr_new, |
| 1590 | // .mspdec = gf100_mspdec_new, |
| 1591 | // .msppp = gf100_msppp_new, |
| 1592 | // .msvld = gf100_msvld_new, |
| 1593 | // .pm = gf117_pm_new, |
| 1594 | // .sw = gf100_sw_new, |
| 1595 | }; |
| 1596 | |
| 1597 | static const struct nvkm_device_chip |
| 1598 | nve4_chipset = { |
| 1599 | .name = "GK104", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1600 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1601 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1602 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1603 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1604 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1605 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1606 | // .fuse = gf100_fuse_new, |
| 1607 | // .gpio = gk104_gpio_new, |
| 1608 | // .i2c = gk104_i2c_new, |
| 1609 | // .ibus = gk104_ibus_new, |
| 1610 | // .imem = nv50_instmem_new, |
| 1611 | // .ltc = gk104_ltc_new, |
| 1612 | // .mc = gf106_mc_new, |
| 1613 | // .mmu = gf100_mmu_new, |
| 1614 | // .mxm = nv50_mxm_new, |
| 1615 | // .pmu = gk104_pmu_new, |
| 1616 | // .therm = gf110_therm_new, |
| 1617 | // .timer = nv04_timer_new, |
| 1618 | // .volt = nv40_volt_new, |
| 1619 | // .ce[0] = gk104_ce0_new, |
| 1620 | // .ce[1] = gk104_ce1_new, |
| 1621 | // .ce[2] = gk104_ce2_new, |
| 1622 | // .disp = gk104_disp_new, |
| 1623 | // .dma = gf119_dma_new, |
| 1624 | // .fifo = gk104_fifo_new, |
| 1625 | // .gr = gk104_gr_new, |
| 1626 | // .mspdec = gk104_mspdec_new, |
| 1627 | // .msppp = gf100_msppp_new, |
| 1628 | // .msvld = gk104_msvld_new, |
| 1629 | // .pm = gk104_pm_new, |
| 1630 | // .sw = gf100_sw_new, |
| 1631 | }; |
| 1632 | |
| 1633 | static const struct nvkm_device_chip |
| 1634 | nve6_chipset = { |
| 1635 | .name = "GK106", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1636 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1637 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1638 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1639 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1640 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1641 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1642 | // .fuse = gf100_fuse_new, |
| 1643 | // .gpio = gk104_gpio_new, |
| 1644 | // .i2c = gk104_i2c_new, |
| 1645 | // .ibus = gk104_ibus_new, |
| 1646 | // .imem = nv50_instmem_new, |
| 1647 | // .ltc = gk104_ltc_new, |
| 1648 | // .mc = gf106_mc_new, |
| 1649 | // .mmu = gf100_mmu_new, |
| 1650 | // .mxm = nv50_mxm_new, |
| 1651 | // .pmu = gk104_pmu_new, |
| 1652 | // .therm = gf110_therm_new, |
| 1653 | // .timer = nv04_timer_new, |
| 1654 | // .volt = nv40_volt_new, |
| 1655 | // .ce[0] = gk104_ce0_new, |
| 1656 | // .ce[1] = gk104_ce1_new, |
| 1657 | // .ce[2] = gk104_ce2_new, |
| 1658 | // .disp = gk104_disp_new, |
| 1659 | // .dma = gf119_dma_new, |
| 1660 | // .fifo = gk104_fifo_new, |
| 1661 | // .gr = gk104_gr_new, |
| 1662 | // .mspdec = gk104_mspdec_new, |
| 1663 | // .msppp = gf100_msppp_new, |
| 1664 | // .msvld = gk104_msvld_new, |
| 1665 | // .pm = gk104_pm_new, |
| 1666 | // .sw = gf100_sw_new, |
| 1667 | }; |
| 1668 | |
| 1669 | static const struct nvkm_device_chip |
| 1670 | nve7_chipset = { |
| 1671 | .name = "GK107", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1672 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1673 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1674 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1675 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1676 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1677 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1678 | // .fuse = gf100_fuse_new, |
| 1679 | // .gpio = gk104_gpio_new, |
| 1680 | // .i2c = gk104_i2c_new, |
| 1681 | // .ibus = gk104_ibus_new, |
| 1682 | // .imem = nv50_instmem_new, |
| 1683 | // .ltc = gk104_ltc_new, |
| 1684 | // .mc = gf106_mc_new, |
| 1685 | // .mmu = gf100_mmu_new, |
| 1686 | // .mxm = nv50_mxm_new, |
| 1687 | // .pmu = gf110_pmu_new, |
| 1688 | // .therm = gf110_therm_new, |
| 1689 | // .timer = nv04_timer_new, |
| 1690 | // .volt = nv40_volt_new, |
| 1691 | // .ce[0] = gk104_ce0_new, |
| 1692 | // .ce[1] = gk104_ce1_new, |
| 1693 | // .ce[2] = gk104_ce2_new, |
| 1694 | // .disp = gk104_disp_new, |
| 1695 | // .dma = gf119_dma_new, |
| 1696 | // .fifo = gk104_fifo_new, |
| 1697 | // .gr = gk104_gr_new, |
| 1698 | // .mspdec = gk104_mspdec_new, |
| 1699 | // .msppp = gf100_msppp_new, |
| 1700 | // .msvld = gk104_msvld_new, |
| 1701 | // .pm = gk104_pm_new, |
| 1702 | // .sw = gf100_sw_new, |
| 1703 | }; |
| 1704 | |
| 1705 | static const struct nvkm_device_chip |
| 1706 | nvea_chipset = { |
| 1707 | .name = "GK20A", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1708 | .bar = gk20a_bar_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1709 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1710 | .clk = gk20a_clk_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1711 | .fb = gk20a_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1712 | // .fuse = gf100_fuse_new, |
| 1713 | // .ibus = gk20a_ibus_new, |
| 1714 | // .imem = gk20a_instmem_new, |
| 1715 | // .ltc = gk104_ltc_new, |
| 1716 | // .mc = gk20a_mc_new, |
| 1717 | // .mmu = gf100_mmu_new, |
| 1718 | // .pmu = gk20a_pmu_new, |
| 1719 | // .timer = gk20a_timer_new, |
| 1720 | // .volt = gk20a_volt_new, |
| 1721 | // .ce[2] = gk104_ce2_new, |
| 1722 | // .dma = gf119_dma_new, |
| 1723 | // .fifo = gk20a_fifo_new, |
| 1724 | // .gr = gk20a_gr_new, |
| 1725 | // .pm = gk104_pm_new, |
| 1726 | // .sw = gf100_sw_new, |
| 1727 | }; |
| 1728 | |
| 1729 | static const struct nvkm_device_chip |
| 1730 | nvf0_chipset = { |
| 1731 | .name = "GK110", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1732 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1733 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1734 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1735 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1736 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1737 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1738 | // .fuse = gf100_fuse_new, |
| 1739 | // .gpio = gk104_gpio_new, |
| 1740 | // .i2c = gk104_i2c_new, |
| 1741 | // .ibus = gk104_ibus_new, |
| 1742 | // .imem = nv50_instmem_new, |
| 1743 | // .ltc = gk104_ltc_new, |
| 1744 | // .mc = gf106_mc_new, |
| 1745 | // .mmu = gf100_mmu_new, |
| 1746 | // .mxm = nv50_mxm_new, |
| 1747 | // .pmu = gk110_pmu_new, |
| 1748 | // .therm = gf110_therm_new, |
| 1749 | // .timer = nv04_timer_new, |
| 1750 | // .volt = nv40_volt_new, |
| 1751 | // .ce[0] = gk104_ce0_new, |
| 1752 | // .ce[1] = gk104_ce1_new, |
| 1753 | // .ce[2] = gk104_ce2_new, |
| 1754 | // .disp = gk110_disp_new, |
| 1755 | // .dma = gf119_dma_new, |
| 1756 | // .fifo = gk104_fifo_new, |
| 1757 | // .gr = gk110_gr_new, |
| 1758 | // .mspdec = gk104_mspdec_new, |
| 1759 | // .msppp = gf100_msppp_new, |
| 1760 | // .msvld = gk104_msvld_new, |
| 1761 | // .pm = gk110_pm_new, |
| 1762 | // .sw = gf100_sw_new, |
| 1763 | }; |
| 1764 | |
| 1765 | static const struct nvkm_device_chip |
| 1766 | nvf1_chipset = { |
| 1767 | .name = "GK110B", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1768 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1769 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1770 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1771 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1772 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1773 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1774 | // .fuse = gf100_fuse_new, |
| 1775 | // .gpio = gk104_gpio_new, |
| 1776 | // .i2c = gf110_i2c_new, |
| 1777 | // .ibus = gk104_ibus_new, |
| 1778 | // .imem = nv50_instmem_new, |
| 1779 | // .ltc = gk104_ltc_new, |
| 1780 | // .mc = gf106_mc_new, |
| 1781 | // .mmu = gf100_mmu_new, |
| 1782 | // .mxm = nv50_mxm_new, |
| 1783 | // .pmu = gk110_pmu_new, |
| 1784 | // .therm = gf110_therm_new, |
| 1785 | // .timer = nv04_timer_new, |
| 1786 | // .volt = nv40_volt_new, |
| 1787 | // .ce[0] = gk104_ce0_new, |
| 1788 | // .ce[1] = gk104_ce1_new, |
| 1789 | // .ce[2] = gk104_ce2_new, |
| 1790 | // .disp = gk110_disp_new, |
| 1791 | // .dma = gf119_dma_new, |
| 1792 | // .fifo = gk104_fifo_new, |
| 1793 | // .gr = gk110b_gr_new, |
| 1794 | // .mspdec = gk104_mspdec_new, |
| 1795 | // .msppp = gf100_msppp_new, |
| 1796 | // .msvld = gk104_msvld_new, |
| 1797 | // .pm = gk110_pm_new, |
| 1798 | // .sw = gf100_sw_new, |
| 1799 | }; |
| 1800 | |
| 1801 | static const struct nvkm_device_chip |
| 1802 | nv106_chipset = { |
| 1803 | .name = "GK208B", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1804 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1805 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1806 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1807 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1808 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1809 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1810 | // .fuse = gf100_fuse_new, |
| 1811 | // .gpio = gk104_gpio_new, |
| 1812 | // .i2c = gk104_i2c_new, |
| 1813 | // .ibus = gk104_ibus_new, |
| 1814 | // .imem = nv50_instmem_new, |
| 1815 | // .ltc = gk104_ltc_new, |
| 1816 | // .mc = gk20a_mc_new, |
| 1817 | // .mmu = gf100_mmu_new, |
| 1818 | // .mxm = nv50_mxm_new, |
| 1819 | // .pmu = gk208_pmu_new, |
| 1820 | // .therm = gf110_therm_new, |
| 1821 | // .timer = nv04_timer_new, |
| 1822 | // .volt = nv40_volt_new, |
| 1823 | // .ce[0] = gk104_ce0_new, |
| 1824 | // .ce[1] = gk104_ce1_new, |
| 1825 | // .ce[2] = gk104_ce2_new, |
| 1826 | // .disp = gk110_disp_new, |
| 1827 | // .dma = gf119_dma_new, |
| 1828 | // .fifo = gk208_fifo_new, |
| 1829 | // .gr = gk208_gr_new, |
| 1830 | // .mspdec = gk104_mspdec_new, |
| 1831 | // .msppp = gf100_msppp_new, |
| 1832 | // .msvld = gk104_msvld_new, |
| 1833 | // .sw = gf100_sw_new, |
| 1834 | }; |
| 1835 | |
| 1836 | static const struct nvkm_device_chip |
| 1837 | nv108_chipset = { |
| 1838 | .name = "GK208", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1839 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1840 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1841 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1842 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1843 | .devinit = gf100_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1844 | .fb = gk104_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1845 | // .fuse = gf100_fuse_new, |
| 1846 | // .gpio = gk104_gpio_new, |
| 1847 | // .i2c = gk104_i2c_new, |
| 1848 | // .ibus = gk104_ibus_new, |
| 1849 | // .imem = nv50_instmem_new, |
| 1850 | // .ltc = gk104_ltc_new, |
| 1851 | // .mc = gk20a_mc_new, |
| 1852 | // .mmu = gf100_mmu_new, |
| 1853 | // .mxm = nv50_mxm_new, |
| 1854 | // .pmu = gk208_pmu_new, |
| 1855 | // .therm = gf110_therm_new, |
| 1856 | // .timer = nv04_timer_new, |
| 1857 | // .volt = nv40_volt_new, |
| 1858 | // .ce[0] = gk104_ce0_new, |
| 1859 | // .ce[1] = gk104_ce1_new, |
| 1860 | // .ce[2] = gk104_ce2_new, |
| 1861 | // .disp = gk110_disp_new, |
| 1862 | // .dma = gf119_dma_new, |
| 1863 | // .fifo = gk208_fifo_new, |
| 1864 | // .gr = gk208_gr_new, |
| 1865 | // .mspdec = gk104_mspdec_new, |
| 1866 | // .msppp = gf100_msppp_new, |
| 1867 | // .msvld = gk104_msvld_new, |
| 1868 | // .sw = gf100_sw_new, |
| 1869 | }; |
| 1870 | |
| 1871 | static const struct nvkm_device_chip |
| 1872 | nv117_chipset = { |
| 1873 | .name = "GM107", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1874 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1875 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1876 | .bus = gf100_bus_new, |
Ben Skeggs | 6625f55 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1877 | .clk = gk104_clk_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1878 | .devinit = gm107_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1879 | .fb = gm107_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1880 | // .fuse = gm107_fuse_new, |
| 1881 | // .gpio = gk104_gpio_new, |
| 1882 | // .i2c = gf110_i2c_new, |
| 1883 | // .ibus = gk104_ibus_new, |
| 1884 | // .imem = nv50_instmem_new, |
| 1885 | // .ltc = gm107_ltc_new, |
| 1886 | // .mc = gk20a_mc_new, |
| 1887 | // .mmu = gf100_mmu_new, |
| 1888 | // .mxm = nv50_mxm_new, |
| 1889 | // .pmu = gk208_pmu_new, |
| 1890 | // .therm = gm107_therm_new, |
| 1891 | // .timer = gk20a_timer_new, |
| 1892 | // .ce[0] = gk104_ce0_new, |
| 1893 | // .ce[2] = gk104_ce2_new, |
| 1894 | // .disp = gm107_disp_new, |
| 1895 | // .dma = gf119_dma_new, |
| 1896 | // .fifo = gk208_fifo_new, |
| 1897 | // .gr = gm107_gr_new, |
| 1898 | // .sw = gf100_sw_new, |
| 1899 | }; |
| 1900 | |
| 1901 | static const struct nvkm_device_chip |
| 1902 | nv124_chipset = { |
| 1903 | .name = "GM204", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1904 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1905 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1906 | .bus = gf100_bus_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1907 | .devinit = gm204_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1908 | .fb = gm107_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1909 | // .fuse = gm107_fuse_new, |
| 1910 | // .gpio = gk104_gpio_new, |
| 1911 | // .i2c = gm204_i2c_new, |
| 1912 | // .ibus = gk104_ibus_new, |
| 1913 | // .imem = nv50_instmem_new, |
| 1914 | // .ltc = gm107_ltc_new, |
| 1915 | // .mc = gk20a_mc_new, |
| 1916 | // .mmu = gf100_mmu_new, |
| 1917 | // .mxm = nv50_mxm_new, |
| 1918 | // .pmu = gk208_pmu_new, |
| 1919 | // .timer = gk20a_timer_new, |
| 1920 | // .ce[0] = gm204_ce0_new, |
| 1921 | // .ce[1] = gm204_ce1_new, |
| 1922 | // .ce[2] = gm204_ce2_new, |
| 1923 | // .disp = gm204_disp_new, |
| 1924 | // .dma = gf119_dma_new, |
| 1925 | // .fifo = gm204_fifo_new, |
| 1926 | // .gr = gm204_gr_new, |
| 1927 | // .sw = gf100_sw_new, |
| 1928 | }; |
| 1929 | |
| 1930 | static const struct nvkm_device_chip |
| 1931 | nv126_chipset = { |
| 1932 | .name = "GM206", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1933 | .bar = gf100_bar_new, |
Ben Skeggs | 4648443 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1934 | .bios = nvkm_bios_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1935 | .bus = gf100_bus_new, |
Ben Skeggs | 151abd4 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1936 | .devinit = gm204_devinit_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1937 | .fb = gm107_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1938 | // .fuse = gm107_fuse_new, |
| 1939 | // .gpio = gk104_gpio_new, |
| 1940 | // .i2c = gm204_i2c_new, |
| 1941 | // .ibus = gk104_ibus_new, |
| 1942 | // .imem = nv50_instmem_new, |
| 1943 | // .ltc = gm107_ltc_new, |
| 1944 | // .mc = gk20a_mc_new, |
| 1945 | // .mmu = gf100_mmu_new, |
| 1946 | // .mxm = nv50_mxm_new, |
| 1947 | // .pmu = gk208_pmu_new, |
| 1948 | // .timer = gk20a_timer_new, |
| 1949 | // .ce[0] = gm204_ce0_new, |
| 1950 | // .ce[1] = gm204_ce1_new, |
| 1951 | // .ce[2] = gm204_ce2_new, |
| 1952 | // .disp = gm204_disp_new, |
| 1953 | // .dma = gf119_dma_new, |
| 1954 | // .fifo = gm204_fifo_new, |
| 1955 | // .gr = gm206_gr_new, |
| 1956 | // .sw = gf100_sw_new, |
| 1957 | }; |
| 1958 | |
| 1959 | static const struct nvkm_device_chip |
| 1960 | nv12b_chipset = { |
| 1961 | .name = "GM20B", |
Ben Skeggs | 3293228 | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1962 | .bar = gk20a_bar_new, |
Ben Skeggs | bb23f9d | 2015-08-20 14:54:20 +1000 | [diff] [blame] | 1963 | .bus = gf100_bus_new, |
Ben Skeggs | 03c8952 | 2015-08-20 14:54:20 +1000 | [diff] [blame^] | 1964 | .fb = gk20a_fb_new, |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1965 | // .fuse = gm107_fuse_new, |
| 1966 | // .ibus = gk20a_ibus_new, |
| 1967 | // .imem = gk20a_instmem_new, |
| 1968 | // .ltc = gm107_ltc_new, |
| 1969 | // .mc = gk20a_mc_new, |
| 1970 | // .mmu = gf100_mmu_new, |
| 1971 | // .mmu = gf100_mmu_new, |
| 1972 | // .timer = gk20a_timer_new, |
| 1973 | // .ce[2] = gm204_ce2_new, |
| 1974 | // .dma = gf119_dma_new, |
| 1975 | // .fifo = gm20b_fifo_new, |
| 1976 | // .gr = gm20b_gr_new, |
| 1977 | // .sw = gf100_sw_new, |
| 1978 | }; |
| 1979 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1980 | #include <core/client.h> |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1981 | |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 1982 | struct nvkm_device * |
Ben Skeggs | a38f37a | 2014-12-05 11:20:19 +1000 | [diff] [blame] | 1983 | nv_device(void *obj) |
| 1984 | { |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 1985 | struct nvkm_object *device = nv_object(obj); |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1986 | |
Ben Skeggs | 8000fb2 | 2014-12-05 12:21:34 +1000 | [diff] [blame] | 1987 | if (device->engine == NULL) { |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1988 | while (device && device->parent) { |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1989 | if (!nv_iclass(device, NV_SUBDEV_CLASS) && |
Ben Skeggs | 24bd093 | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1990 | device->parent == &nvkm_client(device)->object) { |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1991 | struct { |
Ben Skeggs | 2a9f847 | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1992 | struct nvkm_object base; |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1993 | struct nvkm_device *device; |
| 1994 | } *udevice = (void *)device; |
| 1995 | return udevice->device; |
| 1996 | } |
Ben Skeggs | 8000fb2 | 2014-12-05 12:21:34 +1000 | [diff] [blame] | 1997 | device = device->parent; |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1998 | } |
Ben Skeggs | 8000fb2 | 2014-12-05 12:21:34 +1000 | [diff] [blame] | 1999 | } else { |
Ben Skeggs | ec0e554 | 2014-12-05 12:37:19 +1000 | [diff] [blame] | 2000 | device = &nv_object(obj)->engine->subdev.object; |
Ben Skeggs | 490d595 | 2014-12-05 11:26:23 +1000 | [diff] [blame] | 2001 | if (device && device->parent) |
| 2002 | device = device->parent; |
Ben Skeggs | a38f37a | 2014-12-05 11:20:19 +1000 | [diff] [blame] | 2003 | } |
Ben Skeggs | 490d595 | 2014-12-05 11:26:23 +1000 | [diff] [blame] | 2004 | #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA |
Ben Skeggs | 5300394 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 2005 | BUG_ON(!device); |
Ben Skeggs | a38f37a | 2014-12-05 11:20:19 +1000 | [diff] [blame] | 2006 | #endif |
Ben Skeggs | a38f37a | 2014-12-05 11:20:19 +1000 | [diff] [blame] | 2007 | return (void *)device; |
| 2008 | } |
| 2009 | |
Ben Skeggs | 066a5d0 | 2013-04-25 11:35:18 +1000 | [diff] [blame] | 2010 | static int |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2011 | nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, |
| 2012 | struct nvkm_notify *notify) |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 2013 | { |
| 2014 | if (!WARN_ON(size != 0)) { |
| 2015 | notify->size = 0; |
| 2016 | notify->types = 1; |
| 2017 | notify->index = 0; |
| 2018 | return 0; |
| 2019 | } |
| 2020 | return -EINVAL; |
| 2021 | } |
| 2022 | |
| 2023 | static const struct nvkm_event_func |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2024 | nvkm_device_event_func = { |
| 2025 | .ctor = nvkm_device_event_ctor, |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 2026 | }; |
| 2027 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2028 | struct nvkm_subdev * |
| 2029 | nvkm_device_subdev(struct nvkm_device *device, int index) |
Ben Skeggs | 066a5d0 | 2013-04-25 11:35:18 +1000 | [diff] [blame] | 2030 | { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2031 | struct nvkm_engine *engine; |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2032 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2033 | if (device->disable_mask & (1ULL << index)) |
| 2034 | return NULL; |
| 2035 | |
| 2036 | switch (index) { |
| 2037 | #define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break |
| 2038 | _(BAR , device->bar , &device->bar->subdev); |
| 2039 | _(VBIOS , device->bios , &device->bios->subdev); |
| 2040 | _(BUS , device->bus , &device->bus->subdev); |
| 2041 | _(CLK , device->clk , &device->clk->subdev); |
| 2042 | _(DEVINIT, device->devinit, &device->devinit->subdev); |
| 2043 | _(FB , device->fb , &device->fb->subdev); |
| 2044 | _(FUSE , device->fuse , &device->fuse->subdev); |
| 2045 | _(GPIO , device->gpio , &device->gpio->subdev); |
| 2046 | _(I2C , device->i2c , &device->i2c->subdev); |
| 2047 | _(IBUS , device->ibus , device->ibus); |
| 2048 | _(INSTMEM, device->imem , &device->imem->subdev); |
| 2049 | _(LTC , device->ltc , &device->ltc->subdev); |
| 2050 | _(MC , device->mc , &device->mc->subdev); |
| 2051 | _(MMU , device->mmu , &device->mmu->subdev); |
| 2052 | _(MXM , device->mxm , device->mxm); |
| 2053 | _(PMU , device->pmu , &device->pmu->subdev); |
| 2054 | _(THERM , device->therm , &device->therm->subdev); |
| 2055 | _(TIMER , device->timer , &device->timer->subdev); |
| 2056 | _(VOLT , device->volt , &device->volt->subdev); |
| 2057 | #undef _ |
| 2058 | default: |
| 2059 | engine = nvkm_device_engine(device, index); |
| 2060 | if (engine) |
| 2061 | return &engine->subdev; |
| 2062 | break; |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2063 | } |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2064 | return NULL; |
| 2065 | } |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2066 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2067 | struct nvkm_engine * |
| 2068 | nvkm_device_engine(struct nvkm_device *device, int index) |
| 2069 | { |
| 2070 | if (device->disable_mask & (1ULL << index)) |
| 2071 | return NULL; |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2072 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2073 | switch (index) { |
| 2074 | #define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break |
| 2075 | _(BSP , device->bsp , device->bsp); |
| 2076 | _(CE0 , device->ce[0] , device->ce[0]); |
| 2077 | _(CE1 , device->ce[1] , device->ce[1]); |
| 2078 | _(CE2 , device->ce[2] , device->ce[2]); |
| 2079 | _(CIPHER , device->cipher , device->cipher); |
| 2080 | _(DISP , device->disp , &device->disp->engine); |
| 2081 | _(DMAOBJ , device->dma , &device->dma->engine); |
| 2082 | _(FIFO , device->fifo , &device->fifo->engine); |
| 2083 | _(GR , device->gr , &device->gr->engine); |
| 2084 | _(IFB , device->ifb , device->ifb); |
| 2085 | _(ME , device->me , device->me); |
| 2086 | _(MPEG , device->mpeg , device->mpeg); |
| 2087 | _(MSENC , device->msenc , device->msenc); |
| 2088 | _(MSPDEC , device->mspdec , device->mspdec); |
| 2089 | _(MSPPP , device->msppp , device->msppp); |
| 2090 | _(MSVLD , device->msvld , device->msvld); |
| 2091 | _(PM , device->pm , &device->pm->engine); |
| 2092 | _(SEC , device->sec , device->sec); |
| 2093 | _(SW , device->sw , &device->sw->engine); |
| 2094 | _(VIC , device->vic , device->vic); |
| 2095 | _(VP , device->vp , device->vp); |
| 2096 | #undef _ |
| 2097 | default: |
| 2098 | WARN_ON(1); |
| 2099 | break; |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2100 | } |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2101 | return NULL; |
Ben Skeggs | 066a5d0 | 2013-04-25 11:35:18 +1000 | [diff] [blame] | 2102 | } |
| 2103 | |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2104 | int |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2105 | nvkm_device_fini(struct nvkm_device *device, bool suspend) |
| 2106 | { |
| 2107 | const char *action = suspend ? "suspend" : "fini"; |
| 2108 | struct nvkm_subdev *subdev; |
| 2109 | int ret, i; |
| 2110 | s64 time; |
| 2111 | |
| 2112 | nvdev_trace(device, "%s running...\n", action); |
| 2113 | time = ktime_to_us(ktime_get()); |
| 2114 | |
| 2115 | nvkm_acpi_fini(device); |
| 2116 | |
| 2117 | for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { |
| 2118 | if ((subdev = nvkm_device_subdev(device, i))) { |
| 2119 | ret = nvkm_subdev_fini(subdev, suspend); |
| 2120 | if (ret && suspend) |
| 2121 | goto fail; |
| 2122 | } |
| 2123 | } |
| 2124 | |
| 2125 | |
| 2126 | if (device->func->fini) |
| 2127 | device->func->fini(device, suspend); |
| 2128 | |
| 2129 | time = ktime_to_us(ktime_get()) - time; |
| 2130 | nvdev_trace(device, "%s completed in %lldus...\n", action, time); |
| 2131 | return 0; |
| 2132 | |
| 2133 | fail: |
| 2134 | do { |
| 2135 | if ((subdev = nvkm_device_subdev(device, i))) { |
| 2136 | int rret = nvkm_subdev_init(subdev); |
| 2137 | if (rret) |
| 2138 | nvkm_fatal(subdev, "failed restart, %d\n", ret); |
| 2139 | } |
| 2140 | } while (++i < NVDEV_SUBDEV_NR); |
| 2141 | |
| 2142 | nvdev_trace(device, "%s failed with %d\n", action, ret); |
| 2143 | return ret; |
| 2144 | } |
| 2145 | |
| 2146 | static int |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2147 | nvkm_device_preinit(struct nvkm_device *device) |
| 2148 | { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2149 | struct nvkm_subdev *subdev; |
| 2150 | int ret, i; |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2151 | s64 time; |
| 2152 | |
| 2153 | nvdev_trace(device, "preinit running...\n"); |
| 2154 | time = ktime_to_us(ktime_get()); |
| 2155 | |
| 2156 | if (device->func->preinit) { |
| 2157 | ret = device->func->preinit(device); |
| 2158 | if (ret) |
| 2159 | goto fail; |
| 2160 | } |
| 2161 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2162 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { |
| 2163 | if ((subdev = nvkm_device_subdev(device, i))) { |
| 2164 | ret = nvkm_subdev_preinit(subdev); |
| 2165 | if (ret) |
| 2166 | goto fail; |
| 2167 | } |
| 2168 | } |
| 2169 | |
| 2170 | /*XXX: devinit */ |
| 2171 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2172 | time = ktime_to_us(ktime_get()) - time; |
| 2173 | nvdev_trace(device, "preinit completed in %lldus\n", time); |
| 2174 | return 0; |
| 2175 | |
| 2176 | fail: |
| 2177 | nvdev_error(device, "preinit failed with %d\n", ret); |
| 2178 | return ret; |
| 2179 | } |
| 2180 | |
| 2181 | int |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2182 | nvkm_device_init(struct nvkm_device *device) |
Ben Skeggs | 066a5d0 | 2013-04-25 11:35:18 +1000 | [diff] [blame] | 2183 | { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2184 | struct nvkm_subdev *subdev; |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2185 | int ret, i = 0, c; |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2186 | s64 time; |
Ben Skeggs | ed76a87 | 2014-06-13 12:42:21 +1000 | [diff] [blame] | 2187 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2188 | ret = nvkm_device_preinit(device); |
| 2189 | if (ret) |
| 2190 | return ret; |
| 2191 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2192 | nvkm_device_fini(device, false); |
| 2193 | |
| 2194 | nvdev_trace(device, "init running...\n"); |
| 2195 | time = ktime_to_us(ktime_get()); |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2196 | |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2197 | for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2198 | #define _(s,m) case s: if (device->oclass[s] && !device->m) { \ |
Ben Skeggs | aa35888 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 2199 | ret = nvkm_object_old(nv_object(device), NULL, \ |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2200 | device->oclass[s], NULL, (s), \ |
| 2201 | (struct nvkm_object **)&device->m); \ |
| 2202 | if (ret == -ENODEV) { \ |
| 2203 | device->oclass[s] = NULL; \ |
| 2204 | continue; \ |
| 2205 | } \ |
| 2206 | if (ret) \ |
| 2207 | goto fail; \ |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2208 | } break |
| 2209 | switch (i) { |
| 2210 | _(NVDEV_SUBDEV_BAR , bar); |
| 2211 | _(NVDEV_SUBDEV_VBIOS , bios); |
| 2212 | _(NVDEV_SUBDEV_BUS , bus); |
| 2213 | _(NVDEV_SUBDEV_CLK , clk); |
| 2214 | _(NVDEV_SUBDEV_DEVINIT, devinit); |
| 2215 | _(NVDEV_SUBDEV_FB , fb); |
| 2216 | _(NVDEV_SUBDEV_FUSE , fuse); |
| 2217 | _(NVDEV_SUBDEV_GPIO , gpio); |
| 2218 | _(NVDEV_SUBDEV_I2C , i2c); |
| 2219 | _(NVDEV_SUBDEV_IBUS , ibus); |
| 2220 | _(NVDEV_SUBDEV_INSTMEM, imem); |
| 2221 | _(NVDEV_SUBDEV_LTC , ltc); |
| 2222 | _(NVDEV_SUBDEV_MC , mc); |
| 2223 | _(NVDEV_SUBDEV_MMU , mmu); |
| 2224 | _(NVDEV_SUBDEV_MXM , mxm); |
| 2225 | _(NVDEV_SUBDEV_PMU , pmu); |
| 2226 | _(NVDEV_SUBDEV_THERM , therm); |
| 2227 | _(NVDEV_SUBDEV_TIMER , timer); |
| 2228 | _(NVDEV_SUBDEV_VOLT , volt); |
| 2229 | _(NVDEV_ENGINE_BSP , bsp); |
| 2230 | _(NVDEV_ENGINE_CE0 , ce[0]); |
| 2231 | _(NVDEV_ENGINE_CE1 , ce[1]); |
| 2232 | _(NVDEV_ENGINE_CE2 , ce[2]); |
| 2233 | _(NVDEV_ENGINE_CIPHER , cipher); |
| 2234 | _(NVDEV_ENGINE_DISP , disp); |
| 2235 | _(NVDEV_ENGINE_DMAOBJ , dma); |
| 2236 | _(NVDEV_ENGINE_FIFO , fifo); |
| 2237 | _(NVDEV_ENGINE_GR , gr); |
| 2238 | _(NVDEV_ENGINE_IFB , ifb); |
| 2239 | _(NVDEV_ENGINE_ME , me); |
| 2240 | _(NVDEV_ENGINE_MPEG , mpeg); |
| 2241 | _(NVDEV_ENGINE_MSENC , msenc); |
| 2242 | _(NVDEV_ENGINE_MSPDEC , mspdec); |
| 2243 | _(NVDEV_ENGINE_MSPPP , msppp); |
| 2244 | _(NVDEV_ENGINE_MSVLD , msvld); |
| 2245 | _(NVDEV_ENGINE_PM , pm); |
| 2246 | _(NVDEV_ENGINE_SEC , sec); |
| 2247 | _(NVDEV_ENGINE_SW , sw); |
| 2248 | _(NVDEV_ENGINE_VIC , vic); |
| 2249 | _(NVDEV_ENGINE_VP , vp); |
| 2250 | default: |
| 2251 | WARN_ON(1); |
| 2252 | continue; |
| 2253 | } |
| 2254 | #undef _ |
| 2255 | |
| 2256 | /* note: can't init *any* subdevs until devinit has been run |
| 2257 | * due to not knowing exactly what the vbios init tables will |
| 2258 | * mess with. devinit also can't be run until all of its |
| 2259 | * dependencies have been created. |
| 2260 | * |
| 2261 | * this code delays init of any subdev until all of devinit's |
| 2262 | * dependencies have been created, and then initialises each |
| 2263 | * subdev in turn as they're created. |
| 2264 | */ |
| 2265 | while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2266 | if ((subdev = nvkm_device_subdev(device, c++))) { |
| 2267 | ret = nvkm_subdev_init(subdev); |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2268 | if (ret) |
| 2269 | goto fail; |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2270 | } |
| 2271 | } |
| 2272 | } |
| 2273 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2274 | nvkm_acpi_init(device); |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2275 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2276 | time = ktime_to_us(ktime_get()) - time; |
| 2277 | nvdev_trace(device, "init completed in %lldus\n", time); |
| 2278 | return 0; |
| 2279 | |
| 2280 | fail: |
| 2281 | do { |
| 2282 | if ((subdev = nvkm_device_subdev(device, i))) |
| 2283 | nvkm_subdev_fini(subdev, false); |
| 2284 | } while (--i >= 0); |
| 2285 | |
| 2286 | nvdev_error(device, "init failed with %d\n", ret); |
Ben Skeggs | 10caad3 | 2013-04-25 11:43:54 +1000 | [diff] [blame] | 2287 | return ret; |
Ben Skeggs | 066a5d0 | 2013-04-25 11:35:18 +1000 | [diff] [blame] | 2288 | } |
| 2289 | |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2290 | resource_size_t |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2291 | nv_device_resource_start(struct nvkm_device *device, unsigned int bar) |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2292 | { |
| 2293 | if (nv_device_is_pci(device)) { |
| 2294 | return pci_resource_start(device->pdev, bar); |
| 2295 | } else { |
| 2296 | struct resource *res; |
| 2297 | res = platform_get_resource(device->platformdev, |
| 2298 | IORESOURCE_MEM, bar); |
| 2299 | if (!res) |
| 2300 | return 0; |
| 2301 | return res->start; |
| 2302 | } |
| 2303 | } |
| 2304 | |
| 2305 | resource_size_t |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2306 | nv_device_resource_len(struct nvkm_device *device, unsigned int bar) |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2307 | { |
| 2308 | if (nv_device_is_pci(device)) { |
| 2309 | return pci_resource_len(device->pdev, bar); |
| 2310 | } else { |
| 2311 | struct resource *res; |
| 2312 | res = platform_get_resource(device->platformdev, |
| 2313 | IORESOURCE_MEM, bar); |
| 2314 | if (!res) |
| 2315 | return 0; |
| 2316 | return resource_size(res); |
| 2317 | } |
| 2318 | } |
| 2319 | |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2320 | int |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2321 | nv_device_get_irq(struct nvkm_device *device, bool stall) |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2322 | { |
| 2323 | if (nv_device_is_pci(device)) { |
| 2324 | return device->pdev->irq; |
| 2325 | } else { |
| 2326 | return platform_get_irq_byname(device->platformdev, |
| 2327 | stall ? "stall" : "nonstall"); |
| 2328 | } |
| 2329 | } |
| 2330 | |
Ben Skeggs | e781dc8 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2331 | void |
| 2332 | nvkm_device_del(struct nvkm_device **pdevice) |
| 2333 | { |
| 2334 | struct nvkm_device *device = *pdevice; |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2335 | int i; |
Ben Skeggs | e781dc8 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2336 | if (device) { |
Ben Skeggs | e781dc8 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2337 | mutex_lock(&nv_devices_mutex); |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2338 | device->disable_mask = 0; |
| 2339 | for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { |
| 2340 | struct nvkm_subdev *subdev = |
| 2341 | nvkm_device_subdev(device, i); |
| 2342 | nvkm_subdev_del(&subdev); |
| 2343 | } |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2344 | |
| 2345 | nvkm_event_fini(&device->event); |
Ben Skeggs | e781dc8 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2346 | |
| 2347 | if (device->pri) |
| 2348 | iounmap(device->pri); |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2349 | list_del(&device->head); |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2350 | |
| 2351 | if (device->func->dtor) |
| 2352 | *pdevice = device->func->dtor(device); |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2353 | mutex_unlock(&nv_devices_mutex); |
Ben Skeggs | e781dc8 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2354 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2355 | kfree(*pdevice); |
Ben Skeggs | e781dc8 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2356 | *pdevice = NULL; |
| 2357 | } |
| 2358 | } |
| 2359 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2360 | static const struct nvkm_engine_func |
| 2361 | nvkm_device_func = { |
| 2362 | }; |
| 2363 | |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2364 | int |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2365 | nvkm_device_ctor(const struct nvkm_device_func *func, |
| 2366 | const struct nvkm_device_quirk *quirk, |
| 2367 | void *dev, enum nv_bus_type type, u64 handle, |
| 2368 | const char *name, const char *cfg, const char *dbg, |
| 2369 | bool detect, bool mmio, u64 subdev_mask, |
| 2370 | struct nvkm_device *device) |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2371 | { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2372 | struct nvkm_subdev *subdev; |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2373 | u64 mmio_base, mmio_size; |
| 2374 | u32 boot0, strap; |
| 2375 | void __iomem *map; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2376 | int ret = -EEXIST; |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2377 | int i; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2378 | |
| 2379 | mutex_lock(&nv_devices_mutex); |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2380 | if (nvkm_device_find_locked(handle)) |
| 2381 | goto done; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2382 | |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2383 | device->func = func; |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2384 | device->quirk = quirk; |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2385 | switch (type) { |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2386 | case NVKM_BUS_PCI: |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2387 | device->pdev = dev; |
Ben Skeggs | 6d0d40e | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 2388 | device->dev = &device->pdev->dev; |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2389 | break; |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2390 | case NVKM_BUS_PLATFORM: |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2391 | device->platformdev = dev; |
Ben Skeggs | 6d0d40e | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 2392 | device->dev = &device->platformdev->dev; |
Alexandre Courbot | 420b946 | 2014-02-17 15:17:26 +0900 | [diff] [blame] | 2393 | break; |
| 2394 | } |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2395 | device->handle = handle; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2396 | device->cfgopt = cfg; |
| 2397 | device->dbgopt = dbg; |
Ben Skeggs | 7974dd1 | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2398 | device->name = name; |
Ben Skeggs | 0d5dd3f | 2015-08-20 14:54:05 +1000 | [diff] [blame] | 2399 | list_add_tail(&device->head, &nv_devices); |
Ben Skeggs | ed76a87 | 2014-06-13 12:42:21 +1000 | [diff] [blame] | 2400 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2401 | ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0, |
| 2402 | true, &device->engine); |
| 2403 | device->engine.subdev.object.parent = NULL; |
| 2404 | if (ret) |
| 2405 | goto done; |
| 2406 | |
Ben Skeggs | 9719047 | 2015-01-14 15:35:00 +1000 | [diff] [blame] | 2407 | ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2408 | if (ret) |
| 2409 | goto done; |
| 2410 | |
| 2411 | mmio_base = nv_device_resource_start(device, 0); |
| 2412 | mmio_size = nv_device_resource_len(device, 0); |
| 2413 | |
| 2414 | /* identify the chipset, and determine classes of subdev/engines */ |
| 2415 | if (detect) { |
| 2416 | map = ioremap(mmio_base, 0x102000); |
| 2417 | if (ret = -ENOMEM, map == NULL) |
| 2418 | goto done; |
| 2419 | |
| 2420 | /* switch mmio to cpu's native endianness */ |
| 2421 | #ifndef __BIG_ENDIAN |
| 2422 | if (ioread32_native(map + 0x000004) != 0x00000000) { |
| 2423 | #else |
| 2424 | if (ioread32_native(map + 0x000004) == 0x00000000) { |
| 2425 | #endif |
| 2426 | iowrite32_native(0x01000001, map + 0x000004); |
| 2427 | ioread32_native(map); |
| 2428 | } |
| 2429 | |
| 2430 | /* read boot0 and strapping information */ |
| 2431 | boot0 = ioread32_native(map + 0x000000); |
| 2432 | strap = ioread32_native(map + 0x101000); |
| 2433 | iounmap(map); |
| 2434 | |
| 2435 | /* determine chipset and derive architecture from it */ |
| 2436 | if ((boot0 & 0x1f000000) > 0) { |
| 2437 | device->chipset = (boot0 & 0x1ff00000) >> 20; |
| 2438 | device->chiprev = (boot0 & 0x000000ff); |
| 2439 | switch (device->chipset & 0x1f0) { |
| 2440 | case 0x010: { |
| 2441 | if (0x461 & (1 << (device->chipset & 0xf))) |
| 2442 | device->card_type = NV_10; |
| 2443 | else |
| 2444 | device->card_type = NV_11; |
| 2445 | device->chiprev = 0x00; |
| 2446 | break; |
| 2447 | } |
| 2448 | case 0x020: device->card_type = NV_20; break; |
| 2449 | case 0x030: device->card_type = NV_30; break; |
| 2450 | case 0x040: |
| 2451 | case 0x060: device->card_type = NV_40; break; |
| 2452 | case 0x050: |
| 2453 | case 0x080: |
| 2454 | case 0x090: |
| 2455 | case 0x0a0: device->card_type = NV_50; break; |
| 2456 | case 0x0c0: |
| 2457 | case 0x0d0: device->card_type = NV_C0; break; |
| 2458 | case 0x0e0: |
| 2459 | case 0x0f0: |
| 2460 | case 0x100: device->card_type = NV_E0; break; |
| 2461 | case 0x110: |
| 2462 | case 0x120: device->card_type = GM100; break; |
| 2463 | default: |
| 2464 | break; |
| 2465 | } |
| 2466 | } else |
| 2467 | if ((boot0 & 0xff00fff0) == 0x20004000) { |
| 2468 | if (boot0 & 0x00f00000) |
| 2469 | device->chipset = 0x05; |
| 2470 | else |
| 2471 | device->chipset = 0x04; |
| 2472 | device->card_type = NV_04; |
| 2473 | } |
| 2474 | |
| 2475 | switch (device->card_type) { |
| 2476 | case NV_04: ret = nv04_identify(device); break; |
| 2477 | case NV_10: |
| 2478 | case NV_11: ret = nv10_identify(device); break; |
| 2479 | case NV_20: ret = nv20_identify(device); break; |
| 2480 | case NV_30: ret = nv30_identify(device); break; |
| 2481 | case NV_40: ret = nv40_identify(device); break; |
| 2482 | case NV_50: ret = nv50_identify(device); break; |
| 2483 | case NV_C0: ret = gf100_identify(device); break; |
| 2484 | case NV_E0: ret = gk104_identify(device); break; |
| 2485 | case GM100: ret = gm100_identify(device); break; |
| 2486 | default: |
| 2487 | ret = -EINVAL; |
| 2488 | break; |
| 2489 | } |
| 2490 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2491 | switch (!ret * device->chipset) { |
| 2492 | case 0x004: device->chip = &nv4_chipset; break; |
| 2493 | case 0x005: device->chip = &nv5_chipset; break; |
| 2494 | case 0x010: device->chip = &nv10_chipset; break; |
| 2495 | case 0x011: device->chip = &nv11_chipset; break; |
| 2496 | case 0x015: device->chip = &nv15_chipset; break; |
| 2497 | case 0x017: device->chip = &nv17_chipset; break; |
| 2498 | case 0x018: device->chip = &nv18_chipset; break; |
| 2499 | case 0x01a: device->chip = &nv1a_chipset; break; |
| 2500 | case 0x01f: device->chip = &nv1f_chipset; break; |
| 2501 | case 0x020: device->chip = &nv20_chipset; break; |
| 2502 | case 0x025: device->chip = &nv25_chipset; break; |
| 2503 | case 0x028: device->chip = &nv28_chipset; break; |
| 2504 | case 0x02a: device->chip = &nv2a_chipset; break; |
| 2505 | case 0x030: device->chip = &nv30_chipset; break; |
| 2506 | case 0x031: device->chip = &nv31_chipset; break; |
| 2507 | case 0x034: device->chip = &nv34_chipset; break; |
| 2508 | case 0x035: device->chip = &nv35_chipset; break; |
| 2509 | case 0x036: device->chip = &nv36_chipset; break; |
| 2510 | case 0x040: device->chip = &nv40_chipset; break; |
| 2511 | case 0x041: device->chip = &nv41_chipset; break; |
| 2512 | case 0x042: device->chip = &nv42_chipset; break; |
| 2513 | case 0x043: device->chip = &nv43_chipset; break; |
| 2514 | case 0x044: device->chip = &nv44_chipset; break; |
| 2515 | case 0x045: device->chip = &nv45_chipset; break; |
| 2516 | case 0x046: device->chip = &nv46_chipset; break; |
| 2517 | case 0x047: device->chip = &nv47_chipset; break; |
| 2518 | case 0x049: device->chip = &nv49_chipset; break; |
| 2519 | case 0x04a: device->chip = &nv4a_chipset; break; |
| 2520 | case 0x04b: device->chip = &nv4b_chipset; break; |
| 2521 | case 0x04c: device->chip = &nv4c_chipset; break; |
| 2522 | case 0x04e: device->chip = &nv4e_chipset; break; |
| 2523 | case 0x050: device->chip = &nv50_chipset; break; |
| 2524 | case 0x063: device->chip = &nv63_chipset; break; |
| 2525 | case 0x067: device->chip = &nv67_chipset; break; |
| 2526 | case 0x068: device->chip = &nv68_chipset; break; |
| 2527 | case 0x084: device->chip = &nv84_chipset; break; |
| 2528 | case 0x086: device->chip = &nv86_chipset; break; |
| 2529 | case 0x092: device->chip = &nv92_chipset; break; |
| 2530 | case 0x094: device->chip = &nv94_chipset; break; |
| 2531 | case 0x096: device->chip = &nv96_chipset; break; |
| 2532 | case 0x098: device->chip = &nv98_chipset; break; |
| 2533 | case 0x0a0: device->chip = &nva0_chipset; break; |
| 2534 | case 0x0a3: device->chip = &nva3_chipset; break; |
| 2535 | case 0x0a5: device->chip = &nva5_chipset; break; |
| 2536 | case 0x0a8: device->chip = &nva8_chipset; break; |
| 2537 | case 0x0aa: device->chip = &nvaa_chipset; break; |
| 2538 | case 0x0ac: device->chip = &nvac_chipset; break; |
| 2539 | case 0x0af: device->chip = &nvaf_chipset; break; |
| 2540 | case 0x0c0: device->chip = &nvc0_chipset; break; |
| 2541 | case 0x0c1: device->chip = &nvc1_chipset; break; |
| 2542 | case 0x0c3: device->chip = &nvc3_chipset; break; |
| 2543 | case 0x0c4: device->chip = &nvc4_chipset; break; |
| 2544 | case 0x0c8: device->chip = &nvc8_chipset; break; |
| 2545 | case 0x0ce: device->chip = &nvce_chipset; break; |
| 2546 | case 0x0cf: device->chip = &nvcf_chipset; break; |
| 2547 | case 0x0d7: device->chip = &nvd7_chipset; break; |
| 2548 | case 0x0d9: device->chip = &nvd9_chipset; break; |
| 2549 | case 0x0e4: device->chip = &nve4_chipset; break; |
| 2550 | case 0x0e6: device->chip = &nve6_chipset; break; |
| 2551 | case 0x0e7: device->chip = &nve7_chipset; break; |
| 2552 | case 0x0ea: device->chip = &nvea_chipset; break; |
| 2553 | case 0x0f0: device->chip = &nvf0_chipset; break; |
| 2554 | case 0x0f1: device->chip = &nvf1_chipset; break; |
| 2555 | case 0x106: device->chip = &nv106_chipset; break; |
| 2556 | case 0x108: device->chip = &nv108_chipset; break; |
| 2557 | case 0x117: device->chip = &nv117_chipset; break; |
| 2558 | case 0x124: device->chip = &nv124_chipset; break; |
| 2559 | case 0x126: device->chip = &nv126_chipset; break; |
| 2560 | case 0x12b: device->chip = &nv12b_chipset; break; |
| 2561 | default: |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2562 | nvdev_error(device, "unknown chipset (%08x)\n", boot0); |
| 2563 | goto done; |
| 2564 | } |
| 2565 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2566 | nvdev_info(device, "NVIDIA %s (%08x)\n", |
| 2567 | device->chip->name, boot0); |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2568 | |
| 2569 | /* determine frequency of timing crystal */ |
| 2570 | if ( device->card_type <= NV_10 || device->chipset < 0x17 || |
| 2571 | (device->chipset >= 0x20 && device->chipset < 0x25)) |
| 2572 | strap &= 0x00000040; |
| 2573 | else |
| 2574 | strap &= 0x00400040; |
| 2575 | |
| 2576 | switch (strap) { |
| 2577 | case 0x00000000: device->crystal = 13500; break; |
| 2578 | case 0x00000040: device->crystal = 14318; break; |
| 2579 | case 0x00400000: device->crystal = 27000; break; |
| 2580 | case 0x00400040: device->crystal = 25000; break; |
| 2581 | } |
| 2582 | } else { |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2583 | device->chip = &null_chipset; |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2584 | } |
| 2585 | |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2586 | if (!device->name) |
| 2587 | device->name = device->chip->name; |
| 2588 | |
Ben Skeggs | 0ac9d21 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2589 | if (mmio) { |
| 2590 | device->pri = ioremap(mmio_base, mmio_size); |
| 2591 | if (!device->pri) { |
| 2592 | nvdev_error(device, "unable to map PRI\n"); |
| 2593 | return -ENOMEM; |
| 2594 | } |
| 2595 | } |
| 2596 | |
| 2597 | /* disable subdevs that aren't required (used by tools) */ |
| 2598 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { |
| 2599 | if (!(subdev_mask & (1ULL << i))) |
| 2600 | device->oclass[i] = NULL; |
| 2601 | } |
| 2602 | |
Ben Skeggs | a1e8873 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2603 | atomic_set(&device->engine.subdev.object.usecount, 2); |
| 2604 | mutex_init(&device->mutex); |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 2605 | |
| 2606 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { |
| 2607 | #define _(s,m) case s: \ |
| 2608 | if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ |
| 2609 | ret = device->chip->m(device, (s), &device->m); \ |
| 2610 | if (ret) { \ |
| 2611 | subdev = nvkm_device_subdev(device, (s)); \ |
| 2612 | nvkm_subdev_del(&subdev); \ |
| 2613 | device->m = NULL; \ |
| 2614 | if (ret != -ENODEV) { \ |
| 2615 | nvdev_error(device, "%s ctor failed, %d\n", \ |
| 2616 | nvkm_subdev_name[s], ret); \ |
| 2617 | goto done; \ |
| 2618 | } \ |
| 2619 | } \ |
| 2620 | } \ |
| 2621 | break |
| 2622 | switch (i) { |
| 2623 | _(NVDEV_SUBDEV_BAR , bar); |
| 2624 | _(NVDEV_SUBDEV_VBIOS , bios); |
| 2625 | _(NVDEV_SUBDEV_BUS , bus); |
| 2626 | _(NVDEV_SUBDEV_CLK , clk); |
| 2627 | _(NVDEV_SUBDEV_DEVINIT, devinit); |
| 2628 | _(NVDEV_SUBDEV_FB , fb); |
| 2629 | _(NVDEV_SUBDEV_FUSE , fuse); |
| 2630 | _(NVDEV_SUBDEV_GPIO , gpio); |
| 2631 | _(NVDEV_SUBDEV_I2C , i2c); |
| 2632 | _(NVDEV_SUBDEV_IBUS , ibus); |
| 2633 | _(NVDEV_SUBDEV_INSTMEM, imem); |
| 2634 | _(NVDEV_SUBDEV_LTC , ltc); |
| 2635 | _(NVDEV_SUBDEV_MC , mc); |
| 2636 | _(NVDEV_SUBDEV_MMU , mmu); |
| 2637 | _(NVDEV_SUBDEV_MXM , mxm); |
| 2638 | _(NVDEV_SUBDEV_PMU , pmu); |
| 2639 | _(NVDEV_SUBDEV_THERM , therm); |
| 2640 | _(NVDEV_SUBDEV_TIMER , timer); |
| 2641 | _(NVDEV_SUBDEV_VOLT , volt); |
| 2642 | _(NVDEV_ENGINE_BSP , bsp); |
| 2643 | _(NVDEV_ENGINE_CE0 , ce[0]); |
| 2644 | _(NVDEV_ENGINE_CE1 , ce[1]); |
| 2645 | _(NVDEV_ENGINE_CE2 , ce[2]); |
| 2646 | _(NVDEV_ENGINE_CIPHER , cipher); |
| 2647 | _(NVDEV_ENGINE_DISP , disp); |
| 2648 | _(NVDEV_ENGINE_DMAOBJ , dma); |
| 2649 | _(NVDEV_ENGINE_FIFO , fifo); |
| 2650 | _(NVDEV_ENGINE_GR , gr); |
| 2651 | _(NVDEV_ENGINE_IFB , ifb); |
| 2652 | _(NVDEV_ENGINE_ME , me); |
| 2653 | _(NVDEV_ENGINE_MPEG , mpeg); |
| 2654 | _(NVDEV_ENGINE_MSENC , msenc); |
| 2655 | _(NVDEV_ENGINE_MSPDEC , mspdec); |
| 2656 | _(NVDEV_ENGINE_MSPPP , msppp); |
| 2657 | _(NVDEV_ENGINE_MSVLD , msvld); |
| 2658 | _(NVDEV_ENGINE_PM , pm); |
| 2659 | _(NVDEV_ENGINE_SEC , sec); |
| 2660 | _(NVDEV_ENGINE_SW , sw); |
| 2661 | _(NVDEV_ENGINE_VIC , vic); |
| 2662 | _(NVDEV_ENGINE_VP , vp); |
| 2663 | default: |
| 2664 | WARN_ON(1); |
| 2665 | continue; |
| 2666 | } |
| 2667 | #undef _ |
| 2668 | } |
| 2669 | |
| 2670 | ret = 0; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 2671 | done: |
| 2672 | mutex_unlock(&nv_devices_mutex); |
| 2673 | return ret; |
| 2674 | } |