Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 CPU idle Routines |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Instruments, Inc. |
| 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 6 | * Rajendra Nayak <rnayak@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/sched.h> |
| 14 | #include <linux/cpuidle.h> |
| 15 | #include <linux/cpu_pm.h> |
| 16 | #include <linux/export.h> |
Santosh Shilimkar | 98be0dd | 2011-01-16 00:42:31 +0530 | [diff] [blame] | 17 | #include <linux/clockchips.h> |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 18 | |
| 19 | #include <asm/proc-fns.h> |
| 20 | |
| 21 | #include "common.h" |
| 22 | #include "pm.h" |
| 23 | #include "prm.h" |
| 24 | |
| 25 | #ifdef CONFIG_CPU_IDLE |
| 26 | |
| 27 | /* Machine specific information to be recorded in the C-state driver_data */ |
| 28 | struct omap4_idle_statedata { |
| 29 | u32 cpu_state; |
| 30 | u32 mpu_logic_state; |
| 31 | u32 mpu_state; |
| 32 | u8 valid; |
| 33 | }; |
| 34 | |
| 35 | static struct cpuidle_params cpuidle_params_table[] = { |
| 36 | /* C1 - CPU0 ON + CPU1 ON + MPU ON */ |
| 37 | {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, |
| 38 | /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ |
| 39 | {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, |
| 40 | /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ |
| 41 | {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, |
| 42 | }; |
| 43 | |
| 44 | #define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table) |
| 45 | |
| 46 | struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES]; |
| 47 | static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; |
| 48 | |
| 49 | /** |
| 50 | * omap4_enter_idle - Programs OMAP4 to enter the specified state |
| 51 | * @dev: cpuidle device |
| 52 | * @drv: cpuidle driver |
| 53 | * @index: the index of state to be entered |
| 54 | * |
| 55 | * Called from the CPUidle framework to program the device to the |
| 56 | * specified low power state selected by the governor. |
| 57 | * Returns the amount of time spent in the low power state. |
| 58 | */ |
| 59 | static int omap4_enter_idle(struct cpuidle_device *dev, |
| 60 | struct cpuidle_driver *drv, |
| 61 | int index) |
| 62 | { |
| 63 | struct omap4_idle_statedata *cx = |
| 64 | cpuidle_get_statedata(&dev->states_usage[index]); |
| 65 | struct timespec ts_preidle, ts_postidle, ts_idle; |
| 66 | u32 cpu1_state; |
| 67 | int idle_time; |
Santosh Shilimkar | 98be0dd | 2011-01-16 00:42:31 +0530 | [diff] [blame] | 68 | int cpu_id = smp_processor_id(); |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 69 | |
| 70 | /* Used to keep track of the total time in idle */ |
| 71 | getnstimeofday(&ts_preidle); |
| 72 | |
| 73 | local_irq_disable(); |
| 74 | local_fiq_disable(); |
| 75 | |
| 76 | /* |
| 77 | * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state. |
| 78 | * This is necessary to honour hardware recommondation |
| 79 | * of triggeing all the possible low power modes once CPU1 is |
| 80 | * out of coherency and in OFF mode. |
| 81 | * Update dev->last_state so that governor stats reflects right |
| 82 | * data. |
| 83 | */ |
| 84 | cpu1_state = pwrdm_read_pwrst(cpu1_pd); |
| 85 | if (cpu1_state != PWRDM_POWER_OFF) { |
Santosh Shilimkar | 03e4fd6 | 2012-02-05 13:18:44 +0530 | [diff] [blame^] | 86 | index = drv->safe_state_index; |
| 87 | cx = cpuidle_get_statedata(&dev->states_usage[index]); |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 88 | } |
| 89 | |
Santosh Shilimkar | 98be0dd | 2011-01-16 00:42:31 +0530 | [diff] [blame] | 90 | if (index > 0) |
| 91 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id); |
| 92 | |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 93 | /* |
| 94 | * Call idle CPU PM enter notifier chain so that |
| 95 | * VFP and per CPU interrupt context is saved. |
| 96 | */ |
| 97 | if (cx->cpu_state == PWRDM_POWER_OFF) |
| 98 | cpu_pm_enter(); |
| 99 | |
| 100 | pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); |
| 101 | omap_set_pwrdm_state(mpu_pd, cx->mpu_state); |
| 102 | |
| 103 | /* |
| 104 | * Call idle CPU cluster PM enter notifier chain |
| 105 | * to save GIC and wakeupgen context. |
| 106 | */ |
| 107 | if ((cx->mpu_state == PWRDM_POWER_RET) && |
| 108 | (cx->mpu_logic_state == PWRDM_POWER_OFF)) |
| 109 | cpu_cluster_pm_enter(); |
| 110 | |
| 111 | omap4_enter_lowpower(dev->cpu, cx->cpu_state); |
| 112 | |
| 113 | /* |
| 114 | * Call idle CPU PM exit notifier chain to restore |
| 115 | * VFP and per CPU IRQ context. Only CPU0 state is |
| 116 | * considered since CPU1 is managed by CPU hotplug. |
| 117 | */ |
| 118 | if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF) |
| 119 | cpu_pm_exit(); |
| 120 | |
| 121 | /* |
| 122 | * Call idle CPU cluster PM exit notifier chain |
| 123 | * to restore GIC and wakeupgen context. |
| 124 | */ |
| 125 | if (omap4_mpuss_read_prev_context_state()) |
| 126 | cpu_cluster_pm_exit(); |
| 127 | |
Santosh Shilimkar | 98be0dd | 2011-01-16 00:42:31 +0530 | [diff] [blame] | 128 | if (index > 0) |
| 129 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id); |
| 130 | |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 131 | getnstimeofday(&ts_postidle); |
| 132 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
| 133 | |
| 134 | local_irq_enable(); |
| 135 | local_fiq_enable(); |
| 136 | |
| 137 | idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \ |
| 138 | USEC_PER_SEC; |
| 139 | |
| 140 | /* Update cpuidle counters */ |
| 141 | dev->last_residency = idle_time; |
| 142 | |
| 143 | return index; |
| 144 | } |
| 145 | |
| 146 | DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); |
| 147 | |
| 148 | struct cpuidle_driver omap4_idle_driver = { |
| 149 | .name = "omap4_idle", |
| 150 | .owner = THIS_MODULE, |
| 151 | }; |
| 152 | |
| 153 | static inline void _fill_cstate(struct cpuidle_driver *drv, |
| 154 | int idx, const char *descr) |
| 155 | { |
| 156 | struct cpuidle_state *state = &drv->states[idx]; |
| 157 | |
| 158 | state->exit_latency = cpuidle_params_table[idx].exit_latency; |
| 159 | state->target_residency = cpuidle_params_table[idx].target_residency; |
| 160 | state->flags = CPUIDLE_FLAG_TIME_VALID; |
| 161 | state->enter = omap4_enter_idle; |
| 162 | sprintf(state->name, "C%d", idx + 1); |
| 163 | strncpy(state->desc, descr, CPUIDLE_DESC_LEN); |
| 164 | } |
| 165 | |
| 166 | static inline struct omap4_idle_statedata *_fill_cstate_usage( |
| 167 | struct cpuidle_device *dev, |
| 168 | int idx) |
| 169 | { |
| 170 | struct omap4_idle_statedata *cx = &omap4_idle_data[idx]; |
| 171 | struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; |
| 172 | |
| 173 | cx->valid = cpuidle_params_table[idx].valid; |
| 174 | cpuidle_set_statedata(state_usage, cx); |
| 175 | |
| 176 | return cx; |
| 177 | } |
| 178 | |
| 179 | |
| 180 | |
| 181 | /** |
| 182 | * omap4_idle_init - Init routine for OMAP4 idle |
| 183 | * |
| 184 | * Registers the OMAP4 specific cpuidle driver to the cpuidle |
| 185 | * framework with the valid set of states. |
| 186 | */ |
| 187 | int __init omap4_idle_init(void) |
| 188 | { |
| 189 | struct omap4_idle_statedata *cx; |
| 190 | struct cpuidle_device *dev; |
| 191 | struct cpuidle_driver *drv = &omap4_idle_driver; |
| 192 | unsigned int cpu_id = 0; |
| 193 | |
| 194 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); |
| 195 | cpu0_pd = pwrdm_lookup("cpu0_pwrdm"); |
| 196 | cpu1_pd = pwrdm_lookup("cpu1_pwrdm"); |
| 197 | if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) |
| 198 | return -ENODEV; |
| 199 | |
| 200 | |
| 201 | drv->safe_state_index = -1; |
| 202 | dev = &per_cpu(omap4_idle_dev, cpu_id); |
| 203 | dev->cpu = cpu_id; |
| 204 | |
| 205 | /* C1 - CPU0 ON + CPU1 ON + MPU ON */ |
| 206 | _fill_cstate(drv, 0, "MPUSS ON"); |
| 207 | drv->safe_state_index = 0; |
| 208 | cx = _fill_cstate_usage(dev, 0); |
| 209 | cx->valid = 1; /* C1 is always valid */ |
| 210 | cx->cpu_state = PWRDM_POWER_ON; |
| 211 | cx->mpu_state = PWRDM_POWER_ON; |
| 212 | cx->mpu_logic_state = PWRDM_POWER_RET; |
| 213 | |
| 214 | /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ |
| 215 | _fill_cstate(drv, 1, "MPUSS CSWR"); |
| 216 | cx = _fill_cstate_usage(dev, 1); |
| 217 | cx->cpu_state = PWRDM_POWER_OFF; |
| 218 | cx->mpu_state = PWRDM_POWER_RET; |
| 219 | cx->mpu_logic_state = PWRDM_POWER_RET; |
| 220 | |
| 221 | /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ |
| 222 | _fill_cstate(drv, 2, "MPUSS OSWR"); |
| 223 | cx = _fill_cstate_usage(dev, 2); |
| 224 | cx->cpu_state = PWRDM_POWER_OFF; |
| 225 | cx->mpu_state = PWRDM_POWER_RET; |
| 226 | cx->mpu_logic_state = PWRDM_POWER_OFF; |
| 227 | |
| 228 | drv->state_count = OMAP4_NUM_STATES; |
| 229 | cpuidle_register_driver(&omap4_idle_driver); |
| 230 | |
| 231 | dev->state_count = OMAP4_NUM_STATES; |
| 232 | if (cpuidle_register_device(dev)) { |
| 233 | pr_err("%s: CPUidle register device failed\n", __func__); |
| 234 | return -EIO; |
| 235 | } |
| 236 | |
| 237 | return 0; |
| 238 | } |
| 239 | #else |
| 240 | int __init omap4_idle_init(void) |
| 241 | { |
| 242 | return 0; |
| 243 | } |
| 244 | #endif /* CONFIG_CPU_IDLE */ |