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Magnus Dammd5ed4c22009-04-30 07:02:49 +00001/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clockchips.h>
Paul Mundt46a12f72009-05-03 17:57:17 +090031#include <linux/sh_timer.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Magnus Dammd5ed4c22009-04-30 07:02:49 +000033
34struct sh_mtu2_priv {
35 void __iomem *mapbase;
36 struct clk *clk;
37 struct irqaction irqaction;
38 struct platform_device *pdev;
39 unsigned long rate;
40 unsigned long periodic;
41 struct clock_event_device ced;
42};
43
44static DEFINE_SPINLOCK(sh_mtu2_lock);
45
46#define TSTR -1 /* shared register */
47#define TCR 0 /* channel register */
48#define TMDR 1 /* channel register */
49#define TIOR 2 /* channel register */
50#define TIER 3 /* channel register */
51#define TSR 4 /* channel register */
52#define TCNT 5 /* channel register */
53#define TGR 6 /* channel register */
54
55static unsigned long mtu2_reg_offs[] = {
56 [TCR] = 0,
57 [TMDR] = 1,
58 [TIOR] = 2,
59 [TIER] = 4,
60 [TSR] = 5,
61 [TCNT] = 6,
62 [TGR] = 8,
63};
64
65static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
66{
Paul Mundt46a12f72009-05-03 17:57:17 +090067 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Dammd5ed4c22009-04-30 07:02:49 +000068 void __iomem *base = p->mapbase;
69 unsigned long offs;
70
71 if (reg_nr == TSTR)
72 return ioread8(base + cfg->channel_offset);
73
74 offs = mtu2_reg_offs[reg_nr];
75
76 if ((reg_nr == TCNT) || (reg_nr == TGR))
77 return ioread16(base + offs);
78 else
79 return ioread8(base + offs);
80}
81
82static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
83 unsigned long value)
84{
Paul Mundt46a12f72009-05-03 17:57:17 +090085 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Dammd5ed4c22009-04-30 07:02:49 +000086 void __iomem *base = p->mapbase;
87 unsigned long offs;
88
89 if (reg_nr == TSTR) {
90 iowrite8(value, base + cfg->channel_offset);
91 return;
92 }
93
94 offs = mtu2_reg_offs[reg_nr];
95
96 if ((reg_nr == TCNT) || (reg_nr == TGR))
97 iowrite16(value, base + offs);
98 else
99 iowrite8(value, base + offs);
100}
101
102static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
103{
Paul Mundt46a12f72009-05-03 17:57:17 +0900104 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000105 unsigned long flags, value;
106
107 /* start stop register shared by multiple timer channels */
108 spin_lock_irqsave(&sh_mtu2_lock, flags);
109 value = sh_mtu2_read(p, TSTR);
110
111 if (start)
112 value |= 1 << cfg->timer_bit;
113 else
114 value &= ~(1 << cfg->timer_bit);
115
116 sh_mtu2_write(p, TSTR, value);
117 spin_unlock_irqrestore(&sh_mtu2_lock, flags);
118}
119
120static int sh_mtu2_enable(struct sh_mtu2_priv *p)
121{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000122 int ret;
123
124 /* enable clock */
125 ret = clk_enable(p->clk);
126 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900127 dev_err(&p->pdev->dev, "cannot enable clock\n");
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000128 return ret;
129 }
130
131 /* make sure channel is disabled */
132 sh_mtu2_start_stop_ch(p, 0);
133
134 p->rate = clk_get_rate(p->clk) / 64;
135 p->periodic = (p->rate + HZ/2) / HZ;
136
137 /* "Periodic Counter Operation" */
138 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
139 sh_mtu2_write(p, TIOR, 0);
140 sh_mtu2_write(p, TGR, p->periodic);
141 sh_mtu2_write(p, TCNT, 0);
142 sh_mtu2_write(p, TMDR, 0);
143 sh_mtu2_write(p, TIER, 0x01);
144
145 /* enable channel */
146 sh_mtu2_start_stop_ch(p, 1);
147
148 return 0;
149}
150
151static void sh_mtu2_disable(struct sh_mtu2_priv *p)
152{
153 /* disable channel */
154 sh_mtu2_start_stop_ch(p, 0);
155
156 /* stop clock */
157 clk_disable(p->clk);
158}
159
160static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
161{
162 struct sh_mtu2_priv *p = dev_id;
163
164 /* acknowledge interrupt */
165 sh_mtu2_read(p, TSR);
166 sh_mtu2_write(p, TSR, 0xfe);
167
168 /* notify clockevent layer */
169 p->ced.event_handler(&p->ced);
170 return IRQ_HANDLED;
171}
172
173static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
174{
175 return container_of(ced, struct sh_mtu2_priv, ced);
176}
177
178static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
179 struct clock_event_device *ced)
180{
181 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
182 int disabled = 0;
183
184 /* deal with old setting first */
185 switch (ced->mode) {
186 case CLOCK_EVT_MODE_PERIODIC:
187 sh_mtu2_disable(p);
188 disabled = 1;
189 break;
190 default:
191 break;
192 }
193
194 switch (mode) {
195 case CLOCK_EVT_MODE_PERIODIC:
Paul Mundt214a6072010-03-10 16:26:25 +0900196 dev_info(&p->pdev->dev, "used for periodic clock events\n");
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000197 sh_mtu2_enable(p);
198 break;
199 case CLOCK_EVT_MODE_UNUSED:
200 if (!disabled)
201 sh_mtu2_disable(p);
202 break;
203 case CLOCK_EVT_MODE_SHUTDOWN:
204 default:
205 break;
206 }
207}
208
209static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
210 char *name, unsigned long rating)
211{
212 struct clock_event_device *ced = &p->ced;
213 int ret;
214
215 memset(ced, 0, sizeof(*ced));
216
217 ced->name = name;
218 ced->features = CLOCK_EVT_FEAT_PERIODIC;
219 ced->rating = rating;
220 ced->cpumask = cpumask_of(0);
221 ced->set_mode = sh_mtu2_clock_event_mode;
222
Paul Mundt214a6072010-03-10 16:26:25 +0900223 dev_info(&p->pdev->dev, "used for clock events\n");
Paul Mundtda64c2a2010-02-25 16:37:46 +0900224 clockevents_register_device(ced);
225
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000226 ret = setup_irq(p->irqaction.irq, &p->irqaction);
227 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900228 dev_err(&p->pdev->dev, "failed to request irq %d\n",
229 p->irqaction.irq);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000230 return;
231 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000232}
233
Paul Mundtd1fcc0a2009-05-03 18:05:42 +0900234static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
235 unsigned long clockevent_rating)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000236{
237 if (clockevent_rating)
238 sh_mtu2_register_clockevent(p, name, clockevent_rating);
239
240 return 0;
241}
242
243static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
244{
Paul Mundt46a12f72009-05-03 17:57:17 +0900245 struct sh_timer_config *cfg = pdev->dev.platform_data;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000246 struct resource *res;
247 int irq, ret;
248 ret = -ENXIO;
249
250 memset(p, 0, sizeof(*p));
251 p->pdev = pdev;
252
253 if (!cfg) {
254 dev_err(&p->pdev->dev, "missing platform data\n");
255 goto err0;
256 }
257
258 platform_set_drvdata(pdev, p);
259
260 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
261 if (!res) {
262 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
263 goto err0;
264 }
265
266 irq = platform_get_irq(p->pdev, 0);
267 if (irq < 0) {
268 dev_err(&p->pdev->dev, "failed to get irq\n");
269 goto err0;
270 }
271
272 /* map memory, let mapbase point to our channel */
273 p->mapbase = ioremap_nocache(res->start, resource_size(res));
274 if (p->mapbase == NULL) {
Paul Mundt214a6072010-03-10 16:26:25 +0900275 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000276 goto err0;
277 }
278
279 /* setup data for setup_irq() (too early for request_irq()) */
Paul Mundt214a6072010-03-10 16:26:25 +0900280 p->irqaction.name = dev_name(&p->pdev->dev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000281 p->irqaction.handler = sh_mtu2_interrupt;
282 p->irqaction.dev_id = p;
283 p->irqaction.irq = irq;
Paul Mundtfecf0662010-04-15 11:59:28 +0900284 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
285 IRQF_IRQPOLL | IRQF_NOBALANCING;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000286
287 /* get hold of clock */
Paul Mundtc2a25e82010-03-29 16:55:43 +0900288 p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000289 if (IS_ERR(p->clk)) {
Paul Mundtc2a25e82010-03-29 16:55:43 +0900290 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
291 p->clk = clk_get(&p->pdev->dev, cfg->clk);
292 if (IS_ERR(p->clk)) {
293 dev_err(&p->pdev->dev, "cannot get clock\n");
294 ret = PTR_ERR(p->clk);
295 goto err1;
296 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000297 }
298
Paul Mundt214a6072010-03-10 16:26:25 +0900299 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
300 cfg->clockevent_rating);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000301 err1:
302 iounmap(p->mapbase);
303 err0:
304 return ret;
305}
306
307static int __devinit sh_mtu2_probe(struct platform_device *pdev)
308{
309 struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000310 int ret;
311
312 if (p) {
Paul Mundt214a6072010-03-10 16:26:25 +0900313 dev_info(&pdev->dev, "kept as earlytimer\n");
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000314 return 0;
315 }
316
317 p = kmalloc(sizeof(*p), GFP_KERNEL);
318 if (p == NULL) {
319 dev_err(&pdev->dev, "failed to allocate driver data\n");
320 return -ENOMEM;
321 }
322
323 ret = sh_mtu2_setup(p, pdev);
324 if (ret) {
325 kfree(p);
326 platform_set_drvdata(pdev, NULL);
327 }
328 return ret;
329}
330
331static int __devexit sh_mtu2_remove(struct platform_device *pdev)
332{
333 return -EBUSY; /* cannot unregister clockevent */
334}
335
336static struct platform_driver sh_mtu2_device_driver = {
337 .probe = sh_mtu2_probe,
338 .remove = __devexit_p(sh_mtu2_remove),
339 .driver = {
340 .name = "sh_mtu2",
341 }
342};
343
344static int __init sh_mtu2_init(void)
345{
346 return platform_driver_register(&sh_mtu2_device_driver);
347}
348
349static void __exit sh_mtu2_exit(void)
350{
351 platform_driver_unregister(&sh_mtu2_device_driver);
352}
353
354early_platform_init("earlytimer", &sh_mtu2_device_driver);
355module_init(sh_mtu2_init);
356module_exit(sh_mtu2_exit);
357
358MODULE_AUTHOR("Magnus Damm");
359MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
360MODULE_LICENSE("GPL v2");