Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
| 34 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 36 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 39 | static const u32 hpd_ibx[] = { |
| 40 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
| 41 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, |
| 42 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, |
| 43 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, |
| 44 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG |
| 45 | }; |
| 46 | |
| 47 | static const u32 hpd_cpt[] = { |
| 48 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 49 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 50 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 51 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 52 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT |
| 53 | }; |
| 54 | |
| 55 | static const u32 hpd_mask_i915[] = { |
| 56 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
| 57 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, |
| 58 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, |
| 59 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, |
| 60 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, |
| 61 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN |
| 62 | }; |
| 63 | |
| 64 | static const u32 hpd_status_gen4[] = { |
| 65 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, |
| 67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, |
| 68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 71 | }; |
| 72 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 73 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
| 74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, |
| 76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, |
| 77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 80 | }; |
| 81 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 82 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 83 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 84 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 85 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 86 | assert_spin_locked(&dev_priv->irq_lock); |
| 87 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 88 | if (dev_priv->pc8.irqs_disabled) { |
| 89 | WARN(1, "IRQs disabled\n"); |
| 90 | dev_priv->pc8.regsave.deimr &= ~mask; |
| 91 | return; |
| 92 | } |
| 93 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 94 | if ((dev_priv->irq_mask & mask) != 0) { |
| 95 | dev_priv->irq_mask &= ~mask; |
| 96 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 97 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 98 | } |
| 99 | } |
| 100 | |
Paulo Zanoni | 0ff9800 | 2013-02-22 17:05:31 -0300 | [diff] [blame] | 101 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 102 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 103 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 104 | assert_spin_locked(&dev_priv->irq_lock); |
| 105 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 106 | if (dev_priv->pc8.irqs_disabled) { |
| 107 | WARN(1, "IRQs disabled\n"); |
| 108 | dev_priv->pc8.regsave.deimr |= mask; |
| 109 | return; |
| 110 | } |
| 111 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 112 | if ((dev_priv->irq_mask & mask) != mask) { |
| 113 | dev_priv->irq_mask |= mask; |
| 114 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 115 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 116 | } |
| 117 | } |
| 118 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 119 | /** |
| 120 | * ilk_update_gt_irq - update GTIMR |
| 121 | * @dev_priv: driver private |
| 122 | * @interrupt_mask: mask of interrupt bits to update |
| 123 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 124 | */ |
| 125 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, |
| 126 | uint32_t interrupt_mask, |
| 127 | uint32_t enabled_irq_mask) |
| 128 | { |
| 129 | assert_spin_locked(&dev_priv->irq_lock); |
| 130 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 131 | if (dev_priv->pc8.irqs_disabled) { |
| 132 | WARN(1, "IRQs disabled\n"); |
| 133 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; |
| 134 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & |
| 135 | interrupt_mask); |
| 136 | return; |
| 137 | } |
| 138 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 139 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
| 140 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); |
| 141 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 142 | POSTING_READ(GTIMR); |
| 143 | } |
| 144 | |
| 145 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 146 | { |
| 147 | ilk_update_gt_irq(dev_priv, mask, mask); |
| 148 | } |
| 149 | |
| 150 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 151 | { |
| 152 | ilk_update_gt_irq(dev_priv, mask, 0); |
| 153 | } |
| 154 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 155 | /** |
| 156 | * snb_update_pm_irq - update GEN6_PMIMR |
| 157 | * @dev_priv: driver private |
| 158 | * @interrupt_mask: mask of interrupt bits to update |
| 159 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 160 | */ |
| 161 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
| 162 | uint32_t interrupt_mask, |
| 163 | uint32_t enabled_irq_mask) |
| 164 | { |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 165 | uint32_t new_val; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 166 | |
| 167 | assert_spin_locked(&dev_priv->irq_lock); |
| 168 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 169 | if (dev_priv->pc8.irqs_disabled) { |
| 170 | WARN(1, "IRQs disabled\n"); |
| 171 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; |
| 172 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & |
| 173 | interrupt_mask); |
| 174 | return; |
| 175 | } |
| 176 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 177 | new_val = dev_priv->pm_irq_mask; |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 178 | new_val &= ~interrupt_mask; |
| 179 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 180 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 181 | if (new_val != dev_priv->pm_irq_mask) { |
| 182 | dev_priv->pm_irq_mask = new_val; |
| 183 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 184 | POSTING_READ(GEN6_PMIMR); |
| 185 | } |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 189 | { |
| 190 | snb_update_pm_irq(dev_priv, mask, mask); |
| 191 | } |
| 192 | |
| 193 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 194 | { |
| 195 | snb_update_pm_irq(dev_priv, mask, 0); |
| 196 | } |
| 197 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 198 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
| 199 | { |
| 200 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 201 | struct intel_crtc *crtc; |
| 202 | enum pipe pipe; |
| 203 | |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 204 | assert_spin_locked(&dev_priv->irq_lock); |
| 205 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 206 | for_each_pipe(pipe) { |
| 207 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 208 | |
| 209 | if (crtc->cpu_fifo_underrun_disabled) |
| 210 | return false; |
| 211 | } |
| 212 | |
| 213 | return true; |
| 214 | } |
| 215 | |
| 216 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
| 217 | { |
| 218 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 219 | enum pipe pipe; |
| 220 | struct intel_crtc *crtc; |
| 221 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 222 | assert_spin_locked(&dev_priv->irq_lock); |
| 223 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 224 | for_each_pipe(pipe) { |
| 225 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 226 | |
| 227 | if (crtc->pch_fifo_underrun_disabled) |
| 228 | return false; |
| 229 | } |
| 230 | |
| 231 | return true; |
| 232 | } |
| 233 | |
| 234 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
| 235 | enum pipe pipe, bool enable) |
| 236 | { |
| 237 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 238 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
| 239 | DE_PIPEB_FIFO_UNDERRUN; |
| 240 | |
| 241 | if (enable) |
| 242 | ironlake_enable_display_irq(dev_priv, bit); |
| 243 | else |
| 244 | ironlake_disable_display_irq(dev_priv, bit); |
| 245 | } |
| 246 | |
| 247 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 248 | enum pipe pipe, bool enable) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 249 | { |
| 250 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 251 | if (enable) { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 252 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
| 253 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 254 | if (!ivb_can_enable_err_int(dev)) |
| 255 | return; |
| 256 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 257 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 258 | } else { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 259 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
| 260 | |
| 261 | /* Change the state _after_ we've read out the current one. */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 262 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 263 | |
| 264 | if (!was_enabled && |
| 265 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { |
| 266 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", |
| 267 | pipe_name(pipe)); |
| 268 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 269 | } |
| 270 | } |
| 271 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 272 | /** |
| 273 | * ibx_display_interrupt_update - update SDEIMR |
| 274 | * @dev_priv: driver private |
| 275 | * @interrupt_mask: mask of interrupt bits to update |
| 276 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 277 | */ |
| 278 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 279 | uint32_t interrupt_mask, |
| 280 | uint32_t enabled_irq_mask) |
| 281 | { |
| 282 | uint32_t sdeimr = I915_READ(SDEIMR); |
| 283 | sdeimr &= ~interrupt_mask; |
| 284 | sdeimr |= (~enabled_irq_mask & interrupt_mask); |
| 285 | |
| 286 | assert_spin_locked(&dev_priv->irq_lock); |
| 287 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 288 | if (dev_priv->pc8.irqs_disabled && |
| 289 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { |
| 290 | WARN(1, "IRQs disabled\n"); |
| 291 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; |
| 292 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & |
| 293 | interrupt_mask); |
| 294 | return; |
| 295 | } |
| 296 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 297 | I915_WRITE(SDEIMR, sdeimr); |
| 298 | POSTING_READ(SDEIMR); |
| 299 | } |
| 300 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
| 301 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
| 302 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
| 303 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
| 304 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 305 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
| 306 | enum transcoder pch_transcoder, |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 307 | bool enable) |
| 308 | { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 309 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 310 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
| 311 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 312 | |
| 313 | if (enable) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 314 | ibx_enable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 315 | else |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 316 | ibx_disable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
| 320 | enum transcoder pch_transcoder, |
| 321 | bool enable) |
| 322 | { |
| 323 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 324 | |
| 325 | if (enable) { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 326 | I915_WRITE(SERR_INT, |
| 327 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
| 328 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 329 | if (!cpt_can_enable_serr_int(dev)) |
| 330 | return; |
| 331 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 332 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 333 | } else { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 334 | uint32_t tmp = I915_READ(SERR_INT); |
| 335 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); |
| 336 | |
| 337 | /* Change the state _after_ we've read out the current one. */ |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 338 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 339 | |
| 340 | if (!was_enabled && |
| 341 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { |
| 342 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", |
| 343 | transcoder_name(pch_transcoder)); |
| 344 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 345 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | /** |
| 349 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 350 | * @dev: drm device |
| 351 | * @pipe: pipe |
| 352 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 353 | * |
| 354 | * This function makes us disable or enable CPU fifo underruns for a specific |
| 355 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun |
| 356 | * reporting for one pipe may also disable all the other CPU error interruts for |
| 357 | * the other pipes, due to the fact that there's just one interrupt mask/enable |
| 358 | * bit for all the pipes. |
| 359 | * |
| 360 | * Returns the previous state of underrun reporting. |
| 361 | */ |
| 362 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 363 | enum pipe pipe, bool enable) |
| 364 | { |
| 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 366 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 368 | unsigned long flags; |
| 369 | bool ret; |
| 370 | |
| 371 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 372 | |
| 373 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
| 374 | |
| 375 | if (enable == ret) |
| 376 | goto done; |
| 377 | |
| 378 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
| 379 | |
| 380 | if (IS_GEN5(dev) || IS_GEN6(dev)) |
| 381 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
| 382 | else if (IS_GEN7(dev)) |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 383 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 384 | |
| 385 | done: |
| 386 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 387 | return ret; |
| 388 | } |
| 389 | |
| 390 | /** |
| 391 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 392 | * @dev: drm device |
| 393 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
| 394 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 395 | * |
| 396 | * This function makes us disable or enable PCH fifo underruns for a specific |
| 397 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO |
| 398 | * underrun reporting for one transcoder may also disable all the other PCH |
| 399 | * error interruts for the other transcoders, due to the fact that there's just |
| 400 | * one interrupt mask/enable bit for all the transcoders. |
| 401 | * |
| 402 | * Returns the previous state of underrun reporting. |
| 403 | */ |
| 404 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| 405 | enum transcoder pch_transcoder, |
| 406 | bool enable) |
| 407 | { |
| 408 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 409 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
| 410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 411 | unsigned long flags; |
| 412 | bool ret; |
| 413 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 414 | /* |
| 415 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT |
| 416 | * has only one pch transcoder A that all pipes can use. To avoid racy |
| 417 | * pch transcoder -> pipe lookups from interrupt code simply store the |
| 418 | * underrun statistics in crtc A. Since we never expose this anywhere |
| 419 | * nor use it outside of the fifo underrun code here using the "wrong" |
| 420 | * crtc on LPT won't cause issues. |
| 421 | */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 422 | |
| 423 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 424 | |
| 425 | ret = !intel_crtc->pch_fifo_underrun_disabled; |
| 426 | |
| 427 | if (enable == ret) |
| 428 | goto done; |
| 429 | |
| 430 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
| 431 | |
| 432 | if (HAS_PCH_IBX(dev)) |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 433 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 434 | else |
| 435 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
| 436 | |
| 437 | done: |
| 438 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 439 | return ret; |
| 440 | } |
| 441 | |
| 442 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 443 | void |
| 444 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 445 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 446 | u32 reg = PIPESTAT(pipe); |
| 447 | u32 pipestat = I915_READ(reg) & 0x7fff0000; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 448 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 449 | assert_spin_locked(&dev_priv->irq_lock); |
| 450 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 451 | if ((pipestat & mask) == mask) |
| 452 | return; |
| 453 | |
| 454 | /* Enable the interrupt, clear any pending status */ |
| 455 | pipestat |= mask | (mask >> 16); |
| 456 | I915_WRITE(reg, pipestat); |
| 457 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | void |
| 461 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 462 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 463 | u32 reg = PIPESTAT(pipe); |
| 464 | u32 pipestat = I915_READ(reg) & 0x7fff0000; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 465 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 466 | assert_spin_locked(&dev_priv->irq_lock); |
| 467 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 468 | if ((pipestat & mask) == 0) |
| 469 | return; |
| 470 | |
| 471 | pipestat &= ~mask; |
| 472 | I915_WRITE(reg, pipestat); |
| 473 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 474 | } |
| 475 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 476 | /** |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 477 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 478 | */ |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 479 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 480 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 481 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 482 | unsigned long irqflags; |
| 483 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 484 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
| 485 | return; |
| 486 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 487 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 488 | |
Jani Nikula | f898780 | 2013-04-29 13:02:53 +0300 | [diff] [blame] | 489 | i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE); |
| 490 | if (INTEL_INFO(dev)->gen >= 4) |
| 491 | i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 492 | |
| 493 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 497 | * i915_pipe_enabled - check if a pipe is enabled |
| 498 | * @dev: DRM device |
| 499 | * @pipe: pipe to check |
| 500 | * |
| 501 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 502 | * Use this routine to make sure the PLL is running and the pipe is active |
| 503 | * before reading such registers if unsure. |
| 504 | */ |
| 505 | static int |
| 506 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 507 | { |
| 508 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 509 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 510 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 511 | /* Locking is horribly broken here, but whatever. */ |
| 512 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 71f8ba6 | 2013-05-03 12:15:39 -0300 | [diff] [blame] | 514 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 515 | return intel_crtc->active; |
| 516 | } else { |
| 517 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
| 518 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 519 | } |
| 520 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 521 | /* Called from drm generic code, passed a 'crtc', which |
| 522 | * we use as a pipe index |
| 523 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 524 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 525 | { |
| 526 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 527 | unsigned long high_frame; |
| 528 | unsigned long low_frame; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 529 | u32 high1, high2, low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 530 | |
| 531 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 532 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 533 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 534 | return 0; |
| 535 | } |
| 536 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 537 | high_frame = PIPEFRAME(pipe); |
| 538 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 539 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 540 | /* |
| 541 | * High & low register fields aren't synchronized, so make sure |
| 542 | * we get a low value that's stable across two reads of the high |
| 543 | * register. |
| 544 | */ |
| 545 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 546 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 547 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; |
| 548 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 549 | } while (high1 != high2); |
| 550 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 551 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
| 552 | low >>= PIPE_FRAME_LOW_SHIFT; |
| 553 | return (high1 << 8) | low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 554 | } |
| 555 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 556 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 557 | { |
| 558 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 559 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 560 | |
| 561 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 562 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 563 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | return I915_READ(reg); |
| 568 | } |
| 569 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 570 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 571 | int *vpos, int *hpos) |
| 572 | { |
| 573 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 574 | u32 vbl = 0, position = 0; |
| 575 | int vbl_start, vbl_end, htotal, vtotal; |
| 576 | bool in_vbl = true; |
| 577 | int ret = 0; |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 578 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 579 | pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 580 | |
| 581 | if (!i915_pipe_enabled(dev, pipe)) { |
| 582 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 583 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | /* Get vtotal. */ |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 588 | vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 589 | |
| 590 | if (INTEL_INFO(dev)->gen >= 4) { |
| 591 | /* No obvious pixelcount register. Only query vertical |
| 592 | * scanout position from Display scan line register. |
| 593 | */ |
| 594 | position = I915_READ(PIPEDSL(pipe)); |
| 595 | |
| 596 | /* Decode into vertical scanout position. Don't have |
| 597 | * horizontal scanout position. |
| 598 | */ |
| 599 | *vpos = position & 0x1fff; |
| 600 | *hpos = 0; |
| 601 | } else { |
| 602 | /* Have access to pixelcount since start of frame. |
| 603 | * We can split this into vertical and horizontal |
| 604 | * scanout position. |
| 605 | */ |
| 606 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
| 607 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 608 | htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 609 | *vpos = position / htotal; |
| 610 | *hpos = position - (*vpos * htotal); |
| 611 | } |
| 612 | |
| 613 | /* Query vblank area. */ |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 614 | vbl = I915_READ(VBLANK(cpu_transcoder)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 615 | |
| 616 | /* Test position against vblank region. */ |
| 617 | vbl_start = vbl & 0x1fff; |
| 618 | vbl_end = (vbl >> 16) & 0x1fff; |
| 619 | |
| 620 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) |
| 621 | in_vbl = false; |
| 622 | |
| 623 | /* Inside "upper part" of vblank area? Apply corrective offset: */ |
| 624 | if (in_vbl && (*vpos >= vbl_start)) |
| 625 | *vpos = *vpos - vtotal; |
| 626 | |
| 627 | /* Readouts valid? */ |
| 628 | if (vbl > 0) |
| 629 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 630 | |
| 631 | /* In vblank? */ |
| 632 | if (in_vbl) |
| 633 | ret |= DRM_SCANOUTPOS_INVBL; |
| 634 | |
| 635 | return ret; |
| 636 | } |
| 637 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 638 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 639 | int *max_error, |
| 640 | struct timeval *vblank_time, |
| 641 | unsigned flags) |
| 642 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 643 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 644 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 645 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 646 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 647 | return -EINVAL; |
| 648 | } |
| 649 | |
| 650 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 651 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 652 | if (crtc == NULL) { |
| 653 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 654 | return -EINVAL; |
| 655 | } |
| 656 | |
| 657 | if (!crtc->enabled) { |
| 658 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 659 | return -EBUSY; |
| 660 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 661 | |
| 662 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 663 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 664 | vblank_time, flags, |
| 665 | crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 666 | } |
| 667 | |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 668 | static bool intel_hpd_irq_event(struct drm_device *dev, |
| 669 | struct drm_connector *connector) |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 670 | { |
| 671 | enum drm_connector_status old_status; |
| 672 | |
| 673 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 674 | old_status = connector->status; |
| 675 | |
| 676 | connector->status = connector->funcs->detect(connector, false); |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 677 | if (old_status == connector->status) |
| 678 | return false; |
| 679 | |
| 680 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 681 | connector->base.id, |
| 682 | drm_get_connector_name(connector), |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 683 | drm_get_connector_status_name(old_status), |
| 684 | drm_get_connector_status_name(connector->status)); |
| 685 | |
| 686 | return true; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 687 | } |
| 688 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 689 | /* |
| 690 | * Handle hotplug events outside the interrupt handler proper. |
| 691 | */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 692 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
| 693 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 694 | static void i915_hotplug_work_func(struct work_struct *work) |
| 695 | { |
| 696 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 697 | hotplug_work); |
| 698 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 699 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 700 | struct intel_connector *intel_connector; |
| 701 | struct intel_encoder *intel_encoder; |
| 702 | struct drm_connector *connector; |
| 703 | unsigned long irqflags; |
| 704 | bool hpd_disabled = false; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 705 | bool changed = false; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 706 | u32 hpd_event_bits; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 707 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 708 | /* HPD irq before everything is fully set up. */ |
| 709 | if (!dev_priv->enable_hotplug_processing) |
| 710 | return; |
| 711 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 712 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 713 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 714 | |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 715 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 716 | |
| 717 | hpd_event_bits = dev_priv->hpd_event_bits; |
| 718 | dev_priv->hpd_event_bits = 0; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 719 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 720 | intel_connector = to_intel_connector(connector); |
| 721 | intel_encoder = intel_connector->encoder; |
| 722 | if (intel_encoder->hpd_pin > HPD_NONE && |
| 723 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && |
| 724 | connector->polled == DRM_CONNECTOR_POLL_HPD) { |
| 725 | DRM_INFO("HPD interrupt storm detected on connector %s: " |
| 726 | "switching from hotplug detection to polling\n", |
| 727 | drm_get_connector_name(connector)); |
| 728 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
| 729 | connector->polled = DRM_CONNECTOR_POLL_CONNECT |
| 730 | | DRM_CONNECTOR_POLL_DISCONNECT; |
| 731 | hpd_disabled = true; |
| 732 | } |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 733 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 734 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", |
| 735 | drm_get_connector_name(connector), intel_encoder->hpd_pin); |
| 736 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 737 | } |
| 738 | /* if there were no outputs to poll, poll was disabled, |
| 739 | * therefore make sure it's enabled when disabling HPD on |
| 740 | * some connectors */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 741 | if (hpd_disabled) { |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 742 | drm_kms_helper_poll_enable(dev); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 743 | mod_timer(&dev_priv->hotplug_reenable_timer, |
| 744 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
| 745 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 746 | |
| 747 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 748 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 749 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 750 | intel_connector = to_intel_connector(connector); |
| 751 | intel_encoder = intel_connector->encoder; |
| 752 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 753 | if (intel_encoder->hot_plug) |
| 754 | intel_encoder->hot_plug(intel_encoder); |
| 755 | if (intel_hpd_irq_event(dev, connector)) |
| 756 | changed = true; |
| 757 | } |
| 758 | } |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 759 | mutex_unlock(&mode_config->mutex); |
| 760 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 761 | if (changed) |
| 762 | drm_kms_helper_hotplug_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 763 | } |
| 764 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 765 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 766 | { |
| 767 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 768 | u32 busy_up, busy_down, max_avg, min_avg; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 769 | u8 new_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 770 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 771 | spin_lock(&mchdev_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 772 | |
Daniel Vetter | 73edd18f | 2012-08-08 23:35:37 +0200 | [diff] [blame] | 773 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 774 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 775 | new_delay = dev_priv->ips.cur_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 776 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 777 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 778 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 779 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 780 | max_avg = I915_READ(RCBMAXAVG); |
| 781 | min_avg = I915_READ(RCBMINAVG); |
| 782 | |
| 783 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 784 | if (busy_up > max_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 785 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
| 786 | new_delay = dev_priv->ips.cur_delay - 1; |
| 787 | if (new_delay < dev_priv->ips.max_delay) |
| 788 | new_delay = dev_priv->ips.max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 789 | } else if (busy_down < min_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 790 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
| 791 | new_delay = dev_priv->ips.cur_delay + 1; |
| 792 | if (new_delay > dev_priv->ips.min_delay) |
| 793 | new_delay = dev_priv->ips.min_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 794 | } |
| 795 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 796 | if (ironlake_set_drps(dev, new_delay)) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 797 | dev_priv->ips.cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 798 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 799 | spin_unlock(&mchdev_lock); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 800 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 801 | return; |
| 802 | } |
| 803 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 804 | static void notify_ring(struct drm_device *dev, |
| 805 | struct intel_ring_buffer *ring) |
| 806 | { |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 807 | if (ring->obj == NULL) |
| 808 | return; |
| 809 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 810 | trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 811 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 812 | wake_up_all(&ring->irq_queue); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 813 | i915_queue_hangcheck(dev); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 814 | } |
| 815 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 816 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 817 | { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 818 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 819 | rps.work); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 820 | u32 pm_iir; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 821 | u8 new_delay; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 822 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 823 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 824 | pm_iir = dev_priv->rps.pm_iir; |
| 825 | dev_priv->rps.pm_iir = 0; |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 826 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 827 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 828 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 829 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 830 | /* Make sure we didn't queue anything we're not going to process. */ |
| 831 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); |
| 832 | |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 833 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 834 | return; |
| 835 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 836 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 837 | |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 838 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 839 | new_delay = dev_priv->rps.cur_delay + 1; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 840 | |
| 841 | /* |
| 842 | * For better performance, jump directly |
| 843 | * to RPe if we're below it. |
| 844 | */ |
| 845 | if (IS_VALLEYVIEW(dev_priv->dev) && |
| 846 | dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay) |
| 847 | new_delay = dev_priv->rps.rpe_delay; |
| 848 | } else |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 849 | new_delay = dev_priv->rps.cur_delay - 1; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 850 | |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 851 | /* sysfs frequency interfaces may have snuck in while servicing the |
| 852 | * interrupt |
| 853 | */ |
Ville Syrjälä | d8289c9 | 2013-06-25 19:21:05 +0300 | [diff] [blame] | 854 | if (new_delay >= dev_priv->rps.min_delay && |
| 855 | new_delay <= dev_priv->rps.max_delay) { |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 856 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 857 | valleyview_set_rps(dev_priv->dev, new_delay); |
| 858 | else |
| 859 | gen6_set_rps(dev_priv->dev, new_delay); |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 860 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 861 | |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 862 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 863 | /* |
| 864 | * On VLV, when we enter RC6 we may not be at the minimum |
| 865 | * voltage level, so arm a timer to check. It should only |
| 866 | * fire when there's activity or once after we've entered |
| 867 | * RC6, and then won't be re-armed until the next RPS interrupt. |
| 868 | */ |
| 869 | mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work, |
| 870 | msecs_to_jiffies(100)); |
| 871 | } |
| 872 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 873 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 874 | } |
| 875 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 876 | |
| 877 | /** |
| 878 | * ivybridge_parity_work - Workqueue called when a parity error interrupt |
| 879 | * occurred. |
| 880 | * @work: workqueue struct |
| 881 | * |
| 882 | * Doesn't actually do anything except notify userspace. As a consequence of |
| 883 | * this event, userspace should try to remap the bad rows since statistically |
| 884 | * it is likely the same row is more likely to go bad again. |
| 885 | */ |
| 886 | static void ivybridge_parity_work(struct work_struct *work) |
| 887 | { |
| 888 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 889 | l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 890 | u32 error_status, row, bank, subbank; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 891 | char *parity_event[6]; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 892 | uint32_t misccpctl; |
| 893 | unsigned long flags; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 894 | uint8_t slice = 0; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 895 | |
| 896 | /* We must turn off DOP level clock gating to access the L3 registers. |
| 897 | * In order to prevent a get/put style interface, acquire struct mutex |
| 898 | * any time we access those registers. |
| 899 | */ |
| 900 | mutex_lock(&dev_priv->dev->struct_mutex); |
| 901 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 902 | /* If we've screwed up tracking, just let the interrupt fire again */ |
| 903 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) |
| 904 | goto out; |
| 905 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 906 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 907 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 908 | POSTING_READ(GEN7_MISCCPCTL); |
| 909 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 910 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
| 911 | u32 reg; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 912 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 913 | slice--; |
| 914 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) |
| 915 | break; |
| 916 | |
| 917 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
| 918 | |
| 919 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
| 920 | |
| 921 | error_status = I915_READ(reg); |
| 922 | row = GEN7_PARITY_ERROR_ROW(error_status); |
| 923 | bank = GEN7_PARITY_ERROR_BANK(error_status); |
| 924 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); |
| 925 | |
| 926 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); |
| 927 | POSTING_READ(reg); |
| 928 | |
| 929 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; |
| 930 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); |
| 931 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); |
| 932 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); |
| 933 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); |
| 934 | parity_event[5] = NULL; |
| 935 | |
| 936 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, |
| 937 | KOBJ_CHANGE, parity_event); |
| 938 | |
| 939 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
| 940 | slice, row, bank, subbank); |
| 941 | |
| 942 | kfree(parity_event[4]); |
| 943 | kfree(parity_event[3]); |
| 944 | kfree(parity_event[2]); |
| 945 | kfree(parity_event[1]); |
| 946 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 947 | |
| 948 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 949 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 950 | out: |
| 951 | WARN_ON(dev_priv->l3_parity.which_slice); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 952 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 953 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 954 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 955 | |
| 956 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 957 | } |
| 958 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 959 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 960 | { |
| 961 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 962 | |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 963 | if (!HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 964 | return; |
| 965 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 966 | spin_lock(&dev_priv->irq_lock); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 967 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 968 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 969 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 970 | iir &= GT_PARITY_ERROR(dev); |
| 971 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
| 972 | dev_priv->l3_parity.which_slice |= 1 << 1; |
| 973 | |
| 974 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
| 975 | dev_priv->l3_parity.which_slice |= 1 << 0; |
| 976 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 977 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 978 | } |
| 979 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 980 | static void ilk_gt_irq_handler(struct drm_device *dev, |
| 981 | struct drm_i915_private *dev_priv, |
| 982 | u32 gt_iir) |
| 983 | { |
| 984 | if (gt_iir & |
| 985 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
| 986 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 987 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
| 988 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 989 | } |
| 990 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 991 | static void snb_gt_irq_handler(struct drm_device *dev, |
| 992 | struct drm_i915_private *dev_priv, |
| 993 | u32 gt_iir) |
| 994 | { |
| 995 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 996 | if (gt_iir & |
| 997 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 998 | notify_ring(dev, &dev_priv->ring[RCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 999 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1000 | notify_ring(dev, &dev_priv->ring[VCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1001 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1002 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 1003 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1004 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
| 1005 | GT_BSD_CS_ERROR_INTERRUPT | |
| 1006 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1007 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
| 1008 | i915_handle_error(dev, false); |
| 1009 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1010 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1011 | if (gt_iir & GT_PARITY_ERROR(dev)) |
| 1012 | ivybridge_parity_error_irq_handler(dev, gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1013 | } |
| 1014 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1015 | #define HPD_STORM_DETECT_PERIOD 1000 |
| 1016 | #define HPD_STORM_THRESHOLD 5 |
| 1017 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1018 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 1019 | u32 hotplug_trigger, |
| 1020 | const u32 *hpd) |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1021 | { |
| 1022 | drm_i915_private_t *dev_priv = dev->dev_private; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1023 | int i; |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1024 | bool storm_detected = false; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1025 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1026 | if (!hotplug_trigger) |
| 1027 | return; |
| 1028 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1029 | spin_lock(&dev_priv->irq_lock); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1030 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 1031 | |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1032 | WARN(((hpd[i] & hotplug_trigger) && |
| 1033 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED), |
| 1034 | "Received HPD interrupt although disabled\n"); |
| 1035 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1036 | if (!(hpd[i] & hotplug_trigger) || |
| 1037 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) |
| 1038 | continue; |
| 1039 | |
Jani Nikula | bc5ead8c | 2013-05-07 15:10:29 +0300 | [diff] [blame] | 1040 | dev_priv->hpd_event_bits |= (1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1041 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
| 1042 | dev_priv->hpd_stats[i].hpd_last_jiffies |
| 1043 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { |
| 1044 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; |
| 1045 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1046 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1047 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
| 1048 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1049 | dev_priv->hpd_event_bits &= ~(1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1050 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1051 | storm_detected = true; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1052 | } else { |
| 1053 | dev_priv->hpd_stats[i].hpd_cnt++; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1054 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
| 1055 | dev_priv->hpd_stats[i].hpd_cnt); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1056 | } |
| 1057 | } |
| 1058 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1059 | if (storm_detected) |
| 1060 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1061 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 5876fa0 | 2013-06-27 17:52:13 +0200 | [diff] [blame] | 1062 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1063 | /* |
| 1064 | * Our hotplug handler can grab modeset locks (by calling down into the |
| 1065 | * fb helpers). Hence it must not be run on our own dev-priv->wq work |
| 1066 | * queue for otherwise the flush_work in the pageflip code will |
| 1067 | * deadlock. |
| 1068 | */ |
| 1069 | schedule_work(&dev_priv->hotplug_work); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1070 | } |
| 1071 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1072 | static void gmbus_irq_handler(struct drm_device *dev) |
| 1073 | { |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1074 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1075 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1076 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1077 | } |
| 1078 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1079 | static void dp_aux_irq_handler(struct drm_device *dev) |
| 1080 | { |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1081 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1082 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1083 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1084 | } |
| 1085 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1086 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
| 1087 | * IMR bits until the work is done. Other interrupts can be processed without |
| 1088 | * the work queue. */ |
| 1089 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1090 | { |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1091 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1092 | spin_lock(&dev_priv->irq_lock); |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1093 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
Paulo Zanoni | 4d3b3d5 | 2013-08-09 17:04:36 -0300 | [diff] [blame] | 1094 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1095 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 2adbee6 | 2013-07-04 23:35:27 +0200 | [diff] [blame] | 1096 | |
| 1097 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1098 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1099 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1100 | if (HAS_VEBOX(dev_priv->dev)) { |
| 1101 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
| 1102 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1103 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1104 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
| 1105 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); |
| 1106 | i915_handle_error(dev_priv->dev, false); |
| 1107 | } |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1108 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1109 | } |
| 1110 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 1111 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1112 | { |
| 1113 | struct drm_device *dev = (struct drm_device *) arg; |
| 1114 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1115 | u32 iir, gt_iir, pm_iir; |
| 1116 | irqreturn_t ret = IRQ_NONE; |
| 1117 | unsigned long irqflags; |
| 1118 | int pipe; |
| 1119 | u32 pipe_stats[I915_MAX_PIPES]; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1120 | |
| 1121 | atomic_inc(&dev_priv->irq_received); |
| 1122 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1123 | while (true) { |
| 1124 | iir = I915_READ(VLV_IIR); |
| 1125 | gt_iir = I915_READ(GTIIR); |
| 1126 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1127 | |
| 1128 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
| 1129 | goto out; |
| 1130 | |
| 1131 | ret = IRQ_HANDLED; |
| 1132 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1133 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1134 | |
| 1135 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1136 | for_each_pipe(pipe) { |
| 1137 | int reg = PIPESTAT(pipe); |
| 1138 | pipe_stats[pipe] = I915_READ(reg); |
| 1139 | |
| 1140 | /* |
| 1141 | * Clear the PIPE*STAT regs before the IIR |
| 1142 | */ |
| 1143 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 1144 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 1145 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 1146 | pipe_name(pipe)); |
| 1147 | I915_WRITE(reg, pipe_stats[pipe]); |
| 1148 | } |
| 1149 | } |
| 1150 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1151 | |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1152 | for_each_pipe(pipe) { |
| 1153 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) |
| 1154 | drm_handle_vblank(dev, pipe); |
| 1155 | |
| 1156 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { |
| 1157 | intel_prepare_page_flip(dev, pipe); |
| 1158 | intel_finish_page_flip(dev, pipe); |
| 1159 | } |
| 1160 | } |
| 1161 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1162 | /* Consume port. Then clear IIR or we'll miss events */ |
| 1163 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
| 1164 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1165 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1166 | |
| 1167 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 1168 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1169 | |
| 1170 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
| 1171 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1172 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1173 | I915_READ(PORT_HOTPLUG_STAT); |
| 1174 | } |
| 1175 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1176 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 1177 | gmbus_irq_handler(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1178 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1179 | if (pm_iir) |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1180 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1181 | |
| 1182 | I915_WRITE(GTIIR, gt_iir); |
| 1183 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1184 | I915_WRITE(VLV_IIR, iir); |
| 1185 | } |
| 1186 | |
| 1187 | out: |
| 1188 | return ret; |
| 1189 | } |
| 1190 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1191 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1192 | { |
| 1193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1194 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1195 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1196 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1197 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
| 1198 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1199 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
| 1200 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 1201 | SDE_AUDIO_POWER_SHIFT); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1202 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1203 | port_name(port)); |
| 1204 | } |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1205 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1206 | if (pch_iir & SDE_AUX_MASK) |
| 1207 | dp_aux_irq_handler(dev); |
| 1208 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1209 | if (pch_iir & SDE_GMBUS) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1210 | gmbus_irq_handler(dev); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1211 | |
| 1212 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 1213 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 1214 | |
| 1215 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 1216 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 1217 | |
| 1218 | if (pch_iir & SDE_POISON) |
| 1219 | DRM_ERROR("PCH poison interrupt\n"); |
| 1220 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1221 | if (pch_iir & SDE_FDI_MASK) |
| 1222 | for_each_pipe(pipe) |
| 1223 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1224 | pipe_name(pipe), |
| 1225 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1226 | |
| 1227 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 1228 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 1229 | |
| 1230 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 1231 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 1232 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1233 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1234 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 1235 | false)) |
| 1236 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); |
| 1237 | |
| 1238 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
| 1239 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 1240 | false)) |
| 1241 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); |
| 1242 | } |
| 1243 | |
| 1244 | static void ivb_err_int_handler(struct drm_device *dev) |
| 1245 | { |
| 1246 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1247 | u32 err_int = I915_READ(GEN7_ERR_INT); |
| 1248 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1249 | if (err_int & ERR_INT_POISON) |
| 1250 | DRM_ERROR("Poison interrupt\n"); |
| 1251 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1252 | if (err_int & ERR_INT_FIFO_UNDERRUN_A) |
| 1253 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) |
| 1254 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); |
| 1255 | |
| 1256 | if (err_int & ERR_INT_FIFO_UNDERRUN_B) |
| 1257 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) |
| 1258 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); |
| 1259 | |
| 1260 | if (err_int & ERR_INT_FIFO_UNDERRUN_C) |
| 1261 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false)) |
| 1262 | DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n"); |
| 1263 | |
| 1264 | I915_WRITE(GEN7_ERR_INT, err_int); |
| 1265 | } |
| 1266 | |
| 1267 | static void cpt_serr_int_handler(struct drm_device *dev) |
| 1268 | { |
| 1269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1270 | u32 serr_int = I915_READ(SERR_INT); |
| 1271 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1272 | if (serr_int & SERR_INT_POISON) |
| 1273 | DRM_ERROR("PCH poison interrupt\n"); |
| 1274 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1275 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
| 1276 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 1277 | false)) |
| 1278 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); |
| 1279 | |
| 1280 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) |
| 1281 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 1282 | false)) |
| 1283 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); |
| 1284 | |
| 1285 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) |
| 1286 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, |
| 1287 | false)) |
| 1288 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); |
| 1289 | |
| 1290 | I915_WRITE(SERR_INT, serr_int); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1291 | } |
| 1292 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1293 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
| 1294 | { |
| 1295 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1296 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1297 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1298 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1299 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
| 1300 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1301 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
| 1302 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> |
| 1303 | SDE_AUDIO_POWER_SHIFT_CPT); |
| 1304 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", |
| 1305 | port_name(port)); |
| 1306 | } |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1307 | |
| 1308 | if (pch_iir & SDE_AUX_MASK_CPT) |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1309 | dp_aux_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1310 | |
| 1311 | if (pch_iir & SDE_GMBUS_CPT) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1312 | gmbus_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1313 | |
| 1314 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
| 1315 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
| 1316 | |
| 1317 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) |
| 1318 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); |
| 1319 | |
| 1320 | if (pch_iir & SDE_FDI_MASK_CPT) |
| 1321 | for_each_pipe(pipe) |
| 1322 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1323 | pipe_name(pipe), |
| 1324 | I915_READ(FDI_RX_IIR(pipe))); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1325 | |
| 1326 | if (pch_iir & SDE_ERROR_CPT) |
| 1327 | cpt_serr_int_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1328 | } |
| 1329 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1330 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 1331 | { |
| 1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1333 | |
| 1334 | if (de_iir & DE_AUX_CHANNEL_A) |
| 1335 | dp_aux_irq_handler(dev); |
| 1336 | |
| 1337 | if (de_iir & DE_GSE) |
| 1338 | intel_opregion_asle_intr(dev); |
| 1339 | |
| 1340 | if (de_iir & DE_PIPEA_VBLANK) |
| 1341 | drm_handle_vblank(dev, 0); |
| 1342 | |
| 1343 | if (de_iir & DE_PIPEB_VBLANK) |
| 1344 | drm_handle_vblank(dev, 1); |
| 1345 | |
| 1346 | if (de_iir & DE_POISON) |
| 1347 | DRM_ERROR("Poison interrupt\n"); |
| 1348 | |
| 1349 | if (de_iir & DE_PIPEA_FIFO_UNDERRUN) |
| 1350 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) |
| 1351 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); |
| 1352 | |
| 1353 | if (de_iir & DE_PIPEB_FIFO_UNDERRUN) |
| 1354 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) |
| 1355 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); |
| 1356 | |
| 1357 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
| 1358 | intel_prepare_page_flip(dev, 0); |
| 1359 | intel_finish_page_flip_plane(dev, 0); |
| 1360 | } |
| 1361 | |
| 1362 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 1363 | intel_prepare_page_flip(dev, 1); |
| 1364 | intel_finish_page_flip_plane(dev, 1); |
| 1365 | } |
| 1366 | |
| 1367 | /* check event from PCH */ |
| 1368 | if (de_iir & DE_PCH_EVENT) { |
| 1369 | u32 pch_iir = I915_READ(SDEIIR); |
| 1370 | |
| 1371 | if (HAS_PCH_CPT(dev)) |
| 1372 | cpt_irq_handler(dev, pch_iir); |
| 1373 | else |
| 1374 | ibx_irq_handler(dev, pch_iir); |
| 1375 | |
| 1376 | /* should clear PCH hotplug event before clear CPU irq */ |
| 1377 | I915_WRITE(SDEIIR, pch_iir); |
| 1378 | } |
| 1379 | |
| 1380 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
| 1381 | ironlake_rps_change_irq_handler(dev); |
| 1382 | } |
| 1383 | |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 1384 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 1385 | { |
| 1386 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1387 | int i; |
| 1388 | |
| 1389 | if (de_iir & DE_ERR_INT_IVB) |
| 1390 | ivb_err_int_handler(dev); |
| 1391 | |
| 1392 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
| 1393 | dp_aux_irq_handler(dev); |
| 1394 | |
| 1395 | if (de_iir & DE_GSE_IVB) |
| 1396 | intel_opregion_asle_intr(dev); |
| 1397 | |
| 1398 | for (i = 0; i < 3; i++) { |
| 1399 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) |
| 1400 | drm_handle_vblank(dev, i); |
| 1401 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { |
| 1402 | intel_prepare_page_flip(dev, i); |
| 1403 | intel_finish_page_flip_plane(dev, i); |
| 1404 | } |
| 1405 | } |
| 1406 | |
| 1407 | /* check event from PCH */ |
| 1408 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { |
| 1409 | u32 pch_iir = I915_READ(SDEIIR); |
| 1410 | |
| 1411 | cpt_irq_handler(dev, pch_iir); |
| 1412 | |
| 1413 | /* clear PCH hotplug event before clear CPU irq */ |
| 1414 | I915_WRITE(SDEIIR, pch_iir); |
| 1415 | } |
| 1416 | } |
| 1417 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1418 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1419 | { |
| 1420 | struct drm_device *dev = (struct drm_device *) arg; |
| 1421 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1422 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1423 | irqreturn_t ret = IRQ_NONE; |
Paulo Zanoni | 333a820 | 2013-08-06 18:57:16 -0300 | [diff] [blame] | 1424 | bool err_int_reenable = false; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1425 | |
| 1426 | atomic_inc(&dev_priv->irq_received); |
| 1427 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1428 | /* We get interrupts on unclaimed registers, so check for this before we |
| 1429 | * do any I915_{READ,WRITE}. */ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1430 | intel_uncore_check_errors(dev); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1431 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1432 | /* disable master interrupt before clearing iir */ |
| 1433 | de_ier = I915_READ(DEIER); |
| 1434 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Paulo Zanoni | 23a7851 | 2013-07-12 16:35:14 -0300 | [diff] [blame] | 1435 | POSTING_READ(DEIER); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1436 | |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 1437 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
| 1438 | * interrupts will will be stored on its back queue, and then we'll be |
| 1439 | * able to process them after we restore SDEIER (as soon as we restore |
| 1440 | * it, we'll get an interrupt if SDEIIR still has something to process |
| 1441 | * due to its back queue). */ |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 1442 | if (!HAS_PCH_NOP(dev)) { |
| 1443 | sde_ier = I915_READ(SDEIER); |
| 1444 | I915_WRITE(SDEIER, 0); |
| 1445 | POSTING_READ(SDEIER); |
| 1446 | } |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 1447 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1448 | /* On Haswell, also mask ERR_INT because we don't want to risk |
| 1449 | * generating "unclaimed register" interrupts from inside the interrupt |
| 1450 | * handler. */ |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 1451 | if (IS_HASWELL(dev)) { |
| 1452 | spin_lock(&dev_priv->irq_lock); |
Paulo Zanoni | 333a820 | 2013-08-06 18:57:16 -0300 | [diff] [blame] | 1453 | err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB; |
| 1454 | if (err_int_reenable) |
| 1455 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 1456 | spin_unlock(&dev_priv->irq_lock); |
| 1457 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1458 | |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1459 | gt_iir = I915_READ(GTIIR); |
| 1460 | if (gt_iir) { |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 1461 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1462 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 1463 | else |
| 1464 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1465 | I915_WRITE(GTIIR, gt_iir); |
| 1466 | ret = IRQ_HANDLED; |
| 1467 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1468 | |
| 1469 | de_iir = I915_READ(DEIIR); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1470 | if (de_iir) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1471 | if (INTEL_INFO(dev)->gen >= 7) |
| 1472 | ivb_display_irq_handler(dev, de_iir); |
| 1473 | else |
| 1474 | ilk_display_irq_handler(dev, de_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1475 | I915_WRITE(DEIIR, de_iir); |
| 1476 | ret = IRQ_HANDLED; |
| 1477 | } |
| 1478 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1479 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1480 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
| 1481 | if (pm_iir) { |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1482 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1483 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1484 | ret = IRQ_HANDLED; |
| 1485 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1486 | } |
| 1487 | |
Paulo Zanoni | 333a820 | 2013-08-06 18:57:16 -0300 | [diff] [blame] | 1488 | if (err_int_reenable) { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 1489 | spin_lock(&dev_priv->irq_lock); |
| 1490 | if (ivb_can_enable_err_int(dev)) |
| 1491 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 1492 | spin_unlock(&dev_priv->irq_lock); |
| 1493 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1494 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1495 | I915_WRITE(DEIER, de_ier); |
| 1496 | POSTING_READ(DEIER); |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 1497 | if (!HAS_PCH_NOP(dev)) { |
| 1498 | I915_WRITE(SDEIER, sde_ier); |
| 1499 | POSTING_READ(SDEIER); |
| 1500 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1501 | |
| 1502 | return ret; |
| 1503 | } |
| 1504 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1505 | /** |
| 1506 | * i915_error_work_func - do process context error handling work |
| 1507 | * @work: work struct |
| 1508 | * |
| 1509 | * Fire an error uevent so userspace can see that a hang or error |
| 1510 | * was detected. |
| 1511 | */ |
| 1512 | static void i915_error_work_func(struct work_struct *work) |
| 1513 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1514 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
| 1515 | work); |
| 1516 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, |
| 1517 | gpu_error); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1518 | struct drm_device *dev = dev_priv->dev; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1519 | struct intel_ring_buffer *ring; |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 1520 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
| 1521 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; |
| 1522 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1523 | int i, ret; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1524 | |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1525 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1526 | |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 1527 | /* |
| 1528 | * Note that there's only one work item which does gpu resets, so we |
| 1529 | * need not worry about concurrent gpu resets potentially incrementing |
| 1530 | * error->reset_counter twice. We only need to take care of another |
| 1531 | * racing irq/hangcheck declaring the gpu dead for a second time. A |
| 1532 | * quick check for that is good enough: schedule_work ensures the |
| 1533 | * correct ordering between hang detection and this work item, and since |
| 1534 | * the reset in-progress bit is only ever set by code outside of this |
| 1535 | * work we don't need to worry about any other races. |
| 1536 | */ |
| 1537 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 1538 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 1539 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
| 1540 | reset_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1541 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1542 | ret = i915_reset(dev); |
| 1543 | |
| 1544 | if (ret == 0) { |
| 1545 | /* |
| 1546 | * After all the gem state is reset, increment the reset |
| 1547 | * counter and wake up everyone waiting for the reset to |
| 1548 | * complete. |
| 1549 | * |
| 1550 | * Since unlock operations are a one-sided barrier only, |
| 1551 | * we need to insert a barrier here to order any seqno |
| 1552 | * updates before |
| 1553 | * the counter increment. |
| 1554 | */ |
| 1555 | smp_mb__before_atomic_inc(); |
| 1556 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
| 1557 | |
| 1558 | kobject_uevent_env(&dev->primary->kdev.kobj, |
| 1559 | KOBJ_CHANGE, reset_done_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1560 | } else { |
| 1561 | atomic_set(&error->reset_counter, I915_WEDGED); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1562 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1563 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1564 | for_each_ring(ring, dev_priv, i) |
| 1565 | wake_up_all(&ring->irq_queue); |
| 1566 | |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 1567 | intel_display_handle_reset(dev); |
| 1568 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1569 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1570 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1571 | } |
| 1572 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1573 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1574 | { |
| 1575 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 1576 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1577 | u32 eir = I915_READ(EIR); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 1578 | int pipe, i; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1579 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1580 | if (!eir) |
| 1581 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1582 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1583 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1584 | |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 1585 | i915_get_extra_instdone(dev, instdone); |
| 1586 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1587 | if (IS_G4X(dev)) { |
| 1588 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 1589 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1590 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1591 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1592 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 1593 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 1594 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1595 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1596 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1597 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1598 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1599 | } |
| 1600 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 1601 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1602 | pr_err("page table error\n"); |
| 1603 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1604 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1605 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1606 | } |
| 1607 | } |
| 1608 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1609 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1610 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 1611 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1612 | pr_err("page table error\n"); |
| 1613 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1614 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1615 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1616 | } |
| 1617 | } |
| 1618 | |
| 1619 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1620 | pr_err("memory refresh error:\n"); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1621 | for_each_pipe(pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1622 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1623 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1624 | /* pipestat has already been acked */ |
| 1625 | } |
| 1626 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1627 | pr_err("instruction error\n"); |
| 1628 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 1629 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 1630 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1631 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1632 | u32 ipeir = I915_READ(IPEIR); |
| 1633 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1634 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 1635 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1636 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1637 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1638 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1639 | } else { |
| 1640 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1641 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1642 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1643 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1644 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1645 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1646 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1647 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1648 | } |
| 1649 | } |
| 1650 | |
| 1651 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1652 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1653 | eir = I915_READ(EIR); |
| 1654 | if (eir) { |
| 1655 | /* |
| 1656 | * some errors might have become stuck, |
| 1657 | * mask them. |
| 1658 | */ |
| 1659 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 1660 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 1661 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 1662 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1663 | } |
| 1664 | |
| 1665 | /** |
| 1666 | * i915_handle_error - handle an error interrupt |
| 1667 | * @dev: drm device |
| 1668 | * |
| 1669 | * Do some basic checking of regsiter state at error interrupt time and |
| 1670 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 1671 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 1672 | * so userspace knows something bad happened (should trigger collection |
| 1673 | * of a ring dump etc.). |
| 1674 | */ |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1675 | void i915_handle_error(struct drm_device *dev, bool wedged) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1676 | { |
| 1677 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1678 | struct intel_ring_buffer *ring; |
| 1679 | int i; |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1680 | |
| 1681 | i915_capture_error_state(dev); |
| 1682 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1683 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1684 | if (wedged) { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1685 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
| 1686 | &dev_priv->gpu_error.reset_counter); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1687 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1688 | /* |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1689 | * Wakeup waiting processes so that the reset work item |
| 1690 | * doesn't deadlock trying to grab various locks. |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1691 | */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1692 | for_each_ring(ring, dev_priv, i) |
| 1693 | wake_up_all(&ring->irq_queue); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1694 | } |
| 1695 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1696 | queue_work(dev_priv->wq, &dev_priv->gpu_error.work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1697 | } |
| 1698 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 1699 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1700 | { |
| 1701 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1702 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1704 | struct drm_i915_gem_object *obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1705 | struct intel_unpin_work *work; |
| 1706 | unsigned long flags; |
| 1707 | bool stall_detected; |
| 1708 | |
| 1709 | /* Ignore early vblank irqs */ |
| 1710 | if (intel_crtc == NULL) |
| 1711 | return; |
| 1712 | |
| 1713 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1714 | work = intel_crtc->unpin_work; |
| 1715 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 1716 | if (work == NULL || |
| 1717 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || |
| 1718 | !work->enable_stall_check) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1719 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 1720 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1721 | return; |
| 1722 | } |
| 1723 | |
| 1724 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1725 | obj = work->pending_flip_obj; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1726 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1727 | int dspsurf = DSPSURF(intel_crtc->plane); |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 1728 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1729 | i915_gem_obj_ggtt_offset(obj); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1730 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1731 | int dspaddr = DSPADDR(intel_crtc->plane); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1732 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1733 | crtc->y * crtc->fb->pitches[0] + |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1734 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 1735 | } |
| 1736 | |
| 1737 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1738 | |
| 1739 | if (stall_detected) { |
| 1740 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 1741 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 1742 | } |
| 1743 | } |
| 1744 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1745 | /* Called from drm generic code, passed 'crtc' which |
| 1746 | * we use as a pipe index |
| 1747 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1748 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1749 | { |
| 1750 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1751 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1752 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1753 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1754 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1755 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1756 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1757 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1758 | i915_enable_pipestat(dev_priv, pipe, |
| 1759 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1760 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1761 | i915_enable_pipestat(dev_priv, pipe, |
| 1762 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1763 | |
| 1764 | /* maintain vblank delivery even in deep C-states */ |
| 1765 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1766 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1767 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1768 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1769 | return 0; |
| 1770 | } |
| 1771 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1772 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1773 | { |
| 1774 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1775 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1776 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
| 1777 | DE_PIPE_VBLANK_ILK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1778 | |
| 1779 | if (!i915_pipe_enabled(dev, pipe)) |
| 1780 | return -EINVAL; |
| 1781 | |
| 1782 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1783 | ironlake_enable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1784 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1785 | |
| 1786 | return 0; |
| 1787 | } |
| 1788 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1789 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
| 1790 | { |
| 1791 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1792 | unsigned long irqflags; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1793 | u32 imr; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1794 | |
| 1795 | if (!i915_pipe_enabled(dev, pipe)) |
| 1796 | return -EINVAL; |
| 1797 | |
| 1798 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1799 | imr = I915_READ(VLV_IMR); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1800 | if (pipe == 0) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1801 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1802 | else |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1803 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1804 | I915_WRITE(VLV_IMR, imr); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1805 | i915_enable_pipestat(dev_priv, pipe, |
| 1806 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1807 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1808 | |
| 1809 | return 0; |
| 1810 | } |
| 1811 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1812 | /* Called from drm generic code, passed 'crtc' which |
| 1813 | * we use as a pipe index |
| 1814 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1815 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1816 | { |
| 1817 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1818 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1819 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1820 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1821 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1822 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1823 | |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1824 | i915_disable_pipestat(dev_priv, pipe, |
| 1825 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 1826 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
| 1827 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1828 | } |
| 1829 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1830 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1831 | { |
| 1832 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1833 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1834 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
| 1835 | DE_PIPE_VBLANK_ILK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1836 | |
| 1837 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1838 | ironlake_disable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1839 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1840 | } |
| 1841 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1842 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
| 1843 | { |
| 1844 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1845 | unsigned long irqflags; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1846 | u32 imr; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1847 | |
| 1848 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1849 | i915_disable_pipestat(dev_priv, pipe, |
| 1850 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1851 | imr = I915_READ(VLV_IMR); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1852 | if (pipe == 0) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1853 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1854 | else |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1855 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1856 | I915_WRITE(VLV_IMR, imr); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1857 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1858 | } |
| 1859 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1860 | static u32 |
| 1861 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1862 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1863 | return list_entry(ring->request_list.prev, |
| 1864 | struct drm_i915_gem_request, list)->seqno; |
| 1865 | } |
| 1866 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1867 | static bool |
| 1868 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1869 | { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1870 | return (list_empty(&ring->request_list) || |
| 1871 | i915_seqno_passed(seqno, ring_last_seqno(ring))); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1872 | } |
| 1873 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1874 | static struct intel_ring_buffer * |
| 1875 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1876 | { |
| 1877 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1878 | u32 cmd, ipehr, acthd, acthd_min; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1879 | |
| 1880 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); |
| 1881 | if ((ipehr & ~(0x3 << 16)) != |
| 1882 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1883 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1884 | |
| 1885 | /* ACTHD is likely pointing to the dword after the actual command, |
| 1886 | * so scan backwards until we find the MBOX. |
| 1887 | */ |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1888 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1889 | acthd_min = max((int)acthd - 3 * 4, 0); |
| 1890 | do { |
| 1891 | cmd = ioread32(ring->virtual_start + acthd); |
| 1892 | if (cmd == ipehr) |
| 1893 | break; |
| 1894 | |
| 1895 | acthd -= 4; |
| 1896 | if (acthd < acthd_min) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1897 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1898 | } while (1); |
| 1899 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1900 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
| 1901 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1902 | } |
| 1903 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1904 | static int semaphore_passed(struct intel_ring_buffer *ring) |
| 1905 | { |
| 1906 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1907 | struct intel_ring_buffer *signaller; |
| 1908 | u32 seqno, ctl; |
| 1909 | |
| 1910 | ring->hangcheck.deadlock = true; |
| 1911 | |
| 1912 | signaller = semaphore_waits_for(ring, &seqno); |
| 1913 | if (signaller == NULL || signaller->hangcheck.deadlock) |
| 1914 | return -1; |
| 1915 | |
| 1916 | /* cursory check for an unkickable deadlock */ |
| 1917 | ctl = I915_READ_CTL(signaller); |
| 1918 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) |
| 1919 | return -1; |
| 1920 | |
| 1921 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); |
| 1922 | } |
| 1923 | |
| 1924 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) |
| 1925 | { |
| 1926 | struct intel_ring_buffer *ring; |
| 1927 | int i; |
| 1928 | |
| 1929 | for_each_ring(ring, dev_priv, i) |
| 1930 | ring->hangcheck.deadlock = false; |
| 1931 | } |
| 1932 | |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 1933 | static enum intel_ring_hangcheck_action |
| 1934 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1935 | { |
| 1936 | struct drm_device *dev = ring->dev; |
| 1937 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1938 | u32 tmp; |
| 1939 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1940 | if (ring->hangcheck.acthd != acthd) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1941 | return HANGCHECK_ACTIVE; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1942 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1943 | if (IS_GEN2(dev)) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1944 | return HANGCHECK_HUNG; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1945 | |
| 1946 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 1947 | * If so we can simply poke the RB_WAIT bit |
| 1948 | * and break the hang. This should work on |
| 1949 | * all but the second generation chipsets. |
| 1950 | */ |
| 1951 | tmp = I915_READ_CTL(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1952 | if (tmp & RING_WAIT) { |
| 1953 | DRM_ERROR("Kicking stuck wait on %s\n", |
| 1954 | ring->name); |
| 1955 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1956 | return HANGCHECK_KICK; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1957 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1958 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1959 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
| 1960 | switch (semaphore_passed(ring)) { |
| 1961 | default: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1962 | return HANGCHECK_HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1963 | case 1: |
| 1964 | DRM_ERROR("Kicking stuck semaphore on %s\n", |
| 1965 | ring->name); |
| 1966 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1967 | return HANGCHECK_KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1968 | case 0: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1969 | return HANGCHECK_WAIT; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1970 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1971 | } |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 1972 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1973 | return HANGCHECK_HUNG; |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 1974 | } |
| 1975 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1976 | /** |
| 1977 | * This is called when the chip hasn't reported back with completed |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1978 | * batchbuffers in a long time. We keep track per ring seqno progress and |
| 1979 | * if there are no progress, hangcheck score for that ring is increased. |
| 1980 | * Further, acthd is inspected to see if the ring is stuck. On stuck case |
| 1981 | * we kick the ring. If we see no progress on three subsequent calls |
| 1982 | * we assume chip is wedged and try to fix it by resetting the chip. |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1983 | */ |
Damien Lespiau | a658b5d | 2013-08-08 22:28:56 +0100 | [diff] [blame] | 1984 | static void i915_hangcheck_elapsed(unsigned long data) |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1985 | { |
| 1986 | struct drm_device *dev = (struct drm_device *)data; |
| 1987 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1988 | struct intel_ring_buffer *ring; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1989 | int i; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1990 | int busy_count = 0, rings_hung = 0; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1991 | bool stuck[I915_NUM_RINGS] = { 0 }; |
| 1992 | #define BUSY 1 |
| 1993 | #define KICK 5 |
| 1994 | #define HUNG 20 |
| 1995 | #define FIRE 30 |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1996 | |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1997 | if (!i915_enable_hangcheck) |
| 1998 | return; |
| 1999 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2000 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2001 | u32 seqno, acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2002 | bool busy = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2003 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2004 | semaphore_clear_deadlocks(dev_priv); |
| 2005 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2006 | seqno = ring->get_seqno(ring, false); |
| 2007 | acthd = intel_ring_get_active_head(ring); |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 2008 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2009 | if (ring->hangcheck.seqno == seqno) { |
| 2010 | if (ring_idle(ring, seqno)) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2011 | ring->hangcheck.action = HANGCHECK_IDLE; |
| 2012 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2013 | if (waitqueue_active(&ring->irq_queue)) { |
| 2014 | /* Issue a wake-up to catch stuck h/w. */ |
| 2015 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", |
| 2016 | ring->name); |
| 2017 | wake_up_all(&ring->irq_queue); |
| 2018 | ring->hangcheck.score += HUNG; |
| 2019 | } else |
| 2020 | busy = false; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2021 | } else { |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2022 | /* We always increment the hangcheck score |
| 2023 | * if the ring is busy and still processing |
| 2024 | * the same request, so that no single request |
| 2025 | * can run indefinitely (such as a chain of |
| 2026 | * batches). The only time we do not increment |
| 2027 | * the hangcheck score on this ring, if this |
| 2028 | * ring is in a legitimate wait for another |
| 2029 | * ring. In that case the waiting ring is a |
| 2030 | * victim and we want to be sure we catch the |
| 2031 | * right culprit. Then every time we do kick |
| 2032 | * the ring, add a small increment to the |
| 2033 | * score so that we can catch a batch that is |
| 2034 | * being repeatedly kicked and so responsible |
| 2035 | * for stalling the machine. |
| 2036 | */ |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 2037 | ring->hangcheck.action = ring_stuck(ring, |
| 2038 | acthd); |
| 2039 | |
| 2040 | switch (ring->hangcheck.action) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2041 | case HANGCHECK_IDLE: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2042 | case HANGCHECK_WAIT: |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2043 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2044 | case HANGCHECK_ACTIVE: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 2045 | ring->hangcheck.score += BUSY; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2046 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2047 | case HANGCHECK_KICK: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 2048 | ring->hangcheck.score += KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2049 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2050 | case HANGCHECK_HUNG: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 2051 | ring->hangcheck.score += HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2052 | stuck[i] = true; |
| 2053 | break; |
| 2054 | } |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2055 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2056 | } else { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2057 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
| 2058 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2059 | /* Gradually reduce the count so that we catch DoS |
| 2060 | * attempts across multiple batches. |
| 2061 | */ |
| 2062 | if (ring->hangcheck.score > 0) |
| 2063 | ring->hangcheck.score--; |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 2064 | } |
| 2065 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2066 | ring->hangcheck.seqno = seqno; |
| 2067 | ring->hangcheck.acthd = acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2068 | busy_count += busy; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2069 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 2070 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2071 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2072 | if (ring->hangcheck.score > FIRE) { |
Daniel Vetter | b8d88d1 | 2013-08-28 10:57:59 +0200 | [diff] [blame] | 2073 | DRM_INFO("%s on %s\n", |
| 2074 | stuck[i] ? "stuck" : "no progress", |
| 2075 | ring->name); |
Chris Wilson | a43adf0 | 2013-06-10 11:20:22 +0100 | [diff] [blame] | 2076 | rings_hung++; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2077 | } |
| 2078 | } |
| 2079 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2080 | if (rings_hung) |
| 2081 | return i915_handle_error(dev, true); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2082 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2083 | if (busy_count) |
| 2084 | /* Reset timer case chip hangs without another request |
| 2085 | * being added */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2086 | i915_queue_hangcheck(dev); |
| 2087 | } |
| 2088 | |
| 2089 | void i915_queue_hangcheck(struct drm_device *dev) |
| 2090 | { |
| 2091 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2092 | if (!i915_enable_hangcheck) |
| 2093 | return; |
| 2094 | |
| 2095 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 2096 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2097 | } |
| 2098 | |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 2099 | static void ibx_irq_preinstall(struct drm_device *dev) |
| 2100 | { |
| 2101 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2102 | |
| 2103 | if (HAS_PCH_NOP(dev)) |
| 2104 | return; |
| 2105 | |
| 2106 | /* south display irq */ |
| 2107 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2108 | /* |
| 2109 | * SDEIER is also touched by the interrupt handler to work around missed |
| 2110 | * PCH interrupts. Hence we can't update it after the interrupt handler |
| 2111 | * is enabled - instead we unconditionally enable all PCH interrupt |
| 2112 | * sources here, but then only unmask them as needed with SDEIMR. |
| 2113 | */ |
| 2114 | I915_WRITE(SDEIER, 0xffffffff); |
| 2115 | POSTING_READ(SDEIER); |
| 2116 | } |
| 2117 | |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2118 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
| 2119 | { |
| 2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2121 | |
| 2122 | /* and GT */ |
| 2123 | I915_WRITE(GTIMR, 0xffffffff); |
| 2124 | I915_WRITE(GTIER, 0x0); |
| 2125 | POSTING_READ(GTIER); |
| 2126 | |
| 2127 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2128 | /* and PM */ |
| 2129 | I915_WRITE(GEN6_PMIMR, 0xffffffff); |
| 2130 | I915_WRITE(GEN6_PMIER, 0x0); |
| 2131 | POSTING_READ(GEN6_PMIER); |
| 2132 | } |
| 2133 | } |
| 2134 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2135 | /* drm_dma.h hooks |
| 2136 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2137 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2138 | { |
| 2139 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2140 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2141 | atomic_set(&dev_priv->irq_received, 0); |
| 2142 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2143 | I915_WRITE(HWSTAM, 0xeffe); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 2144 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2145 | I915_WRITE(DEIMR, 0xffffffff); |
| 2146 | I915_WRITE(DEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2147 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2148 | |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2149 | gen5_gt_irq_preinstall(dev); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 2150 | |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 2151 | ibx_irq_preinstall(dev); |
Ben Widawsky | 7d99163 | 2013-05-28 19:22:25 -0700 | [diff] [blame] | 2152 | } |
| 2153 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2154 | static void valleyview_irq_preinstall(struct drm_device *dev) |
| 2155 | { |
| 2156 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2157 | int pipe; |
| 2158 | |
| 2159 | atomic_set(&dev_priv->irq_received, 0); |
| 2160 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2161 | /* VLV magic */ |
| 2162 | I915_WRITE(VLV_IMR, 0); |
| 2163 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); |
| 2164 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); |
| 2165 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); |
| 2166 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2167 | /* and GT */ |
| 2168 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2169 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2170 | |
| 2171 | gen5_gt_irq_preinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2172 | |
| 2173 | I915_WRITE(DPINVGTT, 0xff); |
| 2174 | |
| 2175 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2176 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2177 | for_each_pipe(pipe) |
| 2178 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2179 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2180 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 2181 | I915_WRITE(VLV_IER, 0x0); |
| 2182 | POSTING_READ(VLV_IER); |
| 2183 | } |
| 2184 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2185 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2186 | { |
| 2187 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2188 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2189 | struct intel_encoder *intel_encoder; |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2190 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2191 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2192 | if (HAS_PCH_IBX(dev)) { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2193 | hotplug_irqs = SDE_HOTPLUG_MASK; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2194 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2195 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2196 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2197 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2198 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2199 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2200 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2201 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2202 | } |
| 2203 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2204 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2205 | |
| 2206 | /* |
| 2207 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 2208 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 2209 | * |
| 2210 | * This register is the same on all known PCH chips. |
| 2211 | */ |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2212 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 2213 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 2214 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 2215 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 2216 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 2217 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 2218 | } |
| 2219 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2220 | static void ibx_irq_postinstall(struct drm_device *dev) |
| 2221 | { |
| 2222 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2223 | u32 mask; |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2224 | |
Daniel Vetter | 692a04c | 2013-05-29 21:43:05 +0200 | [diff] [blame] | 2225 | if (HAS_PCH_NOP(dev)) |
| 2226 | return; |
| 2227 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2228 | if (HAS_PCH_IBX(dev)) { |
| 2229 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2230 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2231 | } else { |
| 2232 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; |
| 2233 | |
| 2234 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); |
| 2235 | } |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2236 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2237 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 2238 | I915_WRITE(SDEIMR, ~mask); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2239 | } |
| 2240 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2241 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
| 2242 | { |
| 2243 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2244 | u32 pm_irqs, gt_irqs; |
| 2245 | |
| 2246 | pm_irqs = gt_irqs = 0; |
| 2247 | |
| 2248 | dev_priv->gt_irq_mask = ~0; |
| 2249 | if (HAS_L3_GPU_CACHE(dev)) { |
| 2250 | /* L3 parity interrupt is always unmasked. */ |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 2251 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
| 2252 | gt_irqs |= GT_PARITY_ERROR(dev); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2253 | } |
| 2254 | |
| 2255 | gt_irqs |= GT_RENDER_USER_INTERRUPT; |
| 2256 | if (IS_GEN5(dev)) { |
| 2257 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | |
| 2258 | ILK_BSD_USER_INTERRUPT; |
| 2259 | } else { |
| 2260 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
| 2261 | } |
| 2262 | |
| 2263 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2264 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 2265 | I915_WRITE(GTIER, gt_irqs); |
| 2266 | POSTING_READ(GTIER); |
| 2267 | |
| 2268 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2269 | pm_irqs |= GEN6_PM_RPS_EVENTS; |
| 2270 | |
| 2271 | if (HAS_VEBOX(dev)) |
| 2272 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
| 2273 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 2274 | dev_priv->pm_irq_mask = 0xffffffff; |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2275 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 2276 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2277 | I915_WRITE(GEN6_PMIER, pm_irqs); |
| 2278 | POSTING_READ(GEN6_PMIER); |
| 2279 | } |
| 2280 | } |
| 2281 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2282 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2283 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2284 | unsigned long irqflags; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2285 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2286 | u32 display_mask, extra_mask; |
| 2287 | |
| 2288 | if (INTEL_INFO(dev)->gen >= 7) { |
| 2289 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 2290 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | |
| 2291 | DE_PLANEB_FLIP_DONE_IVB | |
| 2292 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | |
| 2293 | DE_ERR_INT_IVB); |
| 2294 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
| 2295 | DE_PIPEA_VBLANK_IVB); |
| 2296 | |
| 2297 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
| 2298 | } else { |
| 2299 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 2300 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
| 2301 | DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN | |
| 2302 | DE_PIPEA_FIFO_UNDERRUN | DE_POISON); |
| 2303 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; |
| 2304 | } |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2305 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2306 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2307 | |
| 2308 | /* should always can generate irq */ |
| 2309 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2310 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2311 | I915_WRITE(DEIER, display_mask | extra_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2312 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2313 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2314 | gen5_gt_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2315 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2316 | ibx_irq_postinstall(dev); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2317 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2318 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 6005ce4 | 2013-06-27 13:44:59 +0200 | [diff] [blame] | 2319 | /* Enable PCU event interrupts |
| 2320 | * |
| 2321 | * spinlocking not required here for correctness since interrupt |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2322 | * setup is guaranteed to run in single-threaded context. But we |
| 2323 | * need it to make the assert_spin_locked happy. */ |
| 2324 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2325 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2326 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2327 | } |
| 2328 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2329 | return 0; |
| 2330 | } |
| 2331 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2332 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 2333 | { |
| 2334 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2335 | u32 enable_mask; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2336 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2337 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2338 | |
| 2339 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2340 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2341 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2342 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2343 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 2344 | |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2345 | /* |
| 2346 | *Leave vblank interrupts masked initially. enable/disable will |
| 2347 | * toggle them based on usage. |
| 2348 | */ |
| 2349 | dev_priv->irq_mask = (~enable_mask) | |
| 2350 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2351 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2352 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2353 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2354 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2355 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2356 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 2357 | I915_WRITE(VLV_IER, enable_mask); |
| 2358 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2359 | I915_WRITE(PIPESTAT(0), 0xffff); |
| 2360 | I915_WRITE(PIPESTAT(1), 0xffff); |
| 2361 | POSTING_READ(VLV_IER); |
| 2362 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2363 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 2364 | * just to make the assert_spin_locked check happy. */ |
| 2365 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2366 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2367 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2368 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2369 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2370 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2371 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2372 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2373 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2374 | gen5_gt_irq_postinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2375 | |
| 2376 | /* ack & enable invalid PTE error interrupts */ |
| 2377 | #if 0 /* FIXME: add support to irq handler for checking these bits */ |
| 2378 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 2379 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); |
| 2380 | #endif |
| 2381 | |
| 2382 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2383 | |
| 2384 | return 0; |
| 2385 | } |
| 2386 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2387 | static void valleyview_irq_uninstall(struct drm_device *dev) |
| 2388 | { |
| 2389 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2390 | int pipe; |
| 2391 | |
| 2392 | if (!dev_priv) |
| 2393 | return; |
| 2394 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2395 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2396 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2397 | for_each_pipe(pipe) |
| 2398 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2399 | |
| 2400 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2401 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2402 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2403 | for_each_pipe(pipe) |
| 2404 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2405 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2406 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 2407 | I915_WRITE(VLV_IER, 0x0); |
| 2408 | POSTING_READ(VLV_IER); |
| 2409 | } |
| 2410 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2411 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2412 | { |
| 2413 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2414 | |
| 2415 | if (!dev_priv) |
| 2416 | return; |
| 2417 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2418 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2419 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2420 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2421 | |
| 2422 | I915_WRITE(DEIMR, 0xffffffff); |
| 2423 | I915_WRITE(DEIER, 0x0); |
| 2424 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2425 | if (IS_GEN7(dev)) |
| 2426 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2427 | |
| 2428 | I915_WRITE(GTIMR, 0xffffffff); |
| 2429 | I915_WRITE(GTIER, 0x0); |
| 2430 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 2431 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2432 | if (HAS_PCH_NOP(dev)) |
| 2433 | return; |
| 2434 | |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 2435 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2436 | I915_WRITE(SDEIER, 0x0); |
| 2437 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2438 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
| 2439 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2440 | } |
| 2441 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2442 | static void i8xx_irq_preinstall(struct drm_device * dev) |
| 2443 | { |
| 2444 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2445 | int pipe; |
| 2446 | |
| 2447 | atomic_set(&dev_priv->irq_received, 0); |
| 2448 | |
| 2449 | for_each_pipe(pipe) |
| 2450 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2451 | I915_WRITE16(IMR, 0xffff); |
| 2452 | I915_WRITE16(IER, 0x0); |
| 2453 | POSTING_READ16(IER); |
| 2454 | } |
| 2455 | |
| 2456 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 2457 | { |
| 2458 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2459 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2460 | I915_WRITE16(EMR, |
| 2461 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 2462 | |
| 2463 | /* Unmask the interrupts that we always want on. */ |
| 2464 | dev_priv->irq_mask = |
| 2465 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2466 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2467 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2468 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2469 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2470 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 2471 | |
| 2472 | I915_WRITE16(IER, |
| 2473 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2474 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2475 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 2476 | I915_USER_INTERRUPT); |
| 2477 | POSTING_READ16(IER); |
| 2478 | |
| 2479 | return 0; |
| 2480 | } |
| 2481 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2482 | /* |
| 2483 | * Returns true when a page flip has completed. |
| 2484 | */ |
| 2485 | static bool i8xx_handle_vblank(struct drm_device *dev, |
| 2486 | int pipe, u16 iir) |
| 2487 | { |
| 2488 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2489 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); |
| 2490 | |
| 2491 | if (!drm_handle_vblank(dev, pipe)) |
| 2492 | return false; |
| 2493 | |
| 2494 | if ((iir & flip_pending) == 0) |
| 2495 | return false; |
| 2496 | |
| 2497 | intel_prepare_page_flip(dev, pipe); |
| 2498 | |
| 2499 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 2500 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 2501 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 2502 | * the flip is completed (no longer pending). Since this doesn't raise |
| 2503 | * an interrupt per se, we watch for the change at vblank. |
| 2504 | */ |
| 2505 | if (I915_READ16(ISR) & flip_pending) |
| 2506 | return false; |
| 2507 | |
| 2508 | intel_finish_page_flip(dev, pipe); |
| 2509 | |
| 2510 | return true; |
| 2511 | } |
| 2512 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2513 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2514 | { |
| 2515 | struct drm_device *dev = (struct drm_device *) arg; |
| 2516 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2517 | u16 iir, new_iir; |
| 2518 | u32 pipe_stats[2]; |
| 2519 | unsigned long irqflags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2520 | int pipe; |
| 2521 | u16 flip_mask = |
| 2522 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2523 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 2524 | |
| 2525 | atomic_inc(&dev_priv->irq_received); |
| 2526 | |
| 2527 | iir = I915_READ16(IIR); |
| 2528 | if (iir == 0) |
| 2529 | return IRQ_NONE; |
| 2530 | |
| 2531 | while (iir & ~flip_mask) { |
| 2532 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2533 | * have been cleared after the pipestat interrupt was received. |
| 2534 | * It doesn't set the bit in iir again, but it still produces |
| 2535 | * interrupts (for non-MSI). |
| 2536 | */ |
| 2537 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2538 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2539 | i915_handle_error(dev, false); |
| 2540 | |
| 2541 | for_each_pipe(pipe) { |
| 2542 | int reg = PIPESTAT(pipe); |
| 2543 | pipe_stats[pipe] = I915_READ(reg); |
| 2544 | |
| 2545 | /* |
| 2546 | * Clear the PIPE*STAT regs before the IIR |
| 2547 | */ |
| 2548 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2549 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2550 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2551 | pipe_name(pipe)); |
| 2552 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2553 | } |
| 2554 | } |
| 2555 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2556 | |
| 2557 | I915_WRITE16(IIR, iir & ~flip_mask); |
| 2558 | new_iir = I915_READ16(IIR); /* Flush posted writes */ |
| 2559 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 2560 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2561 | |
| 2562 | if (iir & I915_USER_INTERRUPT) |
| 2563 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 2564 | |
| 2565 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2566 | i8xx_handle_vblank(dev, 0, iir)) |
| 2567 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2568 | |
| 2569 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2570 | i8xx_handle_vblank(dev, 1, iir)) |
| 2571 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2572 | |
| 2573 | iir = new_iir; |
| 2574 | } |
| 2575 | |
| 2576 | return IRQ_HANDLED; |
| 2577 | } |
| 2578 | |
| 2579 | static void i8xx_irq_uninstall(struct drm_device * dev) |
| 2580 | { |
| 2581 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2582 | int pipe; |
| 2583 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2584 | for_each_pipe(pipe) { |
| 2585 | /* Clear enable bits; then clear status bits */ |
| 2586 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2587 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 2588 | } |
| 2589 | I915_WRITE16(IMR, 0xffff); |
| 2590 | I915_WRITE16(IER, 0x0); |
| 2591 | I915_WRITE16(IIR, I915_READ16(IIR)); |
| 2592 | } |
| 2593 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2594 | static void i915_irq_preinstall(struct drm_device * dev) |
| 2595 | { |
| 2596 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2597 | int pipe; |
| 2598 | |
| 2599 | atomic_set(&dev_priv->irq_received, 0); |
| 2600 | |
| 2601 | if (I915_HAS_HOTPLUG(dev)) { |
| 2602 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2603 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2604 | } |
| 2605 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 2606 | I915_WRITE16(HWSTAM, 0xeffe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2607 | for_each_pipe(pipe) |
| 2608 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2609 | I915_WRITE(IMR, 0xffffffff); |
| 2610 | I915_WRITE(IER, 0x0); |
| 2611 | POSTING_READ(IER); |
| 2612 | } |
| 2613 | |
| 2614 | static int i915_irq_postinstall(struct drm_device *dev) |
| 2615 | { |
| 2616 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2617 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2618 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2619 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 2620 | |
| 2621 | /* Unmask the interrupts that we always want on. */ |
| 2622 | dev_priv->irq_mask = |
| 2623 | ~(I915_ASLE_INTERRUPT | |
| 2624 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2625 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2626 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2627 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2628 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2629 | |
| 2630 | enable_mask = |
| 2631 | I915_ASLE_INTERRUPT | |
| 2632 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2633 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2634 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 2635 | I915_USER_INTERRUPT; |
| 2636 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2637 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2638 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2639 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2640 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2641 | /* Enable in IER... */ |
| 2642 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 2643 | /* and unmask in IMR */ |
| 2644 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 2645 | } |
| 2646 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2647 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 2648 | I915_WRITE(IER, enable_mask); |
| 2649 | POSTING_READ(IER); |
| 2650 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 2651 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2652 | |
| 2653 | return 0; |
| 2654 | } |
| 2655 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2656 | /* |
| 2657 | * Returns true when a page flip has completed. |
| 2658 | */ |
| 2659 | static bool i915_handle_vblank(struct drm_device *dev, |
| 2660 | int plane, int pipe, u32 iir) |
| 2661 | { |
| 2662 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2663 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
| 2664 | |
| 2665 | if (!drm_handle_vblank(dev, pipe)) |
| 2666 | return false; |
| 2667 | |
| 2668 | if ((iir & flip_pending) == 0) |
| 2669 | return false; |
| 2670 | |
| 2671 | intel_prepare_page_flip(dev, plane); |
| 2672 | |
| 2673 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 2674 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 2675 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 2676 | * the flip is completed (no longer pending). Since this doesn't raise |
| 2677 | * an interrupt per se, we watch for the change at vblank. |
| 2678 | */ |
| 2679 | if (I915_READ(ISR) & flip_pending) |
| 2680 | return false; |
| 2681 | |
| 2682 | intel_finish_page_flip(dev, pipe); |
| 2683 | |
| 2684 | return true; |
| 2685 | } |
| 2686 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2687 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2688 | { |
| 2689 | struct drm_device *dev = (struct drm_device *) arg; |
| 2690 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2691 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2692 | unsigned long irqflags; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2693 | u32 flip_mask = |
| 2694 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2695 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2696 | int pipe, ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2697 | |
| 2698 | atomic_inc(&dev_priv->irq_received); |
| 2699 | |
| 2700 | iir = I915_READ(IIR); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2701 | do { |
| 2702 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2703 | bool blc_event = false; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2704 | |
| 2705 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2706 | * have been cleared after the pipestat interrupt was received. |
| 2707 | * It doesn't set the bit in iir again, but it still produces |
| 2708 | * interrupts (for non-MSI). |
| 2709 | */ |
| 2710 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2711 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2712 | i915_handle_error(dev, false); |
| 2713 | |
| 2714 | for_each_pipe(pipe) { |
| 2715 | int reg = PIPESTAT(pipe); |
| 2716 | pipe_stats[pipe] = I915_READ(reg); |
| 2717 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2718 | /* Clear the PIPE*STAT regs before the IIR */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2719 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2720 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2721 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2722 | pipe_name(pipe)); |
| 2723 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2724 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2725 | } |
| 2726 | } |
| 2727 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2728 | |
| 2729 | if (!irq_received) |
| 2730 | break; |
| 2731 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2732 | /* Consume port. Then clear IIR or we'll miss events */ |
| 2733 | if ((I915_HAS_HOTPLUG(dev)) && |
| 2734 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 2735 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2736 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2737 | |
| 2738 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 2739 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2740 | |
| 2741 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
| 2742 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2743 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2744 | POSTING_READ(PORT_HOTPLUG_STAT); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2745 | } |
| 2746 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2747 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2748 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 2749 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2750 | if (iir & I915_USER_INTERRUPT) |
| 2751 | notify_ring(dev, &dev_priv->ring[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2752 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2753 | for_each_pipe(pipe) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2754 | int plane = pipe; |
| 2755 | if (IS_MOBILE(dev)) |
| 2756 | plane = !plane; |
Ville Syrjälä | 5e2032d | 2013-02-19 15:16:38 +0200 | [diff] [blame] | 2757 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2758 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 2759 | i915_handle_vblank(dev, plane, pipe, iir)) |
| 2760 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2761 | |
| 2762 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2763 | blc_event = true; |
| 2764 | } |
| 2765 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2766 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2767 | intel_opregion_asle_intr(dev); |
| 2768 | |
| 2769 | /* With MSI, interrupts are only generated when iir |
| 2770 | * transitions from zero to nonzero. If another bit got |
| 2771 | * set while we were handling the existing iir bits, then |
| 2772 | * we would never get another interrupt. |
| 2773 | * |
| 2774 | * This is fine on non-MSI as well, as if we hit this path |
| 2775 | * we avoid exiting the interrupt handler only to generate |
| 2776 | * another one. |
| 2777 | * |
| 2778 | * Note that for MSI this could cause a stray interrupt report |
| 2779 | * if an interrupt landed in the time between writing IIR and |
| 2780 | * the posting read. This should be rare enough to never |
| 2781 | * trigger the 99% of 100,000 interrupts test for disabling |
| 2782 | * stray interrupts. |
| 2783 | */ |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2784 | ret = IRQ_HANDLED; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2785 | iir = new_iir; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2786 | } while (iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2787 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 2788 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2789 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2790 | return ret; |
| 2791 | } |
| 2792 | |
| 2793 | static void i915_irq_uninstall(struct drm_device * dev) |
| 2794 | { |
| 2795 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2796 | int pipe; |
| 2797 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2798 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2799 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2800 | if (I915_HAS_HOTPLUG(dev)) { |
| 2801 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2802 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2803 | } |
| 2804 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 2805 | I915_WRITE16(HWSTAM, 0xffff); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 2806 | for_each_pipe(pipe) { |
| 2807 | /* Clear enable bits; then clear status bits */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2808 | I915_WRITE(PIPESTAT(pipe), 0); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 2809 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 2810 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2811 | I915_WRITE(IMR, 0xffffffff); |
| 2812 | I915_WRITE(IER, 0x0); |
| 2813 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2814 | I915_WRITE(IIR, I915_READ(IIR)); |
| 2815 | } |
| 2816 | |
| 2817 | static void i965_irq_preinstall(struct drm_device * dev) |
| 2818 | { |
| 2819 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2820 | int pipe; |
| 2821 | |
| 2822 | atomic_set(&dev_priv->irq_received, 0); |
| 2823 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2824 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2825 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2826 | |
| 2827 | I915_WRITE(HWSTAM, 0xeffe); |
| 2828 | for_each_pipe(pipe) |
| 2829 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2830 | I915_WRITE(IMR, 0xffffffff); |
| 2831 | I915_WRITE(IER, 0x0); |
| 2832 | POSTING_READ(IER); |
| 2833 | } |
| 2834 | |
| 2835 | static int i965_irq_postinstall(struct drm_device *dev) |
| 2836 | { |
| 2837 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2838 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2839 | u32 error_mask; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2840 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2841 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2842 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2843 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2844 | I915_DISPLAY_PORT_INTERRUPT | |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2845 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2846 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2847 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2848 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2849 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2850 | |
| 2851 | enable_mask = ~dev_priv->irq_mask; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2852 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2853 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2854 | enable_mask |= I915_USER_INTERRUPT; |
| 2855 | |
| 2856 | if (IS_G4X(dev)) |
| 2857 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2858 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2859 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 2860 | * just to make the assert_spin_locked check happy. */ |
| 2861 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2862 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2863 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2864 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2865 | /* |
| 2866 | * Enable some error detection, note the instruction error mask |
| 2867 | * bit is reserved, so we leave it masked. |
| 2868 | */ |
| 2869 | if (IS_G4X(dev)) { |
| 2870 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 2871 | GM45_ERROR_MEM_PRIV | |
| 2872 | GM45_ERROR_CP_PRIV | |
| 2873 | I915_ERROR_MEMORY_REFRESH); |
| 2874 | } else { |
| 2875 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 2876 | I915_ERROR_MEMORY_REFRESH); |
| 2877 | } |
| 2878 | I915_WRITE(EMR, error_mask); |
| 2879 | |
| 2880 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 2881 | I915_WRITE(IER, enable_mask); |
| 2882 | POSTING_READ(IER); |
| 2883 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2884 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2885 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2886 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 2887 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2888 | |
| 2889 | return 0; |
| 2890 | } |
| 2891 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2892 | static void i915_hpd_irq_setup(struct drm_device *dev) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2893 | { |
| 2894 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 2895 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2896 | struct intel_encoder *intel_encoder; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2897 | u32 hotplug_en; |
| 2898 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 2899 | assert_spin_locked(&dev_priv->irq_lock); |
| 2900 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2901 | if (I915_HAS_HOTPLUG(dev)) { |
| 2902 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 2903 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; |
| 2904 | /* Note HDMI and DP share hotplug bits */ |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 2905 | /* enable bits are the same for all generations */ |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2906 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
| 2907 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
| 2908 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2909 | /* Programming the CRT detection parameters tends |
| 2910 | to generate a spurious hotplug event about three |
| 2911 | seconds later. So just do it once. |
| 2912 | */ |
| 2913 | if (IS_G4X(dev)) |
| 2914 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
Daniel Vetter | 85fc95b | 2013-03-27 15:47:11 +0100 | [diff] [blame] | 2915 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2916 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2917 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2918 | /* Ignore TV since it's buggy */ |
| 2919 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 2920 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2921 | } |
| 2922 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2923 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2924 | { |
| 2925 | struct drm_device *dev = (struct drm_device *) arg; |
| 2926 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2927 | u32 iir, new_iir; |
| 2928 | u32 pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2929 | unsigned long irqflags; |
| 2930 | int irq_received; |
| 2931 | int ret = IRQ_NONE, pipe; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2932 | u32 flip_mask = |
| 2933 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2934 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2935 | |
| 2936 | atomic_inc(&dev_priv->irq_received); |
| 2937 | |
| 2938 | iir = I915_READ(IIR); |
| 2939 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2940 | for (;;) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2941 | bool blc_event = false; |
| 2942 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2943 | irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2944 | |
| 2945 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2946 | * have been cleared after the pipestat interrupt was received. |
| 2947 | * It doesn't set the bit in iir again, but it still produces |
| 2948 | * interrupts (for non-MSI). |
| 2949 | */ |
| 2950 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2951 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2952 | i915_handle_error(dev, false); |
| 2953 | |
| 2954 | for_each_pipe(pipe) { |
| 2955 | int reg = PIPESTAT(pipe); |
| 2956 | pipe_stats[pipe] = I915_READ(reg); |
| 2957 | |
| 2958 | /* |
| 2959 | * Clear the PIPE*STAT regs before the IIR |
| 2960 | */ |
| 2961 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2962 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2963 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2964 | pipe_name(pipe)); |
| 2965 | I915_WRITE(reg, pipe_stats[pipe]); |
| 2966 | irq_received = 1; |
| 2967 | } |
| 2968 | } |
| 2969 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2970 | |
| 2971 | if (!irq_received) |
| 2972 | break; |
| 2973 | |
| 2974 | ret = IRQ_HANDLED; |
| 2975 | |
| 2976 | /* Consume port. Then clear IIR or we'll miss events */ |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2977 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2978 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2979 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
| 2980 | HOTPLUG_INT_STATUS_G4X : |
Daniel Vetter | 4f7fd70 | 2013-06-24 21:33:28 +0200 | [diff] [blame] | 2981 | HOTPLUG_INT_STATUS_I915); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2982 | |
| 2983 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 2984 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2985 | |
| 2986 | intel_hpd_irq_handler(dev, hotplug_trigger, |
| 2987 | IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); |
| 2988 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2989 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 2990 | I915_READ(PORT_HOTPLUG_STAT); |
| 2991 | } |
| 2992 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2993 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2994 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 2995 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2996 | if (iir & I915_USER_INTERRUPT) |
| 2997 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 2998 | if (iir & I915_BSD_USER_INTERRUPT) |
| 2999 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 3000 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3001 | for_each_pipe(pipe) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 3002 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3003 | i915_handle_vblank(dev, pipe, pipe, iir)) |
| 3004 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3005 | |
| 3006 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 3007 | blc_event = true; |
| 3008 | } |
| 3009 | |
| 3010 | |
| 3011 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 3012 | intel_opregion_asle_intr(dev); |
| 3013 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 3014 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 3015 | gmbus_irq_handler(dev); |
| 3016 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3017 | /* With MSI, interrupts are only generated when iir |
| 3018 | * transitions from zero to nonzero. If another bit got |
| 3019 | * set while we were handling the existing iir bits, then |
| 3020 | * we would never get another interrupt. |
| 3021 | * |
| 3022 | * This is fine on non-MSI as well, as if we hit this path |
| 3023 | * we avoid exiting the interrupt handler only to generate |
| 3024 | * another one. |
| 3025 | * |
| 3026 | * Note that for MSI this could cause a stray interrupt report |
| 3027 | * if an interrupt landed in the time between writing IIR and |
| 3028 | * the posting read. This should be rare enough to never |
| 3029 | * trigger the 99% of 100,000 interrupts test for disabling |
| 3030 | * stray interrupts. |
| 3031 | */ |
| 3032 | iir = new_iir; |
| 3033 | } |
| 3034 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 3035 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 3036 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3037 | return ret; |
| 3038 | } |
| 3039 | |
| 3040 | static void i965_irq_uninstall(struct drm_device * dev) |
| 3041 | { |
| 3042 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3043 | int pipe; |
| 3044 | |
| 3045 | if (!dev_priv) |
| 3046 | return; |
| 3047 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3048 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 3049 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 3050 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3051 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3052 | |
| 3053 | I915_WRITE(HWSTAM, 0xffffffff); |
| 3054 | for_each_pipe(pipe) |
| 3055 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3056 | I915_WRITE(IMR, 0xffffffff); |
| 3057 | I915_WRITE(IER, 0x0); |
| 3058 | |
| 3059 | for_each_pipe(pipe) |
| 3060 | I915_WRITE(PIPESTAT(pipe), |
| 3061 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
| 3062 | I915_WRITE(IIR, I915_READ(IIR)); |
| 3063 | } |
| 3064 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3065 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
| 3066 | { |
| 3067 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; |
| 3068 | struct drm_device *dev = dev_priv->dev; |
| 3069 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 3070 | unsigned long irqflags; |
| 3071 | int i; |
| 3072 | |
| 3073 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3074 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
| 3075 | struct drm_connector *connector; |
| 3076 | |
| 3077 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) |
| 3078 | continue; |
| 3079 | |
| 3080 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 3081 | |
| 3082 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 3083 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3084 | |
| 3085 | if (intel_connector->encoder->hpd_pin == i) { |
| 3086 | if (connector->polled != intel_connector->polled) |
| 3087 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", |
| 3088 | drm_get_connector_name(connector)); |
| 3089 | connector->polled = intel_connector->polled; |
| 3090 | if (!connector->polled) |
| 3091 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 3092 | } |
| 3093 | } |
| 3094 | } |
| 3095 | if (dev_priv->display.hpd_irq_setup) |
| 3096 | dev_priv->display.hpd_irq_setup(dev); |
| 3097 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3098 | } |
| 3099 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3100 | void intel_irq_init(struct drm_device *dev) |
| 3101 | { |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 3102 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3103 | |
| 3104 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3105 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3106 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3107 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 3108 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3109 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 3110 | i915_hangcheck_elapsed, |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 3111 | (unsigned long) dev); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3112 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
| 3113 | (unsigned long) dev_priv); |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 3114 | |
Tomas Janousek | 97a19a2 | 2012-12-08 13:48:13 +0100 | [diff] [blame] | 3115 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 3116 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3117 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 3118 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Eugeni Dodonov | 7d4e146 | 2012-05-09 15:37:09 -0300 | [diff] [blame] | 3119 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3120 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 3121 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
| 3122 | } |
| 3123 | |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 3124 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3125 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
| 3126 | else |
| 3127 | dev->driver->get_vblank_timestamp = NULL; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3128 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 3129 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3130 | if (IS_VALLEYVIEW(dev)) { |
| 3131 | dev->driver->irq_handler = valleyview_irq_handler; |
| 3132 | dev->driver->irq_preinstall = valleyview_irq_preinstall; |
| 3133 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
| 3134 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
| 3135 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 3136 | dev->driver->disable_vblank = valleyview_disable_vblank; |
Egbert Eich | fa00abe | 2013-02-25 12:06:48 -0500 | [diff] [blame] | 3137 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3138 | } else if (HAS_PCH_SPLIT(dev)) { |
| 3139 | dev->driver->irq_handler = ironlake_irq_handler; |
| 3140 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 3141 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 3142 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 3143 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 3144 | dev->driver->disable_vblank = ironlake_disable_vblank; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3145 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3146 | } else { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3147 | if (INTEL_INFO(dev)->gen == 2) { |
| 3148 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
| 3149 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 3150 | dev->driver->irq_handler = i8xx_irq_handler; |
| 3151 | dev->driver->irq_uninstall = i8xx_irq_uninstall; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3152 | } else if (INTEL_INFO(dev)->gen == 3) { |
| 3153 | dev->driver->irq_preinstall = i915_irq_preinstall; |
| 3154 | dev->driver->irq_postinstall = i915_irq_postinstall; |
| 3155 | dev->driver->irq_uninstall = i915_irq_uninstall; |
| 3156 | dev->driver->irq_handler = i915_irq_handler; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3157 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3158 | } else { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3159 | dev->driver->irq_preinstall = i965_irq_preinstall; |
| 3160 | dev->driver->irq_postinstall = i965_irq_postinstall; |
| 3161 | dev->driver->irq_uninstall = i965_irq_uninstall; |
| 3162 | dev->driver->irq_handler = i965_irq_handler; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3163 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3164 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3165 | dev->driver->enable_vblank = i915_enable_vblank; |
| 3166 | dev->driver->disable_vblank = i915_disable_vblank; |
| 3167 | } |
| 3168 | } |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3169 | |
| 3170 | void intel_hpd_init(struct drm_device *dev) |
| 3171 | { |
| 3172 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3173 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 3174 | struct drm_connector *connector; |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3175 | unsigned long irqflags; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3176 | int i; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3177 | |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3178 | for (i = 1; i < HPD_NUM_PINS; i++) { |
| 3179 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
| 3180 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 3181 | } |
| 3182 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 3183 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3184 | connector->polled = intel_connector->polled; |
| 3185 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
| 3186 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 3187 | } |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3188 | |
| 3189 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3190 | * just to make the assert_spin_locked checks happy. */ |
| 3191 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3192 | if (dev_priv->display.hpd_irq_setup) |
| 3193 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3194 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3195 | } |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 3196 | |
| 3197 | /* Disable interrupts so we can allow Package C8+. */ |
| 3198 | void hsw_pc8_disable_interrupts(struct drm_device *dev) |
| 3199 | { |
| 3200 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3201 | unsigned long irqflags; |
| 3202 | |
| 3203 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3204 | |
| 3205 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); |
| 3206 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); |
| 3207 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); |
| 3208 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); |
| 3209 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); |
| 3210 | |
| 3211 | ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB); |
| 3212 | ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT); |
| 3213 | ilk_disable_gt_irq(dev_priv, 0xffffffff); |
| 3214 | snb_disable_pm_irq(dev_priv, 0xffffffff); |
| 3215 | |
| 3216 | dev_priv->pc8.irqs_disabled = true; |
| 3217 | |
| 3218 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3219 | } |
| 3220 | |
| 3221 | /* Restore interrupts so we can recover from Package C8+. */ |
| 3222 | void hsw_pc8_restore_interrupts(struct drm_device *dev) |
| 3223 | { |
| 3224 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3225 | unsigned long irqflags; |
| 3226 | uint32_t val, expected; |
| 3227 | |
| 3228 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3229 | |
| 3230 | val = I915_READ(DEIMR); |
| 3231 | expected = ~DE_PCH_EVENT_IVB; |
| 3232 | WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected); |
| 3233 | |
| 3234 | val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT; |
| 3235 | expected = ~SDE_HOTPLUG_MASK_CPT; |
| 3236 | WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n", |
| 3237 | val, expected); |
| 3238 | |
| 3239 | val = I915_READ(GTIMR); |
| 3240 | expected = 0xffffffff; |
| 3241 | WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected); |
| 3242 | |
| 3243 | val = I915_READ(GEN6_PMIMR); |
| 3244 | expected = 0xffffffff; |
| 3245 | WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val, |
| 3246 | expected); |
| 3247 | |
| 3248 | dev_priv->pc8.irqs_disabled = false; |
| 3249 | |
| 3250 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); |
| 3251 | ibx_enable_display_interrupt(dev_priv, |
| 3252 | ~dev_priv->pc8.regsave.sdeimr & |
| 3253 | ~SDE_HOTPLUG_MASK_CPT); |
| 3254 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); |
| 3255 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); |
| 3256 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); |
| 3257 | |
| 3258 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3259 | } |