Peter Ujfalusi | 9ac33b0 | 2014-05-07 13:20:47 +0300 | [diff] [blame] | 1 | /* |
| 2 | * DRA7 ATL (Audio Tracking Logic) clock driver |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 13 | * kind, whether express or implied; without even the implied warranty |
| 14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/clk-provider.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/of_address.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/pm_runtime.h> |
| 26 | |
| 27 | #define DRA7_ATL_INSTANCES 4 |
| 28 | |
| 29 | #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80)) |
| 30 | #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80)) |
| 31 | #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80)) |
| 32 | #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80)) |
| 33 | #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80)) |
| 34 | #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80)) |
| 35 | #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80)) |
| 36 | |
| 37 | #define DRA7_ATL_SWEN BIT(0) |
| 38 | #define DRA7_ATL_DIVIDER_MASK (0x1f) |
| 39 | #define DRA7_ATL_PCLKMUX BIT(0) |
| 40 | struct dra7_atl_clock_info; |
| 41 | |
| 42 | struct dra7_atl_desc { |
| 43 | struct clk *clk; |
| 44 | struct clk_hw hw; |
| 45 | struct dra7_atl_clock_info *cinfo; |
| 46 | int id; |
| 47 | |
| 48 | bool probed; /* the driver for the IP has been loaded */ |
| 49 | bool valid; /* configured */ |
| 50 | bool enabled; |
| 51 | u32 bws; /* Baseband Word Select Mux */ |
| 52 | u32 aws; /* Audio Word Select Mux */ |
| 53 | u32 divider; /* Cached divider value */ |
| 54 | }; |
| 55 | |
| 56 | struct dra7_atl_clock_info { |
| 57 | struct device *dev; |
| 58 | void __iomem *iobase; |
| 59 | |
| 60 | struct dra7_atl_desc *cdesc; |
| 61 | }; |
| 62 | |
| 63 | #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw) |
| 64 | |
| 65 | static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg, |
| 66 | u32 val) |
| 67 | { |
| 68 | __raw_writel(val, cinfo->iobase + reg); |
| 69 | } |
| 70 | |
| 71 | static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg) |
| 72 | { |
| 73 | return __raw_readl(cinfo->iobase + reg); |
| 74 | } |
| 75 | |
| 76 | static int atl_clk_enable(struct clk_hw *hw) |
| 77 | { |
| 78 | struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
| 79 | |
| 80 | if (!cdesc->probed) |
| 81 | goto out; |
| 82 | |
| 83 | if (unlikely(!cdesc->valid)) |
| 84 | dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n", |
| 85 | cdesc->id); |
| 86 | pm_runtime_get_sync(cdesc->cinfo->dev); |
| 87 | |
| 88 | atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id), |
| 89 | cdesc->divider - 1); |
| 90 | atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN); |
| 91 | |
| 92 | out: |
| 93 | cdesc->enabled = true; |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static void atl_clk_disable(struct clk_hw *hw) |
| 99 | { |
| 100 | struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
| 101 | |
| 102 | if (!cdesc->probed) |
| 103 | goto out; |
| 104 | |
| 105 | atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0); |
| 106 | pm_runtime_put_sync(cdesc->cinfo->dev); |
| 107 | |
| 108 | out: |
| 109 | cdesc->enabled = false; |
| 110 | } |
| 111 | |
| 112 | static int atl_clk_is_enabled(struct clk_hw *hw) |
| 113 | { |
| 114 | struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
| 115 | |
| 116 | return cdesc->enabled; |
| 117 | } |
| 118 | |
| 119 | static unsigned long atl_clk_recalc_rate(struct clk_hw *hw, |
| 120 | unsigned long parent_rate) |
| 121 | { |
| 122 | struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
| 123 | |
| 124 | return parent_rate / cdesc->divider; |
| 125 | } |
| 126 | |
| 127 | static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 128 | unsigned long *parent_rate) |
| 129 | { |
| 130 | unsigned divider; |
| 131 | |
| 132 | divider = (*parent_rate + rate / 2) / rate; |
| 133 | if (divider > DRA7_ATL_DIVIDER_MASK + 1) |
| 134 | divider = DRA7_ATL_DIVIDER_MASK + 1; |
| 135 | |
| 136 | return *parent_rate / divider; |
| 137 | } |
| 138 | |
| 139 | static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 140 | unsigned long parent_rate) |
| 141 | { |
| 142 | struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
| 143 | u32 divider; |
| 144 | |
| 145 | divider = ((parent_rate + rate / 2) / rate) - 1; |
| 146 | if (divider > DRA7_ATL_DIVIDER_MASK) |
| 147 | divider = DRA7_ATL_DIVIDER_MASK; |
| 148 | |
| 149 | cdesc->divider = divider + 1; |
| 150 | |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | const struct clk_ops atl_clk_ops = { |
| 155 | .enable = atl_clk_enable, |
| 156 | .disable = atl_clk_disable, |
| 157 | .is_enabled = atl_clk_is_enabled, |
| 158 | .recalc_rate = atl_clk_recalc_rate, |
| 159 | .round_rate = atl_clk_round_rate, |
| 160 | .set_rate = atl_clk_set_rate, |
| 161 | }; |
| 162 | |
| 163 | static void __init of_dra7_atl_clock_setup(struct device_node *node) |
| 164 | { |
| 165 | struct dra7_atl_desc *clk_hw = NULL; |
| 166 | struct clk_init_data init = { 0 }; |
| 167 | const char **parent_names = NULL; |
| 168 | struct clk *clk; |
| 169 | |
| 170 | clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
| 171 | if (!clk_hw) { |
| 172 | pr_err("%s: could not allocate dra7_atl_desc\n", __func__); |
| 173 | return; |
| 174 | } |
| 175 | |
| 176 | clk_hw->hw.init = &init; |
| 177 | clk_hw->divider = 1; |
| 178 | init.name = node->name; |
| 179 | init.ops = &atl_clk_ops; |
| 180 | init.flags = CLK_IGNORE_UNUSED; |
| 181 | init.num_parents = of_clk_get_parent_count(node); |
| 182 | |
| 183 | if (init.num_parents != 1) { |
| 184 | pr_err("%s: atl clock %s must have 1 parent\n", __func__, |
| 185 | node->name); |
| 186 | goto cleanup; |
| 187 | } |
| 188 | |
| 189 | parent_names = kzalloc(sizeof(char *), GFP_KERNEL); |
| 190 | |
| 191 | if (!parent_names) |
| 192 | goto cleanup; |
| 193 | |
| 194 | parent_names[0] = of_clk_get_parent_name(node, 0); |
| 195 | |
| 196 | init.parent_names = parent_names; |
| 197 | |
| 198 | clk = clk_register(NULL, &clk_hw->hw); |
| 199 | |
| 200 | if (!IS_ERR(clk)) { |
| 201 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
Tero Kristo | 73b5d5f | 2014-09-12 16:39:07 +0300 | [diff] [blame] | 202 | kfree(parent_names); |
Peter Ujfalusi | 9ac33b0 | 2014-05-07 13:20:47 +0300 | [diff] [blame] | 203 | return; |
| 204 | } |
| 205 | cleanup: |
| 206 | kfree(parent_names); |
| 207 | kfree(clk_hw); |
| 208 | } |
| 209 | CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup); |
| 210 | |
| 211 | static int of_dra7_atl_clk_probe(struct platform_device *pdev) |
| 212 | { |
| 213 | struct device_node *node = pdev->dev.of_node; |
| 214 | struct dra7_atl_clock_info *cinfo; |
| 215 | int i; |
| 216 | int ret = 0; |
| 217 | |
| 218 | if (!node) |
| 219 | return -ENODEV; |
| 220 | |
| 221 | cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL); |
| 222 | if (!cinfo) |
| 223 | return -ENOMEM; |
| 224 | |
| 225 | cinfo->iobase = of_iomap(node, 0); |
| 226 | cinfo->dev = &pdev->dev; |
| 227 | pm_runtime_enable(cinfo->dev); |
Peter Ujfalusi | 04ed831 | 2014-09-29 11:10:33 +0300 | [diff] [blame^] | 228 | pm_runtime_irq_safe(cinfo->dev); |
Peter Ujfalusi | 9ac33b0 | 2014-05-07 13:20:47 +0300 | [diff] [blame] | 229 | |
| 230 | pm_runtime_get_sync(cinfo->dev); |
| 231 | atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); |
| 232 | |
| 233 | for (i = 0; i < DRA7_ATL_INSTANCES; i++) { |
| 234 | struct device_node *cfg_node; |
| 235 | char prop[5]; |
| 236 | struct dra7_atl_desc *cdesc; |
| 237 | struct of_phandle_args clkspec; |
| 238 | struct clk *clk; |
| 239 | int rc; |
| 240 | |
| 241 | rc = of_parse_phandle_with_args(node, "ti,provided-clocks", |
| 242 | NULL, i, &clkspec); |
| 243 | |
| 244 | if (rc) { |
| 245 | pr_err("%s: failed to lookup atl clock %d\n", __func__, |
| 246 | i); |
| 247 | return -EINVAL; |
| 248 | } |
| 249 | |
| 250 | clk = of_clk_get_from_provider(&clkspec); |
| 251 | |
| 252 | cdesc = to_atl_desc(__clk_get_hw(clk)); |
| 253 | cdesc->cinfo = cinfo; |
| 254 | cdesc->id = i; |
| 255 | |
| 256 | /* Get configuration for the ATL instances */ |
| 257 | snprintf(prop, sizeof(prop), "atl%u", i); |
| 258 | cfg_node = of_find_node_by_name(node, prop); |
| 259 | if (cfg_node) { |
| 260 | ret = of_property_read_u32(cfg_node, "bws", |
| 261 | &cdesc->bws); |
| 262 | ret |= of_property_read_u32(cfg_node, "aws", |
| 263 | &cdesc->aws); |
| 264 | if (!ret) { |
| 265 | cdesc->valid = true; |
| 266 | atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i), |
| 267 | cdesc->bws); |
| 268 | atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i), |
| 269 | cdesc->aws); |
| 270 | } |
| 271 | } |
| 272 | |
| 273 | cdesc->probed = true; |
| 274 | /* |
| 275 | * Enable the clock if it has been asked prior to loading the |
| 276 | * hw driver |
| 277 | */ |
| 278 | if (cdesc->enabled) |
| 279 | atl_clk_enable(__clk_get_hw(clk)); |
| 280 | } |
| 281 | pm_runtime_put_sync(cinfo->dev); |
| 282 | |
| 283 | return ret; |
| 284 | } |
| 285 | |
| 286 | static int of_dra7_atl_clk_remove(struct platform_device *pdev) |
| 287 | { |
| 288 | pm_runtime_disable(&pdev->dev); |
| 289 | |
| 290 | return 0; |
| 291 | } |
| 292 | |
| 293 | static struct of_device_id of_dra7_atl_clk_match_tbl[] = { |
| 294 | { .compatible = "ti,dra7-atl", }, |
| 295 | {}, |
| 296 | }; |
| 297 | MODULE_DEVICE_TABLE(of, of_dra7_atl_clk_match_tbl); |
| 298 | |
| 299 | static struct platform_driver dra7_atl_clk_driver = { |
| 300 | .driver = { |
| 301 | .name = "dra7-atl", |
| 302 | .owner = THIS_MODULE, |
| 303 | .of_match_table = of_dra7_atl_clk_match_tbl, |
| 304 | }, |
| 305 | .probe = of_dra7_atl_clk_probe, |
| 306 | .remove = of_dra7_atl_clk_remove, |
| 307 | }; |
| 308 | |
| 309 | module_platform_driver(dra7_atl_clk_driver); |
| 310 | |
| 311 | MODULE_DESCRIPTION("Clock driver for DRA7 Audio Tracking Logic"); |
| 312 | MODULE_ALIAS("platform:dra7-atl-clock"); |
| 313 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); |
| 314 | MODULE_LICENSE("GPL v2"); |