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Alan Cox6b406782009-06-24 18:29:44 +01001/*
2 * pata_rdc - Driver for later RDC PATA controllers
3 *
4 * This is actually a driver for hardware meeting
5 * INCITS 370-2004 (1510D): ATA Host Adapter Standards
6 *
7 * Based on ata_piix.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; see the file COPYING. If not, write to
21 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/gfp.h>
Alan Cox6b406782009-06-24 18:29:44 +010032#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/dmi.h>
35
36#define DRV_NAME "pata_rdc"
37#define DRV_VERSION "0.01"
38
39struct rdc_host_priv {
40 u32 saved_iocfg;
41};
42
43/**
44 * rdc_pata_cable_detect - Probe host controller cable detect info
45 * @ap: Port for which cable detect info is desired
46 *
47 * Read 80c cable indicator from ATA PCI device's PCI config
48 * register. This register is normally set by firmware (BIOS).
49 *
50 * LOCKING:
51 * None (inherited from caller).
52 */
53
54static int rdc_pata_cable_detect(struct ata_port *ap)
55{
56 struct rdc_host_priv *hpriv = ap->host->private_data;
57 u8 mask;
58
59 /* check BIOS cable detect results */
60 mask = 0x30 << (2 * ap->port_no);
61 if ((hpriv->saved_iocfg & mask) == 0)
62 return ATA_CBL_PATA40;
63 return ATA_CBL_PATA80;
64}
65
66/**
67 * rdc_pata_prereset - prereset for PATA host controller
68 * @link: Target link
69 * @deadline: deadline jiffies for the operation
70 *
71 * LOCKING:
72 * None (inherited from caller).
73 */
74static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
75{
76 struct ata_port *ap = link->ap;
77 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
78
79 static const struct pci_bits rdc_enable_bits[] = {
80 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
81 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
82 };
83
84 if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no]))
85 return -ENOENT;
86 return ata_sff_prereset(link, deadline);
87}
88
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +020089static DEFINE_SPINLOCK(rdc_lock);
90
Alan Cox6b406782009-06-24 18:29:44 +010091/**
92 * rdc_set_piomode - Initialize host controller PATA PIO timings
93 * @ap: Port whose timings we are configuring
94 * @adev: um
95 *
96 * Set PIO mode for device, in host controller PCI config space.
97 *
98 * LOCKING:
99 * None (inherited from caller).
100 */
101
102static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
103{
104 unsigned int pio = adev->pio_mode - XFER_PIO_0;
105 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +0200106 unsigned long flags;
Alan Cox6b406782009-06-24 18:29:44 +0100107 unsigned int is_slave = (adev->devno != 0);
108 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
109 unsigned int slave_port = 0x44;
110 u16 master_data;
111 u8 slave_data;
112 u8 udma_enable;
113 int control = 0;
114
115 static const /* ISP RTC */
116 u8 timings[][2] = { { 0, 0 },
117 { 0, 0 },
118 { 1, 0 },
119 { 2, 1 },
120 { 2, 3 }, };
121
122 if (pio >= 2)
123 control |= 1; /* TIME1 enable */
124 if (ata_pio_need_iordy(adev))
125 control |= 2; /* IE enable */
126
127 if (adev->class == ATA_DEV_ATA)
128 control |= 4; /* PPE enable */
129
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +0200130 spin_lock_irqsave(&rdc_lock, flags);
131
Alan Cox6b406782009-06-24 18:29:44 +0100132 /* PIO configuration clears DTE unconditionally. It will be
133 * programmed in set_dmamode which is guaranteed to be called
134 * after set_piomode if any DMA mode is available.
135 */
136 pci_read_config_word(dev, master_port, &master_data);
137 if (is_slave) {
138 /* clear TIME1|IE1|PPE1|DTE1 */
139 master_data &= 0xff0f;
140 /* Enable SITRE (separate slave timing register) */
141 master_data |= 0x4000;
142 /* enable PPE1, IE1 and TIME1 as needed */
143 master_data |= (control << 4);
144 pci_read_config_byte(dev, slave_port, &slave_data);
145 slave_data &= (ap->port_no ? 0x0f : 0xf0);
146 /* Load the timing nibble for this slave */
147 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
148 << (ap->port_no ? 4 : 0);
149 } else {
150 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
151 master_data &= 0xccf0;
152 /* Enable PPE, IE and TIME as appropriate */
153 master_data |= control;
154 /* load ISP and RCT */
155 master_data |=
156 (timings[pio][0] << 12) |
157 (timings[pio][1] << 8);
158 }
159 pci_write_config_word(dev, master_port, master_data);
160 if (is_slave)
161 pci_write_config_byte(dev, slave_port, slave_data);
162
163 /* Ensure the UDMA bit is off - it will be turned back on if
164 UDMA is selected */
165
166 pci_read_config_byte(dev, 0x48, &udma_enable);
167 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
168 pci_write_config_byte(dev, 0x48, udma_enable);
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +0200169
170 spin_unlock_irqrestore(&rdc_lock, flags);
Alan Cox6b406782009-06-24 18:29:44 +0100171}
172
173/**
174 * rdc_set_dmamode - Initialize host controller PATA PIO timings
175 * @ap: Port whose timings we are configuring
176 * @adev: Drive in question
177 *
178 * Set UDMA mode for device, in host controller PCI config space.
179 *
180 * LOCKING:
181 * None (inherited from caller).
182 */
183
184static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
185{
186 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +0200187 unsigned long flags;
Alan Cox6b406782009-06-24 18:29:44 +0100188 u8 master_port = ap->port_no ? 0x42 : 0x40;
189 u16 master_data;
190 u8 speed = adev->dma_mode;
191 int devid = adev->devno + 2 * ap->port_no;
192 u8 udma_enable = 0;
193
194 static const /* ISP RTC */
195 u8 timings[][2] = { { 0, 0 },
196 { 0, 0 },
197 { 1, 0 },
198 { 2, 1 },
199 { 2, 3 }, };
200
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +0200201 spin_lock_irqsave(&rdc_lock, flags);
202
Alan Cox6b406782009-06-24 18:29:44 +0100203 pci_read_config_word(dev, master_port, &master_data);
204 pci_read_config_byte(dev, 0x48, &udma_enable);
205
206 if (speed >= XFER_UDMA_0) {
207 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
208 u16 udma_timing;
209 u16 ideconf;
210 int u_clock, u_speed;
211
212 /*
213 * UDMA is handled by a combination of clock switching and
214 * selection of dividers
215 *
216 * Handy rule: Odd modes are UDMATIMx 01, even are 02
217 * except UDMA0 which is 00
218 */
219 u_speed = min(2 - (udma & 1), udma);
220 if (udma == 5)
221 u_clock = 0x1000; /* 100Mhz */
222 else if (udma > 2)
223 u_clock = 1; /* 66Mhz */
224 else
225 u_clock = 0; /* 33Mhz */
226
227 udma_enable |= (1 << devid);
228
229 /* Load the CT/RP selection */
230 pci_read_config_word(dev, 0x4A, &udma_timing);
231 udma_timing &= ~(3 << (4 * devid));
232 udma_timing |= u_speed << (4 * devid);
233 pci_write_config_word(dev, 0x4A, udma_timing);
234
235 /* Select a 33/66/100Mhz clock */
236 pci_read_config_word(dev, 0x54, &ideconf);
237 ideconf &= ~(0x1001 << devid);
238 ideconf |= u_clock << devid;
239 pci_write_config_word(dev, 0x54, ideconf);
240 } else {
241 /*
242 * MWDMA is driven by the PIO timings. We must also enable
243 * IORDY unconditionally along with TIME1. PPE has already
244 * been set when the PIO timing was set.
245 */
246 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
247 unsigned int control;
248 u8 slave_data;
249 const unsigned int needed_pio[3] = {
250 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
251 };
252 int pio = needed_pio[mwdma] - XFER_PIO_0;
253
254 control = 3; /* IORDY|TIME1 */
255
256 /* If the drive MWDMA is faster than it can do PIO then
257 we must force PIO into PIO0 */
258
259 if (adev->pio_mode < needed_pio[mwdma])
260 /* Enable DMA timing only */
261 control |= 8; /* PIO cycles in PIO0 */
262
263 if (adev->devno) { /* Slave */
264 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
265 master_data |= control << 4;
266 pci_read_config_byte(dev, 0x44, &slave_data);
267 slave_data &= (ap->port_no ? 0x0f : 0xf0);
268 /* Load the matching timing */
269 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
270 pci_write_config_byte(dev, 0x44, slave_data);
271 } else { /* Master */
272 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
273 and master timing bits */
274 master_data |= control;
275 master_data |=
276 (timings[pio][0] << 12) |
277 (timings[pio][1] << 8);
278 }
279
280 udma_enable &= ~(1 << devid);
281 pci_write_config_word(dev, master_port, master_data);
282 }
283 pci_write_config_byte(dev, 0x48, udma_enable);
Bartlomiej Zolnierkiewiczbb612cb2011-10-13 16:06:04 +0200284
285 spin_unlock_irqrestore(&rdc_lock, flags);
Alan Cox6b406782009-06-24 18:29:44 +0100286}
287
288static struct ata_port_operations rdc_pata_ops = {
289 .inherits = &ata_bmdma32_port_ops,
290 .cable_detect = rdc_pata_cable_detect,
291 .set_piomode = rdc_set_piomode,
292 .set_dmamode = rdc_set_dmamode,
293 .prereset = rdc_pata_prereset,
294};
295
296static struct ata_port_info rdc_port_info = {
297
298 .flags = ATA_FLAG_SLAVE_POSS,
299 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz82563232009-12-03 17:52:16 -0500300 .mwdma_mask = ATA_MWDMA12_ONLY,
Alan Cox6b406782009-06-24 18:29:44 +0100301 .udma_mask = ATA_UDMA5,
302 .port_ops = &rdc_pata_ops,
303};
304
305static struct scsi_host_template rdc_sht = {
306 ATA_BMDMA_SHT(DRV_NAME),
307};
308
309/**
310 * rdc_init_one - Register PIIX ATA PCI device with kernel services
311 * @pdev: PCI device to register
312 * @ent: Entry in rdc_pci_tbl matching with @pdev
313 *
314 * Called from kernel PCI layer. We probe for combined mode (sigh),
315 * and then hand over control to libata, for it to do the rest.
316 *
317 * LOCKING:
318 * Inherited from PCI layer (may sleep).
319 *
320 * RETURNS:
321 * Zero on success, or -ERRNO value.
322 */
323
324static int __devinit rdc_init_one(struct pci_dev *pdev,
325 const struct pci_device_id *ent)
326{
Alan Cox6b406782009-06-24 18:29:44 +0100327 struct device *dev = &pdev->dev;
328 struct ata_port_info port_info[2];
329 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
330 unsigned long port_flags;
331 struct ata_host *host;
332 struct rdc_host_priv *hpriv;
333 int rc;
334
Joe Perches06296a12011-04-15 15:52:00 -0700335 ata_print_version_once(&pdev->dev, DRV_VERSION);
Alan Cox6b406782009-06-24 18:29:44 +0100336
337 port_info[0] = rdc_port_info;
338 port_info[1] = rdc_port_info;
339
340 port_flags = port_info[0].flags;
341
342 /* enable device and prepare host */
343 rc = pcim_enable_device(pdev);
344 if (rc)
345 return rc;
346
347 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
348 if (!hpriv)
349 return -ENOMEM;
350
351 /* Save IOCFG, this will be used for cable detection, quirk
352 * detection and restoration on detach.
353 */
354 pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
355
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200356 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Alan Cox6b406782009-06-24 18:29:44 +0100357 if (rc)
358 return rc;
359 host->private_data = hpriv;
360
361 pci_intx(pdev, 1);
362
363 host->flags |= ATA_HOST_PARALLEL_SCAN;
364
365 pci_set_master(pdev);
Tejun Heoc3b28892010-05-19 22:10:21 +0200366 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
Alan Cox6b406782009-06-24 18:29:44 +0100367}
368
369static void rdc_remove_one(struct pci_dev *pdev)
370{
371 struct ata_host *host = dev_get_drvdata(&pdev->dev);
372 struct rdc_host_priv *hpriv = host->private_data;
373
374 pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg);
375
376 ata_pci_remove_one(pdev);
377}
378
379static const struct pci_device_id rdc_pci_tbl[] = {
380 { PCI_DEVICE(0x17F3, 0x1011), },
381 { PCI_DEVICE(0x17F3, 0x1012), },
382 { } /* terminate list */
383};
384
385static struct pci_driver rdc_pci_driver = {
386 .name = DRV_NAME,
387 .id_table = rdc_pci_tbl,
388 .probe = rdc_init_one,
389 .remove = rdc_remove_one,
Bartlomiej Zolnierkiewicz5a298542011-10-13 16:06:31 +0200390#ifdef CONFIG_PM
391 .suspend = ata_pci_device_suspend,
392 .resume = ata_pci_device_resume,
393#endif
Alan Cox6b406782009-06-24 18:29:44 +0100394};
395
396
397static int __init rdc_init(void)
398{
399 return pci_register_driver(&rdc_pci_driver);
400}
401
402static void __exit rdc_exit(void)
403{
404 pci_unregister_driver(&rdc_pci_driver);
405}
406
407module_init(rdc_init);
408module_exit(rdc_exit);
409
410MODULE_AUTHOR("Alan Cox (based on ata_piix)");
411MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers");
412MODULE_LICENSE("GPL");
413MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
414MODULE_VERSION(DRV_VERSION);