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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
David Milburn87943ac2008-10-13 14:38:36 -050052/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
Tejun Heoa22e6442008-03-10 10:25:25 +090063static int ahci_skip_host_reset;
Arjan van de Venf3d7f232009-01-26 02:05:44 -080064static int ahci_ignore_sss;
65
Tejun Heoa22e6442008-03-10 10:25:25 +090066module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
Arjan van de Venf3d7f232009-01-26 02:05:44 -080069module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040072static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -070075static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81enum {
82 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090083 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
Tejun Heo12fad3f2006-05-15 21:03:55 +090086 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090087 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090088 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040090 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090091 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090099 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +0900100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +0900104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +0900105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106
107 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +0900108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4,
Shane Huange427fe02008-12-30 10:53:41 +0800112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
Tejun Heoe297d992008-06-10 00:13:04 +0900113 board_ahci_mcp65 = 6,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400114 board_ahci_nopmp = 7,
Tejun Heoaa431dd2009-04-08 14:25:31 -0700115 board_ahci_yesncq = 8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
Robert Hancock4c521c82009-09-20 17:02:31 -0600125 HOST_CAP2 = 0x24, /* host capabilities, extended */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
127 /* HOST_CTL bits */
128 HOST_RESET = (1 << 0), /* reset controller; self-clear */
129 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
130 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
131
132 /* HOST_CAP bits */
Robert Hancock4c521c82009-09-20 17:02:31 -0600133 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700134 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
Robert Hancock4c521c82009-09-20 17:02:31 -0600135 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
136 HOST_CAP_PART = (1 << 13), /* Partial state capable */
137 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
138 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
139 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
Tejun Heo7d50b602007-09-23 13:19:54 +0900140 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Robert Hancock4c521c82009-09-20 17:02:31 -0600141 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
Tejun Heo22b49982006-01-23 21:38:44 +0900142 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Robert Hancock4c521c82009-09-20 17:02:31 -0600143 HOST_CAP_LED = (1 << 25), /* Supports activity LED */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400144 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900145 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Robert Hancock4c521c82009-09-20 17:02:31 -0600146 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900147 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900148 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900149 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150
Robert Hancock4c521c82009-09-20 17:02:31 -0600151 /* HOST_CAP2 bits */
152 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
153 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
154 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
155
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 /* registers for each SATA port */
157 PORT_LST_ADDR = 0x00, /* command list DMA addr */
158 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
159 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
160 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
161 PORT_IRQ_STAT = 0x10, /* interrupt status */
162 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
163 PORT_CMD = 0x18, /* port command */
164 PORT_TFDATA = 0x20, /* taskfile data */
165 PORT_SIG = 0x24, /* device TF signature */
166 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
168 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
169 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
170 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900171 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173 /* PORT_IRQ_{STAT,MASK} bits */
174 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
175 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
176 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
177 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
178 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
179 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
180 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
181 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
182
183 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
184 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
185 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
186 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
187 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
188 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
189 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
190 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
191 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
192
Tejun Heo78cd52d2006-05-15 20:58:29 +0900193 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
194 PORT_IRQ_IF_ERR |
195 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900196 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900197 PORT_IRQ_UNK_FIS |
198 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900199 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
200 PORT_IRQ_TF_ERR |
201 PORT_IRQ_HBUS_DATA_ERR,
202 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
203 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
204 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205
206 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400207 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
208 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500209 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900210 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
212 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
213 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900214 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
216 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
217 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
218
Tejun Heo0be0aa92006-07-26 15:59:26 +0900219 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
221 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
222 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400223
Tejun Heo417a1a62007-09-23 13:19:55 +0900224 /* hpriv->flags bits */
225 AHCI_HFLAG_NO_NCQ = (1 << 0),
226 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
227 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
228 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
229 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
230 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900231 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400232 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500233 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heoe297d992008-06-10 00:13:04 +0900234 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900235 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
Tejun Heo55946392009-08-04 14:30:08 +0900236 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
237 link offline */
Tejun Heo417a1a62007-09-23 13:19:55 +0900238
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200239 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900240
241 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
242 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400243 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
244 ATA_FLAG_IPM,
Tejun Heoc4f77922007-12-06 15:09:43 +0900245
246 ICH_MAP = 0x90, /* ICH MAP register */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700247
Tejun Heod50ce072009-05-12 10:57:41 +0900248 /* em constants */
249 EM_MAX_SLOTS = 8,
250 EM_MAX_RETRY = 5,
251
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700252 /* em_ctl bits */
253 EM_CTL_RST = (1 << 9), /* Reset */
254 EM_CTL_TM = (1 << 8), /* Transmit Message */
255 EM_CTL_ALHD = (1 << 26), /* Activity LED */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256};
257
258struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000259 __le32 opts;
260 __le32 status;
261 __le32 tbl_addr;
262 __le32 tbl_addr_hi;
263 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264};
265
266struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000267 __le32 addr;
268 __le32 addr_hi;
269 __le32 reserved;
270 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271};
272
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700273struct ahci_em_priv {
274 enum sw_activity blink_policy;
275 struct timer_list timer;
276 unsigned long saved_activity;
277 unsigned long activity;
278 unsigned long led_state;
279};
280
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900282 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900283 u32 cap; /* cap to use */
Robert Hancock4c521c82009-09-20 17:02:31 -0600284 u32 cap2; /* cap2 to use */
Tejun Heod447df12007-03-18 22:15:33 +0900285 u32 port_map; /* port map to use */
286 u32 saved_cap; /* saved initial cap */
Robert Hancock4c521c82009-09-20 17:02:31 -0600287 u32 saved_cap2; /* saved initial cap2 */
Tejun Heod447df12007-03-18 22:15:33 +0900288 u32 saved_port_map; /* saved initial port_map */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700289 u32 em_loc; /* enclosure management location */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290};
291
292struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900293 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 struct ahci_cmd_hdr *cmd_slot;
295 dma_addr_t cmd_slot_dma;
296 void *cmd_tbl;
297 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 void *rx_fis;
299 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900300 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900301 unsigned int ncq_saw_d2h:1;
302 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900303 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700304 u32 intr_mask; /* interrupts to enable */
Tejun Heod50ce072009-05-12 10:57:41 +0900305 /* enclosure management info per PM slot */
306 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307};
308
Tejun Heo82ef04f2008-07-31 17:02:40 +0900309static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
310static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400311static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900312static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900313static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314static int ahci_port_start(struct ata_port *ap);
315static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316static void ahci_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900317static void ahci_freeze(struct ata_port *ap);
318static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900319static void ahci_pmp_attach(struct ata_port *ap);
320static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900321static int ahci_softreset(struct ata_link *link, unsigned int *class,
322 unsigned long deadline);
Shane Huangbd172432008-06-10 15:52:04 +0800323static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
324 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900325static int ahci_hardreset(struct ata_link *link, unsigned int *class,
326 unsigned long deadline);
327static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
328 unsigned long deadline);
329static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
330 unsigned long deadline);
331static void ahci_postreset(struct ata_link *link, unsigned int *class);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900332static void ahci_error_handler(struct ata_port *ap);
333static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400334static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500335static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400336static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
337 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900338#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900339static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900340static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
341static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900342#endif
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700343static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
344static ssize_t ahci_activity_store(struct ata_device *dev,
345 enum sw_activity val);
346static void ahci_init_sw_activity(struct ata_link *link);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
Matthew Garrett77cdec12009-07-17 19:13:47 +0100348static ssize_t ahci_show_host_caps(struct device *dev,
349 struct device_attribute *attr, char *buf);
Robert Hancock4c521c82009-09-20 17:02:31 -0600350static ssize_t ahci_show_host_cap2(struct device *dev,
351 struct device_attribute *attr, char *buf);
Matthew Garrett77cdec12009-07-17 19:13:47 +0100352static ssize_t ahci_show_host_version(struct device *dev,
353 struct device_attribute *attr, char *buf);
354static ssize_t ahci_show_port_cmd(struct device *dev,
355 struct device_attribute *attr, char *buf);
356
357DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
Robert Hancock4c521c82009-09-20 17:02:31 -0600358DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
Matthew Garrett77cdec12009-07-17 19:13:47 +0100359DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
360DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
361
Tony Jonesee959b02008-02-22 00:13:36 +0100362static struct device_attribute *ahci_shost_attrs[] = {
363 &dev_attr_link_power_management_policy,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700364 &dev_attr_em_message_type,
365 &dev_attr_em_message,
Matthew Garrett77cdec12009-07-17 19:13:47 +0100366 &dev_attr_ahci_host_caps,
Robert Hancock4c521c82009-09-20 17:02:31 -0600367 &dev_attr_ahci_host_cap2,
Matthew Garrett77cdec12009-07-17 19:13:47 +0100368 &dev_attr_ahci_host_version,
369 &dev_attr_ahci_port_cmd,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700370 NULL
371};
372
373static struct device_attribute *ahci_sdev_attrs[] = {
374 &dev_attr_sw_activity,
Elias Oltmanns45fabbb2008-09-21 11:54:08 +0200375 &dev_attr_unload_heads,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400376 NULL
377};
378
Jeff Garzik193515d2005-11-07 00:59:37 -0500379static struct scsi_host_template ahci_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900380 ATA_NCQ_SHT(DRV_NAME),
Tejun Heo12fad3f2006-05-15 21:03:55 +0900381 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383 .dma_boundary = AHCI_DMA_BOUNDARY,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400384 .shost_attrs = ahci_shost_attrs,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700385 .sdev_attrs = ahci_sdev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386};
387
Tejun Heo029cfd62008-03-25 12:22:49 +0900388static struct ata_port_operations ahci_ops = {
389 .inherits = &sata_pmp_port_ops,
390
Tejun Heo7d50b602007-09-23 13:19:54 +0900391 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 .qc_prep = ahci_qc_prep,
393 .qc_issue = ahci_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900394 .qc_fill_rtf = ahci_qc_fill_rtf,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395
Tejun Heo78cd52d2006-05-15 20:58:29 +0900396 .freeze = ahci_freeze,
397 .thaw = ahci_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900398 .softreset = ahci_softreset,
399 .hardreset = ahci_hardreset,
400 .postreset = ahci_postreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900401 .pmp_softreset = ahci_softreset,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900402 .error_handler = ahci_error_handler,
403 .post_internal_cmd = ahci_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900404 .dev_config = ahci_dev_config,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900405
Tejun Heo029cfd62008-03-25 12:22:49 +0900406 .scr_read = ahci_scr_read,
407 .scr_write = ahci_scr_write,
Tejun Heo7d50b602007-09-23 13:19:54 +0900408 .pmp_attach = ahci_pmp_attach,
409 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900410
Tejun Heo029cfd62008-03-25 12:22:49 +0900411 .enable_pm = ahci_enable_alpm,
412 .disable_pm = ahci_disable_alpm,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700413 .em_show = ahci_led_show,
414 .em_store = ahci_led_store,
415 .sw_activity_show = ahci_activity_show,
416 .sw_activity_store = ahci_activity_store,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900417#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900418 .port_suspend = ahci_port_suspend,
419 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900420#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 .port_start = ahci_port_start,
422 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423};
424
Tejun Heo029cfd62008-03-25 12:22:49 +0900425static struct ata_port_operations ahci_vt8251_ops = {
426 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900427 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900428};
429
Tejun Heo029cfd62008-03-25 12:22:49 +0900430static struct ata_port_operations ahci_p5wdh_ops = {
431 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900432 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900433};
434
Shane Huangbd172432008-06-10 15:52:04 +0800435static struct ata_port_operations ahci_sb600_ops = {
436 .inherits = &ahci_ops,
437 .softreset = ahci_sb600_softreset,
438 .pmp_softreset = ahci_sb600_softreset,
439};
440
Tejun Heo417a1a62007-09-23 13:19:55 +0900441#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
442
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100443static const struct ata_port_info ahci_port_info[] = {
Jeff Garzik4da646b2009-04-08 02:00:13 -0400444 [board_ahci] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900446 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100447 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400448 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 .port_ops = &ahci_ops,
450 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400451 [board_ahci_vt8251] =
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200452 {
Tejun Heo6949b912007-09-23 13:19:55 +0900453 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900454 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100455 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400456 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900457 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200458 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400459 [board_ahci_ign_iferr] =
Tejun Heo41669552006-11-29 11:33:14 +0900460 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900461 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
462 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100463 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400464 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900465 .port_ops = &ahci_ops,
466 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400467 [board_ahci_sb600] =
Conke Hu55a61602007-03-27 18:33:05 +0800468 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900469 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900470 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
471 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900472 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100473 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400474 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800475 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800476 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400477 [board_ahci_mv] =
Jeff Garzikcd70c262007-07-08 02:29:42 -0400478 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900479 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
Tejun Heo17248462008-08-29 16:03:59 +0200480 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400481 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900482 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100483 .pio_mask = ATA_PIO4,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400484 .udma_mask = ATA_UDMA6,
485 .port_ops = &ahci_ops,
486 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400487 [board_ahci_sb700] = /* for SB700 and SB800 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800488 {
Shane Huangbd172432008-06-10 15:52:04 +0800489 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800490 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100491 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800492 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800493 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800494 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400495 [board_ahci_mcp65] =
Tejun Heoe297d992008-06-10 00:13:04 +0900496 {
497 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
498 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100499 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900500 .udma_mask = ATA_UDMA6,
501 .port_ops = &ahci_ops,
502 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400503 [board_ahci_nopmp] =
Tejun Heo9a3b1032008-06-18 20:56:58 -0400504 {
505 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
506 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100507 .pio_mask = ATA_PIO4,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400508 .udma_mask = ATA_UDMA6,
509 .port_ops = &ahci_ops,
510 },
Tejun Heoaa431dd2009-04-08 14:25:31 -0700511 /* board_ahci_yesncq */
512 {
513 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
514 .flags = AHCI_FLAG_COMMON,
515 .pio_mask = ATA_PIO4,
516 .udma_mask = ATA_UDMA6,
517 .port_ops = &ahci_ops,
518 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519};
520
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500521static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400522 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400523 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
524 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
525 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
526 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
527 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900528 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400529 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
530 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
531 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
532 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900533 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
534 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
535 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
536 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
537 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
538 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
539 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
540 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
541 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
542 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
543 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
544 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
545 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
546 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
547 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
548 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
549 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400550 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
551 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800552 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500553 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800554 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500555 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
556 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700557 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700558 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500559 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700560 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700561 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500562 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400563
Tejun Heoe34bb372007-02-26 20:24:03 +0900564 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
565 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400567
568 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800569 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800570 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
571 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
572 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
573 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
574 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
575 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400576
Shane Huange2dd90b2009-07-29 11:34:49 +0800577 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800578 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huange2dd90b2009-07-29 11:34:49 +0800579 /* AMD is using RAID class only for ahci controllers */
580 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
581 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
582
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400583 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400584 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900585 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400586
587 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900588 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
589 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
590 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
591 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
592 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
593 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
594 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
595 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heoaa431dd2009-04-08 14:25:31 -0700596 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
597 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
598 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
599 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
600 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
601 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
602 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
603 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
604 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
605 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
606 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
607 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
peer chen726206f2009-10-15 16:34:56 +0800608 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */
Tejun Heoaa431dd2009-04-08 14:25:31 -0700609 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
610 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
611 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
612 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
613 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
614 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
615 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
616 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
617 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
618 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
619 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
620 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
Peer Chen0522b282007-06-07 18:05:12 +0800621 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
622 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
623 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
624 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
625 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
626 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
627 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
628 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
629 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
630 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
631 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
632 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800633 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
634 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
635 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
636 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800637 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
638 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
639 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
640 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
641 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
642 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
643 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
644 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen7adbe462009-02-27 16:58:41 +0800645 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
646 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
647 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
648 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
649 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
650 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
651 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
652 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
653 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
654 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
655 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
656 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400657
Jeff Garzik95916ed2006-07-29 04:10:14 -0400658 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900659 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
660 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
661 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400662
Jeff Garzikcd70c262007-07-08 02:29:42 -0400663 /* Marvell */
664 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100665 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400666
Mark Nelsonc77a0362008-10-23 14:08:16 +1100667 /* Promise */
668 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
669
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500670 /* Generic, PCI class code for AHCI */
671 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500672 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500673
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 { } /* terminate list */
675};
676
677
678static struct pci_driver ahci_pci_driver = {
679 .name = DRV_NAME,
680 .id_table = ahci_pci_tbl,
681 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900682 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900683#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900684 .suspend = ahci_pci_device_suspend,
685 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900686#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687};
688
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700689static int ahci_em_messages = 1;
690module_param(ahci_em_messages, int, 0444);
691/* add other LED protocol types when they become supported */
692MODULE_PARM_DESC(ahci_em_messages,
693 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694
Alan Cox5b66c822008-09-03 14:48:34 +0100695#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
696static int marvell_enable;
697#else
698static int marvell_enable = 1;
699#endif
700module_param(marvell_enable, int, 0644);
701MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
702
703
Tejun Heo98fa4b62006-11-02 12:17:23 +0900704static inline int ahci_nr_ports(u32 cap)
705{
706 return (cap & 0x1f) + 1;
707}
708
Jeff Garzikdab632e2007-05-28 08:33:01 -0400709static inline void __iomem *__ahci_port_base(struct ata_host *host,
710 unsigned int port_no)
711{
712 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
713
714 return mmio + 0x100 + (port_no * 0x80);
715}
716
Tejun Heo4447d352007-04-17 23:44:08 +0900717static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400719 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720}
721
Tejun Heob710a1f2008-01-05 23:11:57 +0900722static void ahci_enable_ahci(void __iomem *mmio)
723{
Tejun Heo15fe9822008-04-23 20:52:58 +0900724 int i;
Tejun Heob710a1f2008-01-05 23:11:57 +0900725 u32 tmp;
726
727 /* turn on AHCI_EN */
728 tmp = readl(mmio + HOST_CTL);
Tejun Heo15fe9822008-04-23 20:52:58 +0900729 if (tmp & HOST_AHCI_EN)
730 return;
731
732 /* Some controllers need AHCI_EN to be written multiple times.
733 * Try a few times before giving up.
734 */
735 for (i = 0; i < 5; i++) {
Tejun Heob710a1f2008-01-05 23:11:57 +0900736 tmp |= HOST_AHCI_EN;
737 writel(tmp, mmio + HOST_CTL);
738 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
Tejun Heo15fe9822008-04-23 20:52:58 +0900739 if (tmp & HOST_AHCI_EN)
740 return;
741 msleep(10);
Tejun Heob710a1f2008-01-05 23:11:57 +0900742 }
Tejun Heo15fe9822008-04-23 20:52:58 +0900743
744 WARN_ON(1);
Tejun Heob710a1f2008-01-05 23:11:57 +0900745}
746
Matthew Garrett77cdec12009-07-17 19:13:47 +0100747static ssize_t ahci_show_host_caps(struct device *dev,
748 struct device_attribute *attr, char *buf)
749{
750 struct Scsi_Host *shost = class_to_shost(dev);
751 struct ata_port *ap = ata_shost_to_port(shost);
752 struct ahci_host_priv *hpriv = ap->host->private_data;
753
754 return sprintf(buf, "%x\n", hpriv->cap);
755}
756
Robert Hancock4c521c82009-09-20 17:02:31 -0600757static ssize_t ahci_show_host_cap2(struct device *dev,
758 struct device_attribute *attr, char *buf)
759{
760 struct Scsi_Host *shost = class_to_shost(dev);
761 struct ata_port *ap = ata_shost_to_port(shost);
762 struct ahci_host_priv *hpriv = ap->host->private_data;
763
764 return sprintf(buf, "%x\n", hpriv->cap2);
765}
766
Matthew Garrett77cdec12009-07-17 19:13:47 +0100767static ssize_t ahci_show_host_version(struct device *dev,
768 struct device_attribute *attr, char *buf)
769{
770 struct Scsi_Host *shost = class_to_shost(dev);
771 struct ata_port *ap = ata_shost_to_port(shost);
772 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
773
774 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
775}
776
777static ssize_t ahci_show_port_cmd(struct device *dev,
778 struct device_attribute *attr, char *buf)
779{
780 struct Scsi_Host *shost = class_to_shost(dev);
781 struct ata_port *ap = ata_shost_to_port(shost);
782 void __iomem *port_mmio = ahci_port_base(ap);
783
784 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
785}
786
Tejun Heod447df12007-03-18 22:15:33 +0900787/**
788 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900789 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900790 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900791 *
792 * Some registers containing configuration info might be setup by
793 * BIOS and might be cleared on reset. This function saves the
794 * initial values of those registers into @hpriv such that they
795 * can be restored after controller reset.
796 *
797 * If inconsistent, config values are fixed up by this function.
798 *
799 * LOCKING:
800 * None.
801 */
Tejun Heo4447d352007-04-17 23:44:08 +0900802static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900803 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900804{
Tejun Heo4447d352007-04-17 23:44:08 +0900805 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Robert Hancock4c521c82009-09-20 17:02:31 -0600806 u32 cap, cap2, vers, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900807 int i;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100808 int mv;
Tejun Heod447df12007-03-18 22:15:33 +0900809
Tejun Heob710a1f2008-01-05 23:11:57 +0900810 /* make sure AHCI mode is enabled before accessing CAP */
811 ahci_enable_ahci(mmio);
812
Tejun Heod447df12007-03-18 22:15:33 +0900813 /* Values prefixed with saved_ are written back to host after
814 * reset. Values without are used for driver operation.
815 */
816 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
817 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
818
Robert Hancock4c521c82009-09-20 17:02:31 -0600819 /* CAP2 register is only defined for AHCI 1.2 and later */
820 vers = readl(mmio + HOST_VERSION);
821 if ((vers >> 16) > 1 ||
822 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
823 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
824 else
825 hpriv->saved_cap2 = cap2 = 0;
826
Tejun Heo274c1fd2007-07-16 14:29:40 +0900827 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900828 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200829 dev_printk(KERN_INFO, &pdev->dev,
830 "controller can't do 64bit DMA, forcing 32bit\n");
831 cap &= ~HOST_CAP_64;
832 }
833
Tejun Heo417a1a62007-09-23 13:19:55 +0900834 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900835 dev_printk(KERN_INFO, &pdev->dev,
836 "controller can't do NCQ, turning off CAP_NCQ\n");
837 cap &= ~HOST_CAP_NCQ;
838 }
839
Tejun Heoe297d992008-06-10 00:13:04 +0900840 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
841 dev_printk(KERN_INFO, &pdev->dev,
842 "controller can do NCQ, turning on CAP_NCQ\n");
843 cap |= HOST_CAP_NCQ;
844 }
845
Roel Kluin258cd842008-03-09 21:42:40 +0100846 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900847 dev_printk(KERN_INFO, &pdev->dev,
848 "controller can't do PMP, turning off CAP_PMP\n");
849 cap &= ~HOST_CAP_PMP;
850 }
851
Tejun Heod799e082008-06-17 12:46:30 +0900852 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
853 port_map != 1) {
854 dev_printk(KERN_INFO, &pdev->dev,
855 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
856 port_map, 1);
857 port_map = 1;
858 }
859
Jeff Garzikcd70c262007-07-08 02:29:42 -0400860 /*
861 * Temporary Marvell 6145 hack: PATA port presence
862 * is asserted through the standard AHCI port
863 * presence register, as bit 4 (counting from 0)
864 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900865 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100866 if (pdev->device == 0x6121)
867 mv = 0x3;
868 else
869 mv = 0xf;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400870 dev_printk(KERN_ERR, &pdev->dev,
871 "MV_AHCI HACK: port_map %x -> %x\n",
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100872 port_map,
873 port_map & mv);
Alan Cox5b66c822008-09-03 14:48:34 +0100874 dev_printk(KERN_ERR, &pdev->dev,
875 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
Jeff Garzikcd70c262007-07-08 02:29:42 -0400876
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100877 port_map &= mv;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400878 }
879
Tejun Heo17199b12007-03-18 22:26:53 +0900880 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900881 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900882 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900883
Tejun Heo837f5f82008-02-06 15:13:51 +0900884 for (i = 0; i < AHCI_MAX_PORTS; i++)
885 if (port_map & (1 << i))
886 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900887
Tejun Heo837f5f82008-02-06 15:13:51 +0900888 /* If PI has more ports than n_ports, whine, clear
889 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900890 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900891 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900892 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900893 "implemented port map (0x%x) contains more "
894 "ports than nr_ports (%u), using nr_ports\n",
895 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900896 port_map = 0;
897 }
898 }
899
900 /* fabricate port_map from cap.nr_ports */
901 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900902 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900903 dev_printk(KERN_WARNING, &pdev->dev,
904 "forcing PORTS_IMPL to 0x%x\n", port_map);
905
906 /* write the fixed up value to the PI register */
907 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900908 }
909
Tejun Heod447df12007-03-18 22:15:33 +0900910 /* record values to use during operation */
911 hpriv->cap = cap;
Robert Hancock4c521c82009-09-20 17:02:31 -0600912 hpriv->cap2 = cap2;
Tejun Heod447df12007-03-18 22:15:33 +0900913 hpriv->port_map = port_map;
914}
915
916/**
917 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900918 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900919 *
920 * Restore initial config stored by ahci_save_initial_config().
921 *
922 * LOCKING:
923 * None.
924 */
Tejun Heo4447d352007-04-17 23:44:08 +0900925static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900926{
Tejun Heo4447d352007-04-17 23:44:08 +0900927 struct ahci_host_priv *hpriv = host->private_data;
928 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
929
Tejun Heod447df12007-03-18 22:15:33 +0900930 writel(hpriv->saved_cap, mmio + HOST_CAP);
Robert Hancock4c521c82009-09-20 17:02:31 -0600931 if (hpriv->saved_cap2)
932 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
Tejun Heod447df12007-03-18 22:15:33 +0900933 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
934 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
935}
936
Tejun Heo203ef6c2007-07-16 14:29:40 +0900937static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900939 static const int offset[] = {
940 [SCR_STATUS] = PORT_SCR_STAT,
941 [SCR_CONTROL] = PORT_SCR_CTL,
942 [SCR_ERROR] = PORT_SCR_ERR,
943 [SCR_ACTIVE] = PORT_SCR_ACT,
944 [SCR_NOTIFICATION] = PORT_SCR_NTF,
945 };
946 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947
Tejun Heo203ef6c2007-07-16 14:29:40 +0900948 if (sc_reg < ARRAY_SIZE(offset) &&
949 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
950 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900951 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952}
953
Tejun Heo82ef04f2008-07-31 17:02:40 +0900954static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900956 void __iomem *port_mmio = ahci_port_base(link->ap);
957 int offset = ahci_scr_offset(link->ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958
Tejun Heo203ef6c2007-07-16 14:29:40 +0900959 if (offset) {
960 *val = readl(port_mmio + offset);
961 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900963 return -EINVAL;
964}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965
Tejun Heo82ef04f2008-07-31 17:02:40 +0900966static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Tejun Heo203ef6c2007-07-16 14:29:40 +0900967{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900968 void __iomem *port_mmio = ahci_port_base(link->ap);
969 int offset = ahci_scr_offset(link->ap, sc_reg);
Tejun Heo203ef6c2007-07-16 14:29:40 +0900970
971 if (offset) {
972 writel(val, port_mmio + offset);
973 return 0;
974 }
975 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976}
977
Tejun Heo4447d352007-04-17 23:44:08 +0900978static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900979{
Tejun Heo4447d352007-04-17 23:44:08 +0900980 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900981 u32 tmp;
982
Tejun Heod8fcd112006-07-26 15:59:25 +0900983 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900984 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900985 tmp |= PORT_CMD_START;
986 writel(tmp, port_mmio + PORT_CMD);
987 readl(port_mmio + PORT_CMD); /* flush */
988}
989
Tejun Heo4447d352007-04-17 23:44:08 +0900990static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900991{
Tejun Heo4447d352007-04-17 23:44:08 +0900992 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900993 u32 tmp;
994
995 tmp = readl(port_mmio + PORT_CMD);
996
Tejun Heod8fcd112006-07-26 15:59:25 +0900997 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900998 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
999 return 0;
1000
Tejun Heod8fcd112006-07-26 15:59:25 +09001001 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +09001002 tmp &= ~PORT_CMD_START;
1003 writel(tmp, port_mmio + PORT_CMD);
1004
Tejun Heod8fcd112006-07-26 15:59:25 +09001005 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +09001006 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001007 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +09001008 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +09001009 return -EIO;
1010
1011 return 0;
1012}
1013
Tejun Heo4447d352007-04-17 23:44:08 +09001014static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001015{
Tejun Heo4447d352007-04-17 23:44:08 +09001016 void __iomem *port_mmio = ahci_port_base(ap);
1017 struct ahci_host_priv *hpriv = ap->host->private_data;
1018 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +09001019 u32 tmp;
1020
1021 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +09001022 if (hpriv->cap & HOST_CAP_64)
1023 writel((pp->cmd_slot_dma >> 16) >> 16,
1024 port_mmio + PORT_LST_ADDR_HI);
1025 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001026
Tejun Heo4447d352007-04-17 23:44:08 +09001027 if (hpriv->cap & HOST_CAP_64)
1028 writel((pp->rx_fis_dma >> 16) >> 16,
1029 port_mmio + PORT_FIS_ADDR_HI);
1030 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001031
1032 /* enable FIS reception */
1033 tmp = readl(port_mmio + PORT_CMD);
1034 tmp |= PORT_CMD_FIS_RX;
1035 writel(tmp, port_mmio + PORT_CMD);
1036
1037 /* flush */
1038 readl(port_mmio + PORT_CMD);
1039}
1040
Tejun Heo4447d352007-04-17 23:44:08 +09001041static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001042{
Tejun Heo4447d352007-04-17 23:44:08 +09001043 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001044 u32 tmp;
1045
1046 /* disable FIS reception */
1047 tmp = readl(port_mmio + PORT_CMD);
1048 tmp &= ~PORT_CMD_FIS_RX;
1049 writel(tmp, port_mmio + PORT_CMD);
1050
1051 /* wait for completion, spec says 500ms, give it 1000 */
1052 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1053 PORT_CMD_FIS_ON, 10, 1000);
1054 if (tmp & PORT_CMD_FIS_ON)
1055 return -EBUSY;
1056
1057 return 0;
1058}
1059
Tejun Heo4447d352007-04-17 23:44:08 +09001060static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001061{
Tejun Heo4447d352007-04-17 23:44:08 +09001062 struct ahci_host_priv *hpriv = ap->host->private_data;
1063 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001064 u32 cmd;
1065
1066 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1067
1068 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +09001069 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +09001070 cmd |= PORT_CMD_SPIN_UP;
1071 writel(cmd, port_mmio + PORT_CMD);
1072 }
1073
1074 /* wake up link */
1075 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1076}
1077
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001078static void ahci_disable_alpm(struct ata_port *ap)
1079{
1080 struct ahci_host_priv *hpriv = ap->host->private_data;
1081 void __iomem *port_mmio = ahci_port_base(ap);
1082 u32 cmd;
1083 struct ahci_port_priv *pp = ap->private_data;
1084
1085 /* IPM bits should be disabled by libata-core */
1086 /* get the existing command bits */
1087 cmd = readl(port_mmio + PORT_CMD);
1088
1089 /* disable ALPM and ASP */
1090 cmd &= ~PORT_CMD_ASP;
1091 cmd &= ~PORT_CMD_ALPE;
1092
1093 /* force the interface back to active */
1094 cmd |= PORT_CMD_ICC_ACTIVE;
1095
1096 /* write out new cmd value */
1097 writel(cmd, port_mmio + PORT_CMD);
1098 cmd = readl(port_mmio + PORT_CMD);
1099
1100 /* wait 10ms to be sure we've come out of any low power state */
1101 msleep(10);
1102
1103 /* clear out any PhyRdy stuff from interrupt status */
1104 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1105
1106 /* go ahead and clean out PhyRdy Change from Serror too */
Tejun Heo82ef04f2008-07-31 17:02:40 +09001107 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001108
1109 /*
1110 * Clear flag to indicate that we should ignore all PhyRdy
1111 * state changes
1112 */
1113 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1114
1115 /*
1116 * Enable interrupts on Phy Ready.
1117 */
1118 pp->intr_mask |= PORT_IRQ_PHYRDY;
1119 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1120
1121 /*
1122 * don't change the link pm policy - we can be called
1123 * just to turn of link pm temporarily
1124 */
1125}
1126
1127static int ahci_enable_alpm(struct ata_port *ap,
1128 enum link_pm policy)
1129{
1130 struct ahci_host_priv *hpriv = ap->host->private_data;
1131 void __iomem *port_mmio = ahci_port_base(ap);
1132 u32 cmd;
1133 struct ahci_port_priv *pp = ap->private_data;
1134 u32 asp;
1135
1136 /* Make sure the host is capable of link power management */
1137 if (!(hpriv->cap & HOST_CAP_ALPM))
1138 return -EINVAL;
1139
1140 switch (policy) {
1141 case MAX_PERFORMANCE:
1142 case NOT_AVAILABLE:
1143 /*
1144 * if we came here with NOT_AVAILABLE,
1145 * it just means this is the first time we
1146 * have tried to enable - default to max performance,
1147 * and let the user go to lower power modes on request.
1148 */
1149 ahci_disable_alpm(ap);
1150 return 0;
1151 case MIN_POWER:
1152 /* configure HBA to enter SLUMBER */
1153 asp = PORT_CMD_ASP;
1154 break;
1155 case MEDIUM_POWER:
1156 /* configure HBA to enter PARTIAL */
1157 asp = 0;
1158 break;
1159 default:
1160 return -EINVAL;
1161 }
1162
1163 /*
1164 * Disable interrupts on Phy Ready. This keeps us from
1165 * getting woken up due to spurious phy ready interrupts
1166 * TBD - Hot plug should be done via polling now, is
1167 * that even supported?
1168 */
1169 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1170 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1171
1172 /*
1173 * Set a flag to indicate that we should ignore all PhyRdy
1174 * state changes since these can happen now whenever we
1175 * change link state
1176 */
1177 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1178
1179 /* get the existing command bits */
1180 cmd = readl(port_mmio + PORT_CMD);
1181
1182 /*
1183 * Set ASP based on Policy
1184 */
1185 cmd |= asp;
1186
1187 /*
1188 * Setting this bit will instruct the HBA to aggressively
1189 * enter a lower power link state when it's appropriate and
1190 * based on the value set above for ASP
1191 */
1192 cmd |= PORT_CMD_ALPE;
1193
1194 /* write out new cmd value */
1195 writel(cmd, port_mmio + PORT_CMD);
1196 cmd = readl(port_mmio + PORT_CMD);
1197
1198 /* IPM bits should be set by libata-core */
1199 return 0;
1200}
1201
Tejun Heo438ac6d2007-03-02 17:31:26 +09001202#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001203static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001204{
Tejun Heo4447d352007-04-17 23:44:08 +09001205 struct ahci_host_priv *hpriv = ap->host->private_data;
1206 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001207 u32 cmd, scontrol;
1208
Tejun Heo4447d352007-04-17 23:44:08 +09001209 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001210 return;
1211
1212 /* put device into listen mode, first set PxSCTL.DET to 0 */
1213 scontrol = readl(port_mmio + PORT_SCR_CTL);
1214 scontrol &= ~0xf;
1215 writel(scontrol, port_mmio + PORT_SCR_CTL);
1216
1217 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001218 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001219 cmd &= ~PORT_CMD_SPIN_UP;
1220 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001221}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001222#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001223
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001224static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001225{
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001226 struct ahci_port_priv *pp = ap->private_data;
1227 struct ata_link *link;
1228 struct ahci_em_priv *emp;
David Milburn4c1e9aa2009-04-03 15:36:41 -05001229 ssize_t rc;
1230 int i;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001231
Tejun Heo0be0aa92006-07-26 15:59:26 +09001232 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001233 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001234
1235 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001236 ahci_start_engine(ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001237
1238 /* turn on LEDs */
1239 if (ap->flags & ATA_FLAG_EM) {
Tejun Heo1eca4362008-11-03 20:03:17 +09001240 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001241 emp = &pp->em_priv[link->pmp];
David Milburn4c1e9aa2009-04-03 15:36:41 -05001242
1243 /* EM Transmit bit maybe busy during init */
Tejun Heod50ce072009-05-12 10:57:41 +09001244 for (i = 0; i < EM_MAX_RETRY; i++) {
David Milburn4c1e9aa2009-04-03 15:36:41 -05001245 rc = ahci_transmit_led_message(ap,
1246 emp->led_state,
1247 4);
1248 if (rc == -EBUSY)
Tejun Heod50ce072009-05-12 10:57:41 +09001249 msleep(1);
David Milburn4c1e9aa2009-04-03 15:36:41 -05001250 else
1251 break;
1252 }
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001253 }
1254 }
1255
1256 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
Tejun Heo1eca4362008-11-03 20:03:17 +09001257 ata_for_each_link(link, ap, EDGE)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001258 ahci_init_sw_activity(link);
1259
Tejun Heo0be0aa92006-07-26 15:59:26 +09001260}
1261
Tejun Heo4447d352007-04-17 23:44:08 +09001262static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001263{
1264 int rc;
1265
1266 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001267 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001268 if (rc) {
1269 *emsg = "failed to stop engine";
1270 return rc;
1271 }
1272
1273 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001274 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001275 if (rc) {
1276 *emsg = "failed stop FIS RX";
1277 return rc;
1278 }
1279
Tejun Heo0be0aa92006-07-26 15:59:26 +09001280 return 0;
1281}
1282
Tejun Heo4447d352007-04-17 23:44:08 +09001283static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001284{
Tejun Heo4447d352007-04-17 23:44:08 +09001285 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001286 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001287 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001288 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001289
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001290 /* we must be in AHCI mode, before using anything
1291 * AHCI-specific, such as HOST_RESET.
1292 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001293 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001294
1295 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001296 if (!ahci_skip_host_reset) {
1297 tmp = readl(mmio + HOST_CTL);
1298 if ((tmp & HOST_RESET) == 0) {
1299 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1300 readl(mmio + HOST_CTL); /* flush */
1301 }
Tejun Heod91542c2006-07-26 15:59:26 +09001302
Zhang Rui24920c82008-07-04 13:32:17 +08001303 /*
1304 * to perform host reset, OS should set HOST_RESET
1305 * and poll until this bit is read to be "0".
1306 * reset must complete within 1 second, or
Tejun Heoa22e6442008-03-10 10:25:25 +09001307 * the hardware should be considered fried.
1308 */
Zhang Rui24920c82008-07-04 13:32:17 +08001309 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1310 HOST_RESET, 10, 1000);
Tejun Heod91542c2006-07-26 15:59:26 +09001311
Tejun Heoa22e6442008-03-10 10:25:25 +09001312 if (tmp & HOST_RESET) {
1313 dev_printk(KERN_ERR, host->dev,
1314 "controller reset failed (0x%x)\n", tmp);
1315 return -EIO;
1316 }
Tejun Heod91542c2006-07-26 15:59:26 +09001317
Tejun Heoa22e6442008-03-10 10:25:25 +09001318 /* turn on AHCI mode */
1319 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001320
Tejun Heoa22e6442008-03-10 10:25:25 +09001321 /* Some registers might be cleared on reset. Restore
1322 * initial values.
1323 */
1324 ahci_restore_initial_config(host);
1325 } else
1326 dev_printk(KERN_INFO, host->dev,
1327 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001328
1329 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1330 u16 tmp16;
1331
1332 /* configure PCS */
1333 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001334 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1335 tmp16 |= hpriv->port_map;
1336 pci_write_config_word(pdev, 0x92, tmp16);
1337 }
Tejun Heod91542c2006-07-26 15:59:26 +09001338 }
1339
1340 return 0;
1341}
1342
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001343static void ahci_sw_activity(struct ata_link *link)
1344{
1345 struct ata_port *ap = link->ap;
1346 struct ahci_port_priv *pp = ap->private_data;
1347 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1348
1349 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1350 return;
1351
1352 emp->activity++;
1353 if (!timer_pending(&emp->timer))
1354 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1355}
1356
1357static void ahci_sw_activity_blink(unsigned long arg)
1358{
1359 struct ata_link *link = (struct ata_link *)arg;
1360 struct ata_port *ap = link->ap;
1361 struct ahci_port_priv *pp = ap->private_data;
1362 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1363 unsigned long led_message = emp->led_state;
1364 u32 activity_led_state;
David Milburneb409632008-10-16 09:26:19 -05001365 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001366
David Milburn87943ac2008-10-13 14:38:36 -05001367 led_message &= EM_MSG_LED_VALUE;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001368 led_message |= ap->port_no | (link->pmp << 8);
1369
1370 /* check to see if we've had activity. If so,
1371 * toggle state of LED and reset timer. If not,
1372 * turn LED to desired idle state.
1373 */
David Milburneb409632008-10-16 09:26:19 -05001374 spin_lock_irqsave(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001375 if (emp->saved_activity != emp->activity) {
1376 emp->saved_activity = emp->activity;
1377 /* get the current LED state */
David Milburn87943ac2008-10-13 14:38:36 -05001378 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001379
1380 if (activity_led_state)
1381 activity_led_state = 0;
1382 else
1383 activity_led_state = 1;
1384
1385 /* clear old state */
David Milburn87943ac2008-10-13 14:38:36 -05001386 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001387
1388 /* toggle state */
1389 led_message |= (activity_led_state << 16);
1390 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1391 } else {
1392 /* switch to idle */
David Milburn87943ac2008-10-13 14:38:36 -05001393 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001394 if (emp->blink_policy == BLINK_OFF)
1395 led_message |= (1 << 16);
1396 }
David Milburneb409632008-10-16 09:26:19 -05001397 spin_unlock_irqrestore(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001398 ahci_transmit_led_message(ap, led_message, 4);
1399}
1400
1401static void ahci_init_sw_activity(struct ata_link *link)
1402{
1403 struct ata_port *ap = link->ap;
1404 struct ahci_port_priv *pp = ap->private_data;
1405 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1406
1407 /* init activity stats, setup timer */
1408 emp->saved_activity = emp->activity = 0;
1409 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1410
1411 /* check our blink policy and set flag for link if it's enabled */
1412 if (emp->blink_policy)
1413 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1414}
1415
1416static int ahci_reset_em(struct ata_host *host)
1417{
1418 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1419 u32 em_ctl;
1420
1421 em_ctl = readl(mmio + HOST_EM_CTL);
1422 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1423 return -EINVAL;
1424
1425 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1426 return 0;
1427}
1428
1429static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1430 ssize_t size)
1431{
1432 struct ahci_host_priv *hpriv = ap->host->private_data;
1433 struct ahci_port_priv *pp = ap->private_data;
1434 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1435 u32 em_ctl;
1436 u32 message[] = {0, 0};
Linus Torvalds93082f02008-07-25 10:56:36 -07001437 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001438 int pmp;
1439 struct ahci_em_priv *emp;
1440
1441 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001442 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Tejun Heod50ce072009-05-12 10:57:41 +09001443 if (pmp < EM_MAX_SLOTS)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001444 emp = &pp->em_priv[pmp];
1445 else
1446 return -EINVAL;
1447
1448 spin_lock_irqsave(ap->lock, flags);
1449
1450 /*
1451 * if we are still busy transmitting a previous message,
1452 * do not allow
1453 */
1454 em_ctl = readl(mmio + HOST_EM_CTL);
1455 if (em_ctl & EM_CTL_TM) {
1456 spin_unlock_irqrestore(ap->lock, flags);
David Milburn4c1e9aa2009-04-03 15:36:41 -05001457 return -EBUSY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001458 }
1459
1460 /*
1461 * create message header - this is all zero except for
1462 * the message size, which is 4 bytes.
1463 */
1464 message[0] |= (4 << 8);
1465
1466 /* ignore 0:4 of byte zero, fill in port info yourself */
David Milburn87943ac2008-10-13 14:38:36 -05001467 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001468
1469 /* write message to EM_LOC */
1470 writel(message[0], mmio + hpriv->em_loc);
1471 writel(message[1], mmio + hpriv->em_loc+4);
1472
1473 /* save off new led state for port/slot */
David Milburn208f2a82009-03-20 14:14:23 -05001474 emp->led_state = state;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001475
1476 /*
1477 * tell hardware to transmit the message
1478 */
1479 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1480
1481 spin_unlock_irqrestore(ap->lock, flags);
1482 return size;
1483}
1484
1485static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1486{
1487 struct ahci_port_priv *pp = ap->private_data;
1488 struct ata_link *link;
1489 struct ahci_em_priv *emp;
1490 int rc = 0;
1491
Tejun Heo1eca4362008-11-03 20:03:17 +09001492 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001493 emp = &pp->em_priv[link->pmp];
1494 rc += sprintf(buf, "%lx\n", emp->led_state);
1495 }
1496 return rc;
1497}
1498
1499static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1500 size_t size)
1501{
1502 int state;
1503 int pmp;
1504 struct ahci_port_priv *pp = ap->private_data;
1505 struct ahci_em_priv *emp;
1506
1507 state = simple_strtoul(buf, NULL, 0);
1508
1509 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001510 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Tejun Heod50ce072009-05-12 10:57:41 +09001511 if (pmp < EM_MAX_SLOTS)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001512 emp = &pp->em_priv[pmp];
1513 else
1514 return -EINVAL;
1515
1516 /* mask off the activity bits if we are in sw_activity
1517 * mode, user should turn off sw_activity before setting
1518 * activity led through em_message
1519 */
1520 if (emp->blink_policy)
David Milburn87943ac2008-10-13 14:38:36 -05001521 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001522
1523 return ahci_transmit_led_message(ap, state, size);
1524}
1525
1526static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1527{
1528 struct ata_link *link = dev->link;
1529 struct ata_port *ap = link->ap;
1530 struct ahci_port_priv *pp = ap->private_data;
1531 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1532 u32 port_led_state = emp->led_state;
1533
1534 /* save the desired Activity LED behavior */
1535 if (val == OFF) {
1536 /* clear LFLAG */
1537 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1538
1539 /* set the LED to OFF */
David Milburn87943ac2008-10-13 14:38:36 -05001540 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001541 port_led_state |= (ap->port_no | (link->pmp << 8));
1542 ahci_transmit_led_message(ap, port_led_state, 4);
1543 } else {
1544 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1545 if (val == BLINK_OFF) {
1546 /* set LED to ON for idle */
David Milburn87943ac2008-10-13 14:38:36 -05001547 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001548 port_led_state |= (ap->port_no | (link->pmp << 8));
David Milburn87943ac2008-10-13 14:38:36 -05001549 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001550 ahci_transmit_led_message(ap, port_led_state, 4);
1551 }
1552 }
1553 emp->blink_policy = val;
1554 return 0;
1555}
1556
1557static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1558{
1559 struct ata_link *link = dev->link;
1560 struct ata_port *ap = link->ap;
1561 struct ahci_port_priv *pp = ap->private_data;
1562 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1563
1564 /* display the saved value of activity behavior for this
1565 * disk.
1566 */
1567 return sprintf(buf, "%d\n", emp->blink_policy);
1568}
1569
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001570static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1571 int port_no, void __iomem *mmio,
1572 void __iomem *port_mmio)
1573{
1574 const char *emsg = NULL;
1575 int rc;
1576 u32 tmp;
1577
1578 /* make sure port is not active */
1579 rc = ahci_deinit_port(ap, &emsg);
1580 if (rc)
1581 dev_printk(KERN_WARNING, &pdev->dev,
1582 "%s (%d)\n", emsg, rc);
1583
1584 /* clear SError */
1585 tmp = readl(port_mmio + PORT_SCR_ERR);
1586 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1587 writel(tmp, port_mmio + PORT_SCR_ERR);
1588
1589 /* clear port IRQ */
1590 tmp = readl(port_mmio + PORT_IRQ_STAT);
1591 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1592 if (tmp)
1593 writel(tmp, port_mmio + PORT_IRQ_STAT);
1594
1595 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1596}
1597
Tejun Heo4447d352007-04-17 23:44:08 +09001598static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001599{
Tejun Heo417a1a62007-09-23 13:19:55 +09001600 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001601 struct pci_dev *pdev = to_pci_dev(host->dev);
1602 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001603 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001604 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001605 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001606 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +09001607
Tejun Heo417a1a62007-09-23 13:19:55 +09001608 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001609 if (pdev->device == 0x6121)
1610 mv = 2;
1611 else
1612 mv = 4;
1613 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -04001614
1615 writel(0, port_mmio + PORT_IRQ_MASK);
1616
1617 /* clear port IRQ */
1618 tmp = readl(port_mmio + PORT_IRQ_STAT);
1619 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1620 if (tmp)
1621 writel(tmp, port_mmio + PORT_IRQ_STAT);
1622 }
1623
Tejun Heo4447d352007-04-17 23:44:08 +09001624 for (i = 0; i < host->n_ports; i++) {
1625 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001626
Jeff Garzikcd70c262007-07-08 02:29:42 -04001627 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001628 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001629 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001630
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001631 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001632 }
1633
1634 tmp = readl(mmio + HOST_CTL);
1635 VPRINTK("HOST_CTL 0x%x\n", tmp);
1636 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1637 tmp = readl(mmio + HOST_CTL);
1638 VPRINTK("HOST_CTL 0x%x\n", tmp);
1639}
1640
Jeff Garzika8785392008-02-28 15:43:48 -05001641static void ahci_dev_config(struct ata_device *dev)
1642{
1643 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1644
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001645 if (hpriv->flags & AHCI_HFLAG_SECT255) {
Jeff Garzika8785392008-02-28 15:43:48 -05001646 dev->max_sectors = 255;
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001647 ata_dev_printk(dev, KERN_INFO,
1648 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1649 }
Jeff Garzika8785392008-02-28 15:43:48 -05001650}
1651
Tejun Heo422b7592005-12-19 22:37:17 +09001652static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001653{
Tejun Heo4447d352007-04-17 23:44:08 +09001654 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001655 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001656 u32 tmp;
1657
1658 tmp = readl(port_mmio + PORT_SIG);
1659 tf.lbah = (tmp >> 24) & 0xff;
1660 tf.lbam = (tmp >> 16) & 0xff;
1661 tf.lbal = (tmp >> 8) & 0xff;
1662 tf.nsect = (tmp) & 0xff;
1663
1664 return ata_dev_classify(&tf);
1665}
1666
Tejun Heo12fad3f2006-05-15 21:03:55 +09001667static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1668 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001669{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001670 dma_addr_t cmd_tbl_dma;
1671
1672 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1673
1674 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1675 pp->cmd_slot[tag].status = 0;
1676 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1677 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001678}
1679
Shane Huang78d5ae32009-08-07 15:05:52 +08001680static int ahci_kick_engine(struct ata_port *ap)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001681{
Tejun Heo350756f2008-04-07 22:47:21 +09001682 void __iomem *port_mmio = ahci_port_base(ap);
Jeff Garzikcca39742006-08-24 03:19:22 -04001683 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo520d06f2008-04-07 22:47:21 +09001684 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001685 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001686 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001687
Tejun Heod2e75df2007-07-16 14:29:39 +09001688 /* stop engine */
1689 rc = ahci_stop_engine(ap);
1690 if (rc)
1691 goto out_restart;
1692
Shane Huang78d5ae32009-08-07 15:05:52 +08001693 /* need to do CLO?
1694 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1695 */
1696 busy = status & (ATA_BUSY | ATA_DRQ);
1697 if (!busy && !sata_pmp_attached(ap)) {
Tejun Heod2e75df2007-07-16 14:29:39 +09001698 rc = 0;
1699 goto out_restart;
1700 }
1701
1702 if (!(hpriv->cap & HOST_CAP_CLO)) {
1703 rc = -EOPNOTSUPP;
1704 goto out_restart;
1705 }
1706
1707 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001708 tmp = readl(port_mmio + PORT_CMD);
1709 tmp |= PORT_CMD_CLO;
1710 writel(tmp, port_mmio + PORT_CMD);
1711
Tejun Heod2e75df2007-07-16 14:29:39 +09001712 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001713 tmp = ata_wait_register(port_mmio + PORT_CMD,
1714 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1715 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001716 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001717
Tejun Heod2e75df2007-07-16 14:29:39 +09001718 /* restart engine */
1719 out_restart:
1720 ahci_start_engine(ap);
1721 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001722}
1723
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001724static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1725 struct ata_taskfile *tf, int is_cmd, u16 flags,
1726 unsigned long timeout_msec)
1727{
1728 const u32 cmd_fis_len = 5; /* five dwords */
1729 struct ahci_port_priv *pp = ap->private_data;
1730 void __iomem *port_mmio = ahci_port_base(ap);
1731 u8 *fis = pp->cmd_tbl;
1732 u32 tmp;
1733
1734 /* prep the command */
1735 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1736 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1737
1738 /* issue & wait */
1739 writel(1, port_mmio + PORT_CMD_ISSUE);
1740
1741 if (timeout_msec) {
1742 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1743 1, timeout_msec);
1744 if (tmp & 0x1) {
Shane Huang78d5ae32009-08-07 15:05:52 +08001745 ahci_kick_engine(ap);
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001746 return -EBUSY;
1747 }
1748 } else
1749 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1750
1751 return 0;
1752}
1753
Shane Huangbd172432008-06-10 15:52:04 +08001754static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1755 int pmp, unsigned long deadline,
1756 int (*check_ready)(struct ata_link *link))
Tejun Heo4658f792006-03-22 21:07:03 +09001757{
Tejun Heocc0680a2007-08-06 18:36:23 +09001758 struct ata_port *ap = link->ap;
Tejun Heo55946392009-08-04 14:30:08 +09001759 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo4658f792006-03-22 21:07:03 +09001760 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001761 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001762 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001763 int rc;
1764
1765 DPRINTK("ENTER\n");
1766
1767 /* prepare for SRST (AHCI-1.1 10.4.1) */
Shane Huang78d5ae32009-08-07 15:05:52 +08001768 rc = ahci_kick_engine(ap);
Tejun Heo994056d2007-12-06 15:02:48 +09001769 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001770 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001771 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001772
Tejun Heocc0680a2007-08-06 18:36:23 +09001773 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001774
1775 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001776 msecs = 0;
1777 now = jiffies;
1778 if (time_after(now, deadline))
1779 msecs = jiffies_to_msecs(deadline - now);
1780
Tejun Heo4658f792006-03-22 21:07:03 +09001781 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001782 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001783 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001784 rc = -EIO;
1785 reason = "1st FIS failed";
1786 goto fail;
1787 }
1788
1789 /* spec says at least 5us, but be generous and sleep for 1ms */
1790 msleep(1);
1791
1792 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001793 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001794 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001795
Tejun Heo705e76b2008-04-07 22:47:19 +09001796 /* wait for link to become ready */
Shane Huangbd172432008-06-10 15:52:04 +08001797 rc = ata_wait_after_reset(link, deadline, check_ready);
Tejun Heo55946392009-08-04 14:30:08 +09001798 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1799 /*
1800 * Workaround for cases where link online status can't
1801 * be trusted. Treat device readiness timeout as link
1802 * offline.
1803 */
1804 ata_link_printk(link, KERN_INFO,
1805 "device not ready, treating as offline\n");
1806 *class = ATA_DEV_NONE;
1807 } else if (rc) {
1808 /* link occupied, -ENODEV too is an error */
Tejun Heo9b893912007-02-02 16:50:52 +09001809 reason = "device not ready";
1810 goto fail;
Tejun Heo55946392009-08-04 14:30:08 +09001811 } else
1812 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001813
1814 DPRINTK("EXIT, class=%u\n", *class);
1815 return 0;
1816
Tejun Heo4658f792006-03-22 21:07:03 +09001817 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001818 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001819 return rc;
1820}
1821
Shane Huangbd172432008-06-10 15:52:04 +08001822static int ahci_check_ready(struct ata_link *link)
1823{
1824 void __iomem *port_mmio = ahci_port_base(link->ap);
1825 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1826
1827 return ata_check_ready(status);
1828}
1829
1830static int ahci_softreset(struct ata_link *link, unsigned int *class,
1831 unsigned long deadline)
1832{
1833 int pmp = sata_srst_pmp(link);
1834
1835 DPRINTK("ENTER\n");
1836
1837 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1838}
1839
1840static int ahci_sb600_check_ready(struct ata_link *link)
1841{
1842 void __iomem *port_mmio = ahci_port_base(link->ap);
1843 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1844 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1845
1846 /*
1847 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1848 * which can save timeout delay.
1849 */
1850 if (irq_status & PORT_IRQ_BAD_PMP)
1851 return -EIO;
1852
1853 return ata_check_ready(status);
1854}
1855
1856static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1857 unsigned long deadline)
1858{
1859 struct ata_port *ap = link->ap;
1860 void __iomem *port_mmio = ahci_port_base(ap);
1861 int pmp = sata_srst_pmp(link);
1862 int rc;
1863 u32 irq_sts;
1864
1865 DPRINTK("ENTER\n");
1866
1867 rc = ahci_do_softreset(link, class, pmp, deadline,
1868 ahci_sb600_check_ready);
1869
1870 /*
1871 * Soft reset fails on some ATI chips with IPMS set when PMP
1872 * is enabled but SATA HDD/ODD is connected to SATA port,
1873 * do soft reset again to port 0.
1874 */
1875 if (rc == -EIO) {
1876 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1877 if (irq_sts & PORT_IRQ_BAD_PMP) {
1878 ata_link_printk(link, KERN_WARNING,
Shane Huangb6931c12009-08-05 10:10:41 +08001879 "applying SB600 PMP SRST workaround "
1880 "and retrying\n");
Shane Huangbd172432008-06-10 15:52:04 +08001881 rc = ahci_do_softreset(link, class, 0, deadline,
1882 ahci_check_ready);
1883 }
1884 }
1885
1886 return rc;
1887}
1888
Tejun Heocc0680a2007-08-06 18:36:23 +09001889static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001890 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001891{
Tejun Heo9dadd452008-04-07 22:47:19 +09001892 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
Tejun Heocc0680a2007-08-06 18:36:23 +09001893 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001894 struct ahci_port_priv *pp = ap->private_data;
1895 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1896 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001897 bool online;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001898 int rc;
1899
1900 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901
Tejun Heo4447d352007-04-17 23:44:08 +09001902 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001903
1904 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001905 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001906 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001907 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001908
Tejun Heo9dadd452008-04-07 22:47:19 +09001909 rc = sata_link_hardreset(link, timing, deadline, &online,
1910 ahci_check_ready);
Tejun Heo42969712006-05-31 18:28:18 +09001911
Tejun Heo4447d352007-04-17 23:44:08 +09001912 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913
Tejun Heo9dadd452008-04-07 22:47:19 +09001914 if (online)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001915 *class = ahci_dev_classify(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001916
Tejun Heo4bd00f62006-02-11 16:26:02 +09001917 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1918 return rc;
1919}
1920
Tejun Heocc0680a2007-08-06 18:36:23 +09001921static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001922 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001923{
Tejun Heocc0680a2007-08-06 18:36:23 +09001924 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +09001925 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +09001926 int rc;
1927
1928 DPRINTK("ENTER\n");
1929
Tejun Heo4447d352007-04-17 23:44:08 +09001930 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001931
Tejun Heocc0680a2007-08-06 18:36:23 +09001932 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001933 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +09001934
Tejun Heo4447d352007-04-17 23:44:08 +09001935 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001936
1937 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1938
1939 /* vt8251 doesn't clear BSY on signature FIS reception,
1940 * request follow-up softreset.
1941 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001942 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +09001943}
1944
Tejun Heoedc93052007-10-25 14:59:16 +09001945static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1946 unsigned long deadline)
1947{
1948 struct ata_port *ap = link->ap;
1949 struct ahci_port_priv *pp = ap->private_data;
1950 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1951 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001952 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +09001953 int rc;
1954
1955 ahci_stop_engine(ap);
1956
1957 /* clear D2H reception area to properly wait for D2H FIS */
1958 ata_tf_init(link->device, &tf);
1959 tf.command = 0x80;
1960 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1961
1962 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001963 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +09001964
1965 ahci_start_engine(ap);
1966
Tejun Heoedc93052007-10-25 14:59:16 +09001967 /* The pseudo configuration device on SIMG4726 attached to
1968 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1969 * hardreset if no device is attached to the first downstream
1970 * port && the pseudo device locks up on SRST w/ PMP==0. To
1971 * work around this, wait for !BSY only briefly. If BSY isn't
1972 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1973 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1974 *
1975 * Wait for two seconds. Devices attached to downstream port
1976 * which can't process the following IDENTIFY after this will
1977 * have to be reset again. For most cases, this should
1978 * suffice while making probing snappish enough.
1979 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001980 if (online) {
1981 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1982 ahci_check_ready);
1983 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +08001984 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +09001985 }
Tejun Heo9dadd452008-04-07 22:47:19 +09001986 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +09001987}
1988
Tejun Heocc0680a2007-08-06 18:36:23 +09001989static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001990{
Tejun Heocc0680a2007-08-06 18:36:23 +09001991 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001992 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001993 u32 new_tmp, tmp;
1994
Tejun Heo203c75b2008-04-07 22:47:18 +09001995 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001996
1997 /* Make sure port's ATAPI bit is set appropriately */
1998 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001999 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05002000 new_tmp |= PORT_CMD_ATAPI;
2001 else
2002 new_tmp &= ~PORT_CMD_ATAPI;
2003 if (new_tmp != tmp) {
2004 writel(new_tmp, port_mmio + PORT_CMD);
2005 readl(port_mmio + PORT_CMD); /* flush */
2006 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007}
2008
Tejun Heo12fad3f2006-05-15 21:03:55 +09002009static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002010{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04002011 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002012 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
2013 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014
2015 VPRINTK("ENTER\n");
2016
2017 /*
2018 * Next, the S/G list.
2019 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09002020 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04002021 dma_addr_t addr = sg_dma_address(sg);
2022 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023
Tejun Heoff2aeb12007-12-05 16:43:11 +09002024 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
2025 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
2026 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002027 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05002028
Tejun Heoff2aeb12007-12-05 16:43:11 +09002029 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002030}
2031
2032static void ahci_qc_prep(struct ata_queued_cmd *qc)
2033{
Jeff Garzika0ea7322005-06-04 01:13:15 -04002034 struct ata_port *ap = qc->ap;
2035 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09002036 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09002037 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038 u32 opts;
2039 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05002040 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041
2042 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043 * Fill in command table information. First, the header,
2044 * a SATA Register - Host to Device command FIS.
2045 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09002046 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2047
Tejun Heo7d50b602007-09-23 13:19:54 +09002048 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09002049 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002050 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2051 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04002052 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002053
Tejun Heocc9278e2006-02-10 17:25:47 +09002054 n_elem = 0;
2055 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002056 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002057
Tejun Heocc9278e2006-02-10 17:25:47 +09002058 /*
2059 * Fill in command slot information.
2060 */
Tejun Heo7d50b602007-09-23 13:19:54 +09002061 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09002062 if (qc->tf.flags & ATA_TFLAG_WRITE)
2063 opts |= AHCI_CMD_WRITE;
2064 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09002065 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05002066
Tejun Heo12fad3f2006-05-15 21:03:55 +09002067 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002068}
2069
Tejun Heo78cd52d2006-05-15 20:58:29 +09002070static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002071{
Tejun Heo417a1a62007-09-23 13:19:55 +09002072 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002073 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002074 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2075 struct ata_link *link = NULL;
2076 struct ata_queued_cmd *active_qc;
2077 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002078 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002079
Tejun Heo7d50b602007-09-23 13:19:54 +09002080 /* determine active link */
Tejun Heo1eca4362008-11-03 20:03:17 +09002081 ata_for_each_link(link, ap, EDGE)
Tejun Heo7d50b602007-09-23 13:19:54 +09002082 if (ata_link_active(link))
2083 break;
2084 if (!link)
2085 link = &ap->link;
2086
2087 active_qc = ata_qc_from_tag(ap, link->active_tag);
2088 active_ehi = &link->eh_info;
2089
2090 /* record irq stat */
2091 ata_ehi_clear_desc(host_ehi);
2092 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05002093
Tejun Heo78cd52d2006-05-15 20:58:29 +09002094 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heo82ef04f2008-07-31 17:02:40 +09002095 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2096 ahci_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09002097 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098
Tejun Heo41669552006-11-29 11:33:14 +09002099 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09002100 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09002101 irq_stat &= ~PORT_IRQ_IF_ERR;
2102
Conke Hu55a61602007-03-27 18:33:05 +08002103 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09002104 /* If qc is active, charge it; otherwise, the active
2105 * link. There's no active qc on NCQ errors. It will
2106 * be determined by EH by reading log page 10h.
2107 */
2108 if (active_qc)
2109 active_qc->err_mask |= AC_ERR_DEV;
2110 else
2111 active_ehi->err_mask |= AC_ERR_DEV;
2112
Tejun Heo417a1a62007-09-23 13:19:55 +09002113 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09002114 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002115 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002116
Tejun Heo78cd52d2006-05-15 20:58:29 +09002117 if (irq_stat & PORT_IRQ_UNK_FIS) {
2118 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002119
Tejun Heo7d50b602007-09-23 13:19:54 +09002120 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002121 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002122 ata_ehi_push_desc(active_ehi,
2123 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09002124 unk[0], unk[1], unk[2], unk[3]);
2125 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04002126
Tejun Heo071f44b2008-04-07 22:47:22 +09002127 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
Tejun Heo7d50b602007-09-23 13:19:54 +09002128 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002129 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002130 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2131 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09002132
Tejun Heo7d50b602007-09-23 13:19:54 +09002133 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2134 host_ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002135 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002136 ata_ehi_push_desc(host_ehi, "host bus error");
2137 }
2138
2139 if (irq_stat & PORT_IRQ_IF_ERR) {
2140 host_ehi->err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002141 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002142 ata_ehi_push_desc(host_ehi, "interface fatal error");
2143 }
2144
2145 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2146 ata_ehi_hotplugged(host_ehi);
2147 ata_ehi_push_desc(host_ehi, "%s",
2148 irq_stat & PORT_IRQ_CONNECT ?
2149 "connection status changed" : "PHY RDY changed");
2150 }
2151
2152 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002153
Tejun Heo78cd52d2006-05-15 20:58:29 +09002154 if (irq_stat & PORT_IRQ_FREEZE)
2155 ata_port_freeze(ap);
2156 else
2157 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002158}
2159
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002160static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002161{
Tejun Heo350756f2008-04-07 22:47:21 +09002162 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002163 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09002164 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09002165 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09002166 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09002167 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09002168 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002169
2170 status = readl(port_mmio + PORT_IRQ_STAT);
2171 writel(status, port_mmio + PORT_IRQ_STAT);
2172
Tejun Heob06ce3e2007-10-09 15:06:48 +09002173 /* ignore BAD_PMP while resetting */
2174 if (unlikely(resetting))
2175 status &= ~PORT_IRQ_BAD_PMP;
2176
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002177 /* If we are getting PhyRdy, this is
2178 * just a power state change, we should
2179 * clear out this, plus the PhyRdy/Comm
2180 * Wake bits from Serror
2181 */
2182 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2183 (status & PORT_IRQ_PHYRDY)) {
2184 status &= ~PORT_IRQ_PHYRDY;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002185 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002186 }
2187
Tejun Heo78cd52d2006-05-15 20:58:29 +09002188 if (unlikely(status & PORT_IRQ_ERROR)) {
2189 ahci_error_intr(ap, status);
2190 return;
2191 }
2192
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002193 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09002194 /* If SNotification is available, leave notification
2195 * handling to sata_async_notification(). If not,
2196 * emulate it by snooping SDB FIS RX area.
2197 *
2198 * Snooping FIS RX area is probably cheaper than
2199 * poking SNotification but some constrollers which
2200 * implement SNotification, ICH9 for example, don't
2201 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002202 */
Tejun Heo5f226c62007-10-09 15:02:23 +09002203 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09002204 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09002205 else {
2206 /* If the 'N' bit in word 0 of the FIS is set,
2207 * we just received asynchronous notification.
2208 * Tell libata about it.
2209 */
2210 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2211 u32 f0 = le32_to_cpu(f[0]);
2212
2213 if (f0 & (1 << 15))
2214 sata_async_notification(ap);
2215 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002216 }
2217
Tejun Heo7d50b602007-09-23 13:19:54 +09002218 /* pp->active_link is valid iff any command is in flight */
2219 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002220 qc_active = readl(port_mmio + PORT_SCR_ACT);
2221 else
2222 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2223
Tejun Heo79f97da2008-04-07 22:47:20 +09002224 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heob06ce3e2007-10-09 15:06:48 +09002225
Tejun Heo459ad682007-12-07 12:46:23 +09002226 /* while resetting, invalid completions are expected */
2227 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002228 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002229 ehi->action |= ATA_EH_RESET;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002230 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002232}
2233
David Howells7d12e782006-10-05 14:55:46 +01002234static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002235{
Jeff Garzikcca39742006-08-24 03:19:22 -04002236 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002237 struct ahci_host_priv *hpriv;
2238 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04002239 void __iomem *mmio;
Tejun Heod28f87a2008-07-05 13:10:50 +09002240 u32 irq_stat, irq_masked;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002241
2242 VPRINTK("ENTER\n");
2243
Jeff Garzikcca39742006-08-24 03:19:22 -04002244 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002245 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246
2247 /* sigh. 0xffffffff is a valid return from h/w */
2248 irq_stat = readl(mmio + HOST_IRQ_STAT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002249 if (!irq_stat)
2250 return IRQ_NONE;
2251
Tejun Heod28f87a2008-07-05 13:10:50 +09002252 irq_masked = irq_stat & hpriv->port_map;
2253
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002254 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002255
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002256 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002258
Tejun Heod28f87a2008-07-05 13:10:50 +09002259 if (!(irq_masked & (1 << i)))
Jeff Garzik67846b32005-10-05 02:58:32 -04002260 continue;
2261
Jeff Garzikcca39742006-08-24 03:19:22 -04002262 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04002263 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002264 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04002265 VPRINTK("port %u\n", i);
2266 } else {
2267 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09002268 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04002269 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05002270 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002271 }
Jeff Garzik67846b32005-10-05 02:58:32 -04002272
Linus Torvalds1da177e2005-04-16 15:20:36 -07002273 handled = 1;
2274 }
2275
Tejun Heod28f87a2008-07-05 13:10:50 +09002276 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2277 * it should be cleared after all the port events are cleared;
2278 * otherwise, it will raise a spurious interrupt after each
2279 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2280 * information.
2281 *
2282 * Also, use the unmasked value to clear interrupt as spurious
2283 * pending event on a dummy port might cause screaming IRQ.
2284 */
Tejun Heoea0c62f2008-06-28 01:49:02 +09002285 writel(irq_stat, mmio + HOST_IRQ_STAT);
2286
Jeff Garzikcca39742006-08-24 03:19:22 -04002287 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002288
2289 VPRINTK("EXIT\n");
2290
2291 return IRQ_RETVAL(handled);
2292}
2293
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002294static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002295{
2296 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09002297 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09002298 struct ahci_port_priv *pp = ap->private_data;
2299
2300 /* Keep track of the currently active link. It will be used
2301 * in completion path to determine whether NCQ phase is in
2302 * progress.
2303 */
2304 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002305
Tejun Heo12fad3f2006-05-15 21:03:55 +09002306 if (qc->tf.protocol == ATA_PROT_NCQ)
2307 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2308 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002309
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002310 ahci_sw_activity(qc->dev->link);
2311
Linus Torvalds1da177e2005-04-16 15:20:36 -07002312 return 0;
2313}
2314
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09002315static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2316{
2317 struct ahci_port_priv *pp = qc->ap->private_data;
2318 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2319
2320 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2321 return true;
2322}
2323
Tejun Heo78cd52d2006-05-15 20:58:29 +09002324static void ahci_freeze(struct ata_port *ap)
2325{
Tejun Heo4447d352007-04-17 23:44:08 +09002326 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002327
2328 /* turn IRQ off */
2329 writel(0, port_mmio + PORT_IRQ_MASK);
2330}
2331
2332static void ahci_thaw(struct ata_port *ap)
2333{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002334 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09002335 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002336 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002337 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002338
2339 /* clear IRQ */
2340 tmp = readl(port_mmio + PORT_IRQ_STAT);
2341 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09002342 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002343
Tejun Heo1c954a42007-10-09 15:01:37 +09002344 /* turn IRQ back on */
2345 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002346}
2347
2348static void ahci_error_handler(struct ata_port *ap)
2349{
Tejun Heob51e9e52006-06-29 01:29:30 +09002350 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09002351 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09002352 ahci_stop_engine(ap);
2353 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002354 }
2355
Tejun Heoa1efdab2008-03-25 12:22:50 +09002356 sata_pmp_error_handler(ap);
Tejun Heoedc93052007-10-25 14:59:16 +09002357}
2358
Tejun Heo78cd52d2006-05-15 20:58:29 +09002359static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2360{
2361 struct ata_port *ap = qc->ap;
2362
Tejun Heod2e75df2007-07-16 14:29:39 +09002363 /* make DMA engine forget about the failed command */
2364 if (qc->flags & ATA_QCFLAG_FAILED)
Shane Huang78d5ae32009-08-07 15:05:52 +08002365 ahci_kick_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002366}
2367
Tejun Heo7d50b602007-09-23 13:19:54 +09002368static void ahci_pmp_attach(struct ata_port *ap)
2369{
2370 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002371 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002372 u32 cmd;
2373
2374 cmd = readl(port_mmio + PORT_CMD);
2375 cmd |= PORT_CMD_PMP;
2376 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002377
2378 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2379 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002380}
2381
2382static void ahci_pmp_detach(struct ata_port *ap)
2383{
2384 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002385 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002386 u32 cmd;
2387
2388 cmd = readl(port_mmio + PORT_CMD);
2389 cmd &= ~PORT_CMD_PMP;
2390 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002391
2392 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2393 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002394}
2395
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002396static int ahci_port_resume(struct ata_port *ap)
2397{
2398 ahci_power_up(ap);
2399 ahci_start_port(ap);
2400
Tejun Heo071f44b2008-04-07 22:47:22 +09002401 if (sata_pmp_attached(ap))
Tejun Heo7d50b602007-09-23 13:19:54 +09002402 ahci_pmp_attach(ap);
2403 else
2404 ahci_pmp_detach(ap);
2405
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002406 return 0;
2407}
2408
Tejun Heo438ac6d2007-03-02 17:31:26 +09002409#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09002410static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2411{
Tejun Heoc1332872006-07-26 15:59:26 +09002412 const char *emsg = NULL;
2413 int rc;
2414
Tejun Heo4447d352007-04-17 23:44:08 +09002415 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09002416 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09002417 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09002418 else {
Tejun Heoc1332872006-07-26 15:59:26 +09002419 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002420 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09002421 }
2422
2423 return rc;
2424}
2425
Tejun Heoc1332872006-07-26 15:59:26 +09002426static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2427{
Jeff Garzikcca39742006-08-24 03:19:22 -04002428 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo9b10ae82009-05-30 20:50:12 +09002429 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002430 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09002431 u32 ctl;
2432
Tejun Heo9b10ae82009-05-30 20:50:12 +09002433 if (mesg.event & PM_EVENT_SUSPEND &&
2434 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2435 dev_printk(KERN_ERR, &pdev->dev,
2436 "BIOS update required for suspend/resume\n");
2437 return -EIO;
2438 }
2439
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01002440 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09002441 /* AHCI spec rev1.1 section 8.3.3:
2442 * Software must disable interrupts prior to requesting a
2443 * transition of the HBA to D3 state.
2444 */
2445 ctl = readl(mmio + HOST_CTL);
2446 ctl &= ~HOST_IRQ_EN;
2447 writel(ctl, mmio + HOST_CTL);
2448 readl(mmio + HOST_CTL); /* flush */
2449 }
2450
2451 return ata_pci_device_suspend(pdev, mesg);
2452}
2453
2454static int ahci_pci_device_resume(struct pci_dev *pdev)
2455{
Jeff Garzikcca39742006-08-24 03:19:22 -04002456 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09002457 int rc;
2458
Tejun Heo553c4aa2006-12-26 19:39:50 +09002459 rc = ata_pci_device_do_resume(pdev);
2460 if (rc)
2461 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002462
2463 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002464 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002465 if (rc)
2466 return rc;
2467
Tejun Heo4447d352007-04-17 23:44:08 +09002468 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002469 }
2470
Jeff Garzikcca39742006-08-24 03:19:22 -04002471 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002472
2473 return 0;
2474}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002475#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002476
Tejun Heo254950c2006-07-26 15:59:25 +09002477static int ahci_port_start(struct ata_port *ap)
2478{
Jeff Garzikcca39742006-08-24 03:19:22 -04002479 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002480 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002481 void *mem;
2482 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002483
Tejun Heo24dc5f32007-01-20 16:00:28 +09002484 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002485 if (!pp)
2486 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002487
Tejun Heo24dc5f32007-01-20 16:00:28 +09002488 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2489 GFP_KERNEL);
2490 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002491 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002492 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2493
2494 /*
2495 * First item in chunk of DMA memory: 32-slot command table,
2496 * 32 bytes each in size
2497 */
2498 pp->cmd_slot = mem;
2499 pp->cmd_slot_dma = mem_dma;
2500
2501 mem += AHCI_CMD_SLOT_SZ;
2502 mem_dma += AHCI_CMD_SLOT_SZ;
2503
2504 /*
2505 * Second item: Received-FIS area
2506 */
2507 pp->rx_fis = mem;
2508 pp->rx_fis_dma = mem_dma;
2509
2510 mem += AHCI_RX_FIS_SZ;
2511 mem_dma += AHCI_RX_FIS_SZ;
2512
2513 /*
2514 * Third item: data area for storing a single command
2515 * and its scatter-gather table
2516 */
2517 pp->cmd_tbl = mem;
2518 pp->cmd_tbl_dma = mem_dma;
2519
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002520 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002521 * Save off initial list of interrupts to be enabled.
2522 * This could be changed later
2523 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002524 pp->intr_mask = DEF_PORT_IRQ;
2525
Tejun Heo254950c2006-07-26 15:59:25 +09002526 ap->private_data = pp;
2527
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002528 /* engage engines, captain */
2529 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002530}
2531
2532static void ahci_port_stop(struct ata_port *ap)
2533{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002534 const char *emsg = NULL;
2535 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002536
Tejun Heo0be0aa92006-07-26 15:59:26 +09002537 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002538 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002539 if (rc)
2540 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002541}
2542
Tejun Heo4447d352007-04-17 23:44:08 +09002543static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002545 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002546
Linus Torvalds1da177e2005-04-16 15:20:36 -07002547 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -07002548 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2549 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002550 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07002551 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002552 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002553 dev_printk(KERN_ERR, &pdev->dev,
2554 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002555 return rc;
2556 }
2557 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002558 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07002559 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002560 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002561 dev_printk(KERN_ERR, &pdev->dev,
2562 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002563 return rc;
2564 }
Yang Hongyang284901a2009-04-06 19:01:15 -07002565 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002566 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002567 dev_printk(KERN_ERR, &pdev->dev,
2568 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002569 return rc;
2570 }
2571 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002572 return 0;
2573}
2574
Tejun Heo4447d352007-04-17 23:44:08 +09002575static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002576{
Tejun Heo4447d352007-04-17 23:44:08 +09002577 struct ahci_host_priv *hpriv = host->private_data;
2578 struct pci_dev *pdev = to_pci_dev(host->dev);
2579 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Robert Hancock4c521c82009-09-20 17:02:31 -06002580 u32 vers, cap, cap2, impl, speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002581 const char *speed_s;
2582 u16 cc;
2583 const char *scc_s;
2584
2585 vers = readl(mmio + HOST_VERSION);
2586 cap = hpriv->cap;
Robert Hancock4c521c82009-09-20 17:02:31 -06002587 cap2 = hpriv->cap2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588 impl = hpriv->port_map;
2589
2590 speed = (cap >> 20) & 0xf;
2591 if (speed == 1)
2592 speed_s = "1.5";
2593 else if (speed == 2)
2594 speed_s = "3";
Shane Huang8522ee22008-12-30 11:00:37 +08002595 else if (speed == 3)
2596 speed_s = "6";
Linus Torvalds1da177e2005-04-16 15:20:36 -07002597 else
2598 speed_s = "?";
2599
2600 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002601 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002602 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002603 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002604 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002605 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002606 scc_s = "RAID";
2607 else
2608 scc_s = "unknown";
2609
Jeff Garzika9524a72005-10-30 14:39:11 -05002610 dev_printk(KERN_INFO, &pdev->dev,
2611 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002612 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002613 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002614
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002615 (vers >> 24) & 0xff,
2616 (vers >> 16) & 0xff,
2617 (vers >> 8) & 0xff,
2618 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002619
2620 ((cap >> 8) & 0x1f) + 1,
2621 (cap & 0x1f) + 1,
2622 speed_s,
2623 impl,
2624 scc_s);
2625
Jeff Garzika9524a72005-10-30 14:39:11 -05002626 dev_printk(KERN_INFO, &pdev->dev,
2627 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002628 "%s%s%s%s%s%s%s"
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002629 "%s%s%s%s%s%s%s"
Robert Hancock4c521c82009-09-20 17:02:31 -06002630 "%s%s%s%s%s%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002631 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002632
Robert Hancock4c521c82009-09-20 17:02:31 -06002633 cap & HOST_CAP_64 ? "64bit " : "",
2634 cap & HOST_CAP_NCQ ? "ncq " : "",
2635 cap & HOST_CAP_SNTF ? "sntf " : "",
2636 cap & HOST_CAP_MPS ? "ilck " : "",
2637 cap & HOST_CAP_SSS ? "stag " : "",
2638 cap & HOST_CAP_ALPM ? "pm " : "",
2639 cap & HOST_CAP_LED ? "led " : "",
2640 cap & HOST_CAP_CLO ? "clo " : "",
2641 cap & HOST_CAP_ONLY ? "only " : "",
2642 cap & HOST_CAP_PMP ? "pmp " : "",
2643 cap & HOST_CAP_FBS ? "fbs " : "",
2644 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2645 cap & HOST_CAP_SSC ? "slum " : "",
2646 cap & HOST_CAP_PART ? "part " : "",
2647 cap & HOST_CAP_CCC ? "ccc " : "",
2648 cap & HOST_CAP_EMS ? "ems " : "",
2649 cap & HOST_CAP_SXS ? "sxs " : "",
2650 cap2 & HOST_CAP2_APST ? "apst " : "",
2651 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2652 cap2 & HOST_CAP2_BOH ? "boh " : ""
Linus Torvalds1da177e2005-04-16 15:20:36 -07002653 );
2654}
2655
Tejun Heoedc93052007-10-25 14:59:16 +09002656/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2657 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2658 * support PMP and the 4726 either directly exports the device
2659 * attached to the first downstream port or acts as a hardware storage
2660 * controller and emulate a single ATA device (can be RAID 0/1 or some
2661 * other configuration).
2662 *
2663 * When there's no device attached to the first downstream port of the
2664 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2665 * configure the 4726. However, ATA emulation of the device is very
2666 * lame. It doesn't send signature D2H Reg FIS after the initial
2667 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2668 *
2669 * The following function works around the problem by always using
2670 * hardreset on the port and not depending on receiving signature FIS
2671 * afterward. If signature FIS isn't received soon, ATA class is
2672 * assumed without follow-up softreset.
2673 */
2674static void ahci_p5wdh_workaround(struct ata_host *host)
2675{
2676 static struct dmi_system_id sysids[] = {
2677 {
2678 .ident = "P5W DH Deluxe",
2679 .matches = {
2680 DMI_MATCH(DMI_SYS_VENDOR,
2681 "ASUSTEK COMPUTER INC"),
2682 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2683 },
2684 },
2685 { }
2686 };
2687 struct pci_dev *pdev = to_pci_dev(host->dev);
2688
2689 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2690 dmi_check_system(sysids)) {
2691 struct ata_port *ap = host->ports[1];
2692
2693 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2694 "Deluxe on-board SIMG4726 workaround\n");
2695
2696 ap->ops = &ahci_p5wdh_ops;
2697 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2698 }
2699}
2700
Tejun Heo2fcad9d2009-10-03 18:27:29 +09002701/* only some SB600 ahci controllers can do 64bit DMA */
2702static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +08002703{
2704 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +09002705 /*
2706 * The oldest version known to be broken is 0901 and
2707 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +09002708 * Enable 64bit DMA on 1501 and anything newer.
2709 *
Tejun Heo03d783b2009-08-16 21:04:02 +09002710 * Please read bko#9412 for more info.
2711 */
Shane Huang58a09b32009-05-27 15:04:43 +08002712 {
2713 .ident = "ASUS M2A-VM",
2714 .matches = {
2715 DMI_MATCH(DMI_BOARD_VENDOR,
2716 "ASUSTeK Computer INC."),
2717 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2718 },
Tejun Heo03d783b2009-08-16 21:04:02 +09002719 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +08002720 },
Mark Nelsone65cc192009-11-03 20:06:48 +11002721 /*
2722 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
2723 * support 64bit DMA.
2724 *
2725 * BIOS versions earlier than 1.5 had the Manufacturer DMI
2726 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
2727 * This spelling mistake was fixed in BIOS version 1.5, so
2728 * 1.5 and later have the Manufacturer as
2729 * "MICRO-STAR INTERNATIONAL CO.,LTD".
2730 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
2731 *
2732 * BIOS versions earlier than 1.9 had a Board Product Name
2733 * DMI field of "MS-7376". This was changed to be
2734 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
2735 * match on DMI_BOARD_NAME of "MS-7376".
2736 */
2737 {
2738 .ident = "MSI K9A2 Platinum",
2739 .matches = {
2740 DMI_MATCH(DMI_BOARD_VENDOR,
2741 "MICRO-STAR INTER"),
2742 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
2743 },
2744 },
Shane Huang58a09b32009-05-27 15:04:43 +08002745 { }
2746 };
Tejun Heo03d783b2009-08-16 21:04:02 +09002747 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +09002748 int year, month, date;
2749 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +08002750
Tejun Heo03d783b2009-08-16 21:04:02 +09002751 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +08002752 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +09002753 !match)
Shane Huang58a09b32009-05-27 15:04:43 +08002754 return false;
2755
Mark Nelsone65cc192009-11-03 20:06:48 +11002756 if (!match->driver_data)
2757 goto enable_64bit;
2758
Tejun Heo2fcad9d2009-10-03 18:27:29 +09002759 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2760 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +08002761
Mark Nelsone65cc192009-11-03 20:06:48 +11002762 if (strcmp(buf, match->driver_data) >= 0)
2763 goto enable_64bit;
2764 else {
Tejun Heo03d783b2009-08-16 21:04:02 +09002765 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
2766 "forcing 32bit DMA, update BIOS\n", match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +09002767 return false;
2768 }
Mark Nelsone65cc192009-11-03 20:06:48 +11002769
2770enable_64bit:
2771 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
2772 match->ident);
2773 return true;
Shane Huang58a09b32009-05-27 15:04:43 +08002774}
2775
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002776static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2777{
2778 static const struct dmi_system_id broken_systems[] = {
2779 {
2780 .ident = "HP Compaq nx6310",
2781 .matches = {
2782 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2783 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2784 },
2785 /* PCI slot number of the controller */
2786 .driver_data = (void *)0x1FUL,
2787 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +01002788 {
2789 .ident = "HP Compaq 6720s",
2790 .matches = {
2791 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2792 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2793 },
2794 /* PCI slot number of the controller */
2795 .driver_data = (void *)0x1FUL,
2796 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002797
2798 { } /* terminate list */
2799 };
2800 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2801
2802 if (dmi) {
2803 unsigned long slot = (unsigned long)dmi->driver_data;
2804 /* apply the quirk only to on-board controllers */
2805 return slot == PCI_SLOT(pdev->devfn);
2806 }
2807
2808 return false;
2809}
2810
Tejun Heo9b10ae82009-05-30 20:50:12 +09002811static bool ahci_broken_suspend(struct pci_dev *pdev)
2812{
2813 static const struct dmi_system_id sysids[] = {
2814 /*
2815 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2816 * to the harddisk doesn't become online after
2817 * resuming from STR. Warn and fail suspend.
2818 */
2819 {
2820 .ident = "dv4",
2821 .matches = {
2822 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2823 DMI_MATCH(DMI_PRODUCT_NAME,
2824 "HP Pavilion dv4 Notebook PC"),
2825 },
2826 .driver_data = "F.30", /* cutoff BIOS version */
2827 },
2828 {
2829 .ident = "dv5",
2830 .matches = {
2831 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2832 DMI_MATCH(DMI_PRODUCT_NAME,
2833 "HP Pavilion dv5 Notebook PC"),
2834 },
2835 .driver_data = "F.16", /* cutoff BIOS version */
2836 },
2837 {
2838 .ident = "dv6",
2839 .matches = {
2840 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2841 DMI_MATCH(DMI_PRODUCT_NAME,
2842 "HP Pavilion dv6 Notebook PC"),
2843 },
2844 .driver_data = "F.21", /* cutoff BIOS version */
2845 },
2846 {
2847 .ident = "HDX18",
2848 .matches = {
2849 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2850 DMI_MATCH(DMI_PRODUCT_NAME,
2851 "HP HDX18 Notebook PC"),
2852 },
2853 .driver_data = "F.23", /* cutoff BIOS version */
2854 },
2855 { } /* terminate list */
2856 };
2857 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2858 const char *ver;
2859
2860 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2861 return false;
2862
2863 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2864
2865 return !ver || strcmp(ver, dmi->driver_data) < 0;
2866}
2867
Tejun Heo55946392009-08-04 14:30:08 +09002868static bool ahci_broken_online(struct pci_dev *pdev)
2869{
2870#define ENCODE_BUSDEVFN(bus, slot, func) \
2871 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2872 static const struct dmi_system_id sysids[] = {
2873 /*
2874 * There are several gigabyte boards which use
2875 * SIMG5723s configured as hardware RAID. Certain
2876 * 5723 firmware revisions shipped there keep the link
2877 * online but fail to answer properly to SRST or
2878 * IDENTIFY when no device is attached downstream
2879 * causing libata to retry quite a few times leading
2880 * to excessive detection delay.
2881 *
2882 * As these firmwares respond to the second reset try
2883 * with invalid device signature, considering unknown
2884 * sig as offline works around the problem acceptably.
2885 */
2886 {
2887 .ident = "EP45-DQ6",
2888 .matches = {
2889 DMI_MATCH(DMI_BOARD_VENDOR,
2890 "Gigabyte Technology Co., Ltd."),
2891 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2892 },
2893 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2894 },
2895 {
2896 .ident = "EP45-DS5",
2897 .matches = {
2898 DMI_MATCH(DMI_BOARD_VENDOR,
2899 "Gigabyte Technology Co., Ltd."),
2900 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2901 },
2902 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2903 },
2904 { } /* terminate list */
2905 };
2906#undef ENCODE_BUSDEVFN
2907 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2908 unsigned int val;
2909
2910 if (!dmi)
2911 return false;
2912
2913 val = (unsigned long)dmi->driver_data;
2914
2915 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2916}
2917
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02002918#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +09002919static void ahci_gtf_filter_workaround(struct ata_host *host)
2920{
2921 static const struct dmi_system_id sysids[] = {
2922 /*
2923 * Aspire 3810T issues a bunch of SATA enable commands
2924 * via _GTF including an invalid one and one which is
2925 * rejected by the device. Among the successful ones
2926 * is FPDMA non-zero offset enable which when enabled
2927 * only on the drive side leads to NCQ command
2928 * failures. Filter it out.
2929 */
2930 {
2931 .ident = "Aspire 3810T",
2932 .matches = {
2933 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
2934 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
2935 },
2936 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
2937 },
2938 { }
2939 };
2940 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2941 unsigned int filter;
2942 int i;
2943
2944 if (!dmi)
2945 return;
2946
2947 filter = (unsigned long)dmi->driver_data;
2948 dev_printk(KERN_INFO, host->dev,
2949 "applying extra ACPI _GTF filter 0x%x for %s\n",
2950 filter, dmi->ident);
2951
2952 for (i = 0; i < host->n_ports; i++) {
2953 struct ata_port *ap = host->ports[i];
2954 struct ata_link *link;
2955 struct ata_device *dev;
2956
2957 ata_for_each_link(link, ap, EDGE)
2958 ata_for_each_dev(dev, link, ALL)
2959 dev->gtf_filter |= filter;
2960 }
2961}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02002962#else
2963static inline void ahci_gtf_filter_workaround(struct ata_host *host)
2964{}
2965#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09002966
Tejun Heo24dc5f32007-01-20 16:00:28 +09002967static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002968{
2969 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09002970 unsigned int board_id = ent->driver_data;
2971 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09002972 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002973 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002974 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002975 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002976 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002977
2978 VPRINTK("ENTER\n");
2979
Tejun Heo12fad3f2006-05-15 21:03:55 +09002980 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2981
Linus Torvalds1da177e2005-04-16 15:20:36 -07002982 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002983 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002984
Alan Cox5b66c822008-09-03 14:48:34 +01002985 /* The AHCI driver can only drive the SATA ports, the PATA driver
2986 can drive them all so if both drivers are selected make sure
2987 AHCI stays out of the way */
2988 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2989 return -ENODEV;
2990
Tejun Heo4447d352007-04-17 23:44:08 +09002991 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002992 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002993 if (rc)
2994 return rc;
2995
Tejun Heodea55132008-03-11 19:52:31 +09002996 /* AHCI controllers often implement SFF compatible interface.
2997 * Grab all PCI BARs just in case.
2998 */
2999 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09003000 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09003001 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09003002 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09003003 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003004
Tejun Heoc4f77922007-12-06 15:09:43 +09003005 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
3006 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
3007 u8 map;
3008
3009 /* ICH6s share the same PCI ID for both piix and ahci
3010 * modes. Enabling ahci mode while MAP indicates
3011 * combined mode is a bad idea. Yield to ata_piix.
3012 */
3013 pci_read_config_byte(pdev, ICH_MAP, &map);
3014 if (map & 0x3) {
3015 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
3016 "combined mode, can't enable AHCI mode\n");
3017 return -ENODEV;
3018 }
3019 }
3020
Tejun Heo24dc5f32007-01-20 16:00:28 +09003021 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
3022 if (!hpriv)
3023 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09003024 hpriv->flags |= (unsigned long)pi.private_data;
3025
Tejun Heoe297d992008-06-10 00:13:04 +09003026 /* MCP65 revision A1 and A2 can't do MSI */
3027 if (board_id == board_ahci_mcp65 &&
3028 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
3029 hpriv->flags |= AHCI_HFLAG_NO_MSI;
3030
Shane Huange427fe02008-12-30 10:53:41 +08003031 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
3032 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
3033 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
3034
Tejun Heo2fcad9d2009-10-03 18:27:29 +09003035 /* only some SB600s can do 64bit DMA */
3036 if (ahci_sb600_enable_64bit(pdev))
3037 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08003038
Tejun Heo31b239a2009-09-17 00:34:39 +09003039 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
3040 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003041
Tejun Heo4447d352007-04-17 23:44:08 +09003042 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09003043 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003044
Tejun Heo4447d352007-04-17 23:44:08 +09003045 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09003046 if (hpriv->cap & HOST_CAP_NCQ)
Shaohua Li388539f2009-07-27 09:24:35 +08003047 pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
Tejun Heo4447d352007-04-17 23:44:08 +09003048
Tejun Heo7d50b602007-09-23 13:19:54 +09003049 if (hpriv->cap & HOST_CAP_PMP)
3050 pi.flags |= ATA_FLAG_PMP;
3051
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07003052 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
3053 u8 messages;
3054 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
3055 u32 em_loc = readl(mmio + HOST_EM_LOC);
3056 u32 em_ctl = readl(mmio + HOST_EM_CTL);
3057
David Milburn87943ac2008-10-13 14:38:36 -05003058 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07003059
3060 /* we only support LED message type right now */
3061 if ((messages & 0x01) && (ahci_em_messages == 1)) {
3062 /* store em_loc */
3063 hpriv->em_loc = ((em_loc >> 16) * 4);
3064 pi.flags |= ATA_FLAG_EM;
3065 if (!(em_ctl & EM_CTL_ALHD))
3066 pi.flags |= ATA_FLAG_SW_ACTIVITY;
3067 }
3068 }
3069
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01003070 if (ahci_broken_system_poweroff(pdev)) {
3071 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
3072 dev_info(&pdev->dev,
3073 "quirky BIOS, skipping spindown on poweroff\n");
3074 }
3075
Tejun Heo9b10ae82009-05-30 20:50:12 +09003076 if (ahci_broken_suspend(pdev)) {
3077 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
3078 dev_printk(KERN_WARNING, &pdev->dev,
3079 "BIOS update required for suspend/resume\n");
3080 }
3081
Tejun Heo55946392009-08-04 14:30:08 +09003082 if (ahci_broken_online(pdev)) {
3083 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
3084 dev_info(&pdev->dev,
3085 "online status unreliable, applying workaround\n");
3086 }
3087
Tejun Heo837f5f82008-02-06 15:13:51 +09003088 /* CAP.NP sometimes indicate the index of the last enabled
3089 * port, at other times, that of the last possible port, so
3090 * determining the maximum port number requires looking at
3091 * both CAP.NP and port_map.
3092 */
3093 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
3094
3095 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09003096 if (!host)
3097 return -ENOMEM;
3098 host->iomap = pcim_iomap_table(pdev);
3099 host->private_data = hpriv;
3100
Arjan van de Venf3d7f232009-01-26 02:05:44 -08003101 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08003102 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08003103 else
3104 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08003105
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07003106 if (pi.flags & ATA_FLAG_EM)
3107 ahci_reset_em(host);
3108
Tejun Heo4447d352007-04-17 23:44:08 +09003109 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04003110 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09003111
Tejun Heocbcdd872007-08-18 13:14:55 +09003112 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3113 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3114 0x100 + ap->port_no * 0x80, "port");
3115
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04003116 /* set initial link pm policy */
3117 ap->pm_policy = NOT_AVAILABLE;
3118
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07003119 /* set enclosure management message type */
3120 if (ap->flags & ATA_FLAG_EM)
3121 ap->em_message_type = ahci_em_messages;
3122
3123
Jeff Garzikdab632e2007-05-28 08:33:01 -04003124 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09003125 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04003126 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09003127 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003128
Tejun Heoedc93052007-10-25 14:59:16 +09003129 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3130 ahci_p5wdh_workaround(host);
3131
Tejun Heof80ae7e2009-09-16 04:18:03 +09003132 /* apply gtf filter quirk */
3133 ahci_gtf_filter_workaround(host);
3134
Linus Torvalds1da177e2005-04-16 15:20:36 -07003135 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09003136 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003137 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09003138 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003139
Tejun Heo4447d352007-04-17 23:44:08 +09003140 rc = ahci_reset_controller(host);
3141 if (rc)
3142 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09003143
Tejun Heo4447d352007-04-17 23:44:08 +09003144 ahci_init_controller(host);
3145 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003146
Tejun Heo4447d352007-04-17 23:44:08 +09003147 pci_set_master(pdev);
3148 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3149 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04003150}
Linus Torvalds1da177e2005-04-16 15:20:36 -07003151
3152static int __init ahci_init(void)
3153{
Pavel Roskinb7887192006-08-10 18:13:18 +09003154 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003155}
3156
Linus Torvalds1da177e2005-04-16 15:20:36 -07003157static void __exit ahci_exit(void)
3158{
3159 pci_unregister_driver(&ahci_pci_driver);
3160}
3161
3162
3163MODULE_AUTHOR("Jeff Garzik");
3164MODULE_DESCRIPTION("AHCI SATA low-level driver");
3165MODULE_LICENSE("GPL");
3166MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04003167MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003168
3169module_init(ahci_init);
3170module_exit(ahci_exit);