blob: 29ab75903ec143a42446adff7d75741521d0eb23 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 * Kevin E. Martin <martin@xfree86.org>
32 * Rickard E. Faith <faith@valinux.com>
33 * Alan Hourihane <alanh@fairlite.demon.co.uk>
34 *
35 * References:
36 *
37 * !!!! FIXME !!!!
38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
40 * 1999.
41 *
42 * !!!! FIXME !!!!
43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N
44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
45 *
46 */
47
48/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
51#ifndef _RADEON_REG_H_
52#define _RADEON_REG_H_
53
54#include "r300_reg.h"
55#include "r500_reg.h"
56#include "r600_reg.h"
57
58
59#define RADEON_MC_AGP_LOCATION 0x014c
60#define RADEON_MC_AGP_START_MASK 0x0000FFFF
61#define RADEON_MC_AGP_START_SHIFT 0
62#define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
63#define RADEON_MC_AGP_TOP_SHIFT 16
64#define RADEON_MC_FB_LOCATION 0x0148
65#define RADEON_MC_FB_START_MASK 0x0000FFFF
66#define RADEON_MC_FB_START_SHIFT 0
67#define RADEON_MC_FB_TOP_MASK 0xFFFF0000
68#define RADEON_MC_FB_TOP_SHIFT 16
69#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
70#define RADEON_AGP_BASE 0x0170
71
72#define ATI_DATATYPE_VQ 0
73#define ATI_DATATYPE_CI4 1
74#define ATI_DATATYPE_CI8 2
75#define ATI_DATATYPE_ARGB1555 3
76#define ATI_DATATYPE_RGB565 4
77#define ATI_DATATYPE_RGB888 5
78#define ATI_DATATYPE_ARGB8888 6
79#define ATI_DATATYPE_RGB332 7
80#define ATI_DATATYPE_Y8 8
81#define ATI_DATATYPE_RGB8 9
82#define ATI_DATATYPE_CI16 10
83#define ATI_DATATYPE_VYUY_422 11
84#define ATI_DATATYPE_YVYU_422 12
85#define ATI_DATATYPE_AYUV_444 14
86#define ATI_DATATYPE_ARGB4444 15
87
88 /* Registers for 2D/Video/Overlay */
89#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
90#define RADEON_AGP_BASE 0x0170
91#define RADEON_AGP_CNTL 0x0174
92# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
93# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
94# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
95# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
96# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
97# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
98# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
99# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
100#define RADEON_STATUS_PCI_CONFIG 0x06
101# define RADEON_CAP_LIST 0x100000
102#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
103# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
104# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
105# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
106# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
107#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
108#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
109# define RADEON_AGP_ENABLE (1<<8)
110#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
111#define RADEON_AGP_STATUS 0x0f5c /* PCI */
112# define RADEON_AGP_1X_MODE 0x01
113# define RADEON_AGP_2X_MODE 0x02
114# define RADEON_AGP_4X_MODE 0x04
115# define RADEON_AGP_FW_MODE 0x10
116# define RADEON_AGP_MODE_MASK 0x17
117# define RADEON_AGPv3_MODE 0x08
118# define RADEON_AGPv3_4X_MODE 0x01
119# define RADEON_AGPv3_8X_MODE 0x02
120#define RADEON_ATTRDR 0x03c1 /* VGA */
121#define RADEON_ATTRDW 0x03c0 /* VGA */
122#define RADEON_ATTRX 0x03c0 /* VGA */
123#define RADEON_AUX_SC_CNTL 0x1660
124# define RADEON_AUX1_SC_EN (1 << 0)
125# define RADEON_AUX1_SC_MODE_OR (0 << 1)
126# define RADEON_AUX1_SC_MODE_NAND (1 << 1)
127# define RADEON_AUX2_SC_EN (1 << 2)
128# define RADEON_AUX2_SC_MODE_OR (0 << 3)
129# define RADEON_AUX2_SC_MODE_NAND (1 << 3)
130# define RADEON_AUX3_SC_EN (1 << 4)
131# define RADEON_AUX3_SC_MODE_OR (0 << 5)
132# define RADEON_AUX3_SC_MODE_NAND (1 << 5)
133#define RADEON_AUX1_SC_BOTTOM 0x1670
134#define RADEON_AUX1_SC_LEFT 0x1664
135#define RADEON_AUX1_SC_RIGHT 0x1668
136#define RADEON_AUX1_SC_TOP 0x166c
137#define RADEON_AUX2_SC_BOTTOM 0x1680
138#define RADEON_AUX2_SC_LEFT 0x1674
139#define RADEON_AUX2_SC_RIGHT 0x1678
140#define RADEON_AUX2_SC_TOP 0x167c
141#define RADEON_AUX3_SC_BOTTOM 0x1690
142#define RADEON_AUX3_SC_LEFT 0x1684
143#define RADEON_AUX3_SC_RIGHT 0x1688
144#define RADEON_AUX3_SC_TOP 0x168c
145#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
146#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
147
148#define RADEON_BASE_CODE 0x0f0b
149#define RADEON_BIOS_0_SCRATCH 0x0010
150# define RADEON_FP_PANEL_SCALABLE (1 << 16)
151# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
152# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
153# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
154# define RADEON_DISPLAY_ROT_MASK (3 << 28)
155# define RADEON_DISPLAY_ROT_00 (0 << 28)
156# define RADEON_DISPLAY_ROT_90 (1 << 28)
157# define RADEON_DISPLAY_ROT_180 (2 << 28)
158# define RADEON_DISPLAY_ROT_270 (3 << 28)
159#define RADEON_BIOS_1_SCRATCH 0x0014
160#define RADEON_BIOS_2_SCRATCH 0x0018
161#define RADEON_BIOS_3_SCRATCH 0x001c
162#define RADEON_BIOS_4_SCRATCH 0x0020
163# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
164# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
165# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
166# define RADEON_LCD1_ATTACHED (1 << 2)
167# define RADEON_DFP1_ATTACHED (1 << 3)
168# define RADEON_TV1_ATTACHED_MASK (3 << 4)
169# define RADEON_TV1_ATTACHED_COMP (1 << 4)
170# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
171# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
172# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
173# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
174# define RADEON_DFP2_ATTACHED (1 << 11)
175#define RADEON_BIOS_5_SCRATCH 0x0024
176# define RADEON_LCD1_ON (1 << 0)
177# define RADEON_CRT1_ON (1 << 1)
178# define RADEON_TV1_ON (1 << 2)
179# define RADEON_DFP1_ON (1 << 3)
180# define RADEON_CRT2_ON (1 << 5)
181# define RADEON_CV1_ON (1 << 6)
182# define RADEON_DFP2_ON (1 << 7)
183# define RADEON_LCD1_CRTC_MASK (1 << 8)
184# define RADEON_LCD1_CRTC_SHIFT 8
185# define RADEON_CRT1_CRTC_MASK (1 << 9)
186# define RADEON_CRT1_CRTC_SHIFT 9
187# define RADEON_TV1_CRTC_MASK (1 << 10)
188# define RADEON_TV1_CRTC_SHIFT 10
189# define RADEON_DFP1_CRTC_MASK (1 << 11)
190# define RADEON_DFP1_CRTC_SHIFT 11
191# define RADEON_CRT2_CRTC_MASK (1 << 12)
192# define RADEON_CRT2_CRTC_SHIFT 12
193# define RADEON_CV1_CRTC_MASK (1 << 13)
194# define RADEON_CV1_CRTC_SHIFT 13
195# define RADEON_DFP2_CRTC_MASK (1 << 14)
196# define RADEON_DFP2_CRTC_SHIFT 14
197# define RADEON_ACC_REQ_LCD1 (1 << 16)
198# define RADEON_ACC_REQ_CRT1 (1 << 17)
199# define RADEON_ACC_REQ_TV1 (1 << 18)
200# define RADEON_ACC_REQ_DFP1 (1 << 19)
201# define RADEON_ACC_REQ_CRT2 (1 << 21)
202# define RADEON_ACC_REQ_TV2 (1 << 22)
203# define RADEON_ACC_REQ_DFP2 (1 << 23)
204#define RADEON_BIOS_6_SCRATCH 0x0028
205# define RADEON_ACC_MODE_CHANGE (1 << 2)
206# define RADEON_EXT_DESKTOP_MODE (1 << 3)
207# define RADEON_LCD_DPMS_ON (1 << 20)
208# define RADEON_CRT_DPMS_ON (1 << 21)
209# define RADEON_TV_DPMS_ON (1 << 22)
210# define RADEON_DFP_DPMS_ON (1 << 23)
211# define RADEON_DPMS_MASK (3 << 24)
212# define RADEON_DPMS_ON (0 << 24)
213# define RADEON_DPMS_STANDBY (1 << 24)
214# define RADEON_DPMS_SUSPEND (2 << 24)
215# define RADEON_DPMS_OFF (3 << 24)
216# define RADEON_SCREEN_BLANKING (1 << 26)
217# define RADEON_DRIVER_CRITICAL (1 << 27)
218# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
219#define RADEON_BIOS_7_SCRATCH 0x002c
220# define RADEON_SYS_HOTKEY (1 << 10)
221# define RADEON_DRV_LOADED (1 << 12)
222#define RADEON_BIOS_ROM 0x0f30 /* PCI */
223#define RADEON_BIST 0x0f0f /* PCI */
224#define RADEON_BRUSH_DATA0 0x1480
225#define RADEON_BRUSH_DATA1 0x1484
226#define RADEON_BRUSH_DATA10 0x14a8
227#define RADEON_BRUSH_DATA11 0x14ac
228#define RADEON_BRUSH_DATA12 0x14b0
229#define RADEON_BRUSH_DATA13 0x14b4
230#define RADEON_BRUSH_DATA14 0x14b8
231#define RADEON_BRUSH_DATA15 0x14bc
232#define RADEON_BRUSH_DATA16 0x14c0
233#define RADEON_BRUSH_DATA17 0x14c4
234#define RADEON_BRUSH_DATA18 0x14c8
235#define RADEON_BRUSH_DATA19 0x14cc
236#define RADEON_BRUSH_DATA2 0x1488
237#define RADEON_BRUSH_DATA20 0x14d0
238#define RADEON_BRUSH_DATA21 0x14d4
239#define RADEON_BRUSH_DATA22 0x14d8
240#define RADEON_BRUSH_DATA23 0x14dc
241#define RADEON_BRUSH_DATA24 0x14e0
242#define RADEON_BRUSH_DATA25 0x14e4
243#define RADEON_BRUSH_DATA26 0x14e8
244#define RADEON_BRUSH_DATA27 0x14ec
245#define RADEON_BRUSH_DATA28 0x14f0
246#define RADEON_BRUSH_DATA29 0x14f4
247#define RADEON_BRUSH_DATA3 0x148c
248#define RADEON_BRUSH_DATA30 0x14f8
249#define RADEON_BRUSH_DATA31 0x14fc
250#define RADEON_BRUSH_DATA32 0x1500
251#define RADEON_BRUSH_DATA33 0x1504
252#define RADEON_BRUSH_DATA34 0x1508
253#define RADEON_BRUSH_DATA35 0x150c
254#define RADEON_BRUSH_DATA36 0x1510
255#define RADEON_BRUSH_DATA37 0x1514
256#define RADEON_BRUSH_DATA38 0x1518
257#define RADEON_BRUSH_DATA39 0x151c
258#define RADEON_BRUSH_DATA4 0x1490
259#define RADEON_BRUSH_DATA40 0x1520
260#define RADEON_BRUSH_DATA41 0x1524
261#define RADEON_BRUSH_DATA42 0x1528
262#define RADEON_BRUSH_DATA43 0x152c
263#define RADEON_BRUSH_DATA44 0x1530
264#define RADEON_BRUSH_DATA45 0x1534
265#define RADEON_BRUSH_DATA46 0x1538
266#define RADEON_BRUSH_DATA47 0x153c
267#define RADEON_BRUSH_DATA48 0x1540
268#define RADEON_BRUSH_DATA49 0x1544
269#define RADEON_BRUSH_DATA5 0x1494
270#define RADEON_BRUSH_DATA50 0x1548
271#define RADEON_BRUSH_DATA51 0x154c
272#define RADEON_BRUSH_DATA52 0x1550
273#define RADEON_BRUSH_DATA53 0x1554
274#define RADEON_BRUSH_DATA54 0x1558
275#define RADEON_BRUSH_DATA55 0x155c
276#define RADEON_BRUSH_DATA56 0x1560
277#define RADEON_BRUSH_DATA57 0x1564
278#define RADEON_BRUSH_DATA58 0x1568
279#define RADEON_BRUSH_DATA59 0x156c
280#define RADEON_BRUSH_DATA6 0x1498
281#define RADEON_BRUSH_DATA60 0x1570
282#define RADEON_BRUSH_DATA61 0x1574
283#define RADEON_BRUSH_DATA62 0x1578
284#define RADEON_BRUSH_DATA63 0x157c
285#define RADEON_BRUSH_DATA7 0x149c
286#define RADEON_BRUSH_DATA8 0x14a0
287#define RADEON_BRUSH_DATA9 0x14a4
288#define RADEON_BRUSH_SCALE 0x1470
289#define RADEON_BRUSH_Y_X 0x1474
290#define RADEON_BUS_CNTL 0x0030
291# define RADEON_BUS_MASTER_DIS (1 << 6)
292# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
Alex Deucher3e5cb982009-10-16 12:21:24 -0400293# define RS600_BUS_MASTER_DIS (1 << 14)
294# define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
296# define RADEON_BUS_RD_ABORT_EN (1 << 25)
297# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
298# define RADEON_BUS_WRT_BURST (1 << 29)
299# define RADEON_BUS_READ_BURST (1 << 30)
300#define RADEON_BUS_CNTL1 0x0034
301# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
Alex Deucher3e5cb982009-10-16 12:21:24 -0400302/* rv370/rv380, rv410, r423/r430/r480, r5xx */
303#define RADEON_MSI_REARM_EN 0x0160
304# define RV370_MSI_REARM_EN (1 << 0)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200305
306/* #define RADEON_PCIE_INDEX 0x0030 */
307/* #define RADEON_PCIE_DATA 0x0034 */
308#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
309# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
310# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
311# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
312# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
313# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
314# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
315# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
316# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
317# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
318# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
319# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
320# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
321# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
322# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
323
324#define RADEON_CACHE_CNTL 0x1724
325#define RADEON_CACHE_LINE 0x0f0c /* PCI */
326#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
327#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
328#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
329# define RADEON_DONT_USE_XTALIN (1 << 4)
330# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
331#define RADEON_CLOCK_CNTL_DATA 0x000c
332#define RADEON_CLOCK_CNTL_INDEX 0x0008
333# define RADEON_PLL_WR_EN (1 << 7)
334# define RADEON_PLL_DIV_SEL (3 << 8)
335# define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))
336#define RADEON_CLK_PWRMGT_CNTL 0x0014
337# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
338# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
339# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
340# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
341# define RADEON_MC_BUSY (1 << 16)
342# define RADEON_DLL_READY (1 << 19)
343# define RADEON_CG_NO1_DEBUG_0 (1 << 24)
344# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
345# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
346# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
347# define RADEON_TVCLK_TURNOFF (1 << 31)
348#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
349# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
350#define RADEON_CLR_CMP_CLR_3D 0x1a24
351#define RADEON_CLR_CMP_CLR_DST 0x15c8
352#define RADEON_CLR_CMP_CLR_SRC 0x15c4
353#define RADEON_CLR_CMP_CNTL 0x15c0
354# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
355# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
356# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
357#define RADEON_CLR_CMP_MASK 0x15cc
358# define RADEON_CLR_CMP_MSK 0xffffffff
359#define RADEON_CLR_CMP_MASK_3D 0x1A28
360#define RADEON_COMMAND 0x0f04 /* PCI */
361#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
362#define RADEON_CONFIG_APER_0_BASE 0x0100
363#define RADEON_CONFIG_APER_1_BASE 0x0104
364#define RADEON_CONFIG_APER_SIZE 0x0108
365#define RADEON_CONFIG_BONDS 0x00e8
366#define RADEON_CONFIG_CNTL 0x00e0
367# define RADEON_CFG_ATI_REV_A11 (0 << 16)
368# define RADEON_CFG_ATI_REV_A12 (1 << 16)
369# define RADEON_CFG_ATI_REV_A13 (2 << 16)
370# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
371#define RADEON_CONFIG_MEMSIZE 0x00f8
372#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
373#define RADEON_CONFIG_REG_1_BASE 0x010c
374#define RADEON_CONFIG_REG_APER_SIZE 0x0110
375#define RADEON_CONFIG_XSTRAP 0x00e4
376#define RADEON_CONSTANT_COLOR_C 0x1d34
377# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
378# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
379# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
380#define RADEON_CRC_CMDFIFO_ADDR 0x0740
381#define RADEON_CRC_CMDFIFO_DOUT 0x0744
382#define RADEON_GRPH_BUFFER_CNTL 0x02f0
383# define RADEON_GRPH_START_REQ_MASK (0x7f)
384# define RADEON_GRPH_START_REQ_SHIFT 0
385# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
386# define RADEON_GRPH_STOP_REQ_SHIFT 8
387# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
388# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
389# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
390# define RADEON_GRPH_BUFFER_SIZE (1<<29)
391# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
392# define RADEON_GRPH_STOP_CNTL (1<<31)
393#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
394# define RADEON_GRPH2_START_REQ_MASK (0x7f)
395# define RADEON_GRPH2_START_REQ_SHIFT 0
396# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
397# define RADEON_GRPH2_STOP_REQ_SHIFT 8
398# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
399# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
400# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
401# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
402# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
403# define RADEON_GRPH2_STOP_CNTL (1<<31)
404#define RADEON_CRTC_CRNT_FRAME 0x0214
405#define RADEON_CRTC_EXT_CNTL 0x0054
406# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
407# define RADEON_VGA_ATI_LINEAR (1 << 3)
408# define RADEON_XCRT_CNT_EN (1 << 6)
409# define RADEON_CRTC_HSYNC_DIS (1 << 8)
410# define RADEON_CRTC_VSYNC_DIS (1 << 9)
411# define RADEON_CRTC_DISPLAY_DIS (1 << 10)
412# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
413# define RADEON_CRTC_CRT_ON (1 << 15)
414#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
415# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
416# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
417# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
418#define RADEON_CRTC_GEN_CNTL 0x0050
419# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
420# define RADEON_CRTC_INTERLACE_EN (1 << 1)
421# define RADEON_CRTC_CSYNC_EN (1 << 4)
422# define RADEON_CRTC_ICON_EN (1 << 15)
423# define RADEON_CRTC_CUR_EN (1 << 16)
424# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
425# define RADEON_CRTC_CUR_MODE_SHIFT 20
426# define RADEON_CRTC_CUR_MODE_MONO 0
427# define RADEON_CRTC_CUR_MODE_24BPP 2
428# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
429# define RADEON_CRTC_EN (1 << 25)
430# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
431#define RADEON_CRTC2_GEN_CNTL 0x03f8
432# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
433# define RADEON_CRTC2_INTERLACE_EN (1 << 1)
434# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
435# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
436# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
437# define RADEON_CRTC2_CRT2_ON (1 << 7)
438# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
439# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
440# define RADEON_CRTC2_ICON_EN (1 << 15)
441# define RADEON_CRTC2_CUR_EN (1 << 16)
442# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
443# define RADEON_CRTC2_DISP_DIS (1 << 23)
444# define RADEON_CRTC2_EN (1 << 25)
445# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
446# define RADEON_CRTC2_CSYNC_EN (1 << 27)
447# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
448# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
449#define RADEON_CRTC_MORE_CNTL 0x27c
450# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
451# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
452# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
453# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
454#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
455#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
456# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
457# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
458# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
459# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
460# define RADEON_CRTC_H_SYNC_WID_SHIFT 16
461# define RADEON_CRTC_H_SYNC_POL (1 << 23)
462#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
463# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
464# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
465# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
466# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
467# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
468# define RADEON_CRTC2_H_SYNC_POL (1 << 23)
469#define RADEON_CRTC_H_TOTAL_DISP 0x0200
470# define RADEON_CRTC_H_TOTAL (0x03ff << 0)
471# define RADEON_CRTC_H_TOTAL_SHIFT 0
472# define RADEON_CRTC_H_DISP (0x01ff << 16)
473# define RADEON_CRTC_H_DISP_SHIFT 16
474#define RADEON_CRTC2_H_TOTAL_DISP 0x0300
475# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
476# define RADEON_CRTC2_H_TOTAL_SHIFT 0
477# define RADEON_CRTC2_H_DISP (0x01ff << 16)
478# define RADEON_CRTC2_H_DISP_SHIFT 16
479
480#define RADEON_CRTC_OFFSET_RIGHT 0x0220
481#define RADEON_CRTC_OFFSET 0x0224
482# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
483# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
484
485#define RADEON_CRTC2_OFFSET 0x0324
486# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
487# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
488#define RADEON_CRTC_OFFSET_CNTL 0x0228
489# define RADEON_CRTC_TILE_LINE_SHIFT 0
490# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
491# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
492# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
493# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
494# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
495# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
496# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
497# define R300_CRTC_X_Y_MODE_EN (1 << 9)
498# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
499# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
500# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
501# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
502# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
503# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
504# define R300_CRTC_MICRO_TILE_EN (1 << 13)
505# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
506# define R300_CRTC_MACRO_TILE_EN (1 << 15)
507# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
508# define RADEON_CRTC_TILE_EN (1 << 15)
509# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
510# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
511
512#define R300_CRTC_TILE_X0_Y0 0x0350
513#define R300_CRTC2_TILE_X0_Y0 0x0358
514
515#define RADEON_CRTC2_OFFSET_CNTL 0x0328
516# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
517# define RADEON_CRTC2_TILE_EN (1 << 15)
518#define RADEON_CRTC_PITCH 0x022c
519# define RADEON_CRTC_PITCH__SHIFT 0
520# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16
521
522#define RADEON_CRTC2_PITCH 0x032c
523#define RADEON_CRTC_STATUS 0x005c
524# define RADEON_CRTC_VBLANK_SAVE (1 << 1)
525# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
526#define RADEON_CRTC2_STATUS 0x03fc
527# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
528# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
529#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
530# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
531# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
532# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
533# define RADEON_CRTC_V_SYNC_WID_SHIFT 16
534# define RADEON_CRTC_V_SYNC_POL (1 << 23)
535#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
536# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
537# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
538# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
539# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
540# define RADEON_CRTC2_V_SYNC_POL (1 << 23)
541#define RADEON_CRTC_V_TOTAL_DISP 0x0208
542# define RADEON_CRTC_V_TOTAL (0x07ff << 0)
543# define RADEON_CRTC_V_TOTAL_SHIFT 0
544# define RADEON_CRTC_V_DISP (0x07ff << 16)
545# define RADEON_CRTC_V_DISP_SHIFT 16
546#define RADEON_CRTC2_V_TOTAL_DISP 0x0308
547# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
548# define RADEON_CRTC2_V_TOTAL_SHIFT 0
549# define RADEON_CRTC2_V_DISP (0x07ff << 16)
550# define RADEON_CRTC2_V_DISP_SHIFT 16
551#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
552# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
553#define RADEON_CRTC2_CRNT_FRAME 0x0314
554#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
555#define RADEON_CRTC2_STATUS 0x03fc
556#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
557#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
558#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
559#define RADEON_CUR_CLR0 0x026c
560#define RADEON_CUR_CLR1 0x0270
561#define RADEON_CUR_HORZ_VERT_OFF 0x0268
562#define RADEON_CUR_HORZ_VERT_POSN 0x0264
563#define RADEON_CUR_OFFSET 0x0260
564# define RADEON_CUR_LOCK (1 << 31)
565#define RADEON_CUR2_CLR0 0x036c
566#define RADEON_CUR2_CLR1 0x0370
567#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
568#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
569#define RADEON_CUR2_OFFSET 0x0360
570# define RADEON_CUR2_LOCK (1 << 31)
571
572#define RADEON_DAC_CNTL 0x0058
573# define RADEON_DAC_RANGE_CNTL (3 << 0)
574# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
575# define RADEON_DAC_RANGE_CNTL_MASK 0x03
576# define RADEON_DAC_BLANKING (1 << 2)
577# define RADEON_DAC_CMP_EN (1 << 3)
578# define RADEON_DAC_CMP_OUTPUT (1 << 7)
579# define RADEON_DAC_8BIT_EN (1 << 8)
580# define RADEON_DAC_TVO_EN (1 << 10)
581# define RADEON_DAC_VGA_ADR_EN (1 << 13)
582# define RADEON_DAC_PDWN (1 << 15)
583# define RADEON_DAC_MASK_ALL (0xff << 24)
584#define RADEON_DAC_CNTL2 0x007c
585# define RADEON_DAC2_TV_CLK_SEL (0 << 1)
586# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
587# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
588# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
589# define RADEON_DAC2_CMP_EN (1 << 7)
590# define RADEON_DAC2_CMP_OUT_R (1 << 8)
591# define RADEON_DAC2_CMP_OUT_G (1 << 9)
592# define RADEON_DAC2_CMP_OUT_B (1 << 10)
593# define RADEON_DAC2_CMP_OUTPUT (1 << 11)
594#define RADEON_DAC_EXT_CNTL 0x0280
595# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
596# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
597# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
598# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
599# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
600# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
601# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
602# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
603# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
604# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
605# define RADEON_DAC_FORCE_DATA_SHIFT 8
606#define RADEON_DAC_MACRO_CNTL 0x0d04
607# define RADEON_DAC_PDWN_R (1 << 16)
608# define RADEON_DAC_PDWN_G (1 << 17)
609# define RADEON_DAC_PDWN_B (1 << 18)
610#define RADEON_DISP_PWR_MAN 0x0d08
611# define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
612# define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)
613# define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)
614# define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)
615# define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)
616# define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)
617# define RADEON_DISP_D3_RST (1 << 16)
618# define RADEON_DISP_D3_REG_RST (1 << 17)
619# define RADEON_DISP_D3_GRPH_RST (1 << 18)
620# define RADEON_DISP_D3_SUBPIC_RST (1 << 19)
621# define RADEON_DISP_D3_OV0_RST (1 << 20)
622# define RADEON_DISP_D1D2_GRPH_RST (1 << 21)
623# define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)
624# define RADEON_DISP_D1D2_OV0_RST (1 << 23)
625# define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)
626# define RADEON_TV_ENABLE_RST (1 << 25)
627# define RADEON_AUTO_PWRUP_EN (1 << 26)
628#define RADEON_TV_DAC_CNTL 0x088c
629# define RADEON_TV_DAC_NBLANK (1 << 0)
630# define RADEON_TV_DAC_NHOLD (1 << 1)
631# define RADEON_TV_DAC_PEDESTAL (1 << 2)
632# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
633# define RADEON_TV_DAC_CMPOUT (1 << 5)
634# define RADEON_TV_DAC_STD_MASK (3 << 8)
635# define RADEON_TV_DAC_STD_PAL (0 << 8)
636# define RADEON_TV_DAC_STD_NTSC (1 << 8)
637# define RADEON_TV_DAC_STD_PS2 (2 << 8)
638# define RADEON_TV_DAC_STD_RS343 (3 << 8)
639# define RADEON_TV_DAC_BGSLEEP (1 << 6)
640# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
641# define RADEON_TV_DAC_BGADJ_SHIFT 16
642# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
643# define RADEON_TV_DAC_DACADJ_SHIFT 20
644# define RADEON_TV_DAC_RDACPD (1 << 24)
645# define RADEON_TV_DAC_GDACPD (1 << 25)
646# define RADEON_TV_DAC_BDACPD (1 << 26)
647# define RADEON_TV_DAC_RDACDET (1 << 29)
648# define RADEON_TV_DAC_GDACDET (1 << 30)
649# define RADEON_TV_DAC_BDACDET (1 << 31)
650# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
651# define R420_TV_DAC_RDACPD (1 << 25)
652# define R420_TV_DAC_GDACPD (1 << 26)
653# define R420_TV_DAC_BDACPD (1 << 27)
654# define R420_TV_DAC_TVENABLE (1 << 28)
655#define RADEON_DISP_HW_DEBUG 0x0d14
656# define RADEON_CRT2_DISP1_SEL (1 << 5)
657#define RADEON_DISP_OUTPUT_CNTL 0x0d64
658# define RADEON_DISP_DAC_SOURCE_MASK 0x03
659# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
660# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
661# define RADEON_DISP_DAC_SOURCE_RMX 0x02
662# define RADEON_DISP_DAC_SOURCE_LTU 0x03
663# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
664# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
665# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
666# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
667# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
668# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
669# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
670# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
671# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
672# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
673# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
674# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
675#define RADEON_DISP_TV_OUT_CNTL 0x0d6c
676# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
677# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
678#define RADEON_DAC_CRC_SIG 0x02cc
679#define RADEON_DAC_DATA 0x03c9 /* VGA */
680#define RADEON_DAC_MASK 0x03c6 /* VGA */
681#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
682#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
683#define RADEON_DDA_CONFIG 0x02e0
684#define RADEON_DDA_ON_OFF 0x02e4
685#define RADEON_DEFAULT_OFFSET 0x16e0
686#define RADEON_DEFAULT_PITCH 0x16e4
687#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
688# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
689# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
690#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
691#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
692#define RADEON_DEVICE_ID 0x0f02 /* PCI */
693#define RADEON_DISP_MISC_CNTL 0x0d00
694# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
695#define RADEON_DISP_MERGE_CNTL 0x0d60
696# define RADEON_DISP_ALPHA_MODE_MASK 0x03
697# define RADEON_DISP_ALPHA_MODE_KEY 0
698# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
699# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
700# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
701# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
702# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
703# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
704#define RADEON_DISP2_MERGE_CNTL 0x0d68
705# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
706#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
707#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
708#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
709#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
710#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
711#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
712#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
713#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
714#define RADEON_DP_CNTL 0x16c0
715# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
716# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
717# define RADEON_DP_DST_TILE_LINEAR (0 << 3)
718# define RADEON_DP_DST_TILE_MACRO (1 << 3)
719# define RADEON_DP_DST_TILE_MICRO (2 << 3)
720# define RADEON_DP_DST_TILE_BOTH (3 << 3)
721#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
722# define RADEON_DST_Y_MAJOR (1 << 2)
723# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
724# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
725#define RADEON_DP_DATATYPE 0x16c4
726# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
727#define RADEON_DP_GUI_MASTER_CNTL 0x146c
728# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
729# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
730# define RADEON_GMC_SRC_CLIPPING (1 << 2)
731# define RADEON_GMC_DST_CLIPPING (1 << 3)
732# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
733# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
734# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
735# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
736# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
737# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
738# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
739# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
740# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
741# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
742# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
743# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
744# define RADEON_GMC_BRUSH_NONE (15 << 4)
745# define RADEON_GMC_DST_8BPP_CI (2 << 8)
746# define RADEON_GMC_DST_15BPP (3 << 8)
747# define RADEON_GMC_DST_16BPP (4 << 8)
748# define RADEON_GMC_DST_24BPP (5 << 8)
749# define RADEON_GMC_DST_32BPP (6 << 8)
750# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
751# define RADEON_GMC_DST_Y8 (8 << 8)
752# define RADEON_GMC_DST_RGB8 (9 << 8)
753# define RADEON_GMC_DST_VYUY (11 << 8)
754# define RADEON_GMC_DST_YVYU (12 << 8)
755# define RADEON_GMC_DST_AYUV444 (14 << 8)
756# define RADEON_GMC_DST_ARGB4444 (15 << 8)
757# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
758# define RADEON_GMC_DST_DATATYPE_SHIFT 8
759# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
760# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
761# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
762# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
763# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
764# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
765# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
766# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
767# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
768# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
769# define RADEON_GMC_ROP3_MASK (0xff << 16)
770# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
771# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
772# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
773# define RADEON_GMC_3D_FCN_EN (1 << 27)
774# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
775# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
776# define RADEON_GMC_WR_MSK_DIS (1 << 30)
777# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
778# define RADEON_ROP3_ZERO 0x00000000
779# define RADEON_ROP3_DSa 0x00880000
780# define RADEON_ROP3_SDna 0x00440000
781# define RADEON_ROP3_S 0x00cc0000
782# define RADEON_ROP3_DSna 0x00220000
783# define RADEON_ROP3_D 0x00aa0000
784# define RADEON_ROP3_DSx 0x00660000
785# define RADEON_ROP3_DSo 0x00ee0000
786# define RADEON_ROP3_DSon 0x00110000
787# define RADEON_ROP3_DSxn 0x00990000
788# define RADEON_ROP3_Dn 0x00550000
789# define RADEON_ROP3_SDno 0x00dd0000
790# define RADEON_ROP3_Sn 0x00330000
791# define RADEON_ROP3_DSno 0x00bb0000
792# define RADEON_ROP3_DSan 0x00770000
793# define RADEON_ROP3_ONE 0x00ff0000
794# define RADEON_ROP3_DPa 0x00a00000
795# define RADEON_ROP3_PDna 0x00500000
796# define RADEON_ROP3_P 0x00f00000
797# define RADEON_ROP3_DPna 0x000a0000
798# define RADEON_ROP3_D 0x00aa0000
799# define RADEON_ROP3_DPx 0x005a0000
800# define RADEON_ROP3_DPo 0x00fa0000
801# define RADEON_ROP3_DPon 0x00050000
802# define RADEON_ROP3_PDxn 0x00a50000
803# define RADEON_ROP3_PDno 0x00f50000
804# define RADEON_ROP3_Pn 0x000f0000
805# define RADEON_ROP3_DPno 0x00af0000
806# define RADEON_ROP3_DPan 0x005f0000
807#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
808#define RADEON_DP_MIX 0x16c8
809#define RADEON_DP_SRC_BKGD_CLR 0x15dc
810#define RADEON_DP_SRC_FRGD_CLR 0x15d8
811#define RADEON_DP_WRITE_MASK 0x16cc
812#define RADEON_DST_BRES_DEC 0x1630
813#define RADEON_DST_BRES_ERR 0x1628
814#define RADEON_DST_BRES_INC 0x162c
815#define RADEON_DST_BRES_LNTH 0x1634
816#define RADEON_DST_BRES_LNTH_SUB 0x1638
817#define RADEON_DST_HEIGHT 0x1410
818#define RADEON_DST_HEIGHT_WIDTH 0x143c
819#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
820#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
821#define RADEON_DST_HEIGHT_Y 0x15a0
822#define RADEON_DST_LINE_START 0x1600
823#define RADEON_DST_LINE_END 0x1604
824#define RADEON_DST_LINE_PATCOUNT 0x1608
825# define RADEON_BRES_CNTL_SHIFT 8
826#define RADEON_DST_OFFSET 0x1404
827#define RADEON_DST_PITCH 0x1408
828#define RADEON_DST_PITCH_OFFSET 0x142c
829#define RADEON_DST_PITCH_OFFSET_C 0x1c80
830# define RADEON_PITCH_SHIFT 21
831# define RADEON_DST_TILE_LINEAR (0 << 30)
832# define RADEON_DST_TILE_MACRO (1 << 30)
833# define RADEON_DST_TILE_MICRO (2 << 30)
834# define RADEON_DST_TILE_BOTH (3 << 30)
835#define RADEON_DST_WIDTH 0x140c
836#define RADEON_DST_WIDTH_HEIGHT 0x1598
837#define RADEON_DST_WIDTH_X 0x1588
838#define RADEON_DST_WIDTH_X_INCY 0x159c
839#define RADEON_DST_X 0x141c
840#define RADEON_DST_X_SUB 0x15a4
841#define RADEON_DST_X_Y 0x1594
842#define RADEON_DST_Y 0x1420
843#define RADEON_DST_Y_SUB 0x15a8
844#define RADEON_DST_Y_X 0x1438
845
846#define RADEON_FCP_CNTL 0x0910
847# define RADEON_FCP0_SRC_PCICLK 0
848# define RADEON_FCP0_SRC_PCLK 1
849# define RADEON_FCP0_SRC_PCLKb 2
850# define RADEON_FCP0_SRC_HREF 3
851# define RADEON_FCP0_SRC_GND 4
852# define RADEON_FCP0_SRC_HREFb 5
853#define RADEON_FLUSH_1 0x1704
854#define RADEON_FLUSH_2 0x1708
855#define RADEON_FLUSH_3 0x170c
856#define RADEON_FLUSH_4 0x1710
857#define RADEON_FLUSH_5 0x1714
858#define RADEON_FLUSH_6 0x1718
859#define RADEON_FLUSH_7 0x171c
860#define RADEON_FOG_3D_TABLE_START 0x1810
861#define RADEON_FOG_3D_TABLE_END 0x1814
862#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
863#define RADEON_FOG_TABLE_INDEX 0x1a14
864#define RADEON_FOG_TABLE_DATA 0x1a18
865#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
866#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
867# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
868# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
869# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
870# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
871# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
872# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
873# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
874# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
875# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
876# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
877# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
878# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
879# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
880# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
881# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
882# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
883#define RADEON_FP_GEN_CNTL 0x0284
884# define RADEON_FP_FPON (1 << 0)
885# define RADEON_FP_BLANK_EN (1 << 1)
886# define RADEON_FP_TMDS_EN (1 << 2)
887# define RADEON_FP_PANEL_FORMAT (1 << 3)
888# define RADEON_FP_EN_TMDS (1 << 7)
889# define RADEON_FP_DETECT_SENSE (1 << 8)
890# define R200_FP_SOURCE_SEL_MASK (3 << 10)
891# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
892# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
893# define R200_FP_SOURCE_SEL_RMX (2 << 10)
894# define R200_FP_SOURCE_SEL_TRANS (3 << 10)
895# define RADEON_FP_SEL_CRTC1 (0 << 13)
896# define RADEON_FP_SEL_CRTC2 (1 << 13)
897# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
898# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
899# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
900# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
901# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
902# define RADEON_FP_DFP_SYNC_SEL (1 << 21)
903# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
904# define RADEON_FP_CRT_SYNC_SEL (1 << 23)
905# define RADEON_FP_USE_SHADOW_EN (1 << 24)
906# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
907#define RADEON_FP2_GEN_CNTL 0x0288
908# define RADEON_FP2_BLANK_EN (1 << 1)
909# define RADEON_FP2_ON (1 << 2)
910# define RADEON_FP2_PANEL_FORMAT (1 << 3)
911# define RADEON_FP2_DETECT_SENSE (1 << 8)
912# define R200_FP2_SOURCE_SEL_MASK (3 << 10)
913# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
914# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
915# define R200_FP2_SOURCE_SEL_RMX (2 << 10)
916# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
917# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
918# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
919# define RADEON_FP2_FP_POL (1 << 16)
920# define RADEON_FP2_LP_POL (1 << 17)
921# define RADEON_FP2_SCK_POL (1 << 18)
922# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
923# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
924# define RADEON_FP2_CRC_EN (1 << 23)
925# define RADEON_FP2_CRC_READ_EN (1 << 24)
926# define RADEON_FP2_DVO_EN (1 << 25)
927# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
928# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
929# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
930# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
931#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
932#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
933#define RADEON_FP_HORZ_STRETCH 0x028c
934#define RADEON_FP_HORZ2_STRETCH 0x038c
935# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
936# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
937# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
938# define RADEON_HORZ_PANEL_SHIFT 16
939# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
940# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
941# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
942# define RADEON_HORZ_AUTO_RATIO (1 << 27)
943# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
944# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
945#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
946#define RADEON_FP_V_SYNC_STRT_WID 0x02c8
947#define RADEON_FP_VERT_STRETCH 0x0290
948#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
949#define RADEON_FP_VERT2_STRETCH 0x0390
950# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
951# define RADEON_VERT_PANEL_SHIFT 12
952# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
953# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
954# define RADEON_VERT_STRETCH_RATIO_MAX 4096
955# define RADEON_VERT_STRETCH_ENABLE (1 << 25)
956# define RADEON_VERT_STRETCH_LINEREP (0 << 26)
957# define RADEON_VERT_STRETCH_BLEND (1 << 26)
958# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
959# define RADEON_VERT_AUTO_RATIO_INC (1 << 31)
960# define RADEON_VERT_STRETCH_RESERVED 0x71000000
961#define RS400_FP_2ND_GEN_CNTL 0x0384
962# define RS400_FP_2ND_ON (1 << 0)
963# define RS400_FP_2ND_BLANK_EN (1 << 1)
964# define RS400_TMDS_2ND_EN (1 << 2)
965# define RS400_PANEL_FORMAT_2ND (1 << 3)
966# define RS400_FP_2ND_EN_TMDS (1 << 7)
967# define RS400_FP_2ND_DETECT_SENSE (1 << 8)
968# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)
969# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)
970# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)
971# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)
972# define RS400_FP_2ND_DETECT_EN (1 << 12)
973# define RS400_HPD_2ND_SEL (1 << 13)
974#define RS400_FP2_2_GEN_CNTL 0x0388
975# define RS400_FP2_2_BLANK_EN (1 << 1)
976# define RS400_FP2_2_ON (1 << 2)
977# define RS400_FP2_2_PANEL_FORMAT (1 << 3)
978# define RS400_FP2_2_DETECT_SENSE (1 << 8)
979# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
980# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
981# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
982# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
983# define RS400_FP2_2_DVO2_EN (1 << 25)
984#define RS400_TMDS2_CNTL 0x0394
985#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4
986# define RS400_TMDS2_PLLEN (1 << 0)
987# define RS400_TMDS2_PLLRST (1 << 1)
988
989#define RADEON_GEN_INT_CNTL 0x0040
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200990# define RADEON_CRTC_VBLANK_MASK (1 << 0)
991# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200992# define RADEON_SW_INT_ENABLE (1 << 25)
993#define RADEON_GEN_INT_STATUS 0x0044
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200994# define AVIVO_DISPLAY_INT_STATUS (1 << 0)
995# define RADEON_CRTC_VBLANK_STAT (1 << 0)
996# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
997# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
998# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200999# define RADEON_SW_INT_FIRE (1 << 26)
1000# define RADEON_SW_INT_TEST (1 << 25)
1001# define RADEON_SW_INT_TEST_ACK (1 << 25)
1002#define RADEON_GENENB 0x03c3 /* VGA */
1003#define RADEON_GENFC_RD 0x03ca /* VGA */
1004#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
1005#define RADEON_GENMO_RD 0x03cc /* VGA */
1006#define RADEON_GENMO_WT 0x03c2 /* VGA */
1007#define RADEON_GENS0 0x03c2 /* VGA */
1008#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
1009#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */
1010#define RADEON_GPIO_MONIDB 0x006c
1011#define RADEON_GPIO_CRT2_DDC 0x006c
1012#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */
1013#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */
1014# define RADEON_GPIO_A_0 (1 << 0)
1015# define RADEON_GPIO_A_1 (1 << 1)
1016# define RADEON_GPIO_Y_0 (1 << 8)
1017# define RADEON_GPIO_Y_1 (1 << 9)
1018# define RADEON_GPIO_Y_SHIFT_0 8
1019# define RADEON_GPIO_Y_SHIFT_1 9
1020# define RADEON_GPIO_EN_0 (1 << 16)
1021# define RADEON_GPIO_EN_1 (1 << 17)
1022# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
1023# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
1024#define RADEON_GRPH8_DATA 0x03cf /* VGA */
1025#define RADEON_GRPH8_IDX 0x03ce /* VGA */
1026#define RADEON_GUI_SCRATCH_REG0 0x15e0
1027#define RADEON_GUI_SCRATCH_REG1 0x15e4
1028#define RADEON_GUI_SCRATCH_REG2 0x15e8
1029#define RADEON_GUI_SCRATCH_REG3 0x15ec
1030#define RADEON_GUI_SCRATCH_REG4 0x15f0
1031#define RADEON_GUI_SCRATCH_REG5 0x15f4
1032
1033#define RADEON_HEADER 0x0f0e /* PCI */
1034#define RADEON_HOST_DATA0 0x17c0
1035#define RADEON_HOST_DATA1 0x17c4
1036#define RADEON_HOST_DATA2 0x17c8
1037#define RADEON_HOST_DATA3 0x17cc
1038#define RADEON_HOST_DATA4 0x17d0
1039#define RADEON_HOST_DATA5 0x17d4
1040#define RADEON_HOST_DATA6 0x17d8
1041#define RADEON_HOST_DATA7 0x17dc
1042#define RADEON_HOST_DATA_LAST 0x17e0
1043#define RADEON_HOST_PATH_CNTL 0x0130
1044# define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24)
1045# define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27)
1046# define RADEON_HDP_SOFT_RESET (1 << 26)
1047# define RADEON_HDP_APER_CNTL (1 << 23)
1048#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
1049# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
1050#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
1051
1052 /* Multimedia I2C bus */
1053#define RADEON_I2C_CNTL_0 0x0090
1054#define RADEON_I2C_DONE (1<<0)
1055#define RADEON_I2C_NACK (1<<1)
1056#define RADEON_I2C_HALT (1<<2)
1057#define RADEON_I2C_SOFT_RST (1<<5)
1058#define RADEON_I2C_DRIVE_EN (1<<6)
1059#define RADEON_I2C_DRIVE_SEL (1<<7)
1060#define RADEON_I2C_START (1<<8)
1061#define RADEON_I2C_STOP (1<<9)
1062#define RADEON_I2C_RECEIVE (1<<10)
1063#define RADEON_I2C_ABORT (1<<11)
1064#define RADEON_I2C_GO (1<<12)
1065#define RADEON_I2C_CNTL_1 0x0094
1066#define RADEON_I2C_SEL (1<<16)
1067#define RADEON_I2C_EN (1<<17)
1068#define RADEON_I2C_DATA 0x0098
1069
1070#define RADEON_DVI_I2C_CNTL_0 0x02e0
1071# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
1072# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */
1073# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */
1074# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */
1075#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */
1076#define RADEON_DVI_I2C_DATA 0x02e8
1077
1078#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
1079#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
1080#define RADEON_IO_BASE 0x0f14 /* PCI */
1081
1082#define RADEON_LATENCY 0x0f0d /* PCI */
1083#define RADEON_LEAD_BRES_DEC 0x1608
1084#define RADEON_LEAD_BRES_LNTH 0x161c
1085#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
1086#define RADEON_LVDS_GEN_CNTL 0x02d0
1087# define RADEON_LVDS_ON (1 << 0)
1088# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
1089# define RADEON_LVDS_PANEL_TYPE (1 << 2)
1090# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
1091# define RADEON_LVDS_NO_FM (0 << 4)
1092# define RADEON_LVDS_2_GREY (1 << 4)
1093# define RADEON_LVDS_4_GREY (2 << 4)
1094# define RADEON_LVDS_RST_FM (1 << 6)
1095# define RADEON_LVDS_EN (1 << 7)
1096# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
1097# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
1098# define RADEON_LVDS_BL_MOD_EN (1 << 16)
1099# define RADEON_LVDS_BL_CLK_SEL (1 << 17)
1100# define RADEON_LVDS_DIGON (1 << 18)
1101# define RADEON_LVDS_BLON (1 << 19)
1102# define RADEON_LVDS_FP_POL_LOW (1 << 20)
1103# define RADEON_LVDS_LP_POL_LOW (1 << 21)
1104# define RADEON_LVDS_DTM_POL_LOW (1 << 22)
1105# define RADEON_LVDS_SEL_CRTC2 (1 << 23)
1106# define RADEON_LVDS_FPDI_EN (1 << 27)
1107# define RADEON_LVDS_HSYNC_DELAY_SHIFT 28
1108#define RADEON_LVDS_PLL_CNTL 0x02d4
1109# define RADEON_HSYNC_DELAY_SHIFT 28
1110# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
1111# define RADEON_LVDS_PLL_EN (1 << 16)
1112# define RADEON_LVDS_PLL_RESET (1 << 17)
1113# define R300_LVDS_SRC_SEL_MASK (3 << 18)
1114# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
1115# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
1116# define R300_LVDS_SRC_SEL_RMX (2 << 18)
1117#define RADEON_LVDS_SS_GEN_CNTL 0x02ec
1118# define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16
1119# define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20
1120
1121#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
1122#define RADEON_DISPLAY_BASE_ADDR 0x23c
1123#define RADEON_DISPLAY2_BASE_ADDR 0x33c
1124#define RADEON_OV0_BASE_ADDR 0x43c
1125#define RADEON_NB_TOM 0x15c
1126#define R300_MC_INIT_MISC_LAT_TIMER 0x180
1127# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
1128# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
1129# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
1130# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
1131#define RADEON_MCLK_CNTL 0x0012 /* PLL */
1132# define RADEON_MCLKA_SRC_SEL_MASK 0x7
1133# define RADEON_FORCEON_MCLKA (1 << 16)
1134# define RADEON_FORCEON_MCLKB (1 << 17)
1135# define RADEON_FORCEON_YCLKA (1 << 18)
1136# define RADEON_FORCEON_YCLKB (1 << 19)
1137# define RADEON_FORCEON_MC (1 << 20)
1138# define RADEON_FORCEON_AIC (1 << 21)
1139# define R300_DISABLE_MC_MCLKA (1 << 21)
1140# define R300_DISABLE_MC_MCLKB (1 << 21)
1141#define RADEON_MCLK_MISC 0x001f /* PLL */
1142# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
1143# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
1144# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
1145# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
1146#define RADEON_LCD_GPIO_MASK 0x01a0
1147#define RADEON_GPIOPAD_EN 0x01a0
1148#define RADEON_LCD_GPIO_Y_REG 0x01a4
1149#define RADEON_MDGPIO_A_REG 0x01ac
1150#define RADEON_MDGPIO_EN_REG 0x01b0
1151#define RADEON_MDGPIO_MASK 0x0198
1152#define RADEON_GPIOPAD_MASK 0x0198
1153#define RADEON_GPIOPAD_A 0x019c
1154#define RADEON_MDGPIO_Y_REG 0x01b4
1155#define RADEON_MEM_ADDR_CONFIG 0x0148
1156#define RADEON_MEM_BASE 0x0f10 /* PCI */
1157#define RADEON_MEM_CNTL 0x0140
1158# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
1159# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
1160# define RV100_HALF_MODE (1 << 3)
1161# define R300_MEM_NUM_CHANNELS_MASK 0x03
1162# define R300_MEM_USE_CD_CH_ONLY (1 << 2)
1163#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
1164#define RADEON_MEM_INIT_LAT_TIMER 0x0154
1165#define RADEON_MEM_INTF_CNTL 0x014c
1166#define RADEON_MEM_SDRAM_MODE_REG 0x0158
1167# define RADEON_SDRAM_MODE_MASK 0xffff0000
1168# define RADEON_B3MEM_RESET_MASK 0x6fffffff
1169# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
1170#define RADEON_MEM_STR_CNTL 0x0150
1171# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
1172# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
1173# define R300_MEM_PWRUP_COMPL_C (1 << 2)
1174# define R300_MEM_PWRUP_COMPL_D (1 << 3)
1175# define RADEON_MEM_PWRUP_COMPLETE 0x03
1176# define R300_MEM_PWRUP_COMPLETE 0x0f
1177#define RADEON_MC_STATUS 0x0150
1178# define RADEON_MC_IDLE (1 << 2)
1179# define R300_MC_IDLE (1 << 4)
1180#define RADEON_MEM_VGA_RP_SEL 0x003c
1181#define RADEON_MEM_VGA_WP_SEL 0x0038
1182#define RADEON_MIN_GRANT 0x0f3e /* PCI */
1183#define RADEON_MM_DATA 0x0004
1184#define RADEON_MM_INDEX 0x0000
1185# define RADEON_MM_APER (1 << 31)
1186#define RADEON_MPLL_CNTL 0x000e /* PLL */
1187#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
1188#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
1189#define RADEON_SEPROM_CNTL1 0x01c0
1190# define RADEON_SCK_PRESCALE_SHIFT 24
1191# define RADEON_SCK_PRESCALE_MASK (0xff << 24)
1192#define R300_MC_IND_INDEX 0x01f8
1193# define R300_MC_IND_ADDR_MASK 0x3f
1194# define R300_MC_IND_WR_EN (1 << 8)
1195#define R300_MC_IND_DATA 0x01fc
1196#define R300_MC_READ_CNTL_AB 0x017c
1197# define R300_MEM_RBS_POSITION_A_MASK 0x03
1198#define R300_MC_READ_CNTL_CD_mcind 0x24
1199# define R300_MEM_RBS_POSITION_C_MASK 0x03
1200
1201#define RADEON_N_VIF_COUNT 0x0248
1202
1203#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
1204# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
1205# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
1206# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
1207# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
1208# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
1209# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
1210# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
1211# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
1212# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
1213# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
1214
1215#define RADEON_OV0_COLOUR_CNTL 0x04E0
1216#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
1217#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
1218# define RADEON_EXCL_HORZ_START_MASK 0x000000ff
1219# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
1220# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
1221# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
1222#define RADEON_OV0_EXCLUSIVE_VERT 0x040C
1223# define RADEON_EXCL_VERT_START_MASK 0x000003ff
1224# define RADEON_EXCL_VERT_END_MASK 0x03ff0000
1225#define RADEON_OV0_FILTER_CNTL 0x04A0
1226# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
1227# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
1228# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
1229# define RADEON_FILTER_HC_COEF_VERT_Y 0x4
1230# define RADEON_FILTER_HC_COEF_VERT_UV 0x8
1231# define RADEON_FILTER_HARDCODED_COEF 0xf
1232# define RADEON_FILTER_COEF_MASK 0xf
1233
1234#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
1235#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
1236#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
1237#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
1238#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
1239#define RADEON_OV0_FLAG_CNTL 0x04DC
1240#define RADEON_OV0_GAMMA_000_00F 0x0d40
1241#define RADEON_OV0_GAMMA_010_01F 0x0d44
1242#define RADEON_OV0_GAMMA_020_03F 0x0d48
1243#define RADEON_OV0_GAMMA_040_07F 0x0d4c
1244#define RADEON_OV0_GAMMA_080_0BF 0x0e00
1245#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
1246#define RADEON_OV0_GAMMA_100_13F 0x0e08
1247#define RADEON_OV0_GAMMA_140_17F 0x0e0c
1248#define RADEON_OV0_GAMMA_180_1BF 0x0e10
1249#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
1250#define RADEON_OV0_GAMMA_200_23F 0x0e18
1251#define RADEON_OV0_GAMMA_240_27F 0x0e1c
1252#define RADEON_OV0_GAMMA_280_2BF 0x0e20
1253#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
1254#define RADEON_OV0_GAMMA_300_33F 0x0e28
1255#define RADEON_OV0_GAMMA_340_37F 0x0e2c
1256#define RADEON_OV0_GAMMA_380_3BF 0x0d50
1257#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
1258#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
1259#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
1260#define RADEON_OV0_H_INC 0x0480
1261#define RADEON_OV0_KEY_CNTL 0x04F4
1262# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
1263# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
1264# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
1265# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
1266# define RADEON_VIDEO_KEY_FN_NE 0x00000003L
1267# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
1268# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
1269# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
1270# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
1271# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
1272# define RADEON_CMP_MIX_MASK 0x00000100L
1273# define RADEON_CMP_MIX_OR 0x00000000L
1274# define RADEON_CMP_MIX_AND 0x00000100L
1275#define RADEON_OV0_LIN_TRANS_A 0x0d20
1276#define RADEON_OV0_LIN_TRANS_B 0x0d24
1277#define RADEON_OV0_LIN_TRANS_C 0x0d28
1278#define RADEON_OV0_LIN_TRANS_D 0x0d2c
1279#define RADEON_OV0_LIN_TRANS_E 0x0d30
1280#define RADEON_OV0_LIN_TRANS_F 0x0d34
1281#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
1282# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
1283# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
1284#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
1285#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
1286# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
1287# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
1288#define RADEON_OV0_P1_X_START_END 0x0494
1289#define RADEON_OV0_P2_X_START_END 0x0498
1290#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
1291# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
1292# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
1293#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
1294#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
1295#define RADEON_OV0_P3_X_START_END 0x049C
1296#define RADEON_OV0_REG_LOAD_CNTL 0x0410
1297# define RADEON_REG_LD_CTL_LOCK 0x00000001L
1298# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
1299# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
1300# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
1301# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
1302#define RADEON_OV0_SCALE_CNTL 0x0420
1303# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
1304# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
1305# define RADEON_SCALER_SIGNED_UV 0x00000010L
1306# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
1307# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
1308# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
1309# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
1310# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
1311# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
1312# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
1313# define RADEON_SCALER_SOURCE_15BPP 0x00000300L
1314# define RADEON_SCALER_SOURCE_16BPP 0x00000400L
1315# define RADEON_SCALER_SOURCE_32BPP 0x00000600L
1316# define RADEON_SCALER_SOURCE_YUV9 0x00000900L
1317# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
1318# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
1319# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
1320# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
1321# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
1322# define RADEON_SCALER_CRTC_SEL 0x00004000L
1323# define RADEON_SCALER_SMART_SWITCH 0x00008000L
1324# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
1325# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
1326# define RADEON_SCALER_DIS_LIMIT 0x08000000L
1327# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
1328# define RADEON_SCALER_INT_EMU 0x20000000L
1329# define RADEON_SCALER_ENABLE 0x40000000L
1330# define RADEON_SCALER_SOFT_RESET 0x80000000L
1331#define RADEON_OV0_STEP_BY 0x0484
1332#define RADEON_OV0_TEST 0x04F8
1333#define RADEON_OV0_V_INC 0x0424
1334#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
1335#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
1336#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
1337# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
1338# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
1339# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
1340# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
1341#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
1342# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
1343# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
1344# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
1345# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
1346#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
1347# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
1348# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
1349# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
1350# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
1351#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
1352#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
1353#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
1354#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
1355#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
1356#define RADEON_OV0_Y_X_START 0x0400
1357#define RADEON_OV0_Y_X_END 0x0404
1358#define RADEON_OV1_Y_X_START 0x0600
1359#define RADEON_OV1_Y_X_END 0x0604
1360#define RADEON_OVR_CLR 0x0230
1361#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
1362#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
1363
1364/* first capture unit */
1365
1366#define RADEON_CAP0_BUF0_OFFSET 0x0920
1367#define RADEON_CAP0_BUF1_OFFSET 0x0924
1368#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
1369#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
1370
1371#define RADEON_CAP0_BUF_PITCH 0x0930
1372#define RADEON_CAP0_V_WINDOW 0x0934
1373#define RADEON_CAP0_H_WINDOW 0x0938
1374#define RADEON_CAP0_VBI0_OFFSET 0x093C
1375#define RADEON_CAP0_VBI1_OFFSET 0x0940
1376#define RADEON_CAP0_VBI_V_WINDOW 0x0944
1377#define RADEON_CAP0_VBI_H_WINDOW 0x0948
1378#define RADEON_CAP0_PORT_MODE_CNTL 0x094C
1379#define RADEON_CAP0_TRIG_CNTL 0x0950
1380#define RADEON_CAP0_DEBUG 0x0954
1381#define RADEON_CAP0_CONFIG 0x0958
1382# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
1383# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
1384# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
1385# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
1386# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
1387# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
1388# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
1389# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
1390# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
1391# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
1392# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
1393# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
1394# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
1395# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
1396# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
1397# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
1398# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
1399# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
1400# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
1401# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
1402# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
1403# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
1404# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
1405# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
1406# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
1407# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
1408# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
1409# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
1410# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
1411# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
1412# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
1413# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
1414# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
1415#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
1416#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
1417#define RADEON_CAP0_ANC_H_WINDOW 0x0964
1418#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
1419#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
1420#define RADEON_CAP0_BUF_STATUS 0x0970
1421/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
1422/* #define RADEON_CAP0_XSHARPNESS 0x097C */
1423#define RADEON_CAP0_VBI2_OFFSET 0x0980
1424#define RADEON_CAP0_VBI3_OFFSET 0x0984
1425#define RADEON_CAP0_ANC2_OFFSET 0x0988
1426#define RADEON_CAP0_ANC3_OFFSET 0x098C
1427#define RADEON_VID_BUFFER_CONTROL 0x0900
1428
1429/* second capture unit */
1430
1431#define RADEON_CAP1_BUF0_OFFSET 0x0990
1432#define RADEON_CAP1_BUF1_OFFSET 0x0994
1433#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
1434#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
1435
1436#define RADEON_CAP1_BUF_PITCH 0x09A0
1437#define RADEON_CAP1_V_WINDOW 0x09A4
1438#define RADEON_CAP1_H_WINDOW 0x09A8
1439#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
1440#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
1441#define RADEON_CAP1_VBI_V_WINDOW 0x09B4
1442#define RADEON_CAP1_VBI_H_WINDOW 0x09B8
1443#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
1444#define RADEON_CAP1_TRIG_CNTL 0x09C0
1445#define RADEON_CAP1_DEBUG 0x09C4
1446#define RADEON_CAP1_CONFIG 0x09C8
1447#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
1448#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
1449#define RADEON_CAP1_ANC_H_WINDOW 0x09D4
1450#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
1451#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
1452#define RADEON_CAP1_BUF_STATUS 0x09E0
1453#define RADEON_CAP1_DWNSC_XRATIO 0x09E8
1454#define RADEON_CAP1_XSHARPNESS 0x09EC
1455
1456/* misc multimedia registers */
1457
1458#define RADEON_IDCT_RUNS 0x1F80
1459#define RADEON_IDCT_LEVELS 0x1F84
1460#define RADEON_IDCT_CONTROL 0x1FBC
1461#define RADEON_IDCT_AUTH_CONTROL 0x1F88
1462#define RADEON_IDCT_AUTH 0x1F8C
1463
1464#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
1465# define RADEON_P2PLL_RESET (1 << 0)
1466# define RADEON_P2PLL_SLEEP (1 << 1)
1467# define RADEON_P2PLL_PVG_MASK (7 << 11)
1468# define RADEON_P2PLL_PVG_SHIFT 11
1469# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
1470# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1471# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1472#define RADEON_P2PLL_DIV_0 0x002c
1473# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
1474# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
1475#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
1476# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
1477# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1478# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1479# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
1480# define R300_PPLL_REF_DIV_ACC_SHIFT 18
1481#define RADEON_PALETTE_DATA 0x00b4
1482#define RADEON_PALETTE_30_DATA 0x00b8
1483#define RADEON_PALETTE_INDEX 0x00b0
1484#define RADEON_PCI_GART_PAGE 0x017c
1485#define RADEON_PIXCLKS_CNTL 0x002d
1486# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
1487# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
1488# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
1489# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
1490# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
1491# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
1492# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
1493# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
1494# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1495# define R300_DVOCLK_ALWAYS_ONb (1 << 10)
1496# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
1497# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
1498# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
1499# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
1500# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
1501# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
1502# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
1503# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
1504# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
1505# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
1506# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1507#define RADEON_PLANE_3D_MASK_C 0x1d44
1508#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
1509# define RADEON_PLL_MASK_READ_B (1 << 9)
1510#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
1511#define RADEON_PMI_DATA 0x0f63 /* PCI */
1512#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
1513#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
1514#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
1515#define RADEON_PMI_REGISTER 0x0f5c /* PCI */
1516#define RADEON_PPLL_CNTL 0x0002 /* PLL */
1517# define RADEON_PPLL_RESET (1 << 0)
1518# define RADEON_PPLL_SLEEP (1 << 1)
1519# define RADEON_PPLL_PVG_MASK (7 << 11)
1520# define RADEON_PPLL_PVG_SHIFT 11
1521# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
1522# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1523# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1524#define RADEON_PPLL_DIV_0 0x0004 /* PLL */
1525#define RADEON_PPLL_DIV_1 0x0005 /* PLL */
1526#define RADEON_PPLL_DIV_2 0x0006 /* PLL */
1527#define RADEON_PPLL_DIV_3 0x0007 /* PLL */
1528# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
1529# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
1530#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
1531# define RADEON_PPLL_REF_DIV_MASK 0x03ff
1532# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1533# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1534#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
1535
1536#define RADEON_RBBM_GUICNTL 0x172c
1537# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
1538# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
1539# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
1540# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
1541#define RADEON_RBBM_SOFT_RESET 0x00f0
1542# define RADEON_SOFT_RESET_CP (1 << 0)
1543# define RADEON_SOFT_RESET_HI (1 << 1)
1544# define RADEON_SOFT_RESET_SE (1 << 2)
1545# define RADEON_SOFT_RESET_RE (1 << 3)
1546# define RADEON_SOFT_RESET_PP (1 << 4)
1547# define RADEON_SOFT_RESET_E2 (1 << 5)
1548# define RADEON_SOFT_RESET_RB (1 << 6)
1549# define RADEON_SOFT_RESET_HDP (1 << 7)
1550#define RADEON_RBBM_STATUS 0x0e40
1551# define RADEON_RBBM_FIFOCNT_MASK 0x007f
1552# define RADEON_RBBM_ACTIVE (1 << 31)
1553#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
1554# define RADEON_RB2D_DC_FLUSH (3 << 0)
1555# define RADEON_RB2D_DC_FREE (3 << 2)
1556# define RADEON_RB2D_DC_FLUSH_ALL 0xf
1557# define RADEON_RB2D_DC_BUSY (1 << 31)
1558#define RADEON_RB2D_DSTCACHE_MODE 0x3428
1559#define RADEON_DSTCACHE_CTLSTAT 0x1714
1560
1561#define RADEON_RB3D_ZCACHE_MODE 0x3250
1562#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
1563# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
1564#define RADEON_RB3D_DSTCACHE_MODE 0x3258
1565# define RADEON_RB3D_DC_CACHE_ENABLE (0)
1566# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
1567# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
1568# define RADEON_RB3D_DC_CACHE_DISABLE (3)
1569# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
1570# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
1571# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
1572# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
1573# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
1574# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
1575# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
1576# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
1577# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
1578
1579#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
1580# define RADEON_RB3D_DC_FLUSH (3 << 0)
1581# define RADEON_RB3D_DC_FREE (3 << 2)
1582# define RADEON_RB3D_DC_FLUSH_ALL 0xf
1583# define RADEON_RB3D_DC_BUSY (1 << 31)
1584
1585#define RADEON_REG_BASE 0x0f18 /* PCI */
1586#define RADEON_REGPROG_INF 0x0f09 /* PCI */
1587#define RADEON_REVISION_ID 0x0f08 /* PCI */
1588
1589#define RADEON_SC_BOTTOM 0x164c
1590#define RADEON_SC_BOTTOM_RIGHT 0x16f0
1591#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
1592#define RADEON_SC_LEFT 0x1640
1593#define RADEON_SC_RIGHT 0x1644
1594#define RADEON_SC_TOP 0x1648
1595#define RADEON_SC_TOP_LEFT 0x16ec
1596#define RADEON_SC_TOP_LEFT_C 0x1c88
1597# define RADEON_SC_SIGN_MASK_LO 0x8000
1598# define RADEON_SC_SIGN_MASK_HI 0x80000000
1599#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */
1600# define RADEON_M_SPLL_REF_DIV_SHIFT 0
1601# define RADEON_M_SPLL_REF_DIV_MASK 0xff
1602# define RADEON_MPLL_FB_DIV_SHIFT 8
1603# define RADEON_MPLL_FB_DIV_MASK 0xff
1604# define RADEON_SPLL_FB_DIV_SHIFT 16
1605# define RADEON_SPLL_FB_DIV_MASK 0xff
1606#define RADEON_SPLL_CNTL 0x000c /* PLL */
1607# define RADEON_SPLL_SLEEP (1 << 0)
1608# define RADEON_SPLL_RESET (1 << 1)
1609# define RADEON_SPLL_PCP_MASK 0x7
1610# define RADEON_SPLL_PCP_SHIFT 8
1611# define RADEON_SPLL_PVG_MASK 0x7
1612# define RADEON_SPLL_PVG_SHIFT 11
1613# define RADEON_SPLL_PDC_MASK 0x3
1614# define RADEON_SPLL_PDC_SHIFT 14
1615#define RADEON_SCLK_CNTL 0x000d /* PLL */
1616# define RADEON_SCLK_SRC_SEL_MASK 0x0007
1617# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
1618# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
1619# define RADEON_SCLK_FORCEON_MASK 0xffff8000
1620# define RADEON_SCLK_FORCE_DISP2 (1<<15)
1621# define RADEON_SCLK_FORCE_CP (1<<16)
1622# define RADEON_SCLK_FORCE_HDP (1<<17)
1623# define RADEON_SCLK_FORCE_DISP1 (1<<18)
1624# define RADEON_SCLK_FORCE_TOP (1<<19)
1625# define RADEON_SCLK_FORCE_E2 (1<<20)
1626# define RADEON_SCLK_FORCE_SE (1<<21)
1627# define RADEON_SCLK_FORCE_IDCT (1<<22)
1628# define RADEON_SCLK_FORCE_VIP (1<<23)
1629# define RADEON_SCLK_FORCE_RE (1<<24)
1630# define RADEON_SCLK_FORCE_PB (1<<25)
1631# define RADEON_SCLK_FORCE_TAM (1<<26)
1632# define RADEON_SCLK_FORCE_TDM (1<<27)
1633# define RADEON_SCLK_FORCE_RB (1<<28)
1634# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
1635# define RADEON_SCLK_FORCE_SUBPIC (1<<30)
1636# define RADEON_SCLK_FORCE_OV0 (1<<31)
1637# define R300_SCLK_FORCE_VAP (1<<21)
1638# define R300_SCLK_FORCE_SR (1<<25)
1639# define R300_SCLK_FORCE_PX (1<<26)
1640# define R300_SCLK_FORCE_TX (1<<27)
1641# define R300_SCLK_FORCE_US (1<<28)
1642# define R300_SCLK_FORCE_SU (1<<30)
1643#define R300_SCLK_CNTL2 0x1e /* PLL */
1644# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
1645# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
1646# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
1647# define R300_SCLK_FORCE_TCL (1<<13)
1648# define R300_SCLK_FORCE_CBA (1<<14)
1649# define R300_SCLK_FORCE_GA (1<<15)
1650#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
1651# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
1652# define RADEON_SCLK_MORE_FORCEON 0x0700
1653#define RADEON_SDRAM_MODE_REG 0x0158
1654#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
1655#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
1656#define RADEON_SNAPSHOT_F_COUNT 0x0244
1657#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
1658#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
1659#define RADEON_SRC_OFFSET 0x15ac
1660#define RADEON_SRC_PITCH 0x15b0
1661#define RADEON_SRC_PITCH_OFFSET 0x1428
1662#define RADEON_SRC_SC_BOTTOM 0x165c
1663#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
1664#define RADEON_SRC_SC_RIGHT 0x1654
1665#define RADEON_SRC_X 0x1414
1666#define RADEON_SRC_X_Y 0x1590
1667#define RADEON_SRC_Y 0x1418
1668#define RADEON_SRC_Y_X 0x1434
1669#define RADEON_STATUS 0x0f06 /* PCI */
1670#define RADEON_SUBPIC_CNTL 0x0540 /* ? */
1671#define RADEON_SUB_CLASS 0x0f0a /* PCI */
1672#define RADEON_SURFACE_CNTL 0x0b00
1673# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
1674# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
1675# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
1676# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
1677# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
1678#define RADEON_SURFACE0_INFO 0x0b0c
1679# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
1680# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
1681# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
1682# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
1683# define R200_SURF_TILE_NONE (0 << 16)
1684# define R200_SURF_TILE_COLOR_MACRO (1 << 16)
1685# define R200_SURF_TILE_COLOR_MICRO (2 << 16)
1686# define R200_SURF_TILE_COLOR_BOTH (3 << 16)
1687# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
1688# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
1689# define R300_SURF_TILE_NONE (0 << 16)
1690# define R300_SURF_TILE_COLOR_MACRO (1 << 16)
1691# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
1692# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
1693# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
1694# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
1695# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
1696#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
1697#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
1698#define RADEON_SURFACE1_INFO 0x0b1c
1699#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
1700#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
1701#define RADEON_SURFACE2_INFO 0x0b2c
1702#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
1703#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
1704#define RADEON_SURFACE3_INFO 0x0b3c
1705#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1706#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1707#define RADEON_SURFACE4_INFO 0x0b4c
1708#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1709#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1710#define RADEON_SURFACE5_INFO 0x0b5c
1711#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1712#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1713#define RADEON_SURFACE6_INFO 0x0b6c
1714#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1715#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1716#define RADEON_SURFACE7_INFO 0x0b7c
1717#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1718#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1719#define RADEON_SW_SEMAPHORE 0x013c
1720
1721#define RADEON_TEST_DEBUG_CNTL 0x0120
1722#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
1723
1724#define RADEON_TEST_DEBUG_MUX 0x0124
1725#define RADEON_TEST_DEBUG_OUT 0x012c
1726#define RADEON_TMDS_PLL_CNTL 0x02a8
1727#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
1728# define RADEON_TMDS_TRANSMITTER_PLLEN 1
1729# define RADEON_TMDS_TRANSMITTER_PLLRST 2
1730#define RADEON_TRAIL_BRES_DEC 0x1614
1731#define RADEON_TRAIL_BRES_ERR 0x160c
1732#define RADEON_TRAIL_BRES_INC 0x1610
1733#define RADEON_TRAIL_X 0x1618
1734#define RADEON_TRAIL_X_SUB 0x1620
1735
1736#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
1737# define RADEON_VCLK_SRC_SEL_MASK 0x03
1738# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
1739# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
1740# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
1741# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
1742# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
1743# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
1744# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1745
1746#define RADEON_VENDOR_ID 0x0f00 /* PCI */
1747#define RADEON_VGA_DDA_CONFIG 0x02e8
1748#define RADEON_VGA_DDA_ON_OFF 0x02ec
1749#define RADEON_VID_BUFFER_CONTROL 0x0900
1750#define RADEON_VIDEOMUX_CNTL 0x0190
1751
1752/* VIP bus */
1753#define RADEON_VIPH_CH0_DATA 0x0c00
1754#define RADEON_VIPH_CH1_DATA 0x0c04
1755#define RADEON_VIPH_CH2_DATA 0x0c08
1756#define RADEON_VIPH_CH3_DATA 0x0c0c
1757#define RADEON_VIPH_CH0_ADDR 0x0c10
1758#define RADEON_VIPH_CH1_ADDR 0x0c14
1759#define RADEON_VIPH_CH2_ADDR 0x0c18
1760#define RADEON_VIPH_CH3_ADDR 0x0c1c
1761#define RADEON_VIPH_CH0_SBCNT 0x0c20
1762#define RADEON_VIPH_CH1_SBCNT 0x0c24
1763#define RADEON_VIPH_CH2_SBCNT 0x0c28
1764#define RADEON_VIPH_CH3_SBCNT 0x0c2c
1765#define RADEON_VIPH_CH0_ABCNT 0x0c30
1766#define RADEON_VIPH_CH1_ABCNT 0x0c34
1767#define RADEON_VIPH_CH2_ABCNT 0x0c38
1768#define RADEON_VIPH_CH3_ABCNT 0x0c3c
1769#define RADEON_VIPH_CONTROL 0x0c40
1770# define RADEON_VIP_BUSY 0
1771# define RADEON_VIP_IDLE 1
1772# define RADEON_VIP_RESET 2
1773# define RADEON_VIPH_EN (1 << 21)
1774#define RADEON_VIPH_DV_LAT 0x0c44
1775#define RADEON_VIPH_BM_CHUNK 0x0c48
1776#define RADEON_VIPH_DV_INT 0x0c4c
1777#define RADEON_VIPH_TIMEOUT_STAT 0x0c50
1778#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
1779#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
1780#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
1781
1782#define RADEON_VIPH_REG_DATA 0x0084
1783#define RADEON_VIPH_REG_ADDR 0x0080
1784
1785
1786#define RADEON_WAIT_UNTIL 0x1720
1787# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1788# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
1789# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
1790# define RADEON_WAIT_CRTC_VLINE (1 << 3)
1791# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
1792# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
1793# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
1794# define RADEON_WAIT_OV0_FLIP (1 << 11)
1795# define RADEON_WAIT_AGP_FLUSH (1 << 13)
1796# define RADEON_WAIT_2D_IDLE (1 << 14)
1797# define RADEON_WAIT_3D_IDLE (1 << 15)
1798# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1799# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1800# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1801# define RADEON_CMDFIFO_ENTRIES_SHIFT 10
1802# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
1803# define RADEON_WAIT_VAP_IDLE (1 << 28)
1804# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
1805# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
1806# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
1807
1808#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
1809#define RADEON_XCLK_CNTL 0x000d /* PLL */
1810#define RADEON_XDLL_CNTL 0x000c /* PLL */
1811#define RADEON_XPLL_CNTL 0x000b /* PLL */
1812
1813
1814
1815 /* Registers for 3D/TCL */
1816#define RADEON_PP_BORDER_COLOR_0 0x1d40
1817#define RADEON_PP_BORDER_COLOR_1 0x1d44
1818#define RADEON_PP_BORDER_COLOR_2 0x1d48
1819#define RADEON_PP_CNTL 0x1c38
1820# define RADEON_STIPPLE_ENABLE (1 << 0)
1821# define RADEON_SCISSOR_ENABLE (1 << 1)
1822# define RADEON_PATTERN_ENABLE (1 << 2)
1823# define RADEON_SHADOW_ENABLE (1 << 3)
1824# define RADEON_TEX_ENABLE_MASK (0xf << 4)
1825# define RADEON_TEX_0_ENABLE (1 << 4)
1826# define RADEON_TEX_1_ENABLE (1 << 5)
1827# define RADEON_TEX_2_ENABLE (1 << 6)
1828# define RADEON_TEX_3_ENABLE (1 << 7)
1829# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
1830# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
1831# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
1832# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
1833# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
1834# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
1835# define RADEON_SPECULAR_ENABLE (1 << 21)
1836# define RADEON_FOG_ENABLE (1 << 22)
1837# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
1838# define RADEON_ANTI_ALIAS_NONE (0 << 24)
1839# define RADEON_ANTI_ALIAS_LINE (1 << 24)
1840# define RADEON_ANTI_ALIAS_POLY (2 << 24)
1841# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
1842# define RADEON_BUMP_MAP_ENABLE (1 << 26)
1843# define RADEON_BUMPED_MAP_T0 (0 << 27)
1844# define RADEON_BUMPED_MAP_T1 (1 << 27)
1845# define RADEON_BUMPED_MAP_T2 (2 << 27)
1846# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
1847# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
1848# define RADEON_MC_ENABLE (1 << 31)
1849#define RADEON_PP_FOG_COLOR 0x1c18
1850# define RADEON_FOG_COLOR_MASK 0x00ffffff
1851# define RADEON_FOG_VERTEX (0 << 24)
1852# define RADEON_FOG_TABLE (1 << 24)
1853# define RADEON_FOG_USE_DEPTH (0 << 25)
1854# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
1855# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
1856#define RADEON_PP_LUM_MATRIX 0x1d00
1857#define RADEON_PP_MISC 0x1c14
1858# define RADEON_REF_ALPHA_MASK 0x000000ff
1859# define RADEON_ALPHA_TEST_FAIL (0 << 8)
1860# define RADEON_ALPHA_TEST_LESS (1 << 8)
1861# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
1862# define RADEON_ALPHA_TEST_EQUAL (3 << 8)
1863# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
1864# define RADEON_ALPHA_TEST_GREATER (5 << 8)
1865# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
1866# define RADEON_ALPHA_TEST_PASS (7 << 8)
1867# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
1868# define RADEON_CHROMA_FUNC_FAIL (0 << 16)
1869# define RADEON_CHROMA_FUNC_PASS (1 << 16)
1870# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
1871# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
1872# define RADEON_CHROMA_KEY_NEAREST (0 << 18)
1873# define RADEON_CHROMA_KEY_ZERO (1 << 18)
1874# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
1875# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
1876# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
1877# define RADEON_SHADOW_PASS_1 (0 << 22)
1878# define RADEON_SHADOW_PASS_2 (1 << 22)
1879# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
1880# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
1881#define RADEON_PP_ROT_MATRIX_0 0x1d58
1882#define RADEON_PP_ROT_MATRIX_1 0x1d5c
1883#define RADEON_PP_TXFILTER_0 0x1c54
1884#define RADEON_PP_TXFILTER_1 0x1c6c
1885#define RADEON_PP_TXFILTER_2 0x1c84
1886# define RADEON_MAG_FILTER_NEAREST (0 << 0)
1887# define RADEON_MAG_FILTER_LINEAR (1 << 0)
1888# define RADEON_MAG_FILTER_MASK (1 << 0)
1889# define RADEON_MIN_FILTER_NEAREST (0 << 1)
1890# define RADEON_MIN_FILTER_LINEAR (1 << 1)
1891# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
1892# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
1893# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
1894# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
1895# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
1896# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
1897# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
1898# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
1899# define RADEON_MIN_FILTER_MASK (15 << 1)
1900# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
1901# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
1902# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
1903# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
1904# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
1905# define RADEON_MAX_ANISO_MASK (7 << 5)
1906# define RADEON_LOD_BIAS_MASK (0xff << 8)
1907# define RADEON_LOD_BIAS_SHIFT 8
1908# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
1909# define RADEON_MAX_MIP_LEVEL_SHIFT 16
1910# define RADEON_YUV_TO_RGB (1 << 20)
1911# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
1912# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
1913# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
1914# define RADEON_WRAPEN_S (1 << 22)
1915# define RADEON_CLAMP_S_WRAP (0 << 23)
1916# define RADEON_CLAMP_S_MIRROR (1 << 23)
1917# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
1918# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
1919# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
1920# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
1921# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
1922# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
1923# define RADEON_CLAMP_S_MASK (7 << 23)
1924# define RADEON_WRAPEN_T (1 << 26)
1925# define RADEON_CLAMP_T_WRAP (0 << 27)
1926# define RADEON_CLAMP_T_MIRROR (1 << 27)
1927# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
1928# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
1929# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
1930# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
1931# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
1932# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
1933# define RADEON_CLAMP_T_MASK (7 << 27)
1934# define RADEON_BORDER_MODE_OGL (0 << 31)
1935# define RADEON_BORDER_MODE_D3D (1 << 31)
1936#define RADEON_PP_TXFORMAT_0 0x1c58
1937#define RADEON_PP_TXFORMAT_1 0x1c70
1938#define RADEON_PP_TXFORMAT_2 0x1c88
1939# define RADEON_TXFORMAT_I8 (0 << 0)
1940# define RADEON_TXFORMAT_AI88 (1 << 0)
1941# define RADEON_TXFORMAT_RGB332 (2 << 0)
1942# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
1943# define RADEON_TXFORMAT_RGB565 (4 << 0)
1944# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
1945# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
1946# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
1947# define RADEON_TXFORMAT_Y8 (8 << 0)
1948# define RADEON_TXFORMAT_VYUY422 (10 << 0)
1949# define RADEON_TXFORMAT_YVYU422 (11 << 0)
1950# define RADEON_TXFORMAT_DXT1 (12 << 0)
1951# define RADEON_TXFORMAT_DXT23 (14 << 0)
1952# define RADEON_TXFORMAT_DXT45 (15 << 0)
Dave Airlie551ebd82009-09-01 15:25:57 +10001953# define RADEON_TXFORMAT_SHADOW16 (16 << 0)
1954# define RADEON_TXFORMAT_SHADOW32 (17 << 0)
1955# define RADEON_TXFORMAT_DUDV88 (18 << 0)
1956# define RADEON_TXFORMAT_LDUDV655 (19 << 0)
1957# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001958# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1959# define RADEON_TXFORMAT_FORMAT_SHIFT 0
1960# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
1961# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
1962# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
1963# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
1964# define RADEON_TXFORMAT_WIDTH_SHIFT 8
1965# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
1966# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
1967# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
1968# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
1969# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
1970# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
1971# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
1972# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
1973# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
1974# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
1975# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
1976# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
1977# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
1978# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
1979# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
1980# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
1981# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
1982# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
1983#define RADEON_PP_CUBIC_FACES_0 0x1d24
1984#define RADEON_PP_CUBIC_FACES_1 0x1d28
1985#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1986# define RADEON_FACE_WIDTH_1_SHIFT 0
1987# define RADEON_FACE_HEIGHT_1_SHIFT 4
1988# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
1989# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
1990# define RADEON_FACE_WIDTH_2_SHIFT 8
1991# define RADEON_FACE_HEIGHT_2_SHIFT 12
1992# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
1993# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
1994# define RADEON_FACE_WIDTH_3_SHIFT 16
1995# define RADEON_FACE_HEIGHT_3_SHIFT 20
1996# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
1997# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
1998# define RADEON_FACE_WIDTH_4_SHIFT 24
1999# define RADEON_FACE_HEIGHT_4_SHIFT 28
2000# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
2001# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
2002
2003#define RADEON_PP_TXOFFSET_0 0x1c5c
2004#define RADEON_PP_TXOFFSET_1 0x1c74
2005#define RADEON_PP_TXOFFSET_2 0x1c8c
2006# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
2007# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
2008# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
2009# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
2010# define RADEON_TXO_MACRO_LINEAR (0 << 2)
2011# define RADEON_TXO_MACRO_TILE (1 << 2)
2012# define RADEON_TXO_MICRO_LINEAR (0 << 3)
2013# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
2014# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
2015# define RADEON_TXO_OFFSET_MASK 0xffffffe0
2016# define RADEON_TXO_OFFSET_SHIFT 5
2017
2018#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
2019#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
2020#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
2021#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
2022#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
2023#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
2024#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
2025#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
2026#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
2027#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
2028#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
2029#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
2030#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
2031#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
2032#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
2033
2034#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
2035#define RADEON_PP_TEX_SIZE_1 0x1d0c
2036#define RADEON_PP_TEX_SIZE_2 0x1d14
2037# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
2038# define RADEON_TEX_USIZE_SHIFT 0
2039# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
2040# define RADEON_TEX_VSIZE_SHIFT 16
2041# define RADEON_SIGNED_RGB_MASK (1 << 30)
2042# define RADEON_SIGNED_RGB_SHIFT 30
2043# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
2044# define RADEON_SIGNED_ALPHA_SHIFT 31
2045#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
2046#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
2047#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
2048/* note: bits 13-5: 32 byte aligned stride of texture map */
2049
2050#define RADEON_PP_TXCBLEND_0 0x1c60
2051#define RADEON_PP_TXCBLEND_1 0x1c78
2052#define RADEON_PP_TXCBLEND_2 0x1c90
2053# define RADEON_COLOR_ARG_A_SHIFT 0
2054# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
2055# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
2056# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
2057# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
2058# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
2059# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
2060# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
2061# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
2062# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
2063# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
2064# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
2065# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
2066# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
2067# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
2068# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
2069# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
2070# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
2071# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
2072# define RADEON_COLOR_ARG_B_SHIFT 5
2073# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
2074# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
2075# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
2076# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
2077# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
2078# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
2079# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
2080# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
2081# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
2082# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
2083# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
2084# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
2085# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
2086# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
2087# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
2088# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
2089# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
2090# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
2091# define RADEON_COLOR_ARG_C_SHIFT 10
2092# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
2093# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
2094# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
2095# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
2096# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
2097# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
2098# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
2099# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
2100# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
2101# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
2102# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
2103# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
2104# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
2105# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
2106# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
2107# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
2108# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
2109# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
2110# define RADEON_COMP_ARG_A (1 << 15)
2111# define RADEON_COMP_ARG_A_SHIFT 15
2112# define RADEON_COMP_ARG_B (1 << 16)
2113# define RADEON_COMP_ARG_B_SHIFT 16
2114# define RADEON_COMP_ARG_C (1 << 17)
2115# define RADEON_COMP_ARG_C_SHIFT 17
2116# define RADEON_BLEND_CTL_MASK (7 << 18)
2117# define RADEON_BLEND_CTL_ADD (0 << 18)
2118# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
2119# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
2120# define RADEON_BLEND_CTL_BLEND (3 << 18)
2121# define RADEON_BLEND_CTL_DOT3 (4 << 18)
2122# define RADEON_SCALE_SHIFT 21
2123# define RADEON_SCALE_MASK (3 << 21)
2124# define RADEON_SCALE_1X (0 << 21)
2125# define RADEON_SCALE_2X (1 << 21)
2126# define RADEON_SCALE_4X (2 << 21)
2127# define RADEON_CLAMP_TX (1 << 23)
2128# define RADEON_T0_EQ_TCUR (1 << 24)
2129# define RADEON_T1_EQ_TCUR (1 << 25)
2130# define RADEON_T2_EQ_TCUR (1 << 26)
2131# define RADEON_T3_EQ_TCUR (1 << 27)
2132# define RADEON_COLOR_ARG_MASK 0x1f
2133# define RADEON_COMP_ARG_SHIFT 15
2134#define RADEON_PP_TXABLEND_0 0x1c64
2135#define RADEON_PP_TXABLEND_1 0x1c7c
2136#define RADEON_PP_TXABLEND_2 0x1c94
2137# define RADEON_ALPHA_ARG_A_SHIFT 0
2138# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
2139# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
2140# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
2141# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
2142# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
2143# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
2144# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
2145# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
2146# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
2147# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
2148# define RADEON_ALPHA_ARG_B_SHIFT 4
2149# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
2150# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
2151# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
2152# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
2153# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
2154# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
2155# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
2156# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
2157# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
2158# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
2159# define RADEON_ALPHA_ARG_C_SHIFT 8
2160# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
2161# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
2162# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
2163# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
2164# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
2165# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
2166# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
2167# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
2168# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
2169# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
2170# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
2171# define RADEON_ALPHA_ARG_MASK 0xf
2172
2173#define RADEON_PP_TFACTOR_0 0x1c68
2174#define RADEON_PP_TFACTOR_1 0x1c80
2175#define RADEON_PP_TFACTOR_2 0x1c98
2176
2177#define RADEON_RB3D_BLENDCNTL 0x1c20
2178# define RADEON_COMB_FCN_MASK (3 << 12)
2179# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
2180# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
2181# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
2182# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
2183# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
2184# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
2185# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
2186# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
2187# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
2188# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
2189# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
2190# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
2191# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
2192# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
2193# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
2194# define RADEON_SRC_BLEND_MASK (63 << 16)
2195# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
2196# define RADEON_DST_BLEND_GL_ONE (33 << 24)
2197# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
2198# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
2199# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
2200# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
2201# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
2202# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
2203# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
2204# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
2205# define RADEON_DST_BLEND_MASK (63 << 24)
2206#define RADEON_RB3D_CNTL 0x1c3c
2207# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
2208# define RADEON_PLANE_MASK_ENABLE (1 << 1)
2209# define RADEON_DITHER_ENABLE (1 << 2)
2210# define RADEON_ROUND_ENABLE (1 << 3)
2211# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
2212# define RADEON_DITHER_INIT (1 << 5)
2213# define RADEON_ROP_ENABLE (1 << 6)
2214# define RADEON_STENCIL_ENABLE (1 << 7)
2215# define RADEON_Z_ENABLE (1 << 8)
Dave Airlie551ebd82009-09-01 15:25:57 +10002216# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002217# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10
2218
2219# define RADEON_COLOR_FORMAT_ARGB1555 3
2220# define RADEON_COLOR_FORMAT_RGB565 4
2221# define RADEON_COLOR_FORMAT_ARGB8888 6
2222# define RADEON_COLOR_FORMAT_RGB332 7
2223# define RADEON_COLOR_FORMAT_Y8 8
2224# define RADEON_COLOR_FORMAT_RGB8 9
2225# define RADEON_COLOR_FORMAT_YUV422_VYUY 11
2226# define RADEON_COLOR_FORMAT_YUV422_YVYU 12
2227# define RADEON_COLOR_FORMAT_aYUV444 14
2228# define RADEON_COLOR_FORMAT_ARGB4444 15
2229
2230# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
2231#define RADEON_RB3D_COLOROFFSET 0x1c40
2232# define RADEON_COLOROFFSET_MASK 0xfffffff0
2233#define RADEON_RB3D_COLORPITCH 0x1c48
2234# define RADEON_COLORPITCH_MASK 0x000001ff8
2235# define RADEON_COLOR_TILE_ENABLE (1 << 16)
2236# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
2237# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
2238# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
2239# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
2240#define RADEON_RB3D_DEPTHOFFSET 0x1c24
2241#define RADEON_RB3D_DEPTHPITCH 0x1c28
2242# define RADEON_DEPTHPITCH_MASK 0x00001ff8
2243# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
2244# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
2245# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
2246#define RADEON_RB3D_PLANEMASK 0x1d84
2247#define RADEON_RB3D_ROPCNTL 0x1d80
2248# define RADEON_ROP_MASK (15 << 8)
2249# define RADEON_ROP_CLEAR (0 << 8)
2250# define RADEON_ROP_NOR (1 << 8)
2251# define RADEON_ROP_AND_INVERTED (2 << 8)
2252# define RADEON_ROP_COPY_INVERTED (3 << 8)
2253# define RADEON_ROP_AND_REVERSE (4 << 8)
2254# define RADEON_ROP_INVERT (5 << 8)
2255# define RADEON_ROP_XOR (6 << 8)
2256# define RADEON_ROP_NAND (7 << 8)
2257# define RADEON_ROP_AND (8 << 8)
2258# define RADEON_ROP_EQUIV (9 << 8)
2259# define RADEON_ROP_NOOP (10 << 8)
2260# define RADEON_ROP_OR_INVERTED (11 << 8)
2261# define RADEON_ROP_COPY (12 << 8)
2262# define RADEON_ROP_OR_REVERSE (13 << 8)
2263# define RADEON_ROP_OR (14 << 8)
2264# define RADEON_ROP_SET (15 << 8)
2265#define RADEON_RB3D_STENCILREFMASK 0x1d7c
2266# define RADEON_STENCIL_REF_SHIFT 0
2267# define RADEON_STENCIL_REF_MASK (0xff << 0)
2268# define RADEON_STENCIL_MASK_SHIFT 16
2269# define RADEON_STENCIL_VALUE_MASK (0xff << 16)
2270# define RADEON_STENCIL_WRITEMASK_SHIFT 24
2271# define RADEON_STENCIL_WRITE_MASK (0xff << 24)
2272#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
2273# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
2274# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
2275# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
2276# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
2277# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
2278# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
2279# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
2280# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
2281# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
2282# define RADEON_Z_TEST_NEVER (0 << 4)
2283# define RADEON_Z_TEST_LESS (1 << 4)
2284# define RADEON_Z_TEST_LEQUAL (2 << 4)
2285# define RADEON_Z_TEST_EQUAL (3 << 4)
2286# define RADEON_Z_TEST_GEQUAL (4 << 4)
2287# define RADEON_Z_TEST_GREATER (5 << 4)
2288# define RADEON_Z_TEST_NEQUAL (6 << 4)
2289# define RADEON_Z_TEST_ALWAYS (7 << 4)
2290# define RADEON_Z_TEST_MASK (7 << 4)
2291# define RADEON_STENCIL_TEST_NEVER (0 << 12)
2292# define RADEON_STENCIL_TEST_LESS (1 << 12)
2293# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
2294# define RADEON_STENCIL_TEST_EQUAL (3 << 12)
2295# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
2296# define RADEON_STENCIL_TEST_GREATER (5 << 12)
2297# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
2298# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
2299# define RADEON_STENCIL_TEST_MASK (0x7 << 12)
2300# define RADEON_STENCIL_FAIL_KEEP (0 << 16)
2301# define RADEON_STENCIL_FAIL_ZERO (1 << 16)
2302# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
2303# define RADEON_STENCIL_FAIL_INC (3 << 16)
2304# define RADEON_STENCIL_FAIL_DEC (4 << 16)
2305# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
2306# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
2307# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
2308# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
2309# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
2310# define RADEON_STENCIL_ZPASS_INC (3 << 20)
2311# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
2312# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
2313# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
2314# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
2315# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
2316# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
2317# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
2318# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
2319# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
2320# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
2321# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
2322# define RADEON_FORCE_Z_DIRTY (1 << 29)
2323# define RADEON_Z_WRITE_ENABLE (1 << 30)
2324#define RADEON_RE_LINE_PATTERN 0x1cd0
2325# define RADEON_LINE_PATTERN_MASK 0x0000ffff
2326# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
2327# define RADEON_LINE_PATTERN_START_SHIFT 24
2328# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
2329# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
2330# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
2331#define RADEON_RE_LINE_STATE 0x1cd4
2332# define RADEON_LINE_CURRENT_PTR_SHIFT 0
2333# define RADEON_LINE_CURRENT_COUNT_SHIFT 8
2334#define RADEON_RE_MISC 0x26c4
2335# define RADEON_STIPPLE_COORD_MASK 0x1f
2336# define RADEON_STIPPLE_X_OFFSET_SHIFT 0
2337# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
2338# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
2339# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
2340# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
2341# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
2342#define RADEON_RE_SOLID_COLOR 0x1c1c
2343#define RADEON_RE_TOP_LEFT 0x26c0
2344# define RADEON_RE_LEFT_SHIFT 0
2345# define RADEON_RE_TOP_SHIFT 16
2346#define RADEON_RE_WIDTH_HEIGHT 0x1c44
2347# define RADEON_RE_WIDTH_SHIFT 0
2348# define RADEON_RE_HEIGHT_SHIFT 16
2349
Dave Airlie17782d92009-08-21 10:07:54 +10002350#define RADEON_RB3D_ZPASS_DATA 0x3290
2351#define RADEON_RB3D_ZPASS_ADDR 0x3294
2352
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002353#define RADEON_SE_CNTL 0x1c4c
2354# define RADEON_FFACE_CULL_CW (0 << 0)
2355# define RADEON_FFACE_CULL_CCW (1 << 0)
2356# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
2357# define RADEON_BFACE_CULL (0 << 1)
2358# define RADEON_BFACE_SOLID (3 << 1)
2359# define RADEON_FFACE_CULL (0 << 3)
2360# define RADEON_FFACE_SOLID (3 << 3)
2361# define RADEON_FFACE_CULL_MASK (3 << 3)
2362# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
2363# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
2364# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
2365# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
2366# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
2367# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
2368# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
2369# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
2370# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
2371# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
2372# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
2373# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
2374# define RADEON_ALPHA_SHADE_MASK (3 << 10)
2375# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
2376# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
2377# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
2378# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
2379# define RADEON_FOG_SHADE_SOLID (0 << 14)
2380# define RADEON_FOG_SHADE_FLAT (1 << 14)
2381# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
2382# define RADEON_FOG_SHADE_MASK (3 << 14)
2383# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
2384# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
2385# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
2386# define RADEON_WIDELINE_ENABLE (1 << 20)
2387# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
2388# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
2389# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
2390# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
2391# define RADEON_ROUND_MODE_TRUNC (0 << 28)
2392# define RADEON_ROUND_MODE_ROUND (1 << 28)
2393# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
2394# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
2395# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
2396# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
2397# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
2398# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
2399#define R200_RE_CNTL 0x1c50
2400# define R200_STIPPLE_ENABLE 0x1
2401# define R200_SCISSOR_ENABLE 0x2
2402# define R200_PATTERN_ENABLE 0x4
2403# define R200_PERSPECTIVE_ENABLE 0x8
2404# define R200_POINT_SMOOTH 0x20
2405# define R200_VTX_STQ0_D3D 0x00010000
2406# define R200_VTX_STQ1_D3D 0x00040000
2407# define R200_VTX_STQ2_D3D 0x00100000
2408# define R200_VTX_STQ3_D3D 0x00400000
2409# define R200_VTX_STQ4_D3D 0x01000000
2410# define R200_VTX_STQ5_D3D 0x04000000
2411#define RADEON_SE_CNTL_STATUS 0x2140
2412# define RADEON_VC_NO_SWAP (0 << 0)
2413# define RADEON_VC_16BIT_SWAP (1 << 0)
2414# define RADEON_VC_32BIT_SWAP (2 << 0)
2415# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
2416# define RADEON_TCL_BYPASS (1 << 8)
2417#define RADEON_SE_COORD_FMT 0x1c50
2418# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
2419# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
2420# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
2421# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
2422# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
2423# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
2424# define RADEON_VTX_W0_NORMALIZE (1 << 12)
2425# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
2426# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
2427# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
2428# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
2429# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
2430# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
2431# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
2432#define RADEON_SE_LINE_WIDTH 0x1db8
2433#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
2434# define RADEON_LIGHTING_ENABLE (1 << 0)
2435# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
2436# define RADEON_LOCAL_VIEWER (1 << 2)
2437# define RADEON_NORMALIZE_NORMALS (1 << 3)
2438# define RADEON_RESCALE_NORMALS (1 << 4)
2439# define RADEON_SPECULAR_LIGHTS (1 << 5)
2440# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
2441# define RADEON_LIGHT_ALPHA (1 << 7)
2442# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
2443# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
2444# define RADEON_LM_SOURCE_STATE_PREMULT 0
2445# define RADEON_LM_SOURCE_STATE_MULT 1
2446# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
2447# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
2448# define RADEON_EMISSIVE_SOURCE_SHIFT 16
2449# define RADEON_AMBIENT_SOURCE_SHIFT 18
2450# define RADEON_DIFFUSE_SOURCE_SHIFT 20
2451# define RADEON_SPECULAR_SOURCE_SHIFT 22
2452#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
2453#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
2454#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
2455#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
2456#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
2457#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
2458#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
2459#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
2460#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
2461#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
2462#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
2463#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
2464#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
2465#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
2466#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
2467#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
2468#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
2469# define RADEON_MODELVIEW_0_SHIFT 0
2470# define RADEON_MODELVIEW_1_SHIFT 4
2471# define RADEON_MODELVIEW_2_SHIFT 8
2472# define RADEON_MODELVIEW_3_SHIFT 12
2473# define RADEON_IT_MODELVIEW_0_SHIFT 16
2474# define RADEON_IT_MODELVIEW_1_SHIFT 20
2475# define RADEON_IT_MODELVIEW_2_SHIFT 24
2476# define RADEON_IT_MODELVIEW_3_SHIFT 28
2477#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
2478# define RADEON_MODELPROJECT_0_SHIFT 0
2479# define RADEON_MODELPROJECT_1_SHIFT 4
2480# define RADEON_MODELPROJECT_2_SHIFT 8
2481# define RADEON_MODELPROJECT_3_SHIFT 12
2482# define RADEON_TEXMAT_0_SHIFT 16
2483# define RADEON_TEXMAT_1_SHIFT 20
2484# define RADEON_TEXMAT_2_SHIFT 24
2485# define RADEON_TEXMAT_3_SHIFT 28
2486
2487
2488#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
2489# define RADEON_TCL_VTX_W0 (1 << 0)
2490# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
2491# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
2492# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
2493# define RADEON_TCL_VTX_FP_SPEC (1 << 4)
2494# define RADEON_TCL_VTX_FP_FOG (1 << 5)
2495# define RADEON_TCL_VTX_PK_SPEC (1 << 6)
2496# define RADEON_TCL_VTX_ST0 (1 << 7)
2497# define RADEON_TCL_VTX_ST1 (1 << 8)
2498# define RADEON_TCL_VTX_Q1 (1 << 9)
2499# define RADEON_TCL_VTX_ST2 (1 << 10)
2500# define RADEON_TCL_VTX_Q2 (1 << 11)
2501# define RADEON_TCL_VTX_ST3 (1 << 12)
2502# define RADEON_TCL_VTX_Q3 (1 << 13)
2503# define RADEON_TCL_VTX_Q0 (1 << 14)
2504# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
2505# define RADEON_TCL_VTX_NORM0 (1 << 18)
2506# define RADEON_TCL_VTX_XY1 (1 << 27)
2507# define RADEON_TCL_VTX_Z1 (1 << 28)
2508# define RADEON_TCL_VTX_W1 (1 << 29)
2509# define RADEON_TCL_VTX_NORM1 (1 << 30)
2510# define RADEON_TCL_VTX_Z0 (1 << 31)
2511
2512#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
2513# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
2514# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
2515# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
2516# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
2517# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
2518# define RADEON_TCL_TEX_INPUT_TEX_0 0
2519# define RADEON_TCL_TEX_INPUT_TEX_1 1
2520# define RADEON_TCL_TEX_INPUT_TEX_2 2
2521# define RADEON_TCL_TEX_INPUT_TEX_3 3
2522# define RADEON_TCL_TEX_COMPUTED_TEX_0 8
2523# define RADEON_TCL_TEX_COMPUTED_TEX_1 9
2524# define RADEON_TCL_TEX_COMPUTED_TEX_2 10
2525# define RADEON_TCL_TEX_COMPUTED_TEX_3 11
2526# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
2527# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
2528# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
2529# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
2530
2531#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
2532# define RADEON_LIGHT_0_ENABLE (1 << 0)
2533# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
2534# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
2535# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
2536# define RADEON_LIGHT_0_IS_SPOT (1 << 4)
2537# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
2538# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
2539# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
2540# define RADEON_LIGHT_0_SHIFT 0
2541# define RADEON_LIGHT_1_ENABLE (1 << 16)
2542# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
2543# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
2544# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
2545# define RADEON_LIGHT_1_IS_SPOT (1 << 20)
2546# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
2547# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
2548# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
2549# define RADEON_LIGHT_1_SHIFT 16
2550#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
2551# define RADEON_LIGHT_2_SHIFT 0
2552# define RADEON_LIGHT_3_SHIFT 16
2553#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
2554# define RADEON_LIGHT_4_SHIFT 0
2555# define RADEON_LIGHT_5_SHIFT 16
2556#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
2557# define RADEON_LIGHT_6_SHIFT 0
2558# define RADEON_LIGHT_7_SHIFT 16
2559
2560#define RADEON_SE_TCL_SHININESS 0x2250
2561
2562#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
2563# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
2564# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
2565# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
2566# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
2567# define RADEON_TEXMAT_0_ENABLE (1 << 4)
2568# define RADEON_TEXMAT_1_ENABLE (1 << 5)
2569# define RADEON_TEXMAT_2_ENABLE (1 << 6)
2570# define RADEON_TEXMAT_3_ENABLE (1 << 7)
2571# define RADEON_TEXGEN_INPUT_MASK 0xf
2572# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
2573# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
2574# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
2575# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
2576# define RADEON_TEXGEN_INPUT_OBJ 4
2577# define RADEON_TEXGEN_INPUT_EYE 5
2578# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
2579# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
2580# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
2581# define RADEON_TEXGEN_0_INPUT_SHIFT 16
2582# define RADEON_TEXGEN_1_INPUT_SHIFT 20
2583# define RADEON_TEXGEN_2_INPUT_SHIFT 24
2584# define RADEON_TEXGEN_3_INPUT_SHIFT 28
2585
2586#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
2587# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
2588# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
2589# define RADEON_UCP_ENABLE_0 (1 << 2)
2590# define RADEON_UCP_ENABLE_1 (1 << 3)
2591# define RADEON_UCP_ENABLE_2 (1 << 4)
2592# define RADEON_UCP_ENABLE_3 (1 << 5)
2593# define RADEON_UCP_ENABLE_4 (1 << 6)
2594# define RADEON_UCP_ENABLE_5 (1 << 7)
2595# define RADEON_TCL_FOG_MASK (3 << 8)
2596# define RADEON_TCL_FOG_DISABLE (0 << 8)
2597# define RADEON_TCL_FOG_EXP (1 << 8)
2598# define RADEON_TCL_FOG_EXP2 (2 << 8)
2599# define RADEON_TCL_FOG_LINEAR (3 << 8)
2600# define RADEON_RNG_BASED_FOG (1 << 10)
2601# define RADEON_LIGHT_TWOSIDE (1 << 11)
2602# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
2603# define RADEON_BLEND_OP_COUNT_SHIFT 12
2604# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
2605# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
2606# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
2607# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
2608# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
2609# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
2610# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
2611# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
2612# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
2613# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
2614# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
2615# define RADEON_CULL_FRONT_IS_CW (0 << 28)
2616# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
2617# define RADEON_CULL_FRONT (1 << 29)
2618# define RADEON_CULL_BACK (1 << 30)
2619# define RADEON_FORCE_W_TO_ONE (1 << 31)
2620
2621#define RADEON_SE_VPORT_XSCALE 0x1d98
2622#define RADEON_SE_VPORT_XOFFSET 0x1d9c
2623#define RADEON_SE_VPORT_YSCALE 0x1da0
2624#define RADEON_SE_VPORT_YOFFSET 0x1da4
2625#define RADEON_SE_VPORT_ZSCALE 0x1da8
2626#define RADEON_SE_VPORT_ZOFFSET 0x1dac
2627#define RADEON_SE_ZBIAS_FACTOR 0x1db0
2628#define RADEON_SE_ZBIAS_CONSTANT 0x1db4
2629
2630#define RADEON_SE_VTX_FMT 0x2080
2631# define RADEON_SE_VTX_FMT_XY 0x00000000
2632# define RADEON_SE_VTX_FMT_W0 0x00000001
2633# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
2634# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
2635# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
2636# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
2637# define RADEON_SE_VTX_FMT_FPFOG 0x00000020
2638# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
2639# define RADEON_SE_VTX_FMT_ST0 0x00000080
2640# define RADEON_SE_VTX_FMT_ST1 0x00000100
2641# define RADEON_SE_VTX_FMT_Q1 0x00000200
2642# define RADEON_SE_VTX_FMT_ST2 0x00000400
2643# define RADEON_SE_VTX_FMT_Q2 0x00000800
2644# define RADEON_SE_VTX_FMT_ST3 0x00001000
2645# define RADEON_SE_VTX_FMT_Q3 0x00002000
2646# define RADEON_SE_VTX_FMT_Q0 0x00004000
2647# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
2648# define RADEON_SE_VTX_FMT_N0 0x00040000
2649# define RADEON_SE_VTX_FMT_XY1 0x08000000
2650# define RADEON_SE_VTX_FMT_Z1 0x10000000
2651# define RADEON_SE_VTX_FMT_W1 0x20000000
2652# define RADEON_SE_VTX_FMT_N1 0x40000000
2653# define RADEON_SE_VTX_FMT_Z 0x80000000
2654
2655#define RADEON_SE_VF_CNTL 0x2084
2656# define RADEON_VF_PRIM_TYPE_POINT_LIST 1
2657# define RADEON_VF_PRIM_TYPE_LINE_LIST 2
2658# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
2659# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
2660# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
2661# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
2662# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
2663# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
2664# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
2665# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
2666# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
2667# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
2668# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
2669# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
2670# define RADEON_VF_PRIM_TYPE_POLYGON 15
2671# define RADEON_VF_PRIM_WALK_STATE (0<<4)
2672# define RADEON_VF_PRIM_WALK_INDEX (1<<4)
2673# define RADEON_VF_PRIM_WALK_LIST (2<<4)
2674# define RADEON_VF_PRIM_WALK_DATA (3<<4)
2675# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
2676# define RADEON_VF_RADEON_MODE (1<<8)
2677# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
2678# define RADEON_VF_PROG_STREAM_ENA (1<<10)
2679# define RADEON_VF_INDEX_SIZE_SHIFT 11
2680# define RADEON_VF_NUM_VERTICES_SHIFT 16
2681
2682#define RADEON_SE_PORT_DATA0 0x2000
2683
2684#define R200_SE_VAP_CNTL 0x2080
2685# define R200_VAP_TCL_ENABLE 0x00000001
2686# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010
2687# define R200_VAP_FORCE_W_TO_ONE 0x00010000
2688# define R200_VAP_D3D_TEX_DEFAULT 0x00020000
2689# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18
2690# define R200_VAP_VF_MAX_VTX_NUM (9 << 18)
2691# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000
2692#define R200_VF_MAX_VTX_INDX 0x210c
2693#define R200_VF_MIN_VTX_INDX 0x2110
2694#define R200_SE_VTE_CNTL 0x20b0
2695# define R200_VPORT_X_SCALE_ENA 0x00000001
2696# define R200_VPORT_X_OFFSET_ENA 0x00000002
2697# define R200_VPORT_Y_SCALE_ENA 0x00000004
2698# define R200_VPORT_Y_OFFSET_ENA 0x00000008
2699# define R200_VPORT_Z_SCALE_ENA 0x00000010
2700# define R200_VPORT_Z_OFFSET_ENA 0x00000020
2701# define R200_VTX_XY_FMT 0x00000100
2702# define R200_VTX_Z_FMT 0x00000200
2703# define R200_VTX_W0_FMT 0x00000400
2704# define R200_VTX_W0_NORMALIZE 0x00000800
2705# define R200_VTX_ST_DENORMALIZED 0x00001000
2706#define R200_SE_VAP_CNTL_STATUS 0x2140
2707# define R200_VC_NO_SWAP (0 << 0)
2708# define R200_VC_16BIT_SWAP (1 << 0)
2709# define R200_VC_32BIT_SWAP (2 << 0)
2710#define R200_PP_TXFILTER_0 0x2c00
2711#define R200_PP_TXFILTER_1 0x2c20
2712#define R200_PP_TXFILTER_2 0x2c40
2713#define R200_PP_TXFILTER_3 0x2c60
2714#define R200_PP_TXFILTER_4 0x2c80
2715#define R200_PP_TXFILTER_5 0x2ca0
2716# define R200_MAG_FILTER_NEAREST (0 << 0)
2717# define R200_MAG_FILTER_LINEAR (1 << 0)
2718# define R200_MAG_FILTER_MASK (1 << 0)
2719# define R200_MIN_FILTER_NEAREST (0 << 1)
2720# define R200_MIN_FILTER_LINEAR (1 << 1)
2721# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
2722# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
2723# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
2724# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
2725# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)
2726# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)
2727# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
2728# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
2729# define R200_MIN_FILTER_MASK (15 << 1)
2730# define R200_MAX_ANISO_1_TO_1 (0 << 5)
2731# define R200_MAX_ANISO_2_TO_1 (1 << 5)
2732# define R200_MAX_ANISO_4_TO_1 (2 << 5)
2733# define R200_MAX_ANISO_8_TO_1 (3 << 5)
2734# define R200_MAX_ANISO_16_TO_1 (4 << 5)
2735# define R200_MAX_ANISO_MASK (7 << 5)
2736# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)
2737# define R200_MAX_MIP_LEVEL_SHIFT 16
2738# define R200_YUV_TO_RGB (1 << 20)
2739# define R200_YUV_TEMPERATURE_COOL (0 << 21)
2740# define R200_YUV_TEMPERATURE_HOT (1 << 21)
2741# define R200_YUV_TEMPERATURE_MASK (1 << 21)
2742# define R200_WRAPEN_S (1 << 22)
2743# define R200_CLAMP_S_WRAP (0 << 23)
2744# define R200_CLAMP_S_MIRROR (1 << 23)
2745# define R200_CLAMP_S_CLAMP_LAST (2 << 23)
2746# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
2747# define R200_CLAMP_S_CLAMP_BORDER (4 << 23)
2748# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
2749# define R200_CLAMP_S_CLAMP_GL (6 << 23)
2750# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
2751# define R200_CLAMP_S_MASK (7 << 23)
2752# define R200_WRAPEN_T (1 << 26)
2753# define R200_CLAMP_T_WRAP (0 << 27)
2754# define R200_CLAMP_T_MIRROR (1 << 27)
2755# define R200_CLAMP_T_CLAMP_LAST (2 << 27)
2756# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
2757# define R200_CLAMP_T_CLAMP_BORDER (4 << 27)
2758# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
2759# define R200_CLAMP_T_CLAMP_GL (6 << 27)
2760# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
2761# define R200_CLAMP_T_MASK (7 << 27)
2762# define R200_KILL_LT_ZERO (1 << 30)
2763# define R200_BORDER_MODE_OGL (0 << 31)
2764# define R200_BORDER_MODE_D3D (1 << 31)
2765#define R200_PP_TXFORMAT_0 0x2c04
2766#define R200_PP_TXFORMAT_1 0x2c24
2767#define R200_PP_TXFORMAT_2 0x2c44
2768#define R200_PP_TXFORMAT_3 0x2c64
2769#define R200_PP_TXFORMAT_4 0x2c84
2770#define R200_PP_TXFORMAT_5 0x2ca4
2771# define R200_TXFORMAT_I8 (0 << 0)
2772# define R200_TXFORMAT_AI88 (1 << 0)
2773# define R200_TXFORMAT_RGB332 (2 << 0)
2774# define R200_TXFORMAT_ARGB1555 (3 << 0)
2775# define R200_TXFORMAT_RGB565 (4 << 0)
2776# define R200_TXFORMAT_ARGB4444 (5 << 0)
2777# define R200_TXFORMAT_ARGB8888 (6 << 0)
2778# define R200_TXFORMAT_RGBA8888 (7 << 0)
2779# define R200_TXFORMAT_Y8 (8 << 0)
2780# define R200_TXFORMAT_AVYU4444 (9 << 0)
2781# define R200_TXFORMAT_VYUY422 (10 << 0)
2782# define R200_TXFORMAT_YVYU422 (11 << 0)
2783# define R200_TXFORMAT_DXT1 (12 << 0)
2784# define R200_TXFORMAT_DXT23 (14 << 0)
2785# define R200_TXFORMAT_DXT45 (15 << 0)
Dave Airlie551ebd82009-09-01 15:25:57 +10002786# define R200_TXFORMAT_DVDU88 (18 << 0)
2787# define R200_TXFORMAT_LDVDU655 (19 << 0)
2788# define R200_TXFORMAT_LDVDU8888 (20 << 0)
2789# define R200_TXFORMAT_GR1616 (21 << 0)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002790# define R200_TXFORMAT_ABGR8888 (22 << 0)
Dave Airlie551ebd82009-09-01 15:25:57 +10002791# define R200_TXFORMAT_BGR111110 (23 << 0)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002792# define R200_TXFORMAT_FORMAT_MASK (31 << 0)
2793# define R200_TXFORMAT_FORMAT_SHIFT 0
2794# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
2795# define R200_TXFORMAT_NON_POWER2 (1 << 7)
2796# define R200_TXFORMAT_WIDTH_MASK (15 << 8)
2797# define R200_TXFORMAT_WIDTH_SHIFT 8
2798# define R200_TXFORMAT_HEIGHT_MASK (15 << 12)
2799# define R200_TXFORMAT_HEIGHT_SHIFT 12
2800# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */
2801# define R200_TXFORMAT_F5_WIDTH_SHIFT 16
2802# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
2803# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20
2804# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
2805# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
2806# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
2807# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)
2808# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)
2809# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)
2810# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)
2811# define R200_TXFORMAT_ST_ROUTE_SHIFT 24
2812# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
2813# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
2814# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
2815#define R200_PP_TXFORMAT_X_0 0x2c08
2816#define R200_PP_TXFORMAT_X_1 0x2c28
2817#define R200_PP_TXFORMAT_X_2 0x2c48
2818#define R200_PP_TXFORMAT_X_3 0x2c68
2819#define R200_PP_TXFORMAT_X_4 0x2c88
2820#define R200_PP_TXFORMAT_X_5 0x2ca8
2821
2822#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */
2823#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */
2824#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */
2825#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */
2826#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */
2827#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */
2828
2829#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
2830#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */
2831#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */
2832#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */
2833#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
2834#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
2835
Dave Airlie551ebd82009-09-01 15:25:57 +10002836#define R200_PP_CUBIC_FACES_0 0x2c18
2837#define R200_PP_CUBIC_FACES_1 0x2c38
2838#define R200_PP_CUBIC_FACES_2 0x2c58
2839#define R200_PP_CUBIC_FACES_3 0x2c78
2840#define R200_PP_CUBIC_FACES_4 0x2c98
2841#define R200_PP_CUBIC_FACES_5 0x2cb8
2842
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002843#define R200_PP_TXOFFSET_0 0x2d00
2844# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
2845# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
2846# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)
2847# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
2848# define R200_TXO_MACRO_LINEAR (0 << 2)
2849# define R200_TXO_MACRO_TILE (1 << 2)
2850# define R200_TXO_MICRO_LINEAR (0 << 3)
2851# define R200_TXO_MICRO_TILE (1 << 3)
2852# define R200_TXO_OFFSET_MASK 0xffffffe0
2853# define R200_TXO_OFFSET_SHIFT 5
Dave Airlie551ebd82009-09-01 15:25:57 +10002854#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
2855#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
2856#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
2857#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
2858#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
2859
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002860#define R200_PP_TXOFFSET_1 0x2d18
Dave Airlie551ebd82009-09-01 15:25:57 +10002861#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
2862#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
2863#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
2864#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
2865#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
2866
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002867#define R200_PP_TXOFFSET_2 0x2d30
Dave Airlie551ebd82009-09-01 15:25:57 +10002868#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
2869#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
2870#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
2871#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
2872#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
2873
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002874#define R200_PP_TXOFFSET_3 0x2d48
Dave Airlie551ebd82009-09-01 15:25:57 +10002875#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
2876#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
2877#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
2878#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
2879#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002880#define R200_PP_TXOFFSET_4 0x2d60
Dave Airlie551ebd82009-09-01 15:25:57 +10002881#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
2882#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
2883#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
2884#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
2885#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002886#define R200_PP_TXOFFSET_5 0x2d78
Dave Airlie551ebd82009-09-01 15:25:57 +10002887#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
2888#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
2889#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
2890#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
2891#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002892
2893#define R200_PP_TFACTOR_0 0x2ee0
2894#define R200_PP_TFACTOR_1 0x2ee4
2895#define R200_PP_TFACTOR_2 0x2ee8
2896#define R200_PP_TFACTOR_3 0x2eec
2897#define R200_PP_TFACTOR_4 0x2ef0
2898#define R200_PP_TFACTOR_5 0x2ef4
2899
2900#define R200_PP_TXCBLEND_0 0x2f00
2901# define R200_TXC_ARG_A_ZERO (0)
2902# define R200_TXC_ARG_A_CURRENT_COLOR (2)
2903# define R200_TXC_ARG_A_CURRENT_ALPHA (3)
2904# define R200_TXC_ARG_A_DIFFUSE_COLOR (4)
2905# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)
2906# define R200_TXC_ARG_A_SPECULAR_COLOR (6)
2907# define R200_TXC_ARG_A_SPECULAR_ALPHA (7)
2908# define R200_TXC_ARG_A_TFACTOR_COLOR (8)
2909# define R200_TXC_ARG_A_TFACTOR_ALPHA (9)
2910# define R200_TXC_ARG_A_R0_COLOR (10)
2911# define R200_TXC_ARG_A_R0_ALPHA (11)
2912# define R200_TXC_ARG_A_R1_COLOR (12)
2913# define R200_TXC_ARG_A_R1_ALPHA (13)
2914# define R200_TXC_ARG_A_R2_COLOR (14)
2915# define R200_TXC_ARG_A_R2_ALPHA (15)
2916# define R200_TXC_ARG_A_R3_COLOR (16)
2917# define R200_TXC_ARG_A_R3_ALPHA (17)
2918# define R200_TXC_ARG_A_R4_COLOR (18)
2919# define R200_TXC_ARG_A_R4_ALPHA (19)
2920# define R200_TXC_ARG_A_R5_COLOR (20)
2921# define R200_TXC_ARG_A_R5_ALPHA (21)
2922# define R200_TXC_ARG_A_TFACTOR1_COLOR (26)
2923# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)
2924# define R200_TXC_ARG_A_MASK (31 << 0)
2925# define R200_TXC_ARG_A_SHIFT 0
2926# define R200_TXC_ARG_B_ZERO (0 << 5)
2927# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)
2928# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)
2929# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)
2930# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)
2931# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)
2932# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)
2933# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)
2934# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)
2935# define R200_TXC_ARG_B_R0_COLOR (10 << 5)
2936# define R200_TXC_ARG_B_R0_ALPHA (11 << 5)
2937# define R200_TXC_ARG_B_R1_COLOR (12 << 5)
2938# define R200_TXC_ARG_B_R1_ALPHA (13 << 5)
2939# define R200_TXC_ARG_B_R2_COLOR (14 << 5)
2940# define R200_TXC_ARG_B_R2_ALPHA (15 << 5)
2941# define R200_TXC_ARG_B_R3_COLOR (16 << 5)
2942# define R200_TXC_ARG_B_R3_ALPHA (17 << 5)
2943# define R200_TXC_ARG_B_R4_COLOR (18 << 5)
2944# define R200_TXC_ARG_B_R4_ALPHA (19 << 5)
2945# define R200_TXC_ARG_B_R5_COLOR (20 << 5)
2946# define R200_TXC_ARG_B_R5_ALPHA (21 << 5)
2947# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)
2948# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)
2949# define R200_TXC_ARG_B_MASK (31 << 5)
2950# define R200_TXC_ARG_B_SHIFT 5
2951# define R200_TXC_ARG_C_ZERO (0 << 10)
2952# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)
2953# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)
2954# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)
2955# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)
2956# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)
2957# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)
2958# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)
2959# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)
2960# define R200_TXC_ARG_C_R0_COLOR (10 << 10)
2961# define R200_TXC_ARG_C_R0_ALPHA (11 << 10)
2962# define R200_TXC_ARG_C_R1_COLOR (12 << 10)
2963# define R200_TXC_ARG_C_R1_ALPHA (13 << 10)
2964# define R200_TXC_ARG_C_R2_COLOR (14 << 10)
2965# define R200_TXC_ARG_C_R2_ALPHA (15 << 10)
2966# define R200_TXC_ARG_C_R3_COLOR (16 << 10)
2967# define R200_TXC_ARG_C_R3_ALPHA (17 << 10)
2968# define R200_TXC_ARG_C_R4_COLOR (18 << 10)
2969# define R200_TXC_ARG_C_R4_ALPHA (19 << 10)
2970# define R200_TXC_ARG_C_R5_COLOR (20 << 10)
2971# define R200_TXC_ARG_C_R5_ALPHA (21 << 10)
2972# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)
2973# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)
2974# define R200_TXC_ARG_C_MASK (31 << 10)
2975# define R200_TXC_ARG_C_SHIFT 10
2976# define R200_TXC_COMP_ARG_A (1 << 16)
2977# define R200_TXC_COMP_ARG_A_SHIFT (16)
2978# define R200_TXC_BIAS_ARG_A (1 << 17)
2979# define R200_TXC_SCALE_ARG_A (1 << 18)
2980# define R200_TXC_NEG_ARG_A (1 << 19)
2981# define R200_TXC_COMP_ARG_B (1 << 20)
2982# define R200_TXC_COMP_ARG_B_SHIFT (20)
2983# define R200_TXC_BIAS_ARG_B (1 << 21)
2984# define R200_TXC_SCALE_ARG_B (1 << 22)
2985# define R200_TXC_NEG_ARG_B (1 << 23)
2986# define R200_TXC_COMP_ARG_C (1 << 24)
2987# define R200_TXC_COMP_ARG_C_SHIFT (24)
2988# define R200_TXC_BIAS_ARG_C (1 << 25)
2989# define R200_TXC_SCALE_ARG_C (1 << 26)
2990# define R200_TXC_NEG_ARG_C (1 << 27)
2991# define R200_TXC_OP_MADD (0 << 28)
2992# define R200_TXC_OP_CND0 (2 << 28)
2993# define R200_TXC_OP_LERP (3 << 28)
2994# define R200_TXC_OP_DOT3 (4 << 28)
2995# define R200_TXC_OP_DOT4 (5 << 28)
2996# define R200_TXC_OP_CONDITIONAL (6 << 28)
2997# define R200_TXC_OP_DOT2_ADD (7 << 28)
2998# define R200_TXC_OP_MASK (7 << 28)
2999#define R200_PP_TXCBLEND2_0 0x2f04
3000# define R200_TXC_TFACTOR_SEL_SHIFT 0
3001# define R200_TXC_TFACTOR_SEL_MASK 0x7
3002# define R200_TXC_TFACTOR1_SEL_SHIFT 4
3003# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)
3004# define R200_TXC_SCALE_SHIFT 8
3005# define R200_TXC_SCALE_MASK (7 << 8)
3006# define R200_TXC_SCALE_1X (0 << 8)
3007# define R200_TXC_SCALE_2X (1 << 8)
3008# define R200_TXC_SCALE_4X (2 << 8)
3009# define R200_TXC_SCALE_8X (3 << 8)
3010# define R200_TXC_SCALE_INV2 (5 << 8)
3011# define R200_TXC_SCALE_INV4 (6 << 8)
3012# define R200_TXC_SCALE_INV8 (7 << 8)
3013# define R200_TXC_CLAMP_SHIFT 12
3014# define R200_TXC_CLAMP_MASK (3 << 12)
3015# define R200_TXC_CLAMP_WRAP (0 << 12)
3016# define R200_TXC_CLAMP_0_1 (1 << 12)
3017# define R200_TXC_CLAMP_8_8 (2 << 12)
3018# define R200_TXC_OUTPUT_REG_MASK (7 << 16)
3019# define R200_TXC_OUTPUT_REG_NONE (0 << 16)
3020# define R200_TXC_OUTPUT_REG_R0 (1 << 16)
3021# define R200_TXC_OUTPUT_REG_R1 (2 << 16)
3022# define R200_TXC_OUTPUT_REG_R2 (3 << 16)
3023# define R200_TXC_OUTPUT_REG_R3 (4 << 16)
3024# define R200_TXC_OUTPUT_REG_R4 (5 << 16)
3025# define R200_TXC_OUTPUT_REG_R5 (6 << 16)
3026# define R200_TXC_OUTPUT_MASK_MASK (7 << 20)
3027# define R200_TXC_OUTPUT_MASK_RGB (0 << 20)
3028# define R200_TXC_OUTPUT_MASK_RG (1 << 20)
3029# define R200_TXC_OUTPUT_MASK_RB (2 << 20)
3030# define R200_TXC_OUTPUT_MASK_R (3 << 20)
3031# define R200_TXC_OUTPUT_MASK_GB (4 << 20)
3032# define R200_TXC_OUTPUT_MASK_G (5 << 20)
3033# define R200_TXC_OUTPUT_MASK_B (6 << 20)
3034# define R200_TXC_OUTPUT_MASK_NONE (7 << 20)
3035# define R200_TXC_REPL_NORMAL 0
3036# define R200_TXC_REPL_RED 1
3037# define R200_TXC_REPL_GREEN 2
3038# define R200_TXC_REPL_BLUE 3
3039# define R200_TXC_REPL_ARG_A_SHIFT 26
3040# define R200_TXC_REPL_ARG_A_MASK (3 << 26)
3041# define R200_TXC_REPL_ARG_B_SHIFT 28
3042# define R200_TXC_REPL_ARG_B_MASK (3 << 28)
3043# define R200_TXC_REPL_ARG_C_SHIFT 30
3044# define R200_TXC_REPL_ARG_C_MASK (3 << 30)
3045#define R200_PP_TXABLEND_0 0x2f08
3046# define R200_TXA_ARG_A_ZERO (0)
3047# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */
3048# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */
3049# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)
3050# define R200_TXA_ARG_A_DIFFUSE_BLUE (5)
3051# define R200_TXA_ARG_A_SPECULAR_ALPHA (6)
3052# define R200_TXA_ARG_A_SPECULAR_BLUE (7)
3053# define R200_TXA_ARG_A_TFACTOR_ALPHA (8)
3054# define R200_TXA_ARG_A_TFACTOR_BLUE (9)
3055# define R200_TXA_ARG_A_R0_ALPHA (10)
3056# define R200_TXA_ARG_A_R0_BLUE (11)
3057# define R200_TXA_ARG_A_R1_ALPHA (12)
3058# define R200_TXA_ARG_A_R1_BLUE (13)
3059# define R200_TXA_ARG_A_R2_ALPHA (14)
3060# define R200_TXA_ARG_A_R2_BLUE (15)
3061# define R200_TXA_ARG_A_R3_ALPHA (16)
3062# define R200_TXA_ARG_A_R3_BLUE (17)
3063# define R200_TXA_ARG_A_R4_ALPHA (18)
3064# define R200_TXA_ARG_A_R4_BLUE (19)
3065# define R200_TXA_ARG_A_R5_ALPHA (20)
3066# define R200_TXA_ARG_A_R5_BLUE (21)
3067# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)
3068# define R200_TXA_ARG_A_TFACTOR1_BLUE (27)
3069# define R200_TXA_ARG_A_MASK (31 << 0)
3070# define R200_TXA_ARG_A_SHIFT 0
3071# define R200_TXA_ARG_B_ZERO (0 << 5)
3072# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */
3073# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */
3074# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)
3075# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)
3076# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)
3077# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)
3078# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)
3079# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)
3080# define R200_TXA_ARG_B_R0_ALPHA (10 << 5)
3081# define R200_TXA_ARG_B_R0_BLUE (11 << 5)
3082# define R200_TXA_ARG_B_R1_ALPHA (12 << 5)
3083# define R200_TXA_ARG_B_R1_BLUE (13 << 5)
3084# define R200_TXA_ARG_B_R2_ALPHA (14 << 5)
3085# define R200_TXA_ARG_B_R2_BLUE (15 << 5)
3086# define R200_TXA_ARG_B_R3_ALPHA (16 << 5)
3087# define R200_TXA_ARG_B_R3_BLUE (17 << 5)
3088# define R200_TXA_ARG_B_R4_ALPHA (18 << 5)
3089# define R200_TXA_ARG_B_R4_BLUE (19 << 5)
3090# define R200_TXA_ARG_B_R5_ALPHA (20 << 5)
3091# define R200_TXA_ARG_B_R5_BLUE (21 << 5)
3092# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)
3093# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)
3094# define R200_TXA_ARG_B_MASK (31 << 5)
3095# define R200_TXA_ARG_B_SHIFT 5
3096# define R200_TXA_ARG_C_ZERO (0 << 10)
3097# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */
3098# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */
3099# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)
3100# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)
3101# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)
3102# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)
3103# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)
3104# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)
3105# define R200_TXA_ARG_C_R0_ALPHA (10 << 10)
3106# define R200_TXA_ARG_C_R0_BLUE (11 << 10)
3107# define R200_TXA_ARG_C_R1_ALPHA (12 << 10)
3108# define R200_TXA_ARG_C_R1_BLUE (13 << 10)
3109# define R200_TXA_ARG_C_R2_ALPHA (14 << 10)
3110# define R200_TXA_ARG_C_R2_BLUE (15 << 10)
3111# define R200_TXA_ARG_C_R3_ALPHA (16 << 10)
3112# define R200_TXA_ARG_C_R3_BLUE (17 << 10)
3113# define R200_TXA_ARG_C_R4_ALPHA (18 << 10)
3114# define R200_TXA_ARG_C_R4_BLUE (19 << 10)
3115# define R200_TXA_ARG_C_R5_ALPHA (20 << 10)
3116# define R200_TXA_ARG_C_R5_BLUE (21 << 10)
3117# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)
3118# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)
3119# define R200_TXA_ARG_C_MASK (31 << 10)
3120# define R200_TXA_ARG_C_SHIFT 10
3121# define R200_TXA_COMP_ARG_A (1 << 16)
3122# define R200_TXA_COMP_ARG_A_SHIFT (16)
3123# define R200_TXA_BIAS_ARG_A (1 << 17)
3124# define R200_TXA_SCALE_ARG_A (1 << 18)
3125# define R200_TXA_NEG_ARG_A (1 << 19)
3126# define R200_TXA_COMP_ARG_B (1 << 20)
3127# define R200_TXA_COMP_ARG_B_SHIFT (20)
3128# define R200_TXA_BIAS_ARG_B (1 << 21)
3129# define R200_TXA_SCALE_ARG_B (1 << 22)
3130# define R200_TXA_NEG_ARG_B (1 << 23)
3131# define R200_TXA_COMP_ARG_C (1 << 24)
3132# define R200_TXA_COMP_ARG_C_SHIFT (24)
3133# define R200_TXA_BIAS_ARG_C (1 << 25)
3134# define R200_TXA_SCALE_ARG_C (1 << 26)
3135# define R200_TXA_NEG_ARG_C (1 << 27)
3136# define R200_TXA_OP_MADD (0 << 28)
3137# define R200_TXA_OP_CND0 (2 << 28)
3138# define R200_TXA_OP_LERP (3 << 28)
3139# define R200_TXA_OP_CONDITIONAL (6 << 28)
3140# define R200_TXA_OP_MASK (7 << 28)
3141#define R200_PP_TXABLEND2_0 0x2f0c
3142# define R200_TXA_TFACTOR_SEL_SHIFT 0
3143# define R200_TXA_TFACTOR_SEL_MASK 0x7
3144# define R200_TXA_TFACTOR1_SEL_SHIFT 4
3145# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)
3146# define R200_TXA_SCALE_SHIFT 8
3147# define R200_TXA_SCALE_MASK (7 << 8)
3148# define R200_TXA_SCALE_1X (0 << 8)
3149# define R200_TXA_SCALE_2X (1 << 8)
3150# define R200_TXA_SCALE_4X (2 << 8)
3151# define R200_TXA_SCALE_8X (3 << 8)
3152# define R200_TXA_SCALE_INV2 (5 << 8)
3153# define R200_TXA_SCALE_INV4 (6 << 8)
3154# define R200_TXA_SCALE_INV8 (7 << 8)
3155# define R200_TXA_CLAMP_SHIFT 12
3156# define R200_TXA_CLAMP_MASK (3 << 12)
3157# define R200_TXA_CLAMP_WRAP (0 << 12)
3158# define R200_TXA_CLAMP_0_1 (1 << 12)
3159# define R200_TXA_CLAMP_8_8 (2 << 12)
3160# define R200_TXA_OUTPUT_REG_MASK (7 << 16)
3161# define R200_TXA_OUTPUT_REG_NONE (0 << 16)
3162# define R200_TXA_OUTPUT_REG_R0 (1 << 16)
3163# define R200_TXA_OUTPUT_REG_R1 (2 << 16)
3164# define R200_TXA_OUTPUT_REG_R2 (3 << 16)
3165# define R200_TXA_OUTPUT_REG_R3 (4 << 16)
3166# define R200_TXA_OUTPUT_REG_R4 (5 << 16)
3167# define R200_TXA_OUTPUT_REG_R5 (6 << 16)
3168# define R200_TXA_DOT_ALPHA (1 << 20)
3169# define R200_TXA_REPL_NORMAL 0
3170# define R200_TXA_REPL_RED 1
3171# define R200_TXA_REPL_GREEN 2
3172# define R200_TXA_REPL_ARG_A_SHIFT 26
3173# define R200_TXA_REPL_ARG_A_MASK (3 << 26)
3174# define R200_TXA_REPL_ARG_B_SHIFT 28
3175# define R200_TXA_REPL_ARG_B_MASK (3 << 28)
3176# define R200_TXA_REPL_ARG_C_SHIFT 30
3177# define R200_TXA_REPL_ARG_C_MASK (3 << 30)
3178
3179#define R200_SE_VTX_FMT_0 0x2088
3180# define R200_VTX_XY 0 /* always have xy */
3181# define R200_VTX_Z0 (1<<0)
3182# define R200_VTX_W0 (1<<1)
3183# define R200_VTX_WEIGHT_COUNT_SHIFT (2)
3184# define R200_VTX_PV_MATRIX_SEL (1<<5)
3185# define R200_VTX_N0 (1<<6)
3186# define R200_VTX_POINT_SIZE (1<<7)
3187# define R200_VTX_DISCRETE_FOG (1<<8)
3188# define R200_VTX_SHININESS_0 (1<<9)
3189# define R200_VTX_SHININESS_1 (1<<10)
3190# define R200_VTX_COLOR_NOT_PRESENT 0
3191# define R200_VTX_PK_RGBA 1
3192# define R200_VTX_FP_RGB 2
3193# define R200_VTX_FP_RGBA 3
3194# define R200_VTX_COLOR_MASK 3
3195# define R200_VTX_COLOR_0_SHIFT 11
3196# define R200_VTX_COLOR_1_SHIFT 13
3197# define R200_VTX_COLOR_2_SHIFT 15
3198# define R200_VTX_COLOR_3_SHIFT 17
3199# define R200_VTX_COLOR_4_SHIFT 19
3200# define R200_VTX_COLOR_5_SHIFT 21
3201# define R200_VTX_COLOR_6_SHIFT 23
3202# define R200_VTX_COLOR_7_SHIFT 25
3203# define R200_VTX_XY1 (1<<28)
3204# define R200_VTX_Z1 (1<<29)
3205# define R200_VTX_W1 (1<<30)
3206# define R200_VTX_N1 (1<<31)
3207#define R200_SE_VTX_FMT_1 0x208c
3208# define R200_VTX_TEX0_COMP_CNT_SHIFT 0
3209# define R200_VTX_TEX1_COMP_CNT_SHIFT 3
3210# define R200_VTX_TEX2_COMP_CNT_SHIFT 6
3211# define R200_VTX_TEX3_COMP_CNT_SHIFT 9
3212# define R200_VTX_TEX4_COMP_CNT_SHIFT 12
3213# define R200_VTX_TEX5_COMP_CNT_SHIFT 15
3214
3215#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090
3216#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094
3217#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
3218# define R200_OUTPUT_XYZW (1<<0)
3219# define R200_OUTPUT_COLOR_0 (1<<8)
3220# define R200_OUTPUT_COLOR_1 (1<<9)
3221# define R200_OUTPUT_TEX_0 (1<<16)
3222# define R200_OUTPUT_TEX_1 (1<<17)
3223# define R200_OUTPUT_TEX_2 (1<<18)
3224# define R200_OUTPUT_TEX_3 (1<<19)
3225# define R200_OUTPUT_TEX_4 (1<<20)
3226# define R200_OUTPUT_TEX_5 (1<<21)
3227# define R200_OUTPUT_TEX_MASK (0x3f<<16)
3228# define R200_OUTPUT_DISCRETE_FOG (1<<24)
3229# define R200_OUTPUT_PT_SIZE (1<<25)
3230# define R200_FORCE_INORDER_PROC (1<<31)
3231#define R200_PP_CNTL_X 0x2cc4
3232#define R200_PP_TXMULTI_CTL_0 0x2c1c
Dave Airlie551ebd82009-09-01 15:25:57 +10003233#define R200_PP_TXMULTI_CTL_1 0x2c3c
3234#define R200_PP_TXMULTI_CTL_2 0x2c5c
3235#define R200_PP_TXMULTI_CTL_3 0x2c7c
3236#define R200_PP_TXMULTI_CTL_4 0x2c9c
3237#define R200_PP_TXMULTI_CTL_5 0x2cbc
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003238#define R200_SE_VTX_STATE_CNTL 0x2180
3239# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
3240
3241 /* Registers for CP and Microcode Engine */
3242#define RADEON_CP_ME_RAM_ADDR 0x07d4
3243#define RADEON_CP_ME_RAM_RADDR 0x07d8
3244#define RADEON_CP_ME_RAM_DATAH 0x07dc
3245#define RADEON_CP_ME_RAM_DATAL 0x07e0
3246
3247#define RADEON_CP_RB_BASE 0x0700
3248#define RADEON_CP_RB_CNTL 0x0704
3249# define RADEON_RB_BUFSZ_SHIFT 0
3250# define RADEON_RB_BUFSZ_MASK (0x3f << 0)
3251# define RADEON_RB_BLKSZ_SHIFT 8
3252# define RADEON_RB_BLKSZ_MASK (0x3f << 8)
Michel Dänzer4e484e72009-06-16 17:29:06 +02003253# define RADEON_BUF_SWAP_32BIT (1 << 17)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003254# define RADEON_MAX_FETCH_SHIFT 18
3255# define RADEON_MAX_FETCH_MASK (0x3 << 18)
3256# define RADEON_RB_NO_UPDATE (1 << 27)
3257# define RADEON_RB_RPTR_WR_ENA (1 << 31)
3258#define RADEON_CP_RB_RPTR_ADDR 0x070c
3259#define RADEON_CP_RB_RPTR 0x0710
3260#define RADEON_CP_RB_WPTR 0x0714
3261#define RADEON_CP_RB_RPTR_WR 0x071c
3262
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003263#define RADEON_SCRATCH_UMSK 0x0770
3264#define RADEON_SCRATCH_ADDR 0x0774
3265
3266#define R600_CP_RB_BASE 0xc100
3267#define R600_CP_RB_CNTL 0xc104
3268# define R600_RB_BUFSZ(x) ((x) << 0)
3269# define R600_RB_BLKSZ(x) ((x) << 8)
3270# define R600_RB_NO_UPDATE (1 << 27)
3271# define R600_RB_RPTR_WR_ENA (1 << 31)
3272#define R600_CP_RB_RPTR_WR 0xc108
3273#define R600_CP_RB_RPTR_ADDR 0xc10c
3274#define R600_CP_RB_RPTR_ADDR_HI 0xc110
3275#define R600_CP_RB_WPTR 0xc114
3276#define R600_CP_RB_WPTR_ADDR 0xc118
3277#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
3278#define R600_CP_RB_RPTR 0x8700
3279#define R600_CP_RB_WPTR_DELAY 0x8704
3280
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003281#define RADEON_CP_IB_BASE 0x0738
3282#define RADEON_CP_IB_BUFSZ 0x073c
3283
3284#define RADEON_CP_CSQ_CNTL 0x0740
3285# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
3286# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
3287# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
3288# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
3289# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
3290# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
3291# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
3292
3293#define R300_CP_RESYNC_ADDR 0x778
3294#define R300_CP_RESYNC_DATA 0x77c
3295
3296#define RADEON_CP_CSQ_STAT 0x07f8
3297# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
3298# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
3299# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
3300# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
3301#define RADEON_CP_CSQ2_STAT 0x07fc
3302#define RADEON_CP_CSQ_ADDR 0x07f0
3303#define RADEON_CP_CSQ_DATA 0x07f4
3304#define RADEON_CP_CSQ_APER_PRIMARY 0x1000
3305#define RADEON_CP_CSQ_APER_INDIRECT 0x1300
3306
3307#define RADEON_CP_RB_WPTR_DELAY 0x0718
3308# define RADEON_PRE_WRITE_TIMER_SHIFT 0
3309# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
3310#define RADEON_CP_CSQ_MODE 0x0744
3311# define RADEON_INDIRECT2_START_SHIFT 0
3312# define RADEON_INDIRECT2_START_MASK (0x7f << 0)
3313# define RADEON_INDIRECT1_START_SHIFT 8
3314# define RADEON_INDIRECT1_START_MASK (0x7f << 8)
3315
3316#define RADEON_AIC_CNTL 0x01d0
3317# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
3318# define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)
Alex Deucher3e5cb982009-10-16 12:21:24 -04003319# define RS400_MSI_REARM (1 << 3) /* rs400/rs480 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003320#define RADEON_AIC_LO_ADDR 0x01dc
3321#define RADEON_AIC_PT_BASE 0x01d8
3322#define RADEON_AIC_HI_ADDR 0x01e0
3323
3324
3325
3326 /* Constants */
3327/* #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 */
3328/* efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 */
3329
3330
3331
3332 /* CP packet types */
3333#define RADEON_CP_PACKET0 0x00000000
3334#define RADEON_CP_PACKET1 0x40000000
3335#define RADEON_CP_PACKET2 0x80000000
3336#define RADEON_CP_PACKET3 0xC0000000
3337# define RADEON_CP_PACKET_MASK 0xC0000000
3338# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
3339# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
3340# define RADEON_CP_PACKET0_REG_MASK 0x000007ff
3341# define R300_CP_PACKET0_REG_MASK 0x00001fff
Alex Deucher2f67c6e2009-09-25 16:35:11 -04003342# define R600_CP_PACKET0_REG_MASK 0x0000ffff
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003343# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
3344# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
3345
3346#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
3347
3348#define RADEON_CP_PACKET3_NOP 0xC0001000
3349#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
3350#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
3351#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
3352#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
3353#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
3354#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
3355#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
3356#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
3357#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
3358#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
3359#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
3360#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
3361#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
3362#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
3363#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
3364#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
3365#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
3366#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
3367#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
3368#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
3369#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
3370
3371
3372#define RADEON_CP_VC_FRMT_XY 0x00000000
3373#define RADEON_CP_VC_FRMT_W0 0x00000001
3374#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
3375#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
3376#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
3377#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
3378#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
3379#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
3380#define RADEON_CP_VC_FRMT_ST0 0x00000080
3381#define RADEON_CP_VC_FRMT_ST1 0x00000100
3382#define RADEON_CP_VC_FRMT_Q1 0x00000200
3383#define RADEON_CP_VC_FRMT_ST2 0x00000400
3384#define RADEON_CP_VC_FRMT_Q2 0x00000800
3385#define RADEON_CP_VC_FRMT_ST3 0x00001000
3386#define RADEON_CP_VC_FRMT_Q3 0x00002000
3387#define RADEON_CP_VC_FRMT_Q0 0x00004000
3388#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
3389#define RADEON_CP_VC_FRMT_N0 0x00040000
3390#define RADEON_CP_VC_FRMT_XY1 0x08000000
3391#define RADEON_CP_VC_FRMT_Z1 0x10000000
3392#define RADEON_CP_VC_FRMT_W1 0x20000000
3393#define RADEON_CP_VC_FRMT_N1 0x40000000
3394#define RADEON_CP_VC_FRMT_Z 0x80000000
3395
3396#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
3397#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
3398#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
3399#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
3400#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
3401#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
3402#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
3403#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
3404#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
3405#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
3406#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
3407#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
3408#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
3409#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
3410#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
3411#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
3412#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
3413#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
3414#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
3415#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
3416#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
3417#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
3418
3419#define RADEON_VS_MATRIX_0_ADDR 0
3420#define RADEON_VS_MATRIX_1_ADDR 4
3421#define RADEON_VS_MATRIX_2_ADDR 8
3422#define RADEON_VS_MATRIX_3_ADDR 12
3423#define RADEON_VS_MATRIX_4_ADDR 16
3424#define RADEON_VS_MATRIX_5_ADDR 20
3425#define RADEON_VS_MATRIX_6_ADDR 24
3426#define RADEON_VS_MATRIX_7_ADDR 28
3427#define RADEON_VS_MATRIX_8_ADDR 32
3428#define RADEON_VS_MATRIX_9_ADDR 36
3429#define RADEON_VS_MATRIX_10_ADDR 40
3430#define RADEON_VS_MATRIX_11_ADDR 44
3431#define RADEON_VS_MATRIX_12_ADDR 48
3432#define RADEON_VS_MATRIX_13_ADDR 52
3433#define RADEON_VS_MATRIX_14_ADDR 56
3434#define RADEON_VS_MATRIX_15_ADDR 60
3435#define RADEON_VS_LIGHT_AMBIENT_ADDR 64
3436#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
3437#define RADEON_VS_LIGHT_SPECULAR_ADDR 80
3438#define RADEON_VS_LIGHT_DIRPOS_ADDR 88
3439#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
3440#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
3441#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
3442#define RADEON_VS_UCP_ADDR 116
3443#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
3444#define RADEON_VS_FOG_PARAM_ADDR 123
3445#define RADEON_VS_EYE_VECTOR_ADDR 124
3446
3447#define RADEON_SS_LIGHT_DCD_ADDR 0
3448#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
3449#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
3450#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
3451#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
3452#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
3453#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
3454#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
3455#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
3456#define RADEON_SS_SHININESS 60
3457
3458#define RADEON_TV_MASTER_CNTL 0x0800
3459# define RADEON_TV_ASYNC_RST (1 << 0)
3460# define RADEON_CRT_ASYNC_RST (1 << 1)
3461# define RADEON_RESTART_PHASE_FIX (1 << 3)
3462# define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
3463# define RADEON_VIN_ASYNC_RST (1 << 5)
3464# define RADEON_AUD_ASYNC_RST (1 << 6)
3465# define RADEON_DVS_ASYNC_RST (1 << 7)
3466# define RADEON_CRT_FIFO_CE_EN (1 << 9)
3467# define RADEON_TV_FIFO_CE_EN (1 << 10)
3468# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
3469# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
3470# define RADEON_TV_ON (1 << 31)
3471#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
3472# define RADEON_Y_RED_EN (1 << 0)
3473# define RADEON_C_GRN_EN (1 << 1)
3474# define RADEON_CMP_BLU_EN (1 << 2)
3475# define RADEON_DAC_DITHER_EN (1 << 3)
3476# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
3477# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
3478# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
3479# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
3480#define RADEON_TV_RGB_CNTL 0x0804
3481# define RADEON_SWITCH_TO_BLUE (1 << 4)
3482# define RADEON_RGB_DITHER_EN (1 << 5)
3483# define RADEON_RGB_SRC_SEL_MASK (3 << 8)
3484# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
3485# define RADEON_RGB_SRC_SEL_RMX (1 << 8)
3486# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
3487# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
3488# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
3489# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
Dave Airlie4ce001a2009-08-13 16:32:14 +10003490# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)
3491# define RADEON_TVOUT_SCALE_EN (1 << 26)
3492# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003493#define RADEON_TV_SYNC_CNTL 0x0808
3494# define RADEON_SYNC_OE (1 << 0)
3495# define RADEON_SYNC_OUT (1 << 1)
3496# define RADEON_SYNC_IN (1 << 2)
3497# define RADEON_SYNC_PUB (1 << 3)
3498# define RADEON_SYNC_PD (1 << 4)
3499# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
3500#define RADEON_TV_HTOTAL 0x080c
3501#define RADEON_TV_HDISP 0x0810
3502#define RADEON_TV_HSTART 0x0818
3503#define RADEON_TV_HCOUNT 0x081C
3504#define RADEON_TV_VTOTAL 0x0820
3505#define RADEON_TV_VDISP 0x0824
3506#define RADEON_TV_VCOUNT 0x0828
3507#define RADEON_TV_FTOTAL 0x082c
3508#define RADEON_TV_FCOUNT 0x0830
3509#define RADEON_TV_FRESTART 0x0834
3510#define RADEON_TV_HRESTART 0x0838
3511#define RADEON_TV_VRESTART 0x083c
3512#define RADEON_TV_HOST_READ_DATA 0x0840
3513#define RADEON_TV_HOST_WRITE_DATA 0x0844
3514#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
3515# define RADEON_HOST_FIFO_RD (1 << 12)
3516# define RADEON_HOST_FIFO_RD_ACK (1 << 13)
3517# define RADEON_HOST_FIFO_WT (1 << 14)
3518# define RADEON_HOST_FIFO_WT_ACK (1 << 15)
3519#define RADEON_TV_VSCALER_CNTL1 0x084c
3520# define RADEON_UV_INC_MASK 0xffff
3521# define RADEON_UV_INC_SHIFT 0
3522# define RADEON_Y_W_EN (1 << 24)
3523# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
3524# define RADEON_Y_DEL_W_SIG_SHIFT 26
3525#define RADEON_TV_TIMING_CNTL 0x0850
3526# define RADEON_H_INC_MASK 0xfff
3527# define RADEON_H_INC_SHIFT 0
3528# define RADEON_REQ_Y_FIRST (1 << 19)
3529# define RADEON_FORCE_BURST_ALWAYS (1 << 21)
3530# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
3531# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
3532#define RADEON_TV_VSCALER_CNTL2 0x0854
3533# define RADEON_DITHER_MODE (1 << 0)
3534# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
3535# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
3536# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
3537#define RADEON_TV_Y_FALL_CNTL 0x0858
3538# define RADEON_Y_FALL_PING_PONG (1 << 16)
3539# define RADEON_Y_COEF_EN (1 << 17)
3540#define RADEON_TV_Y_RISE_CNTL 0x085c
3541# define RADEON_Y_RISE_PING_PONG (1 << 16)
3542#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
3543#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
3544# define RADEON_YUPSAMP_EN (1 << 0)
3545# define RADEON_UVUPSAMP_EN (1 << 2)
3546#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
3547# define RADEON_Y_GAIN_LIMIT_SHIFT 0
3548# define RADEON_UV_GAIN_LIMIT_SHIFT 16
3549#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
3550# define RADEON_Y_GAIN_SHIFT 0
3551# define RADEON_UV_GAIN_SHIFT 16
3552#define RADEON_TV_MODULATOR_CNTL1 0x0870
3553# define RADEON_YFLT_EN (1 << 2)
3554# define RADEON_UVFLT_EN (1 << 3)
3555# define RADEON_ALT_PHASE_EN (1 << 6)
3556# define RADEON_SYNC_TIP_LEVEL (1 << 7)
3557# define RADEON_BLANK_LEVEL_SHIFT 8
3558# define RADEON_SET_UP_LEVEL_SHIFT 16
3559# define RADEON_SLEW_RATE_LIMIT (1 << 23)
3560# define RADEON_CY_FILT_BLEND_SHIFT 28
3561#define RADEON_TV_MODULATOR_CNTL2 0x0874
3562# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
3563# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
3564# define RADEON_TV_V_BURST_LEVEL_SHIFT 16
3565#define RADEON_TV_CRC_CNTL 0x0890
3566#define RADEON_TV_UV_ADR 0x08ac
3567# define RADEON_MAX_UV_ADR_MASK 0x000000ff
3568# define RADEON_MAX_UV_ADR_SHIFT 0
3569# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
3570# define RADEON_TABLE1_BOT_ADR_SHIFT 8
3571# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
3572# define RADEON_TABLE3_TOP_ADR_SHIFT 16
3573# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
3574# define RADEON_HCODE_TABLE_SEL_SHIFT 25
3575# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
3576# define RADEON_VCODE_TABLE_SEL_SHIFT 27
3577# define RADEON_TV_MAX_FIFO_ADDR 0x1a7
3578# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
3579#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */
3580#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */
3581# define RADEON_TV_M0LO_MASK 0xff
3582# define RADEON_TV_M0HI_MASK 0x7
3583# define RADEON_TV_M0HI_SHIFT 18
3584# define RADEON_TV_N0LO_MASK 0x1ff
3585# define RADEON_TV_N0LO_SHIFT 8
3586# define RADEON_TV_N0HI_MASK 0x3
3587# define RADEON_TV_N0HI_SHIFT 21
3588# define RADEON_TV_P_MASK 0xf
3589# define RADEON_TV_P_SHIFT 24
3590# define RADEON_TV_SLIP_EN (1 << 23)
3591# define RADEON_TV_DTO_EN (1 << 28)
3592#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */
3593# define RADEON_TVPLL_RESET (1 << 1)
3594# define RADEON_TVPLL_SLEEP (1 << 3)
3595# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
3596# define RADEON_TVPCP_SHIFT 8
3597# define RADEON_TVPCP_MASK (7 << 8)
3598# define RADEON_TVPVG_SHIFT 11
3599# define RADEON_TVPVG_MASK (7 << 11)
3600# define RADEON_TVPDC_SHIFT 14
3601# define RADEON_TVPDC_MASK (3 << 14)
3602# define RADEON_TVPLL_TEST_DIS (1 << 31)
3603# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
3604
3605#define RS400_DISP2_REQ_CNTL1 0xe30
3606# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0
3607# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff
3608# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12
3609# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff
3610# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22
3611# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff
3612#define RS400_DISP2_REQ_CNTL2 0xe34
3613# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12
3614# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff
3615# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22
3616# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff
3617#define RS400_DMIF_MEM_CNTL1 0xe38
3618# define RS400_DISP2_START_ADR_SHIFT 0
3619# define RS400_DISP2_START_ADR_MASK 0x3ff
3620# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12
3621# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff
3622# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22
3623# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff
3624#define RS400_DISP1_REQ_CNTL1 0xe3c
3625# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0
3626# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff
3627# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12
3628# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff
3629# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22
3630# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff
3631
3632#define RADEON_PCIE_INDEX 0x0030
3633#define RADEON_PCIE_DATA 0x0034
3634#define RADEON_PCIE_TX_GART_CNTL 0x10
3635# define RADEON_PCIE_TX_GART_EN (1 << 0)
3636# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
3637# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
3638# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
3639# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
3640# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
3641# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
3642# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
3643#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
3644#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
3645#define RADEON_PCIE_TX_GART_BASE 0x13
3646#define RADEON_PCIE_TX_GART_START_LO 0x14
3647#define RADEON_PCIE_TX_GART_START_HI 0x15
3648#define RADEON_PCIE_TX_GART_END_LO 0x16
3649#define RADEON_PCIE_TX_GART_END_HI 0x17
3650#define RADEON_PCIE_TX_GART_ERROR 0x18
3651
3652#define RADEON_SCRATCH_REG0 0x15e0
3653#define RADEON_SCRATCH_REG1 0x15e4
3654#define RADEON_SCRATCH_REG2 0x15e8
3655#define RADEON_SCRATCH_REG3 0x15ec
3656#define RADEON_SCRATCH_REG4 0x15f0
3657#define RADEON_SCRATCH_REG5 0x15f4
3658
Alex Deucherf779b3e2009-08-19 19:11:39 -04003659#define RV530_GB_PIPE_SELECT2 0x4124
3660
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003661#endif