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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __ASM_ARM_SYSTEM_H
2#define __ASM_ARM_SYSTEM_H
3
4#ifdef __KERNEL__
5
6#include <linux/config.h>
7
8#define CPU_ARCH_UNKNOWN 0
9#define CPU_ARCH_ARMv3 1
10#define CPU_ARCH_ARMv4 2
11#define CPU_ARCH_ARMv4T 3
12#define CPU_ARCH_ARMv5 4
13#define CPU_ARCH_ARMv5T 5
14#define CPU_ARCH_ARMv5TE 6
15#define CPU_ARCH_ARMv5TEJ 7
16#define CPU_ARCH_ARMv6 8
17
18/*
19 * CR1 bits (CP#15 CR1)
20 */
21#define CR_M (1 << 0) /* MMU enable */
22#define CR_A (1 << 1) /* Alignment abort enable */
23#define CR_C (1 << 2) /* Dcache enable */
24#define CR_W (1 << 3) /* Write buffer enable */
25#define CR_P (1 << 4) /* 32-bit exception handler */
26#define CR_D (1 << 5) /* 32-bit data address range */
27#define CR_L (1 << 6) /* Implementation defined */
28#define CR_B (1 << 7) /* Big endian */
29#define CR_S (1 << 8) /* System MMU protection */
30#define CR_R (1 << 9) /* ROM MMU protection */
31#define CR_F (1 << 10) /* Implementation defined */
32#define CR_Z (1 << 11) /* Implementation defined */
33#define CR_I (1 << 12) /* Icache enable */
34#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
35#define CR_RR (1 << 14) /* Round Robin cache replacement */
36#define CR_L4 (1 << 15) /* LDR pc can set T bit */
37#define CR_DT (1 << 16)
38#define CR_IT (1 << 18)
39#define CR_ST (1 << 19)
40#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
41#define CR_U (1 << 22) /* Unaligned access operation */
42#define CR_XP (1 << 23) /* Extended page tables */
43#define CR_VE (1 << 24) /* Vectored interrupts */
44
45#define CPUID_ID 0
46#define CPUID_CACHETYPE 1
47#define CPUID_TCM 2
48#define CPUID_TLBTYPE 3
49
50#define read_cpuid(reg) \
51 ({ \
52 unsigned int __val; \
53 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
54 : "=r" (__val) \
55 : \
56 : "cc"); \
57 __val; \
58 })
59
60/*
61 * This is used to ensure the compiler did actually allocate the register we
62 * asked it for some inline assembly sequences. Apparently we can't trust
63 * the compiler from one version to another so a bit of paranoia won't hurt.
64 * This string is meant to be concatenated with the inline asm string and
65 * will cause compilation to stop on mismatch.
66 * (for details, see gcc PR 15089)
67 */
68#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
69
70#ifndef __ASSEMBLY__
71
72#include <linux/linkage.h>
73
74struct thread_info;
75struct task_struct;
76
77/* information about the system we're running on */
78extern unsigned int system_rev;
79extern unsigned int system_serial_low;
80extern unsigned int system_serial_high;
81extern unsigned int mem_fclk_21285;
82
83struct pt_regs;
84
85void die(const char *msg, struct pt_regs *regs, int err)
86 __attribute__((noreturn));
87
88void die_if_kernel(const char *str, struct pt_regs *regs, int err);
89
90void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
91 struct pt_regs *),
92 int sig, const char *name);
93
94#include <asm/proc-fns.h>
95
96#define xchg(ptr,x) \
97 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
98
99#define tas(ptr) (xchg((ptr),1))
100
101extern asmlinkage void __backtrace(void);
Russell King652a12e2005-04-17 15:50:36 +0100102extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
103extern void show_pte(struct mm_struct *mm, unsigned long addr);
104extern void __show_regs(struct pt_regs *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106extern int cpu_architecture(void);
Russell King36c5ed22005-06-19 18:39:33 +0100107extern void cpu_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
109#define set_cr(x) \
110 __asm__ __volatile__( \
111 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \
112 : : "r" (x) : "cc")
113
114#define get_cr() \
115 ({ \
116 unsigned int __val; \
117 __asm__ __volatile__( \
118 "mrc p15, 0, %0, c1, c0, 0 @ get CR" \
119 : "=r" (__val) : : "cc"); \
120 __val; \
121 })
122
123extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
124extern unsigned long cr_alignment; /* defined in entry-armv.S */
125
126#define UDBG_UNDEFINED (1 << 0)
127#define UDBG_SYSCALL (1 << 1)
128#define UDBG_BADABORT (1 << 2)
129#define UDBG_SEGV (1 << 3)
130#define UDBG_BUS (1 << 4)
131
132extern unsigned int user_debug;
133
134#if __LINUX_ARM_ARCH__ >= 4
135#define vectors_high() (cr_alignment & CR_V)
136#else
137#define vectors_high() (0)
138#endif
139
140#define mb() __asm__ __volatile__ ("" : : : "memory")
141#define rmb() mb()
142#define wmb() mb()
143#define read_barrier_depends() do { } while(0)
144#define set_mb(var, value) do { var = value; mb(); } while (0)
145#define set_wmb(var, value) do { var = value; wmb(); } while (0)
146#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
147
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148/*
Nick Piggin4866cde2005-06-25 14:57:23 -0700149 * switch_mm() may do a full cache flush over the context switch,
150 * so enable interrupts over the context switch to avoid high
151 * latency.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 */
Nick Piggin4866cde2005-06-25 14:57:23 -0700153#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154
155/*
156 * switch_to(prev, next) should switch from task `prev' to `next'
157 * `prev' will never be the same as `next'. schedule() itself
158 * contains the memory barrier to tell GCC not to cache `current'.
159 */
160extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
161
162#define switch_to(prev,next,last) \
163do { \
164 last = __switch_to(prev,prev->thread_info,next->thread_info); \
165} while (0)
166
167/*
168 * CPU interrupt mask handling.
169 */
170#if __LINUX_ARM_ARCH__ >= 6
171
172#define local_irq_save(x) \
173 ({ \
174 __asm__ __volatile__( \
175 "mrs %0, cpsr @ local_irq_save\n" \
176 "cpsid i" \
177 : "=r" (x) : : "memory", "cc"); \
178 })
179
180#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
181#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
182#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
183#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
184
185#else
186
187/*
188 * Save the current interrupt enable state & disable IRQs
189 */
190#define local_irq_save(x) \
191 ({ \
192 unsigned long temp; \
193 (void) (&temp == &x); \
194 __asm__ __volatile__( \
195 "mrs %0, cpsr @ local_irq_save\n" \
196" orr %1, %0, #128\n" \
197" msr cpsr_c, %1" \
198 : "=r" (x), "=r" (temp) \
199 : \
200 : "memory", "cc"); \
201 })
202
203/*
204 * Enable IRQs
205 */
206#define local_irq_enable() \
207 ({ \
208 unsigned long temp; \
209 __asm__ __volatile__( \
210 "mrs %0, cpsr @ local_irq_enable\n" \
211" bic %0, %0, #128\n" \
212" msr cpsr_c, %0" \
213 : "=r" (temp) \
214 : \
215 : "memory", "cc"); \
216 })
217
218/*
219 * Disable IRQs
220 */
221#define local_irq_disable() \
222 ({ \
223 unsigned long temp; \
224 __asm__ __volatile__( \
225 "mrs %0, cpsr @ local_irq_disable\n" \
226" orr %0, %0, #128\n" \
227" msr cpsr_c, %0" \
228 : "=r" (temp) \
229 : \
230 : "memory", "cc"); \
231 })
232
233/*
234 * Enable FIQs
235 */
236#define local_fiq_enable() \
237 ({ \
238 unsigned long temp; \
239 __asm__ __volatile__( \
240 "mrs %0, cpsr @ stf\n" \
241" bic %0, %0, #64\n" \
242" msr cpsr_c, %0" \
243 : "=r" (temp) \
244 : \
245 : "memory", "cc"); \
246 })
247
248/*
249 * Disable FIQs
250 */
251#define local_fiq_disable() \
252 ({ \
253 unsigned long temp; \
254 __asm__ __volatile__( \
255 "mrs %0, cpsr @ clf\n" \
256" orr %0, %0, #64\n" \
257" msr cpsr_c, %0" \
258 : "=r" (temp) \
259 : \
260 : "memory", "cc"); \
261 })
262
263#endif
264
265/*
266 * Save the current interrupt enable state.
267 */
268#define local_save_flags(x) \
269 ({ \
270 __asm__ __volatile__( \
271 "mrs %0, cpsr @ local_save_flags" \
272 : "=r" (x) : : "memory", "cc"); \
273 })
274
275/*
276 * restore saved IRQ & FIQ state
277 */
278#define local_irq_restore(x) \
279 __asm__ __volatile__( \
280 "msr cpsr_c, %0 @ local_irq_restore\n" \
281 : \
282 : "r" (x) \
283 : "memory", "cc")
284
285#define irqs_disabled() \
286({ \
287 unsigned long flags; \
288 local_save_flags(flags); \
Andrew Morton9a558cb2005-06-21 17:14:28 -0700289 (int)(flags & PSR_I_BIT); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290})
291
292#ifdef CONFIG_SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
294#define smp_mb() mb()
295#define smp_rmb() rmb()
296#define smp_wmb() wmb()
297#define smp_read_barrier_depends() read_barrier_depends()
298
299#else
300
301#define smp_mb() barrier()
302#define smp_rmb() barrier()
303#define smp_wmb() barrier()
304#define smp_read_barrier_depends() do { } while(0)
305
Russell King053a7b52005-06-28 19:22:25 +0100306#endif /* CONFIG_SMP */
307
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
309/*
310 * On the StrongARM, "swp" is terminally broken since it bypasses the
311 * cache totally. This means that the cache becomes inconsistent, and,
312 * since we use normal loads/stores as well, this is really bad.
313 * Typically, this causes oopsen in filp_close, but could have other,
314 * more disasterous effects. There are two work-arounds:
315 * 1. Disable interrupts and emulate the atomic swap
316 * 2. Clean the cache, perform atomic swap, flush the cache
317 *
318 * We choose (1) since its the "easiest" to achieve here and is not
319 * dependent on the processor type.
Russell King053a7b52005-06-28 19:22:25 +0100320 *
321 * NOTE that this solution won't work on an SMP system, so explcitly
322 * forbid it here.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 */
Russell King053a7b52005-06-28 19:22:25 +0100324#ifdef CONFIG_SMP
325#error SMP is not supported on SA1100/SA110
326#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327#define swp_is_buggy
328#endif
Russell King053a7b52005-06-28 19:22:25 +0100329#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
331static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
332{
333 extern void __bad_xchg(volatile void *, int);
334 unsigned long ret;
335#ifdef swp_is_buggy
336 unsigned long flags;
337#endif
338
339 switch (size) {
340#ifdef swp_is_buggy
341 case 1:
342 local_irq_save(flags);
343 ret = *(volatile unsigned char *)ptr;
344 *(volatile unsigned char *)ptr = x;
345 local_irq_restore(flags);
346 break;
347
348 case 4:
349 local_irq_save(flags);
350 ret = *(volatile unsigned long *)ptr;
351 *(volatile unsigned long *)ptr = x;
352 local_irq_restore(flags);
353 break;
354#else
355 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
356 : "=&r" (ret)
357 : "r" (x), "r" (ptr)
358 : "memory", "cc");
359 break;
360 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
361 : "=&r" (ret)
362 : "r" (x), "r" (ptr)
363 : "memory", "cc");
364 break;
365#endif
366 default: __bad_xchg(ptr, size), ret = 0;
367 }
368
369 return ret;
370}
371
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372#endif /* __ASSEMBLY__ */
373
374#define arch_align_stack(x) (x)
375
376#endif /* __KERNEL__ */
377
378#endif