Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Cache maintenance |
| 3 | * |
| 4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
Vladimir Murzin | a2d25a5 | 2014-12-01 10:53:08 +0000 | [diff] [blame] | 20 | #include <linux/errno.h> |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 21 | #include <linux/linkage.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <asm/assembler.h> |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 24 | #include <asm/cpufeature.h> |
Marc Zyngier | 8d883b2 | 2015-06-01 10:47:41 +0100 | [diff] [blame] | 25 | #include <asm/alternative.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 26 | #include <asm/uaccess.h> |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 27 | |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 28 | /* |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 29 | * flush_icache_range(start,end) |
| 30 | * |
| 31 | * Ensure that the I and D caches are coherent within specified region. |
| 32 | * This is typically used when code has been written to a memory region, |
| 33 | * and will be executed. |
| 34 | * |
| 35 | * - start - virtual start address of region |
| 36 | * - end - virtual end address of region |
| 37 | */ |
| 38 | ENTRY(flush_icache_range) |
| 39 | /* FALLTHROUGH */ |
| 40 | |
| 41 | /* |
| 42 | * __flush_cache_user_range(start,end) |
| 43 | * |
| 44 | * Ensure that the I and D caches are coherent within specified region. |
| 45 | * This is typically used when code has been written to a memory region, |
| 46 | * and will be executed. |
| 47 | * |
| 48 | * - start - virtual start address of region |
| 49 | * - end - virtual end address of region |
| 50 | */ |
| 51 | ENTRY(__flush_cache_user_range) |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 52 | uaccess_ttbr0_enable x2, x3, x4 |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 53 | dcache_line_size x2, x3 |
| 54 | sub x3, x2, #1 |
| 55 | bic x4, x0, x3 |
| 56 | 1: |
Andre Przywara | 290622e | 2016-06-28 18:07:28 +0100 | [diff] [blame] | 57 | user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 58 | add x4, x4, x2 |
| 59 | cmp x4, x1 |
| 60 | b.lo 1b |
Will Deacon | dc60b77 | 2014-05-02 16:24:15 +0100 | [diff] [blame] | 61 | dsb ish |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 62 | |
| 63 | icache_line_size x2, x3 |
| 64 | sub x3, x2, #1 |
| 65 | bic x4, x0, x3 |
| 66 | 1: |
| 67 | USER(9f, ic ivau, x4 ) // invalidate I line PoU |
| 68 | add x4, x4, x2 |
| 69 | cmp x4, x1 |
| 70 | b.lo 1b |
Will Deacon | dc60b77 | 2014-05-02 16:24:15 +0100 | [diff] [blame] | 71 | dsb ish |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 72 | isb |
Vladimir Murzin | a2d25a5 | 2014-12-01 10:53:08 +0000 | [diff] [blame] | 73 | mov x0, #0 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 74 | 1: |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 75 | uaccess_ttbr0_disable x1, x2 |
Vladimir Murzin | a2d25a5 | 2014-12-01 10:53:08 +0000 | [diff] [blame] | 76 | ret |
| 77 | 9: |
| 78 | mov x0, #-EFAULT |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 79 | b 1b |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 80 | ENDPROC(flush_icache_range) |
| 81 | ENDPROC(__flush_cache_user_range) |
| 82 | |
| 83 | /* |
Jingoo Han | 03324e6 | 2014-01-21 01:17:47 +0000 | [diff] [blame] | 84 | * __flush_dcache_area(kaddr, size) |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 85 | * |
Ashok Kumar | 0a28714 | 2015-12-17 01:38:32 -0800 | [diff] [blame] | 86 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
| 87 | * are cleaned and invalidated to the PoC. |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 88 | * |
| 89 | * - kaddr - kernel address |
| 90 | * - size - size in question |
| 91 | */ |
| 92 | ENTRY(__flush_dcache_area) |
Ashok Kumar | 0a28714 | 2015-12-17 01:38:32 -0800 | [diff] [blame] | 93 | dcache_by_line_op civac, sy, x0, x1, x2, x3 |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 94 | ret |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 95 | ENDPIPROC(__flush_dcache_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 96 | |
| 97 | /* |
Ashok Kumar | 0a28714 | 2015-12-17 01:38:32 -0800 | [diff] [blame] | 98 | * __clean_dcache_area_pou(kaddr, size) |
| 99 | * |
| 100 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
| 101 | * are cleaned to the PoU. |
| 102 | * |
| 103 | * - kaddr - kernel address |
| 104 | * - size - size in question |
| 105 | */ |
| 106 | ENTRY(__clean_dcache_area_pou) |
| 107 | dcache_by_line_op cvau, ish, x0, x1, x2, x3 |
| 108 | ret |
| 109 | ENDPROC(__clean_dcache_area_pou) |
| 110 | |
| 111 | /* |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 112 | * __dma_inv_area(start, size) |
| 113 | * - start - virtual start address of region |
| 114 | * - size - size in question |
| 115 | */ |
| 116 | __dma_inv_area: |
| 117 | add x1, x1, x0 |
| 118 | /* FALLTHROUGH */ |
| 119 | |
| 120 | /* |
Catalin Marinas | c218bca | 2014-03-26 18:25:55 +0000 | [diff] [blame] | 121 | * __inval_cache_range(start, end) |
| 122 | * - start - start address of region |
| 123 | * - end - end address of region |
| 124 | */ |
| 125 | ENTRY(__inval_cache_range) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 126 | dcache_line_size x2, x3 |
| 127 | sub x3, x2, #1 |
Catalin Marinas | ebf81a9 | 2014-04-01 18:32:55 +0100 | [diff] [blame] | 128 | tst x1, x3 // end cache line aligned? |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 129 | bic x1, x1, x3 |
Catalin Marinas | ebf81a9 | 2014-04-01 18:32:55 +0100 | [diff] [blame] | 130 | b.eq 1f |
| 131 | dc civac, x1 // clean & invalidate D / U line |
| 132 | 1: tst x0, x3 // start cache line aligned? |
| 133 | bic x0, x0, x3 |
| 134 | b.eq 2f |
| 135 | dc civac, x0 // clean & invalidate D / U line |
| 136 | b 3f |
| 137 | 2: dc ivac, x0 // invalidate D / U line |
| 138 | 3: add x0, x0, x2 |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 139 | cmp x0, x1 |
Catalin Marinas | ebf81a9 | 2014-04-01 18:32:55 +0100 | [diff] [blame] | 140 | b.lo 2b |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 141 | dsb sy |
| 142 | ret |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 143 | ENDPIPROC(__inval_cache_range) |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 144 | ENDPROC(__dma_inv_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 145 | |
| 146 | /* |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 147 | * __clean_dcache_area_poc(kaddr, size) |
| 148 | * |
| 149 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
| 150 | * are cleaned to the PoC. |
| 151 | * |
| 152 | * - kaddr - kernel address |
| 153 | * - size - size in question |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 154 | */ |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 155 | ENTRY(__clean_dcache_area_poc) |
| 156 | /* FALLTHROUGH */ |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 157 | |
| 158 | /* |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 159 | * __dma_clean_area(start, size) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 160 | * - start - virtual start address of region |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 161 | * - size - size in question |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 162 | */ |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 163 | __dma_clean_area: |
| 164 | dcache_by_line_op cvac, sy, x0, x1, x2, x3 |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 165 | ret |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 166 | ENDPIPROC(__clean_dcache_area_poc) |
| 167 | ENDPROC(__dma_clean_area) |
| 168 | |
| 169 | /* |
| 170 | * __dma_flush_area(start, size) |
| 171 | * |
| 172 | * clean & invalidate D / U line |
| 173 | * |
| 174 | * - start - virtual start address of region |
| 175 | * - size - size in question |
| 176 | */ |
| 177 | ENTRY(__dma_flush_area) |
| 178 | dcache_by_line_op civac, sy, x0, x1, x2, x3 |
| 179 | ret |
| 180 | ENDPIPROC(__dma_flush_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 181 | |
| 182 | /* |
| 183 | * __dma_map_area(start, size, dir) |
| 184 | * - start - kernel virtual start address |
| 185 | * - size - size of region |
| 186 | * - dir - DMA direction |
| 187 | */ |
| 188 | ENTRY(__dma_map_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 189 | cmp w2, #DMA_FROM_DEVICE |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 190 | b.eq __dma_inv_area |
| 191 | b __dma_clean_area |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 192 | ENDPIPROC(__dma_map_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 193 | |
| 194 | /* |
| 195 | * __dma_unmap_area(start, size, dir) |
| 196 | * - start - kernel virtual start address |
| 197 | * - size - size of region |
| 198 | * - dir - DMA direction |
| 199 | */ |
| 200 | ENTRY(__dma_unmap_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 201 | cmp w2, #DMA_TO_DEVICE |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 202 | b.ne __dma_inv_area |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 203 | ret |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 204 | ENDPIPROC(__dma_unmap_area) |