Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block |
| 3 | * |
| 4 | * Created by: Nicolas Pitre, May 2012 |
| 5 | * Copyright: (C) 2012-2013 Linaro Limited |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/spinlock.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/of_address.h> |
| 18 | #include <linux/vexpress.h> |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 19 | #include <linux/arm-cci.h> |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 20 | |
| 21 | #include <asm/mcpm.h> |
| 22 | #include <asm/proc-fns.h> |
| 23 | #include <asm/cacheflush.h> |
| 24 | #include <asm/cputype.h> |
| 25 | #include <asm/cp15.h> |
| 26 | |
| 27 | |
| 28 | #define RST_HOLD0 0x0 |
| 29 | #define RST_HOLD1 0x4 |
| 30 | #define SYS_SWRESET 0x8 |
| 31 | #define RST_STAT0 0xc |
| 32 | #define RST_STAT1 0x10 |
| 33 | #define EAG_CFG_R 0x20 |
| 34 | #define EAG_CFG_W 0x24 |
| 35 | #define KFC_CFG_R 0x28 |
| 36 | #define KFC_CFG_W 0x2c |
| 37 | #define DCS_CFG_R 0x30 |
| 38 | |
| 39 | /* |
| 40 | * We can't use regular spinlocks. In the switcher case, it is possible |
| 41 | * for an outbound CPU to call power_down() while its inbound counterpart |
| 42 | * is already live using the same logical CPU number which trips lockdep |
| 43 | * debugging. |
| 44 | */ |
| 45 | static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
| 46 | |
| 47 | static void __iomem *dcscb_base; |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 48 | static int dcscb_use_count[4][2]; |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 49 | static int dcscb_allcpus_mask[2]; |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 50 | |
| 51 | static int dcscb_power_up(unsigned int cpu, unsigned int cluster) |
| 52 | { |
| 53 | unsigned int rst_hold, cpumask = (1 << cpu); |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 54 | unsigned int all_mask = dcscb_allcpus_mask[cluster]; |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 55 | |
| 56 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
| 57 | if (cpu >= 4 || cluster >= 2) |
| 58 | return -EINVAL; |
| 59 | |
| 60 | /* |
| 61 | * Since this is called with IRQs enabled, and no arch_spin_lock_irq |
| 62 | * variant exists, we need to disable IRQs manually here. |
| 63 | */ |
| 64 | local_irq_disable(); |
| 65 | arch_spin_lock(&dcscb_lock); |
| 66 | |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 67 | dcscb_use_count[cpu][cluster]++; |
| 68 | if (dcscb_use_count[cpu][cluster] == 1) { |
| 69 | rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); |
| 70 | if (rst_hold & (1 << 8)) { |
| 71 | /* remove cluster reset and add individual CPU's reset */ |
| 72 | rst_hold &= ~(1 << 8); |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 73 | rst_hold |= all_mask; |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 74 | } |
| 75 | rst_hold &= ~(cpumask | (cpumask << 4)); |
| 76 | writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); |
| 77 | } else if (dcscb_use_count[cpu][cluster] != 2) { |
| 78 | /* |
| 79 | * The only possible values are: |
| 80 | * 0 = CPU down |
| 81 | * 1 = CPU (still) up |
| 82 | * 2 = CPU requested to be up before it had a chance |
| 83 | * to actually make itself down. |
| 84 | * Any other value is a bug. |
| 85 | */ |
| 86 | BUG(); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 87 | } |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 88 | |
| 89 | arch_spin_unlock(&dcscb_lock); |
| 90 | local_irq_enable(); |
| 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | static void dcscb_power_down(void) |
| 96 | { |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 97 | unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask; |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 98 | bool last_man = false, skip_wfi = false; |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 99 | |
| 100 | mpidr = read_cpuid_mpidr(); |
| 101 | cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
| 102 | cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
| 103 | cpumask = (1 << cpu); |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 104 | all_mask = dcscb_allcpus_mask[cluster]; |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 105 | |
| 106 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
| 107 | BUG_ON(cpu >= 4 || cluster >= 2); |
| 108 | |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 109 | __mcpm_cpu_going_down(cpu, cluster); |
| 110 | |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 111 | arch_spin_lock(&dcscb_lock); |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 112 | BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 113 | dcscb_use_count[cpu][cluster]--; |
| 114 | if (dcscb_use_count[cpu][cluster] == 0) { |
| 115 | rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); |
| 116 | rst_hold |= cpumask; |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 117 | if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) { |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 118 | rst_hold |= (1 << 8); |
| 119 | last_man = true; |
| 120 | } |
| 121 | writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); |
| 122 | } else if (dcscb_use_count[cpu][cluster] == 1) { |
| 123 | /* |
| 124 | * A power_up request went ahead of us. |
| 125 | * Even if we do not want to shut this CPU down, |
| 126 | * the caller expects a certain state as if the WFI |
| 127 | * was aborted. So let's continue with cache cleaning. |
| 128 | */ |
| 129 | skip_wfi = true; |
| 130 | } else |
| 131 | BUG(); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 132 | |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 133 | if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { |
| 134 | arch_spin_unlock(&dcscb_lock); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 135 | |
Nicolas Pitre | 39792c7 | 2013-10-18 22:06:03 +0100 | [diff] [blame] | 136 | /* Flush all cache levels for this cluster. */ |
| 137 | v7_exit_coherency_flush(all); |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * This is a harmless no-op. On platforms with a real |
| 141 | * outer cache this might either be needed or not, |
| 142 | * depending on where the outer cache sits. |
| 143 | */ |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 144 | outer_flush_all(); |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 145 | |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 146 | /* |
| 147 | * Disable cluster-level coherency by masking |
| 148 | * incoming snoops and DVM messages: |
| 149 | */ |
| 150 | cci_disable_port_by_cpu(mpidr); |
| 151 | |
| 152 | __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); |
| 153 | } else { |
| 154 | arch_spin_unlock(&dcscb_lock); |
| 155 | |
Nicolas Pitre | 39792c7 | 2013-10-18 22:06:03 +0100 | [diff] [blame] | 156 | /* Disable and flush the local CPU cache. */ |
| 157 | v7_exit_coherency_flush(louis); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 158 | } |
| 159 | |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 160 | __mcpm_cpu_down(cpu, cluster); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 161 | |
| 162 | /* Now we are prepared for power-down, do it: */ |
| 163 | dsb(); |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 164 | if (!skip_wfi) |
| 165 | wfi(); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 166 | |
| 167 | /* Not dead at this point? Let our caller cope. */ |
| 168 | } |
| 169 | |
| 170 | static const struct mcpm_platform_ops dcscb_power_ops = { |
| 171 | .power_up = dcscb_power_up, |
| 172 | .power_down = dcscb_power_down, |
| 173 | }; |
| 174 | |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 175 | static void __init dcscb_usage_count_init(void) |
| 176 | { |
| 177 | unsigned int mpidr, cpu, cluster; |
| 178 | |
| 179 | mpidr = read_cpuid_mpidr(); |
| 180 | cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
| 181 | cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
| 182 | |
| 183 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
| 184 | BUG_ON(cpu >= 4 || cluster >= 2); |
| 185 | dcscb_use_count[cpu][cluster] = 1; |
| 186 | } |
| 187 | |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 188 | extern void dcscb_power_up_setup(unsigned int affinity_level); |
| 189 | |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 190 | static int __init dcscb_init(void) |
| 191 | { |
| 192 | struct device_node *node; |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 193 | unsigned int cfg; |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 194 | int ret; |
| 195 | |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 196 | if (!cci_probed()) |
| 197 | return -ENODEV; |
| 198 | |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 199 | node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); |
| 200 | if (!node) |
| 201 | return -ENODEV; |
| 202 | dcscb_base = of_iomap(node, 0); |
| 203 | if (!dcscb_base) |
| 204 | return -EADDRNOTAVAIL; |
Nicolas Pitre | 2f2df89 | 2012-07-18 16:41:16 -0400 | [diff] [blame] | 205 | cfg = readl_relaxed(dcscb_base + DCS_CFG_R); |
| 206 | dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; |
| 207 | dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; |
Nicolas Pitre | 13eae144 | 2012-07-16 22:07:10 -0400 | [diff] [blame] | 208 | dcscb_usage_count_init(); |
| 209 | |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 210 | ret = mcpm_platform_register(&dcscb_power_ops); |
Dave Martin | d41418c0 | 2012-07-17 14:25:44 +0100 | [diff] [blame] | 211 | if (!ret) |
| 212 | ret = mcpm_sync_init(dcscb_power_up_setup); |
Nicolas Pitre | 1e904e1 | 2012-05-02 20:56:52 -0400 | [diff] [blame] | 213 | if (ret) { |
| 214 | iounmap(dcscb_base); |
| 215 | return ret; |
| 216 | } |
| 217 | |
| 218 | pr_info("VExpress DCSCB support installed\n"); |
| 219 | |
| 220 | /* |
| 221 | * Future entries into the kernel can now go |
| 222 | * through the cluster entry vectors. |
| 223 | */ |
| 224 | vexpress_flags_set(virt_to_phys(mcpm_entry_point)); |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | early_initcall(dcscb_init); |