blob: 6a1f9404261277991099dbf446cd949b83ce5dcc [file] [log] [blame]
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001/*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020012 * Copyright 2007-2008 OpenedHand Ltd.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080013 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080019#include <linux/kernel.h>
Philipp Zabel9461f652009-06-15 12:10:24 +020020#include <linux/delay.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080021#include <linux/irq.h>
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020022#include <linux/gpio.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080023#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080025#include <linux/spinlock.h>
26#include <linux/platform_device.h>
27
28#include <linux/mfd/asic3.h>
Philipp Zabel9461f652009-06-15 12:10:24 +020029#include <linux/mfd/core.h>
30#include <linux/mfd/ds1wm.h>
Philipp Zabel09f05ce2009-06-15 12:10:25 +020031#include <linux/mfd/tmio.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080032
Philipp Zabele956a2a2009-06-05 18:31:02 +020033enum {
34 ASIC3_CLOCK_SPI,
35 ASIC3_CLOCK_OWM,
36 ASIC3_CLOCK_PWM0,
37 ASIC3_CLOCK_PWM1,
38 ASIC3_CLOCK_LED0,
39 ASIC3_CLOCK_LED1,
40 ASIC3_CLOCK_LED2,
41 ASIC3_CLOCK_SD_HOST,
42 ASIC3_CLOCK_SD_BUS,
43 ASIC3_CLOCK_SMBUS,
44 ASIC3_CLOCK_EX0,
45 ASIC3_CLOCK_EX1,
46};
47
48struct asic3_clk {
49 int enabled;
50 unsigned int cdex;
51 unsigned long rate;
52};
53
54#define INIT_CDEX(_name, _rate) \
55 [ASIC3_CLOCK_##_name] = { \
56 .cdex = CLOCK_CDEX_##_name, \
57 .rate = _rate, \
58 }
59
Mark Brown59f2ad22010-12-11 12:59:35 +000060static struct asic3_clk asic3_clk_init[] __initdata = {
Philipp Zabele956a2a2009-06-05 18:31:02 +020061 INIT_CDEX(SPI, 0),
62 INIT_CDEX(OWM, 5000000),
63 INIT_CDEX(PWM0, 0),
64 INIT_CDEX(PWM1, 0),
65 INIT_CDEX(LED0, 0),
66 INIT_CDEX(LED1, 0),
67 INIT_CDEX(LED2, 0),
68 INIT_CDEX(SD_HOST, 24576000),
69 INIT_CDEX(SD_BUS, 12288000),
70 INIT_CDEX(SMBUS, 0),
71 INIT_CDEX(EX0, 32768),
72 INIT_CDEX(EX1, 24576000),
73};
74
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020075struct asic3 {
76 void __iomem *mapping;
77 unsigned int bus_shift;
78 unsigned int irq_nr;
79 unsigned int irq_base;
80 spinlock_t lock;
81 u16 irq_bothedge[4];
82 struct gpio_chip gpio;
83 struct device *dev;
Ian Molton64e88672010-01-06 13:51:48 +010084 void __iomem *tmio_cnf;
Philipp Zabele956a2a2009-06-05 18:31:02 +020085
86 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020087};
88
89static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
90
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080091static inline void asic3_write_register(struct asic3 *asic,
92 unsigned int reg, u32 value)
93{
Al Virob32661e2008-03-29 03:10:58 +000094 iowrite16(value, asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080095 (reg >> asic->bus_shift));
96}
97
98static inline u32 asic3_read_register(struct asic3 *asic,
99 unsigned int reg)
100{
Al Virob32661e2008-03-29 03:10:58 +0000101 return ioread16(asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800102 (reg >> asic->bus_shift));
103}
104
Mark Brown59f2ad22010-12-11 12:59:35 +0000105static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
Philipp Zabel6483c1b2009-06-05 18:31:01 +0200106{
107 unsigned long flags;
108 u32 val;
109
110 spin_lock_irqsave(&asic->lock, flags);
111 val = asic3_read_register(asic, reg);
112 if (set)
113 val |= bits;
114 else
115 val &= ~bits;
116 asic3_write_register(asic, reg, val);
117 spin_unlock_irqrestore(&asic->lock, flags);
118}
119
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800120/* IRQs */
121#define MAX_ASIC_ISR_LOOPS 20
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200122#define ASIC3_GPIO_BASE_INCR \
123 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800124
125static void asic3_irq_flip_edge(struct asic3 *asic,
126 u32 base, int bit)
127{
128 u16 edge;
129 unsigned long flags;
130
131 spin_lock_irqsave(&asic->lock, flags);
132 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200133 base + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800134 edge ^= bit;
135 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200136 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800137 spin_unlock_irqrestore(&asic->lock, flags);
138}
139
140static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
141{
142 int iter, i;
143 unsigned long flags;
144 struct asic3 *asic;
145
146 desc->chip->ack(irq);
147
148 asic = desc->handler_data;
149
150 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
151 u32 status;
152 int bank;
153
154 spin_lock_irqsave(&asic->lock, flags);
155 status = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200156 ASIC3_OFFSET(INTR, P_INT_STAT));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800157 spin_unlock_irqrestore(&asic->lock, flags);
158
159 /* Check all ten register bits */
160 if ((status & 0x3ff) == 0)
161 break;
162
163 /* Handle GPIO IRQs */
164 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
165 if (status & (1 << bank)) {
166 unsigned long base, istat;
167
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200168 base = ASIC3_GPIO_A_BASE
169 + bank * ASIC3_GPIO_BASE_INCR;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800170
171 spin_lock_irqsave(&asic->lock, flags);
172 istat = asic3_read_register(asic,
173 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200174 ASIC3_GPIO_INT_STATUS);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800175 /* Clearing IntStatus */
176 asic3_write_register(asic,
177 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200178 ASIC3_GPIO_INT_STATUS, 0);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800179 spin_unlock_irqrestore(&asic->lock, flags);
180
181 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
182 int bit = (1 << i);
183 unsigned int irqnr;
184
185 if (!(istat & bit))
186 continue;
187
188 irqnr = asic->irq_base +
189 (ASIC3_GPIOS_PER_BANK * bank)
190 + i;
Yinghai Lu08678b02008-08-19 20:50:05 -0700191 desc = irq_to_desc(irqnr);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800192 desc->handle_irq(irqnr, desc);
193 if (asic->irq_bothedge[bank] & bit)
194 asic3_irq_flip_edge(asic, base,
195 bit);
196 }
197 }
198 }
199
200 /* Handle remaining IRQs in the status register */
201 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
202 /* They start at bit 4 and go up */
203 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
Yinghai Lu08678b02008-08-19 20:50:05 -0700204 desc = irq_to_desc(asic->irq_base + i);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800205 desc->handle_irq(asic->irq_base + i,
206 desc);
207 }
208 }
209 }
210
211 if (iter >= MAX_ASIC_ISR_LOOPS)
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200212 dev_err(asic->dev, "interrupt processing overrun\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800213}
214
215static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
216{
217 int n;
218
219 n = (irq - asic->irq_base) >> 4;
220
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200221 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800222}
223
224static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
225{
226 return (irq - asic->irq_base) & 0xf;
227}
228
Mark Brown0f76aae2010-12-11 13:08:57 +0000229static void asic3_mask_gpio_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800230{
Mark Brown0f76aae2010-12-11 13:08:57 +0000231 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800232 u32 val, bank, index;
233 unsigned long flags;
234
Mark Brown0f76aae2010-12-11 13:08:57 +0000235 bank = asic3_irq_to_bank(asic, data->irq);
236 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800237
238 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200239 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800240 val |= 1 << index;
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200241 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800242 spin_unlock_irqrestore(&asic->lock, flags);
243}
244
Mark Brown0f76aae2010-12-11 13:08:57 +0000245static void asic3_mask_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800246{
Mark Brown0f76aae2010-12-11 13:08:57 +0000247 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800248 int regval;
249 unsigned long flags;
250
251 spin_lock_irqsave(&asic->lock, flags);
252 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200253 ASIC3_INTR_BASE +
254 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800255
256 regval &= ~(ASIC3_INTMASK_MASK0 <<
Mark Brown0f76aae2010-12-11 13:08:57 +0000257 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800258
259 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200260 ASIC3_INTR_BASE +
261 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800262 regval);
263 spin_unlock_irqrestore(&asic->lock, flags);
264}
265
Mark Brown0f76aae2010-12-11 13:08:57 +0000266static void asic3_unmask_gpio_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800267{
Mark Brown0f76aae2010-12-11 13:08:57 +0000268 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800269 u32 val, bank, index;
270 unsigned long flags;
271
Mark Brown0f76aae2010-12-11 13:08:57 +0000272 bank = asic3_irq_to_bank(asic, data->irq);
273 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800274
275 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200276 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800277 val &= ~(1 << index);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200278 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800279 spin_unlock_irqrestore(&asic->lock, flags);
280}
281
Mark Brown0f76aae2010-12-11 13:08:57 +0000282static void asic3_unmask_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800283{
Mark Brown0f76aae2010-12-11 13:08:57 +0000284 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800285 int regval;
286 unsigned long flags;
287
288 spin_lock_irqsave(&asic->lock, flags);
289 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200290 ASIC3_INTR_BASE +
291 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800292
293 regval |= (ASIC3_INTMASK_MASK0 <<
Mark Brown0f76aae2010-12-11 13:08:57 +0000294 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800295
296 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200297 ASIC3_INTR_BASE +
298 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800299 regval);
300 spin_unlock_irqrestore(&asic->lock, flags);
301}
302
Mark Brown0f76aae2010-12-11 13:08:57 +0000303static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800304{
Mark Brown0f76aae2010-12-11 13:08:57 +0000305 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800306 u32 bank, index;
307 u16 trigger, level, edge, bit;
308 unsigned long flags;
309
Mark Brown0f76aae2010-12-11 13:08:57 +0000310 bank = asic3_irq_to_bank(asic, data->irq);
311 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800312 bit = 1<<index;
313
314 spin_lock_irqsave(&asic->lock, flags);
315 level = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200316 bank + ASIC3_GPIO_LEVEL_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800317 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200318 bank + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800319 trigger = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200320 bank + ASIC3_GPIO_TRIGGER_TYPE);
Mark Brown0f76aae2010-12-11 13:08:57 +0000321 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800322
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100323 if (type == IRQ_TYPE_EDGE_RISING) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800324 trigger |= bit;
325 edge |= bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100326 } else if (type == IRQ_TYPE_EDGE_FALLING) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800327 trigger |= bit;
328 edge &= ~bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100329 } else if (type == IRQ_TYPE_EDGE_BOTH) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800330 trigger |= bit;
Mark Brown0f76aae2010-12-11 13:08:57 +0000331 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800332 edge &= ~bit;
333 else
334 edge |= bit;
Mark Brown0f76aae2010-12-11 13:08:57 +0000335 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100336 } else if (type == IRQ_TYPE_LEVEL_LOW) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800337 trigger &= ~bit;
338 level &= ~bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100339 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800340 trigger &= ~bit;
341 level |= bit;
342 } else {
343 /*
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100344 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800345 * be careful to not unmask them if mask was also called.
346 * Probably need internal state for mask.
347 */
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200348 dev_notice(asic->dev, "irq type not changed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800349 }
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200350 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800351 level);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200352 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800353 edge);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200354 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800355 trigger);
356 spin_unlock_irqrestore(&asic->lock, flags);
357 return 0;
358}
359
360static struct irq_chip asic3_gpio_irq_chip = {
361 .name = "ASIC3-GPIO",
Mark Brown0f76aae2010-12-11 13:08:57 +0000362 .irq_ack = asic3_mask_gpio_irq,
363 .irq_mask = asic3_mask_gpio_irq,
364 .irq_unmask = asic3_unmask_gpio_irq,
365 .irq_set_type = asic3_gpio_irq_type,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800366};
367
368static struct irq_chip asic3_irq_chip = {
369 .name = "ASIC3",
Mark Brown0f76aae2010-12-11 13:08:57 +0000370 .irq_ack = asic3_mask_irq,
371 .irq_mask = asic3_mask_irq,
372 .irq_unmask = asic3_unmask_irq,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800373};
374
Philipp Zabel065032f2008-06-21 00:51:38 +0200375static int __init asic3_irq_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800376{
377 struct asic3 *asic = platform_get_drvdata(pdev);
378 unsigned long clksel = 0;
379 unsigned int irq, irq_base;
Roel Kluinc491b2f2008-07-25 19:44:41 -0700380 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800381
Roel Kluinc491b2f2008-07-25 19:44:41 -0700382 ret = platform_get_irq(pdev, 0);
383 if (ret < 0)
384 return ret;
385 asic->irq_nr = ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800386
387 /* turn on clock to IRQ controller */
388 clksel |= CLOCK_SEL_CX;
389 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
390 clksel);
391
392 irq_base = asic->irq_base;
393
394 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
395 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
396 set_irq_chip(irq, &asic3_gpio_irq_chip);
397 else
398 set_irq_chip(irq, &asic3_irq_chip);
399
400 set_irq_chip_data(irq, asic);
401 set_irq_handler(irq, handle_level_irq);
402 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
403 }
404
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200405 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800406 ASIC3_INTMASK_GINTMASK);
407
408 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100409 set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800410 set_irq_data(asic->irq_nr, asic);
411
412 return 0;
413}
414
415static void asic3_irq_remove(struct platform_device *pdev)
416{
417 struct asic3 *asic = platform_get_drvdata(pdev);
418 unsigned int irq, irq_base;
419
420 irq_base = asic->irq_base;
421
422 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
423 set_irq_flags(irq, 0);
424 set_irq_handler(irq, NULL);
425 set_irq_chip(irq, NULL);
426 set_irq_chip_data(irq, NULL);
427 }
428 set_irq_chained_handler(asic->irq_nr, NULL);
429}
430
431/* GPIOs */
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200432static int asic3_gpio_direction(struct gpio_chip *chip,
433 unsigned offset, int out)
434{
435 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
436 unsigned int gpio_base;
437 unsigned long flags;
438 struct asic3 *asic;
439
440 asic = container_of(chip, struct asic3, gpio);
441 gpio_base = ASIC3_GPIO_TO_BASE(offset);
442
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200443 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200444 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
445 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200446 return -EINVAL;
447 }
448
449 spin_lock_irqsave(&asic->lock, flags);
450
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200451 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200452
453 /* Input is 0, Output is 1 */
454 if (out)
455 out_reg |= mask;
456 else
457 out_reg &= ~mask;
458
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200459 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200460
461 spin_unlock_irqrestore(&asic->lock, flags);
462
463 return 0;
464
465}
466
467static int asic3_gpio_direction_input(struct gpio_chip *chip,
468 unsigned offset)
469{
470 return asic3_gpio_direction(chip, offset, 0);
471}
472
473static int asic3_gpio_direction_output(struct gpio_chip *chip,
474 unsigned offset, int value)
475{
476 return asic3_gpio_direction(chip, offset, 1);
477}
478
479static int asic3_gpio_get(struct gpio_chip *chip,
480 unsigned offset)
481{
482 unsigned int gpio_base;
483 u32 mask = ASIC3_GPIO_TO_MASK(offset);
484 struct asic3 *asic;
485
486 asic = container_of(chip, struct asic3, gpio);
487 gpio_base = ASIC3_GPIO_TO_BASE(offset);
488
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200489 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200490 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
491 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200492 return -EINVAL;
493 }
494
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200495 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200496}
497
498static void asic3_gpio_set(struct gpio_chip *chip,
499 unsigned offset, int value)
500{
501 u32 mask, out_reg;
502 unsigned int gpio_base;
503 unsigned long flags;
504 struct asic3 *asic;
505
506 asic = container_of(chip, struct asic3, gpio);
507 gpio_base = ASIC3_GPIO_TO_BASE(offset);
508
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200509 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200510 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
511 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200512 return;
513 }
514
515 mask = ASIC3_GPIO_TO_MASK(offset);
516
517 spin_lock_irqsave(&asic->lock, flags);
518
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200519 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200520
521 if (value)
522 out_reg |= mask;
523 else
524 out_reg &= ~mask;
525
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200526 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200527
528 spin_unlock_irqrestore(&asic->lock, flags);
529
530 return;
531}
532
Philipp Zabel065032f2008-06-21 00:51:38 +0200533static __init int asic3_gpio_probe(struct platform_device *pdev,
534 u16 *gpio_config, int num)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800535{
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800536 struct asic3 *asic = platform_get_drvdata(pdev);
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200537 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
538 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
539 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
540 int i;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800541
Russell King59f0cb02008-10-27 11:24:09 +0000542 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
543 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
544 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200545
546 /* Enable all GPIOs */
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200547 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
548 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
549 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
550 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800551
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200552 for (i = 0; i < num; i++) {
553 u8 alt, pin, dir, init, bank_num, bit_num;
554 u16 config = gpio_config[i];
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800555
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200556 pin = ASIC3_CONFIG_GPIO_PIN(config);
557 alt = ASIC3_CONFIG_GPIO_ALT(config);
558 dir = ASIC3_CONFIG_GPIO_DIR(config);
559 init = ASIC3_CONFIG_GPIO_INIT(config);
560
561 bank_num = ASIC3_GPIO_TO_BANK(pin);
562 bit_num = ASIC3_GPIO_TO_BIT(pin);
563
564 alt_reg[bank_num] |= (alt << bit_num);
565 out_reg[bank_num] |= (init << bit_num);
566 dir_reg[bank_num] |= (dir << bit_num);
567 }
568
569 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
570 asic3_write_register(asic,
571 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200572 ASIC3_GPIO_DIRECTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200573 dir_reg[i]);
574 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200575 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200576 out_reg[i]);
577 asic3_write_register(asic,
578 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200579 ASIC3_GPIO_ALT_FUNCTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200580 alt_reg[i]);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800581 }
582
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200583 return gpiochip_add(&asic->gpio);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800584}
585
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200586static int asic3_gpio_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800587{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200588 struct asic3 *asic = platform_get_drvdata(pdev);
589
590 return gpiochip_remove(&asic->gpio);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800591}
592
Philipp Zabele956a2a2009-06-05 18:31:02 +0200593static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
594{
595 unsigned long flags;
596 u32 cdex;
597
598 spin_lock_irqsave(&asic->lock, flags);
599 if (clk->enabled++ == 0) {
600 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
601 cdex |= clk->cdex;
602 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
603 }
604 spin_unlock_irqrestore(&asic->lock, flags);
605
606 return 0;
607}
608
609static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
610{
611 unsigned long flags;
612 u32 cdex;
613
614 WARN_ON(clk->enabled == 0);
615
616 spin_lock_irqsave(&asic->lock, flags);
617 if (--clk->enabled == 0) {
618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
619 cdex &= ~clk->cdex;
620 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
621 }
622 spin_unlock_irqrestore(&asic->lock, flags);
623}
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800624
Philipp Zabel9461f652009-06-15 12:10:24 +0200625/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
626static struct ds1wm_driver_data ds1wm_pdata = {
627 .active_high = 1,
628};
629
630static struct resource ds1wm_resources[] = {
631 {
632 .start = ASIC3_OWM_BASE,
633 .end = ASIC3_OWM_BASE + 0x13,
634 .flags = IORESOURCE_MEM,
635 },
636 {
637 .start = ASIC3_IRQ_OWM,
Mark Brownfe421422010-12-11 13:00:34 +0000638 .end = ASIC3_IRQ_OWM,
Philipp Zabel9461f652009-06-15 12:10:24 +0200639 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
640 },
641};
642
643static int ds1wm_enable(struct platform_device *pdev)
644{
645 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
646
647 /* Turn on external clocks and the OWM clock */
648 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
649 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
650 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
651 msleep(1);
652
653 /* Reset and enable DS1WM */
654 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
655 ASIC3_EXTCF_OWM_RESET, 1);
656 msleep(1);
657 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
658 ASIC3_EXTCF_OWM_RESET, 0);
659 msleep(1);
660 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
661 ASIC3_EXTCF_OWM_EN, 1);
662 msleep(1);
663
664 return 0;
665}
666
667static int ds1wm_disable(struct platform_device *pdev)
668{
669 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
670
671 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
672 ASIC3_EXTCF_OWM_EN, 0);
673
674 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
675 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
676 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
677
678 return 0;
679}
680
681static struct mfd_cell asic3_cell_ds1wm = {
682 .name = "ds1wm",
683 .enable = ds1wm_enable,
684 .disable = ds1wm_disable,
685 .driver_data = &ds1wm_pdata,
686 .num_resources = ARRAY_SIZE(ds1wm_resources),
687 .resources = ds1wm_resources,
688};
689
Ian Molton64e88672010-01-06 13:51:48 +0100690static void asic3_mmc_pwr(struct platform_device *pdev, int state)
691{
692 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
693
694 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
695}
696
697static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
698{
699 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
700
701 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
702}
703
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200704static struct tmio_mmc_data asic3_mmc_data = {
Ian Molton64e88672010-01-06 13:51:48 +0100705 .hclk = 24576000,
706 .set_pwr = asic3_mmc_pwr,
707 .set_clk_div = asic3_mmc_clk_div,
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200708};
709
710static struct resource asic3_mmc_resources[] = {
711 {
712 .start = ASIC3_SD_CTRL_BASE,
713 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
714 .flags = IORESOURCE_MEM,
715 },
716 {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200717 .start = 0,
718 .end = 0,
719 .flags = IORESOURCE_IRQ,
720 },
721};
722
723static int asic3_mmc_enable(struct platform_device *pdev)
724{
725 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
726
727 /* Not sure if it must be done bit by bit, but leaving as-is */
728 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
729 ASIC3_SDHWCTRL_LEVCD, 1);
730 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
731 ASIC3_SDHWCTRL_LEVWP, 1);
732 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
733 ASIC3_SDHWCTRL_SUSPEND, 0);
734 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
735 ASIC3_SDHWCTRL_PCLR, 0);
736
737 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
738 /* CLK32 used for card detection and for interruption detection
739 * when HCLK is stopped.
740 */
741 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
742 msleep(1);
743
744 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
745 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
746 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
747
748 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
749 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
750 msleep(1);
751
752 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
753 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
754
755 /* Enable SD card slot 3.3V power supply */
756 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
757 ASIC3_SDHWCTRL_SDPWR, 1);
758
Ian Molton64e88672010-01-06 13:51:48 +0100759 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
760 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
761 ASIC3_SD_CTRL_BASE >> 1);
762
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200763 return 0;
764}
765
766static int asic3_mmc_disable(struct platform_device *pdev)
767{
768 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
769
770 /* Put in suspend mode */
771 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
772 ASIC3_SDHWCTRL_SUSPEND, 1);
773
774 /* Disable clocks */
775 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
776 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
777 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
778 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
779 return 0;
780}
781
782static struct mfd_cell asic3_cell_mmc = {
783 .name = "tmio-mmc",
784 .enable = asic3_mmc_enable,
785 .disable = asic3_mmc_disable,
786 .driver_data = &asic3_mmc_data,
787 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
788 .resources = asic3_mmc_resources,
789};
790
Philipp Zabel9461f652009-06-15 12:10:24 +0200791static int __init asic3_mfd_probe(struct platform_device *pdev,
792 struct resource *mem)
793{
794 struct asic3 *asic = platform_get_drvdata(pdev);
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200795 struct resource *mem_sdio;
796 int irq, ret;
797
798 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
799 if (!mem_sdio)
800 dev_dbg(asic->dev, "no SDIO MEM resource\n");
801
802 irq = platform_get_irq(pdev, 1);
803 if (irq < 0)
804 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
Philipp Zabel9461f652009-06-15 12:10:24 +0200805
806 /* DS1WM */
807 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
808 ASIC3_EXTCF_OWM_SMB, 0);
809
810 ds1wm_resources[0].start >>= asic->bus_shift;
811 ds1wm_resources[0].end >>= asic->bus_shift;
812
813 asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
814 asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
815
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200816 /* MMC */
Ian Molton64e88672010-01-06 13:51:48 +0100817 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
818 mem_sdio->start, 0x400 >> asic->bus_shift);
819 if (!asic->tmio_cnf) {
820 ret = -ENOMEM;
821 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
822 goto out;
823 }
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200824 asic3_mmc_resources[0].start >>= asic->bus_shift;
825 asic3_mmc_resources[0].end >>= asic->bus_shift;
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200826
827 asic3_cell_mmc.platform_data = &asic3_cell_mmc;
828 asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc);
829
Philipp Zabel9461f652009-06-15 12:10:24 +0200830 ret = mfd_add_devices(&pdev->dev, pdev->id,
831 &asic3_cell_ds1wm, 1, mem, asic->irq_base);
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200832 if (ret < 0)
833 goto out;
Philipp Zabel9461f652009-06-15 12:10:24 +0200834
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200835 if (mem_sdio && (irq >= 0))
836 ret = mfd_add_devices(&pdev->dev, pdev->id,
837 &asic3_cell_mmc, 1, mem_sdio, irq);
838
839 out:
Philipp Zabel9461f652009-06-15 12:10:24 +0200840 return ret;
841}
842
843static void asic3_mfd_remove(struct platform_device *pdev)
844{
Ian Molton64e88672010-01-06 13:51:48 +0100845 struct asic3 *asic = platform_get_drvdata(pdev);
846
Philipp Zabel9461f652009-06-15 12:10:24 +0200847 mfd_remove_devices(&pdev->dev);
Ian Molton64e88672010-01-06 13:51:48 +0100848 iounmap(asic->tmio_cnf);
Philipp Zabel9461f652009-06-15 12:10:24 +0200849}
850
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800851/* Core */
Philipp Zabel065032f2008-06-21 00:51:38 +0200852static int __init asic3_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800853{
854 struct asic3_platform_data *pdata = pdev->dev.platform_data;
855 struct asic3 *asic;
856 struct resource *mem;
857 unsigned long clksel;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200858 int ret = 0;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800859
860 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200861 if (asic == NULL) {
862 printk(KERN_ERR "kzalloc failed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800863 return -ENOMEM;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200864 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800865
866 spin_lock_init(&asic->lock);
867 platform_set_drvdata(pdev, asic);
868 asic->dev = &pdev->dev;
869
870 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
871 if (!mem) {
872 ret = -ENOMEM;
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200873 dev_err(asic->dev, "no MEM resource\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200874 goto out_free;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800875 }
876
Philipp Zabelbe584bd2009-06-05 18:31:04 +0200877 asic->mapping = ioremap(mem->start, resource_size(mem));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800878 if (!asic->mapping) {
879 ret = -ENOMEM;
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200880 dev_err(asic->dev, "Couldn't ioremap\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200881 goto out_free;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800882 }
883
884 asic->irq_base = pdata->irq_base;
885
Philipp Zabel99cdb0c2008-07-10 02:17:02 +0200886 /* calculate bus shift from mem resource */
Philipp Zabelbe584bd2009-06-05 18:31:04 +0200887 asic->bus_shift = 2 - (resource_size(mem) >> 12);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800888
889 clksel = 0;
890 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
891
892 ret = asic3_irq_probe(pdev);
893 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200894 dev_err(asic->dev, "Couldn't probe IRQs\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200895 goto out_unmap;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800896 }
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200897
898 asic->gpio.base = pdata->gpio_base;
899 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
900 asic->gpio.get = asic3_gpio_get;
901 asic->gpio.set = asic3_gpio_set;
902 asic->gpio.direction_input = asic3_gpio_direction_input;
903 asic->gpio.direction_output = asic3_gpio_direction_output;
904
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200905 ret = asic3_gpio_probe(pdev,
906 pdata->gpio_config,
907 pdata->gpio_config_num);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200908 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200909 dev_err(asic->dev, "GPIO probe failed\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200910 goto out_irq;
911 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800912
Philipp Zabele956a2a2009-06-05 18:31:02 +0200913 /* Making a per-device copy is only needed for the
914 * theoretical case of multiple ASIC3s on one board:
915 */
916 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
917
Philipp Zabel9461f652009-06-15 12:10:24 +0200918 asic3_mfd_probe(pdev, mem);
919
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200920 dev_info(asic->dev, "ASIC3 Core driver\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800921
922 return 0;
923
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200924 out_irq:
925 asic3_irq_remove(pdev);
926
927 out_unmap:
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800928 iounmap(asic->mapping);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200929
930 out_free:
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800931 kfree(asic);
932
933 return ret;
934}
935
Uwe Kleine-König1e3edaf2009-10-01 10:28:05 +0200936static int __devexit asic3_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800937{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200938 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800939 struct asic3 *asic = platform_get_drvdata(pdev);
940
Philipp Zabel9461f652009-06-15 12:10:24 +0200941 asic3_mfd_remove(pdev);
942
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200943 ret = asic3_gpio_remove(pdev);
944 if (ret < 0)
945 return ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800946 asic3_irq_remove(pdev);
947
948 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
949
950 iounmap(asic->mapping);
951
952 kfree(asic);
953
954 return 0;
955}
956
957static void asic3_shutdown(struct platform_device *pdev)
958{
959}
960
961static struct platform_driver asic3_device_driver = {
962 .driver = {
963 .name = "asic3",
964 },
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800965 .remove = __devexit_p(asic3_remove),
966 .shutdown = asic3_shutdown,
967};
968
969static int __init asic3_init(void)
970{
971 int retval = 0;
Philipp Zabel065032f2008-06-21 00:51:38 +0200972 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800973 return retval;
974}
975
976subsys_initcall(asic3_init);