Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1 | /* |
Vivien Didelot | 0d3cd4b | 2016-06-21 12:28:19 -0400 | [diff] [blame] | 2 | * Marvell 88e6xxx Ethernet switch single-chip support |
| 3 | * |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 4 | * Copyright (c) 2008 Marvell Semiconductor |
| 5 | * |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 6 | * Copyright (c) 2015 CMC Electronics, Inc. |
| 7 | * Added support for VLAN Table Unit operations |
| 8 | * |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 9 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
| 10 | * |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | */ |
| 16 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 17 | #include <linux/delay.h> |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 18 | #include <linux/etherdevice.h> |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 19 | #include <linux/ethtool.h> |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 20 | #include <linux/if_bridge.h> |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 21 | #include <linux/jiffies.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 22 | #include <linux/list.h> |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 23 | #include <linux/mdio.h> |
Paul Gortmaker | 2bbba27 | 2012-01-24 10:41:40 +0000 | [diff] [blame] | 24 | #include <linux/module.h> |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 25 | #include <linux/of_device.h> |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 26 | #include <linux/of_mdio.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 27 | #include <linux/netdevice.h> |
Andrew Lunn | c8c1b39 | 2015-11-20 03:56:24 +0100 | [diff] [blame] | 28 | #include <linux/gpio/consumer.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 29 | #include <linux/phy.h> |
Ben Hutchings | c8f0b86 | 2011-11-27 17:06:08 +0000 | [diff] [blame] | 30 | #include <net/dsa.h> |
Vivien Didelot | 1f36faf | 2015-10-08 11:35:13 -0400 | [diff] [blame] | 31 | #include <net/switchdev.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 32 | #include "mv88e6xxx.h" |
| 33 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 34 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 35 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 36 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
| 37 | dev_err(chip->dev, "Switch registers lock not held!\n"); |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 38 | dump_stack(); |
| 39 | } |
| 40 | } |
| 41 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 42 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
| 43 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). |
| 44 | * |
| 45 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it |
| 46 | * is the only device connected to the SMI master. In this mode it responds to |
| 47 | * all 32 possible SMI addresses, and thus maps directly the internal devices. |
| 48 | * |
| 49 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing |
| 50 | * multiple devices to share the SMI interface. In this mode it responds to only |
| 51 | * 2 registers, used to indirectly access the internal SMI devices. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 52 | */ |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 53 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 54 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 55 | int addr, int reg, u16 *val) |
| 56 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 57 | if (!chip->smi_ops) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 58 | return -EOPNOTSUPP; |
| 59 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 60 | return chip->smi_ops->read(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 61 | } |
| 62 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 63 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 64 | int addr, int reg, u16 val) |
| 65 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 66 | if (!chip->smi_ops) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 67 | return -EOPNOTSUPP; |
| 68 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 69 | return chip->smi_ops->write(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 70 | } |
| 71 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 72 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 73 | int addr, int reg, u16 *val) |
| 74 | { |
| 75 | int ret; |
| 76 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 77 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 78 | if (ret < 0) |
| 79 | return ret; |
| 80 | |
| 81 | *val = ret & 0xffff; |
| 82 | |
| 83 | return 0; |
| 84 | } |
| 85 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 86 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 87 | int addr, int reg, u16 val) |
| 88 | { |
| 89 | int ret; |
| 90 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 91 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 92 | if (ret < 0) |
| 93 | return ret; |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = { |
| 99 | .read = mv88e6xxx_smi_single_chip_read, |
| 100 | .write = mv88e6xxx_smi_single_chip_write, |
| 101 | }; |
| 102 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 103 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 104 | { |
| 105 | int ret; |
| 106 | int i; |
| 107 | |
| 108 | for (i = 0; i < 16; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 109 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 110 | if (ret < 0) |
| 111 | return ret; |
| 112 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 113 | if ((ret & SMI_CMD_BUSY) == 0) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | return -ETIMEDOUT; |
| 118 | } |
| 119 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 120 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 121 | int addr, int reg, u16 *val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 122 | { |
| 123 | int ret; |
| 124 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 125 | /* Wait for the bus to become free. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 126 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 127 | if (ret < 0) |
| 128 | return ret; |
| 129 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 130 | /* Transmit the read command. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 131 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
Neil Armstrong | 6e899e6 | 2015-10-22 10:37:53 +0200 | [diff] [blame] | 132 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 133 | if (ret < 0) |
| 134 | return ret; |
| 135 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 136 | /* Wait for the read command to complete. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 137 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 138 | if (ret < 0) |
| 139 | return ret; |
| 140 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 141 | /* Read the data. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 142 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 143 | if (ret < 0) |
| 144 | return ret; |
| 145 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 146 | *val = ret & 0xffff; |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 151 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 152 | int addr, int reg, u16 val) |
| 153 | { |
| 154 | int ret; |
| 155 | |
| 156 | /* Wait for the bus to become free. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 157 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 158 | if (ret < 0) |
| 159 | return ret; |
| 160 | |
| 161 | /* Transmit the data to write. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 162 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 163 | if (ret < 0) |
| 164 | return ret; |
| 165 | |
| 166 | /* Transmit the write command. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 167 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 168 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
| 169 | if (ret < 0) |
| 170 | return ret; |
| 171 | |
| 172 | /* Wait for the write command to complete. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 173 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 174 | if (ret < 0) |
| 175 | return ret; |
| 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = { |
| 181 | .read = mv88e6xxx_smi_multi_chip_read, |
| 182 | .write = mv88e6xxx_smi_multi_chip_write, |
| 183 | }; |
| 184 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 185 | static int mv88e6xxx_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 186 | int addr, int reg, u16 *val) |
| 187 | { |
| 188 | int err; |
| 189 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 190 | assert_reg_lock(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 191 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 192 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 193 | if (err) |
| 194 | return err; |
| 195 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 196 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 197 | addr, reg, *val); |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 202 | static int mv88e6xxx_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 203 | int addr, int reg, u16 val) |
| 204 | { |
| 205 | int err; |
| 206 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 207 | assert_reg_lock(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 208 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 209 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 210 | if (err) |
| 211 | return err; |
| 212 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 213 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 214 | addr, reg, val); |
| 215 | |
| 216 | return 0; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 219 | /* Indirect write to single pointer-data register with an Update bit */ |
| 220 | static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, |
| 221 | u16 update) |
| 222 | { |
| 223 | u16 val; |
| 224 | int i, err; |
| 225 | |
| 226 | /* Wait until the previous operation is completed */ |
| 227 | for (i = 0; i < 16; ++i) { |
| 228 | err = mv88e6xxx_read(chip, addr, reg, &val); |
| 229 | if (err) |
| 230 | return err; |
| 231 | |
| 232 | if (!(val & BIT(15))) |
| 233 | break; |
| 234 | } |
| 235 | |
| 236 | if (i == 16) |
| 237 | return -ETIMEDOUT; |
| 238 | |
| 239 | /* Set the Update bit to trigger a write operation */ |
| 240 | val = BIT(15) | update; |
| 241 | |
| 242 | return mv88e6xxx_write(chip, addr, reg, val); |
| 243 | } |
| 244 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 245 | static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 246 | { |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 247 | u16 val; |
| 248 | int err; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 249 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 250 | err = mv88e6xxx_read(chip, addr, reg, &val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 251 | if (err) |
| 252 | return err; |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 253 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 254 | return val; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 255 | } |
| 256 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 257 | static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 258 | int reg, u16 val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 259 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 260 | return mv88e6xxx_write(chip, addr, reg, val); |
Guenter Roeck | 8d6d09e | 2015-03-26 18:36:31 -0700 | [diff] [blame] | 261 | } |
| 262 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 263 | static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 264 | int addr, int regnum) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 265 | { |
| 266 | if (addr >= 0) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 267 | return _mv88e6xxx_reg_read(chip, addr, regnum); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 268 | return 0xffff; |
| 269 | } |
| 270 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 271 | static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 272 | int addr, int regnum, u16 val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 273 | { |
| 274 | if (addr >= 0) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 275 | return _mv88e6xxx_reg_write(chip, addr, regnum, val); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 276 | return 0; |
| 277 | } |
| 278 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 279 | static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 280 | { |
| 281 | int ret; |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 282 | unsigned long timeout; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 283 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 284 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 285 | if (ret < 0) |
| 286 | return ret; |
| 287 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 288 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 289 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 290 | if (ret) |
| 291 | return ret; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 292 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 293 | timeout = jiffies + 1 * HZ; |
| 294 | while (time_before(jiffies, timeout)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 295 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 296 | if (ret < 0) |
| 297 | return ret; |
| 298 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 299 | usleep_range(1000, 2000); |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 300 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
| 301 | GLOBAL_STATUS_PPU_POLLING) |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 302 | return 0; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | return -ETIMEDOUT; |
| 306 | } |
| 307 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 308 | static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 309 | { |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 310 | int ret, err; |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 311 | unsigned long timeout; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 312 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 313 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 314 | if (ret < 0) |
| 315 | return ret; |
| 316 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 317 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 318 | ret | GLOBAL_CONTROL_PPU_ENABLE); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 319 | if (err) |
| 320 | return err; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 321 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 322 | timeout = jiffies + 1 * HZ; |
| 323 | while (time_before(jiffies, timeout)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 324 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 325 | if (ret < 0) |
| 326 | return ret; |
| 327 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 328 | usleep_range(1000, 2000); |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 329 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
| 330 | GLOBAL_STATUS_PPU_POLLING) |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 331 | return 0; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | return -ETIMEDOUT; |
| 335 | } |
| 336 | |
| 337 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) |
| 338 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 339 | struct mv88e6xxx_chip *chip; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 340 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 341 | chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 342 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 343 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 344 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 345 | if (mutex_trylock(&chip->ppu_mutex)) { |
| 346 | if (mv88e6xxx_ppu_enable(chip) == 0) |
| 347 | chip->ppu_disabled = 0; |
| 348 | mutex_unlock(&chip->ppu_mutex); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 349 | } |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 350 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 351 | mutex_unlock(&chip->reg_lock); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) |
| 355 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 356 | struct mv88e6xxx_chip *chip = (void *)_ps; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 357 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 358 | schedule_work(&chip->ppu_work); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 359 | } |
| 360 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 361 | static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 362 | { |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 363 | int ret; |
| 364 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 365 | mutex_lock(&chip->ppu_mutex); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 366 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 367 | /* If the PHY polling unit is enabled, disable it so that |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 368 | * we can access the PHY registers. If it was already |
| 369 | * disabled, cancel the timer that is going to re-enable |
| 370 | * it. |
| 371 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 372 | if (!chip->ppu_disabled) { |
| 373 | ret = mv88e6xxx_ppu_disable(chip); |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 374 | if (ret < 0) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 375 | mutex_unlock(&chip->ppu_mutex); |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 376 | return ret; |
| 377 | } |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 378 | chip->ppu_disabled = 1; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 379 | } else { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 380 | del_timer(&chip->ppu_timer); |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 381 | ret = 0; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | return ret; |
| 385 | } |
| 386 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 387 | static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 388 | { |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 389 | /* Schedule a timer to re-enable the PHY polling unit. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 390 | mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); |
| 391 | mutex_unlock(&chip->ppu_mutex); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 392 | } |
| 393 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 394 | static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 395 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 396 | mutex_init(&chip->ppu_mutex); |
| 397 | INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); |
| 398 | init_timer(&chip->ppu_timer); |
| 399 | chip->ppu_timer.data = (unsigned long)chip; |
| 400 | chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 401 | } |
| 402 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 403 | static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 404 | int regnum) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 405 | { |
| 406 | int ret; |
| 407 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 408 | ret = mv88e6xxx_ppu_access_get(chip); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 409 | if (ret >= 0) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 410 | ret = _mv88e6xxx_reg_read(chip, addr, regnum); |
| 411 | mv88e6xxx_ppu_access_put(chip); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | return ret; |
| 415 | } |
| 416 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 417 | static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 418 | int regnum, u16 val) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 419 | { |
| 420 | int ret; |
| 421 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 422 | ret = mv88e6xxx_ppu_access_get(chip); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 423 | if (ret >= 0) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 424 | ret = _mv88e6xxx_reg_write(chip, addr, regnum, val); |
| 425 | mv88e6xxx_ppu_access_put(chip); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | return ret; |
| 429 | } |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 430 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 431 | static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 432 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 433 | return chip->info->family == MV88E6XXX_FAMILY_6065; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 434 | } |
| 435 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 436 | static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 437 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 438 | return chip->info->family == MV88E6XXX_FAMILY_6095; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 439 | } |
| 440 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 441 | static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 442 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 443 | return chip->info->family == MV88E6XXX_FAMILY_6097; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 444 | } |
| 445 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 446 | static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 447 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 448 | return chip->info->family == MV88E6XXX_FAMILY_6165; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 449 | } |
| 450 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 451 | static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 452 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 453 | return chip->info->family == MV88E6XXX_FAMILY_6185; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 454 | } |
| 455 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 456 | static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) |
Aleksey S. Kazantsev | 7c3d0d6 | 2015-07-07 20:38:15 -0700 | [diff] [blame] | 457 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 458 | return chip->info->family == MV88E6XXX_FAMILY_6320; |
Aleksey S. Kazantsev | 7c3d0d6 | 2015-07-07 20:38:15 -0700 | [diff] [blame] | 459 | } |
| 460 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 461 | static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 462 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 463 | return chip->info->family == MV88E6XXX_FAMILY_6351; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 464 | } |
| 465 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 466 | static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | f3a8b6b | 2015-04-02 04:06:40 +0200 | [diff] [blame] | 467 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 468 | return chip->info->family == MV88E6XXX_FAMILY_6352; |
Andrew Lunn | f3a8b6b | 2015-04-02 04:06:40 +0200 | [diff] [blame] | 469 | } |
| 470 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 471 | static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 472 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 473 | return chip->info->num_databases; |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 474 | } |
| 475 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 476 | static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip) |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 477 | { |
| 478 | /* Does the device have dedicated FID registers for ATU and VTU ops? */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 479 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
| 480 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 481 | return true; |
| 482 | |
| 483 | return false; |
| 484 | } |
| 485 | |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 486 | /* We expect the switch to perform auto negotiation if there is a real |
| 487 | * phy. However, in the case of a fixed link phy, we force the port |
| 488 | * settings from the fixed link settings. |
| 489 | */ |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 490 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
| 491 | struct phy_device *phydev) |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 492 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 493 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | 4905287 | 2015-09-29 01:53:48 +0200 | [diff] [blame] | 494 | u32 reg; |
| 495 | int ret; |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 496 | |
| 497 | if (!phy_is_pseudo_fixed_link(phydev)) |
| 498 | return; |
| 499 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 500 | mutex_lock(&chip->reg_lock); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 501 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 502 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 503 | if (ret < 0) |
| 504 | goto out; |
| 505 | |
| 506 | reg = ret & ~(PORT_PCS_CTRL_LINK_UP | |
| 507 | PORT_PCS_CTRL_FORCE_LINK | |
| 508 | PORT_PCS_CTRL_DUPLEX_FULL | |
| 509 | PORT_PCS_CTRL_FORCE_DUPLEX | |
| 510 | PORT_PCS_CTRL_UNFORCED); |
| 511 | |
| 512 | reg |= PORT_PCS_CTRL_FORCE_LINK; |
| 513 | if (phydev->link) |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 514 | reg |= PORT_PCS_CTRL_LINK_UP; |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 515 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 516 | if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100) |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 517 | goto out; |
| 518 | |
| 519 | switch (phydev->speed) { |
| 520 | case SPEED_1000: |
| 521 | reg |= PORT_PCS_CTRL_1000; |
| 522 | break; |
| 523 | case SPEED_100: |
| 524 | reg |= PORT_PCS_CTRL_100; |
| 525 | break; |
| 526 | case SPEED_10: |
| 527 | reg |= PORT_PCS_CTRL_10; |
| 528 | break; |
| 529 | default: |
| 530 | pr_info("Unknown speed"); |
| 531 | goto out; |
| 532 | } |
| 533 | |
| 534 | reg |= PORT_PCS_CTRL_FORCE_DUPLEX; |
| 535 | if (phydev->duplex == DUPLEX_FULL) |
| 536 | reg |= PORT_PCS_CTRL_DUPLEX_FULL; |
| 537 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 538 | if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) && |
| 539 | (port >= chip->info->num_ports - 2)) { |
Andrew Lunn | e7e72ac | 2015-08-31 15:56:51 +0200 | [diff] [blame] | 540 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
| 541 | reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; |
| 542 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
| 543 | reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; |
| 544 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
| 545 | reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | |
| 546 | PORT_PCS_CTRL_RGMII_DELAY_TXCLK); |
| 547 | } |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 548 | _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 549 | |
| 550 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 551 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 552 | } |
| 553 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 554 | static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 555 | { |
| 556 | int ret; |
| 557 | int i; |
| 558 | |
| 559 | for (i = 0; i < 10; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 560 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP); |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 561 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | return -ETIMEDOUT; |
| 566 | } |
| 567 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 568 | static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 569 | { |
| 570 | int ret; |
| 571 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 572 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
Andrew Lunn | f3a8b6b | 2015-04-02 04:06:40 +0200 | [diff] [blame] | 573 | port = (port + 1) << 5; |
| 574 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 575 | /* Snapshot the hardware statistics counters for this port. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 576 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, |
Andrew Lunn | 3188823 | 2015-05-06 01:09:54 +0200 | [diff] [blame] | 577 | GLOBAL_STATS_OP_CAPTURE_PORT | |
| 578 | GLOBAL_STATS_OP_HIST_RX_TX | port); |
| 579 | if (ret < 0) |
| 580 | return ret; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 581 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 582 | /* Wait for the snapshotting to complete. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 583 | ret = _mv88e6xxx_stats_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 584 | if (ret < 0) |
| 585 | return ret; |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 590 | static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 591 | int stat, u32 *val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 592 | { |
| 593 | u32 _val; |
| 594 | int ret; |
| 595 | |
| 596 | *val = 0; |
| 597 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 598 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, |
Andrew Lunn | 3188823 | 2015-05-06 01:09:54 +0200 | [diff] [blame] | 599 | GLOBAL_STATS_OP_READ_CAPTURED | |
| 600 | GLOBAL_STATS_OP_HIST_RX_TX | stat); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 601 | if (ret < 0) |
| 602 | return; |
| 603 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 604 | ret = _mv88e6xxx_stats_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 605 | if (ret < 0) |
| 606 | return; |
| 607 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 608 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 609 | if (ret < 0) |
| 610 | return; |
| 611 | |
| 612 | _val = ret << 16; |
| 613 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 614 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 615 | if (ret < 0) |
| 616 | return; |
| 617 | |
| 618 | *val = _val | ret; |
| 619 | } |
| 620 | |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 621 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 622 | { "in_good_octets", 8, 0x00, BANK0, }, |
| 623 | { "in_bad_octets", 4, 0x02, BANK0, }, |
| 624 | { "in_unicast", 4, 0x04, BANK0, }, |
| 625 | { "in_broadcasts", 4, 0x06, BANK0, }, |
| 626 | { "in_multicasts", 4, 0x07, BANK0, }, |
| 627 | { "in_pause", 4, 0x16, BANK0, }, |
| 628 | { "in_undersize", 4, 0x18, BANK0, }, |
| 629 | { "in_fragments", 4, 0x19, BANK0, }, |
| 630 | { "in_oversize", 4, 0x1a, BANK0, }, |
| 631 | { "in_jabber", 4, 0x1b, BANK0, }, |
| 632 | { "in_rx_error", 4, 0x1c, BANK0, }, |
| 633 | { "in_fcs_error", 4, 0x1d, BANK0, }, |
| 634 | { "out_octets", 8, 0x0e, BANK0, }, |
| 635 | { "out_unicast", 4, 0x10, BANK0, }, |
| 636 | { "out_broadcasts", 4, 0x13, BANK0, }, |
| 637 | { "out_multicasts", 4, 0x12, BANK0, }, |
| 638 | { "out_pause", 4, 0x15, BANK0, }, |
| 639 | { "excessive", 4, 0x11, BANK0, }, |
| 640 | { "collisions", 4, 0x1e, BANK0, }, |
| 641 | { "deferred", 4, 0x05, BANK0, }, |
| 642 | { "single", 4, 0x14, BANK0, }, |
| 643 | { "multiple", 4, 0x17, BANK0, }, |
| 644 | { "out_fcs_error", 4, 0x03, BANK0, }, |
| 645 | { "late", 4, 0x1f, BANK0, }, |
| 646 | { "hist_64bytes", 4, 0x08, BANK0, }, |
| 647 | { "hist_65_127bytes", 4, 0x09, BANK0, }, |
| 648 | { "hist_128_255bytes", 4, 0x0a, BANK0, }, |
| 649 | { "hist_256_511bytes", 4, 0x0b, BANK0, }, |
| 650 | { "hist_512_1023bytes", 4, 0x0c, BANK0, }, |
| 651 | { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, |
| 652 | { "sw_in_discards", 4, 0x10, PORT, }, |
| 653 | { "sw_in_filtered", 2, 0x12, PORT, }, |
| 654 | { "sw_out_filtered", 2, 0x13, PORT, }, |
| 655 | { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 656 | { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 657 | { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 658 | { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 659 | { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 660 | { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 661 | { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 662 | { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 663 | { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 664 | { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 665 | { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 666 | { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 667 | { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 668 | { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 669 | { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 670 | { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 671 | { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 672 | { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 673 | { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 674 | { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 675 | { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 676 | { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 677 | { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 678 | { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 679 | { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 680 | { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 681 | }; |
| 682 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 683 | static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip, |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 684 | struct mv88e6xxx_hw_stat *stat) |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 685 | { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 686 | switch (stat->type) { |
| 687 | case BANK0: |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 688 | return true; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 689 | case BANK1: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 690 | return mv88e6xxx_6320_family(chip); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 691 | case PORT: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 692 | return mv88e6xxx_6095_family(chip) || |
| 693 | mv88e6xxx_6185_family(chip) || |
| 694 | mv88e6xxx_6097_family(chip) || |
| 695 | mv88e6xxx_6165_family(chip) || |
| 696 | mv88e6xxx_6351_family(chip) || |
| 697 | mv88e6xxx_6352_family(chip); |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 698 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 699 | return false; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 700 | } |
| 701 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 702 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 703 | struct mv88e6xxx_hw_stat *s, |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 704 | int port) |
| 705 | { |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 706 | u32 low; |
| 707 | u32 high = 0; |
| 708 | int ret; |
| 709 | u64 value; |
| 710 | |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 711 | switch (s->type) { |
| 712 | case PORT: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 713 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg); |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 714 | if (ret < 0) |
| 715 | return UINT64_MAX; |
| 716 | |
| 717 | low = ret; |
| 718 | if (s->sizeof_stat == 4) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 719 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 720 | s->reg + 1); |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 721 | if (ret < 0) |
| 722 | return UINT64_MAX; |
| 723 | high = ret; |
| 724 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 725 | break; |
| 726 | case BANK0: |
| 727 | case BANK1: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 728 | _mv88e6xxx_stats_read(chip, s->reg, &low); |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 729 | if (s->sizeof_stat == 8) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 730 | _mv88e6xxx_stats_read(chip, s->reg + 1, &high); |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 731 | } |
| 732 | value = (((u64)high) << 16) | low; |
| 733 | return value; |
| 734 | } |
| 735 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 736 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
| 737 | uint8_t *data) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 738 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 739 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 740 | struct mv88e6xxx_hw_stat *stat; |
| 741 | int i, j; |
| 742 | |
| 743 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 744 | stat = &mv88e6xxx_hw_stats[i]; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 745 | if (mv88e6xxx_has_stat(chip, stat)) { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 746 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
| 747 | ETH_GSTRING_LEN); |
| 748 | j++; |
| 749 | } |
| 750 | } |
| 751 | } |
| 752 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 753 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 754 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 755 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 756 | struct mv88e6xxx_hw_stat *stat; |
| 757 | int i, j; |
| 758 | |
| 759 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 760 | stat = &mv88e6xxx_hw_stats[i]; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 761 | if (mv88e6xxx_has_stat(chip, stat)) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 762 | j++; |
| 763 | } |
| 764 | return j; |
| 765 | } |
| 766 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 767 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
| 768 | uint64_t *data) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 769 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 770 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 771 | struct mv88e6xxx_hw_stat *stat; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 772 | int ret; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 773 | int i, j; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 774 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 775 | mutex_lock(&chip->reg_lock); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 776 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 777 | ret = _mv88e6xxx_stats_snapshot(chip, port); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 778 | if (ret < 0) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 779 | mutex_unlock(&chip->reg_lock); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 780 | return; |
| 781 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 782 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 783 | stat = &mv88e6xxx_hw_stats[i]; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 784 | if (mv88e6xxx_has_stat(chip, stat)) { |
| 785 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 786 | j++; |
| 787 | } |
| 788 | } |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 789 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 790 | mutex_unlock(&chip->reg_lock); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 791 | } |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 792 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 793 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 794 | { |
| 795 | return 32 * sizeof(u16); |
| 796 | } |
| 797 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 798 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
| 799 | struct ethtool_regs *regs, void *_p) |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 800 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 801 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 802 | u16 *p = _p; |
| 803 | int i; |
| 804 | |
| 805 | regs->version = 0; |
| 806 | |
| 807 | memset(p, 0xff, 32 * sizeof(u16)); |
| 808 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 809 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 2306251 | 2016-05-09 13:22:45 -0400 | [diff] [blame] | 810 | |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 811 | for (i = 0; i < 32; i++) { |
| 812 | int ret; |
| 813 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 814 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i); |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 815 | if (ret >= 0) |
| 816 | p[i] = ret; |
| 817 | } |
Vivien Didelot | 2306251 | 2016-05-09 13:22:45 -0400 | [diff] [blame] | 818 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 819 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 820 | } |
| 821 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 822 | static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset, |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 823 | u16 mask) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 824 | { |
| 825 | unsigned long timeout = jiffies + HZ / 10; |
| 826 | |
| 827 | while (time_before(jiffies, timeout)) { |
| 828 | int ret; |
| 829 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 830 | ret = _mv88e6xxx_reg_read(chip, reg, offset); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 831 | if (ret < 0) |
| 832 | return ret; |
| 833 | if (!(ret & mask)) |
| 834 | return 0; |
| 835 | |
| 836 | usleep_range(1000, 2000); |
| 837 | } |
| 838 | return -ETIMEDOUT; |
| 839 | } |
| 840 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 841 | static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 842 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 843 | return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP, |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 844 | GLOBAL2_SMI_OP_BUSY); |
| 845 | } |
| 846 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 847 | static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 848 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 849 | return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP, |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 850 | GLOBAL_ATU_OP_BUSY); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 851 | } |
| 852 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 853 | static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 854 | int addr, int regnum) |
Andrew Lunn | f304468 | 2015-02-14 19:17:50 +0100 | [diff] [blame] | 855 | { |
| 856 | int ret; |
| 857 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 858 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP, |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 859 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | |
| 860 | regnum); |
Andrew Lunn | f304468 | 2015-02-14 19:17:50 +0100 | [diff] [blame] | 861 | if (ret < 0) |
| 862 | return ret; |
| 863 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 864 | ret = mv88e6xxx_mdio_wait(chip); |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 865 | if (ret < 0) |
| 866 | return ret; |
| 867 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 868 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 869 | |
| 870 | return ret; |
Andrew Lunn | f304468 | 2015-02-14 19:17:50 +0100 | [diff] [blame] | 871 | } |
| 872 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 873 | static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 874 | int addr, int regnum, u16 val) |
Andrew Lunn | f304468 | 2015-02-14 19:17:50 +0100 | [diff] [blame] | 875 | { |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 876 | int ret; |
Andrew Lunn | f304468 | 2015-02-14 19:17:50 +0100 | [diff] [blame] | 877 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 878 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 879 | if (ret < 0) |
| 880 | return ret; |
| 881 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 882 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP, |
Andrew Lunn | 3898c14 | 2015-05-06 01:09:53 +0200 | [diff] [blame] | 883 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | |
| 884 | regnum); |
| 885 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 886 | return mv88e6xxx_mdio_wait(chip); |
Andrew Lunn | f304468 | 2015-02-14 19:17:50 +0100 | [diff] [blame] | 887 | } |
| 888 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 889 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
| 890 | struct ethtool_eee *e) |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 891 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 892 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 893 | int reg; |
| 894 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 895 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
Vivien Didelot | aadbdb8 | 2016-05-09 13:22:44 -0400 | [diff] [blame] | 896 | return -EOPNOTSUPP; |
| 897 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 898 | mutex_lock(&chip->reg_lock); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 899 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 900 | reg = mv88e6xxx_mdio_read_indirect(chip, port, 16); |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 901 | if (reg < 0) |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 902 | goto out; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 903 | |
| 904 | e->eee_enabled = !!(reg & 0x0200); |
| 905 | e->tx_lpi_enabled = !!(reg & 0x0100); |
| 906 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 907 | reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS); |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 908 | if (reg < 0) |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 909 | goto out; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 910 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 911 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 912 | reg = 0; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 913 | |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 914 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 915 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 916 | return reg; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 917 | } |
| 918 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 919 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
| 920 | struct phy_device *phydev, struct ethtool_eee *e) |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 921 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 922 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 923 | int reg; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 924 | int ret; |
| 925 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 926 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
Vivien Didelot | aadbdb8 | 2016-05-09 13:22:44 -0400 | [diff] [blame] | 927 | return -EOPNOTSUPP; |
| 928 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 929 | mutex_lock(&chip->reg_lock); |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 930 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 931 | ret = mv88e6xxx_mdio_read_indirect(chip, port, 16); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 932 | if (ret < 0) |
| 933 | goto out; |
| 934 | |
| 935 | reg = ret & ~0x0300; |
| 936 | if (e->eee_enabled) |
| 937 | reg |= 0x0200; |
| 938 | if (e->tx_lpi_enabled) |
| 939 | reg |= 0x0100; |
| 940 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 941 | ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 942 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 943 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 944 | |
| 945 | return ret; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 946 | } |
| 947 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 948 | static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 949 | { |
| 950 | int ret; |
| 951 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 952 | if (mv88e6xxx_has_fid_reg(chip)) { |
| 953 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID, |
| 954 | fid); |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 955 | if (ret < 0) |
| 956 | return ret; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 957 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 958 | /* ATU DBNum[7:4] are located in ATU Control 15:12 */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 959 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL); |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 960 | if (ret < 0) |
| 961 | return ret; |
| 962 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 963 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 964 | (ret & 0xfff) | |
| 965 | ((fid << 8) & 0xf000)); |
| 966 | if (ret < 0) |
| 967 | return ret; |
| 968 | |
| 969 | /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ |
| 970 | cmd |= fid & 0xf; |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 971 | } |
| 972 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 973 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 974 | if (ret < 0) |
| 975 | return ret; |
| 976 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 977 | return _mv88e6xxx_atu_wait(chip); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 978 | } |
| 979 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 980 | static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 37705b7 | 2015-09-04 14:34:11 -0400 | [diff] [blame] | 981 | struct mv88e6xxx_atu_entry *entry) |
| 982 | { |
| 983 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; |
| 984 | |
| 985 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
| 986 | unsigned int mask, shift; |
| 987 | |
| 988 | if (entry->trunk) { |
| 989 | data |= GLOBAL_ATU_DATA_TRUNK; |
| 990 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; |
| 991 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; |
| 992 | } else { |
| 993 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; |
| 994 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; |
| 995 | } |
| 996 | |
| 997 | data |= (entry->portv_trunkid << shift) & mask; |
| 998 | } |
| 999 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1000 | return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data); |
Vivien Didelot | 37705b7 | 2015-09-04 14:34:11 -0400 | [diff] [blame] | 1001 | } |
| 1002 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1003 | static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1004 | struct mv88e6xxx_atu_entry *entry, |
| 1005 | bool static_too) |
| 1006 | { |
| 1007 | int op; |
| 1008 | int err; |
| 1009 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1010 | err = _mv88e6xxx_atu_wait(chip); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1011 | if (err) |
| 1012 | return err; |
| 1013 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1014 | err = _mv88e6xxx_atu_data_write(chip, entry); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1015 | if (err) |
| 1016 | return err; |
| 1017 | |
| 1018 | if (entry->fid) { |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1019 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : |
| 1020 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; |
| 1021 | } else { |
| 1022 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : |
| 1023 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; |
| 1024 | } |
| 1025 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1026 | return _mv88e6xxx_atu_cmd(chip, entry->fid, op); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1027 | } |
| 1028 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1029 | static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1030 | u16 fid, bool static_too) |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1031 | { |
| 1032 | struct mv88e6xxx_atu_entry entry = { |
| 1033 | .fid = fid, |
| 1034 | .state = 0, /* EntryState bits must be 0 */ |
| 1035 | }; |
| 1036 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1037 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1038 | } |
| 1039 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1040 | static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1041 | int from_port, int to_port, bool static_too) |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1042 | { |
| 1043 | struct mv88e6xxx_atu_entry entry = { |
| 1044 | .trunk = false, |
| 1045 | .fid = fid, |
| 1046 | }; |
| 1047 | |
| 1048 | /* EntryState bits must be 0xF */ |
| 1049 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; |
| 1050 | |
| 1051 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ |
| 1052 | entry.portv_trunkid = (to_port & 0x0f) << 4; |
| 1053 | entry.portv_trunkid |= from_port & 0x0f; |
| 1054 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1055 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1056 | } |
| 1057 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1058 | static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1059 | int port, bool static_too) |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1060 | { |
| 1061 | /* Destination port 0xF means remove the entries */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1062 | return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1063 | } |
| 1064 | |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1065 | static const char * const mv88e6xxx_port_state_names[] = { |
| 1066 | [PORT_CONTROL_STATE_DISABLED] = "Disabled", |
| 1067 | [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", |
| 1068 | [PORT_CONTROL_STATE_LEARNING] = "Learning", |
| 1069 | [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", |
| 1070 | }; |
| 1071 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1072 | static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1073 | u8 state) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1074 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1075 | struct dsa_switch *ds = chip->ds; |
Geert Uytterhoeven | c3ffe6d | 2015-04-16 20:49:14 +0200 | [diff] [blame] | 1076 | int reg, ret = 0; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1077 | u8 oldstate; |
| 1078 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1079 | reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL); |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1080 | if (reg < 0) |
| 1081 | return reg; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1082 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1083 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1084 | |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1085 | if (oldstate != state) { |
| 1086 | /* Flush forwarding database if we're moving a port |
| 1087 | * from Learning or Forwarding state to Disabled or |
| 1088 | * Blocking or Listening state. |
| 1089 | */ |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1090 | if ((oldstate == PORT_CONTROL_STATE_LEARNING || |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1091 | oldstate == PORT_CONTROL_STATE_FORWARDING) && |
| 1092 | (state == PORT_CONTROL_STATE_DISABLED || |
| 1093 | state == PORT_CONTROL_STATE_BLOCKING)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1094 | ret = _mv88e6xxx_atu_remove(chip, 0, port, false); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1095 | if (ret) |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1096 | return ret; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1097 | } |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1098 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1099 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1100 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL, |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1101 | reg); |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1102 | if (ret) |
| 1103 | return ret; |
| 1104 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1105 | netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n", |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1106 | mv88e6xxx_port_state_names[state], |
| 1107 | mv88e6xxx_port_state_names[oldstate]); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1108 | } |
| 1109 | |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1110 | return ret; |
| 1111 | } |
| 1112 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1113 | static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1114 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1115 | struct net_device *bridge = chip->ports[port].bridge_dev; |
| 1116 | const u16 mask = (1 << chip->info->num_ports) - 1; |
| 1117 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1118 | u16 output_ports = 0; |
Vivien Didelot | ede8098 | 2015-10-11 18:08:35 -0400 | [diff] [blame] | 1119 | int reg; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1120 | int i; |
| 1121 | |
| 1122 | /* allow CPU port or DSA link(s) to send frames to every port */ |
| 1123 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
| 1124 | output_ports = mask; |
| 1125 | } else { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1126 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1127 | /* allow sending frames to every group member */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1128 | if (bridge && chip->ports[i].bridge_dev == bridge) |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1129 | output_ports |= BIT(i); |
| 1130 | |
| 1131 | /* allow sending frames to CPU port and DSA link(s) */ |
| 1132 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
| 1133 | output_ports |= BIT(i); |
| 1134 | } |
| 1135 | } |
| 1136 | |
| 1137 | /* prevent frames from going back out of the port they came in on */ |
| 1138 | output_ports &= ~BIT(port); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1139 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1140 | reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN); |
Vivien Didelot | ede8098 | 2015-10-11 18:08:35 -0400 | [diff] [blame] | 1141 | if (reg < 0) |
| 1142 | return reg; |
| 1143 | |
| 1144 | reg &= ~mask; |
| 1145 | reg |= output_ports & mask; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1146 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1147 | return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1148 | } |
| 1149 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1150 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
| 1151 | u8 state) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1152 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1153 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1154 | int stp_state; |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1155 | int err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1156 | |
| 1157 | switch (state) { |
| 1158 | case BR_STATE_DISABLED: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1159 | stp_state = PORT_CONTROL_STATE_DISABLED; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1160 | break; |
| 1161 | case BR_STATE_BLOCKING: |
| 1162 | case BR_STATE_LISTENING: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1163 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1164 | break; |
| 1165 | case BR_STATE_LEARNING: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1166 | stp_state = PORT_CONTROL_STATE_LEARNING; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1167 | break; |
| 1168 | case BR_STATE_FORWARDING: |
| 1169 | default: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1170 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1171 | break; |
| 1172 | } |
| 1173 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1174 | mutex_lock(&chip->reg_lock); |
| 1175 | err = _mv88e6xxx_port_state(chip, port, stp_state); |
| 1176 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1177 | |
| 1178 | if (err) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1179 | netdev_err(ds->ports[port].netdev, |
| 1180 | "failed to update state to %s\n", |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1181 | mv88e6xxx_port_state_names[stp_state]); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1182 | } |
| 1183 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1184 | static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1185 | u16 *new, u16 *old) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1186 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1187 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1188 | u16 pvid; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1189 | int ret; |
| 1190 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1191 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1192 | if (ret < 0) |
| 1193 | return ret; |
| 1194 | |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1195 | pvid = ret & PORT_DEFAULT_VLAN_MASK; |
| 1196 | |
| 1197 | if (new) { |
| 1198 | ret &= ~PORT_DEFAULT_VLAN_MASK; |
| 1199 | ret |= *new & PORT_DEFAULT_VLAN_MASK; |
| 1200 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1201 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1202 | PORT_DEFAULT_VLAN, ret); |
| 1203 | if (ret < 0) |
| 1204 | return ret; |
| 1205 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1206 | netdev_dbg(ds->ports[port].netdev, |
| 1207 | "DefaultVID %d (was %d)\n", *new, pvid); |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1208 | } |
| 1209 | |
| 1210 | if (old) |
| 1211 | *old = pvid; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1212 | |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1216 | static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1217 | int port, u16 *pvid) |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1218 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1219 | return _mv88e6xxx_port_pvid(chip, port, NULL, pvid); |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1220 | } |
| 1221 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1222 | static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1223 | int port, u16 pvid) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1224 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1225 | return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1226 | } |
| 1227 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1228 | static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1229 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1230 | return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP, |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1231 | GLOBAL_VTU_OP_BUSY); |
| 1232 | } |
| 1233 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1234 | static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1235 | { |
| 1236 | int ret; |
| 1237 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1238 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1239 | if (ret < 0) |
| 1240 | return ret; |
| 1241 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1242 | return _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1243 | } |
| 1244 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1245 | static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1246 | { |
| 1247 | int ret; |
| 1248 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1249 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1250 | if (ret < 0) |
| 1251 | return ret; |
| 1252 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1253 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1254 | } |
| 1255 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1256 | static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1257 | struct mv88e6xxx_vtu_stu_entry *entry, |
| 1258 | unsigned int nibble_offset) |
| 1259 | { |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1260 | u16 regs[3]; |
| 1261 | int i; |
| 1262 | int ret; |
| 1263 | |
| 1264 | for (i = 0; i < 3; ++i) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1265 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1266 | GLOBAL_VTU_DATA_0_3 + i); |
| 1267 | if (ret < 0) |
| 1268 | return ret; |
| 1269 | |
| 1270 | regs[i] = ret; |
| 1271 | } |
| 1272 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1273 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1274 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
| 1275 | u16 reg = regs[i / 4]; |
| 1276 | |
| 1277 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; |
| 1278 | } |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1283 | static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1284 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1285 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1286 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1287 | } |
| 1288 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1289 | static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1290 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1291 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1292 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1293 | } |
| 1294 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1295 | static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1296 | struct mv88e6xxx_vtu_stu_entry *entry, |
| 1297 | unsigned int nibble_offset) |
| 1298 | { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1299 | u16 regs[3] = { 0 }; |
| 1300 | int i; |
| 1301 | int ret; |
| 1302 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1303 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1304 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
| 1305 | u8 data = entry->data[i]; |
| 1306 | |
| 1307 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; |
| 1308 | } |
| 1309 | |
| 1310 | for (i = 0; i < 3; ++i) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1311 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1312 | GLOBAL_VTU_DATA_0_3 + i, regs[i]); |
| 1313 | if (ret < 0) |
| 1314 | return ret; |
| 1315 | } |
| 1316 | |
| 1317 | return 0; |
| 1318 | } |
| 1319 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1320 | static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1321 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1322 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1323 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1324 | } |
| 1325 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1326 | static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1327 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1328 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1329 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1330 | } |
| 1331 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1332 | static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) |
Vivien Didelot | 36d04ba1 | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1333 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1334 | return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, |
Vivien Didelot | 36d04ba1 | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1335 | vid & GLOBAL_VTU_VID_MASK); |
| 1336 | } |
| 1337 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1338 | static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1339 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1340 | { |
| 1341 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; |
| 1342 | int ret; |
| 1343 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1344 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1345 | if (ret < 0) |
| 1346 | return ret; |
| 1347 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1348 | ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1349 | if (ret < 0) |
| 1350 | return ret; |
| 1351 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1352 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1353 | if (ret < 0) |
| 1354 | return ret; |
| 1355 | |
| 1356 | next.vid = ret & GLOBAL_VTU_VID_MASK; |
| 1357 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); |
| 1358 | |
| 1359 | if (next.valid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1360 | ret = mv88e6xxx_vtu_data_read(chip, &next); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1361 | if (ret < 0) |
| 1362 | return ret; |
| 1363 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1364 | if (mv88e6xxx_has_fid_reg(chip)) { |
| 1365 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1366 | GLOBAL_VTU_FID); |
| 1367 | if (ret < 0) |
| 1368 | return ret; |
| 1369 | |
| 1370 | next.fid = ret & GLOBAL_VTU_FID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1371 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1372 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
| 1373 | * VTU DBNum[3:0] are located in VTU Operation 3:0 |
| 1374 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1375 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1376 | GLOBAL_VTU_OP); |
| 1377 | if (ret < 0) |
| 1378 | return ret; |
| 1379 | |
| 1380 | next.fid = (ret & 0xf00) >> 4; |
| 1381 | next.fid |= ret & 0xf; |
Vivien Didelot | 2e7bd5e | 2016-03-31 16:53:41 -0400 | [diff] [blame] | 1382 | } |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1383 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1384 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
| 1385 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1386 | GLOBAL_VTU_SID); |
| 1387 | if (ret < 0) |
| 1388 | return ret; |
| 1389 | |
| 1390 | next.sid = ret & GLOBAL_VTU_SID_MASK; |
| 1391 | } |
| 1392 | } |
| 1393 | |
| 1394 | *entry = next; |
| 1395 | return 0; |
| 1396 | } |
| 1397 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1398 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
| 1399 | struct switchdev_obj_port_vlan *vlan, |
| 1400 | int (*cb)(struct switchdev_obj *obj)) |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1401 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1402 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1403 | struct mv88e6xxx_vtu_stu_entry next; |
| 1404 | u16 pvid; |
| 1405 | int err; |
| 1406 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1407 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1408 | return -EOPNOTSUPP; |
| 1409 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1410 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1411 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1412 | err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1413 | if (err) |
| 1414 | goto unlock; |
| 1415 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1416 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1417 | if (err) |
| 1418 | goto unlock; |
| 1419 | |
| 1420 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1421 | err = _mv88e6xxx_vtu_getnext(chip, &next); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1422 | if (err) |
| 1423 | break; |
| 1424 | |
| 1425 | if (!next.valid) |
| 1426 | break; |
| 1427 | |
| 1428 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
| 1429 | continue; |
| 1430 | |
| 1431 | /* reinit and dump this VLAN obj */ |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1432 | vlan->vid_begin = next.vid; |
| 1433 | vlan->vid_end = next.vid; |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1434 | vlan->flags = 0; |
| 1435 | |
| 1436 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) |
| 1437 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; |
| 1438 | |
| 1439 | if (next.vid == pvid) |
| 1440 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; |
| 1441 | |
| 1442 | err = cb(&vlan->obj); |
| 1443 | if (err) |
| 1444 | break; |
| 1445 | } while (next.vid < GLOBAL_VTU_VID_MASK); |
| 1446 | |
| 1447 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1448 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1449 | |
| 1450 | return err; |
| 1451 | } |
| 1452 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1453 | static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1454 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1455 | { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1456 | u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1457 | u16 reg = 0; |
| 1458 | int ret; |
| 1459 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1460 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1461 | if (ret < 0) |
| 1462 | return ret; |
| 1463 | |
| 1464 | if (!entry->valid) |
| 1465 | goto loadpurge; |
| 1466 | |
| 1467 | /* Write port member tags */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1468 | ret = mv88e6xxx_vtu_data_write(chip, entry); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1469 | if (ret < 0) |
| 1470 | return ret; |
| 1471 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1472 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1473 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1474 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, |
| 1475 | reg); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1476 | if (ret < 0) |
| 1477 | return ret; |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 1478 | } |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1479 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1480 | if (mv88e6xxx_has_fid_reg(chip)) { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1481 | reg = entry->fid & GLOBAL_VTU_FID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1482 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID, |
| 1483 | reg); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1484 | if (ret < 0) |
| 1485 | return ret; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1486 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1487 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
| 1488 | * VTU DBNum[3:0] are located in VTU Operation 3:0 |
| 1489 | */ |
| 1490 | op |= (entry->fid & 0xf0) << 8; |
| 1491 | op |= entry->fid & 0xf; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1492 | } |
| 1493 | |
| 1494 | reg = GLOBAL_VTU_VID_VALID; |
| 1495 | loadpurge: |
| 1496 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1497 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1498 | if (ret < 0) |
| 1499 | return ret; |
| 1500 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1501 | return _mv88e6xxx_vtu_cmd(chip, op); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1502 | } |
| 1503 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1504 | static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1505 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1506 | { |
| 1507 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; |
| 1508 | int ret; |
| 1509 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1510 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1511 | if (ret < 0) |
| 1512 | return ret; |
| 1513 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1514 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1515 | sid & GLOBAL_VTU_SID_MASK); |
| 1516 | if (ret < 0) |
| 1517 | return ret; |
| 1518 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1519 | ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1520 | if (ret < 0) |
| 1521 | return ret; |
| 1522 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1523 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1524 | if (ret < 0) |
| 1525 | return ret; |
| 1526 | |
| 1527 | next.sid = ret & GLOBAL_VTU_SID_MASK; |
| 1528 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1529 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1530 | if (ret < 0) |
| 1531 | return ret; |
| 1532 | |
| 1533 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); |
| 1534 | |
| 1535 | if (next.valid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1536 | ret = mv88e6xxx_stu_data_read(chip, &next); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1537 | if (ret < 0) |
| 1538 | return ret; |
| 1539 | } |
| 1540 | |
| 1541 | *entry = next; |
| 1542 | return 0; |
| 1543 | } |
| 1544 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1545 | static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1546 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1547 | { |
| 1548 | u16 reg = 0; |
| 1549 | int ret; |
| 1550 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1551 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1552 | if (ret < 0) |
| 1553 | return ret; |
| 1554 | |
| 1555 | if (!entry->valid) |
| 1556 | goto loadpurge; |
| 1557 | |
| 1558 | /* Write port states */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1559 | ret = mv88e6xxx_stu_data_write(chip, entry); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1560 | if (ret < 0) |
| 1561 | return ret; |
| 1562 | |
| 1563 | reg = GLOBAL_VTU_VID_VALID; |
| 1564 | loadpurge: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1565 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1566 | if (ret < 0) |
| 1567 | return ret; |
| 1568 | |
| 1569 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1570 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1571 | if (ret < 0) |
| 1572 | return ret; |
| 1573 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1574 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1575 | } |
| 1576 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1577 | static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1578 | u16 *new, u16 *old) |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1579 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1580 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1581 | u16 upper_mask; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1582 | u16 fid; |
| 1583 | int ret; |
| 1584 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1585 | if (mv88e6xxx_num_databases(chip) == 4096) |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1586 | upper_mask = 0xff; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1587 | else if (mv88e6xxx_num_databases(chip) == 256) |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1588 | upper_mask = 0xf; |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1589 | else |
| 1590 | return -EOPNOTSUPP; |
| 1591 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1592 | /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1593 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1594 | if (ret < 0) |
| 1595 | return ret; |
| 1596 | |
| 1597 | fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12; |
| 1598 | |
| 1599 | if (new) { |
| 1600 | ret &= ~PORT_BASE_VLAN_FID_3_0_MASK; |
| 1601 | ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; |
| 1602 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1603 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1604 | ret); |
| 1605 | if (ret < 0) |
| 1606 | return ret; |
| 1607 | } |
| 1608 | |
| 1609 | /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1610 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1611 | if (ret < 0) |
| 1612 | return ret; |
| 1613 | |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1614 | fid |= (ret & upper_mask) << 4; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1615 | |
| 1616 | if (new) { |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1617 | ret &= ~upper_mask; |
| 1618 | ret |= (*new >> 4) & upper_mask; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1619 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1620 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1, |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1621 | ret); |
| 1622 | if (ret < 0) |
| 1623 | return ret; |
| 1624 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1625 | netdev_dbg(ds->ports[port].netdev, |
| 1626 | "FID %d (was %d)\n", *new, fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1627 | } |
| 1628 | |
| 1629 | if (old) |
| 1630 | *old = fid; |
| 1631 | |
| 1632 | return 0; |
| 1633 | } |
| 1634 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1635 | static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1636 | int port, u16 *fid) |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1637 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1638 | return _mv88e6xxx_port_fid(chip, port, NULL, fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1639 | } |
| 1640 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1641 | static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1642 | int port, u16 fid) |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1643 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1644 | return _mv88e6xxx_port_fid(chip, port, &fid, NULL); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1645 | } |
| 1646 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1647 | static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1648 | { |
| 1649 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); |
| 1650 | struct mv88e6xxx_vtu_stu_entry vlan; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1651 | int i, err; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1652 | |
| 1653 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); |
| 1654 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1655 | /* Set every FID bit used by the (un)bridged ports */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1656 | for (i = 0; i < chip->info->num_ports; ++i) { |
| 1657 | err = _mv88e6xxx_port_fid_get(chip, i, fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1658 | if (err) |
| 1659 | return err; |
| 1660 | |
| 1661 | set_bit(*fid, fid_bitmap); |
| 1662 | } |
| 1663 | |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1664 | /* Set every FID bit used by the VLAN entries */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1665 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1666 | if (err) |
| 1667 | return err; |
| 1668 | |
| 1669 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1670 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1671 | if (err) |
| 1672 | return err; |
| 1673 | |
| 1674 | if (!vlan.valid) |
| 1675 | break; |
| 1676 | |
| 1677 | set_bit(vlan.fid, fid_bitmap); |
| 1678 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
| 1679 | |
| 1680 | /* The reset value 0x000 is used to indicate that multiple address |
| 1681 | * databases are not needed. Return the next positive available. |
| 1682 | */ |
| 1683 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1684 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1685 | return -ENOSPC; |
| 1686 | |
| 1687 | /* Clear the database */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1688 | return _mv88e6xxx_atu_flush(chip, *fid, true); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1689 | } |
| 1690 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1691 | static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1692 | struct mv88e6xxx_vtu_stu_entry *entry) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1693 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1694 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1695 | struct mv88e6xxx_vtu_stu_entry vlan = { |
| 1696 | .valid = true, |
| 1697 | .vid = vid, |
| 1698 | }; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1699 | int i, err; |
| 1700 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1701 | err = _mv88e6xxx_fid_new(chip, &vlan.fid); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1702 | if (err) |
| 1703 | return err; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1704 | |
Vivien Didelot | 3d131f0 | 2015-11-03 10:52:52 -0500 | [diff] [blame] | 1705 | /* exclude all ports except the CPU and DSA ports */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1706 | for (i = 0; i < chip->info->num_ports; ++i) |
Vivien Didelot | 3d131f0 | 2015-11-03 10:52:52 -0500 | [diff] [blame] | 1707 | vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) |
| 1708 | ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED |
| 1709 | : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1710 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1711 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
| 1712 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1713 | struct mv88e6xxx_vtu_stu_entry vstp; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1714 | |
| 1715 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not |
| 1716 | * implemented, only one STU entry is needed to cover all VTU |
| 1717 | * entries. Thus, validate the SID 0. |
| 1718 | */ |
| 1719 | vlan.sid = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1720 | err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1721 | if (err) |
| 1722 | return err; |
| 1723 | |
| 1724 | if (vstp.sid != vlan.sid || !vstp.valid) { |
| 1725 | memset(&vstp, 0, sizeof(vstp)); |
| 1726 | vstp.valid = true; |
| 1727 | vstp.sid = vlan.sid; |
| 1728 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1729 | err = _mv88e6xxx_stu_loadpurge(chip, &vstp); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1730 | if (err) |
| 1731 | return err; |
| 1732 | } |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1733 | } |
| 1734 | |
| 1735 | *entry = vlan; |
| 1736 | return 0; |
| 1737 | } |
| 1738 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1739 | static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1740 | struct mv88e6xxx_vtu_stu_entry *entry, bool creat) |
| 1741 | { |
| 1742 | int err; |
| 1743 | |
| 1744 | if (!vid) |
| 1745 | return -EINVAL; |
| 1746 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1747 | err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1748 | if (err) |
| 1749 | return err; |
| 1750 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1751 | err = _mv88e6xxx_vtu_getnext(chip, entry); |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1752 | if (err) |
| 1753 | return err; |
| 1754 | |
| 1755 | if (entry->vid != vid || !entry->valid) { |
| 1756 | if (!creat) |
| 1757 | return -EOPNOTSUPP; |
| 1758 | /* -ENOENT would've been more appropriate, but switchdev expects |
| 1759 | * -EOPNOTSUPP to inform bridge about an eventual software VLAN. |
| 1760 | */ |
| 1761 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1762 | err = _mv88e6xxx_vtu_new(chip, vid, entry); |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1763 | } |
| 1764 | |
| 1765 | return err; |
| 1766 | } |
| 1767 | |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1768 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
| 1769 | u16 vid_begin, u16 vid_end) |
| 1770 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1771 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1772 | struct mv88e6xxx_vtu_stu_entry vlan; |
| 1773 | int i, err; |
| 1774 | |
| 1775 | if (!vid_begin) |
| 1776 | return -EOPNOTSUPP; |
| 1777 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1778 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1779 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1780 | err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1781 | if (err) |
| 1782 | goto unlock; |
| 1783 | |
| 1784 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1785 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1786 | if (err) |
| 1787 | goto unlock; |
| 1788 | |
| 1789 | if (!vlan.valid) |
| 1790 | break; |
| 1791 | |
| 1792 | if (vlan.vid > vid_end) |
| 1793 | break; |
| 1794 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1795 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1796 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
| 1797 | continue; |
| 1798 | |
| 1799 | if (vlan.data[i] == |
| 1800 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
| 1801 | continue; |
| 1802 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1803 | if (chip->ports[i].bridge_dev == |
| 1804 | chip->ports[port].bridge_dev) |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1805 | break; /* same bridge, check next VLAN */ |
| 1806 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1807 | netdev_warn(ds->ports[port].netdev, |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1808 | "hardware VLAN %d already used by %s\n", |
| 1809 | vlan.vid, |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1810 | netdev_name(chip->ports[i].bridge_dev)); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1811 | err = -EOPNOTSUPP; |
| 1812 | goto unlock; |
| 1813 | } |
| 1814 | } while (vlan.vid < vid_end); |
| 1815 | |
| 1816 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1817 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1818 | |
| 1819 | return err; |
| 1820 | } |
| 1821 | |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1822 | static const char * const mv88e6xxx_port_8021q_mode_names[] = { |
| 1823 | [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", |
| 1824 | [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", |
| 1825 | [PORT_CONTROL_2_8021Q_CHECK] = "Check", |
| 1826 | [PORT_CONTROL_2_8021Q_SECURE] = "Secure", |
| 1827 | }; |
| 1828 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1829 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
| 1830 | bool vlan_filtering) |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1831 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1832 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1833 | u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : |
| 1834 | PORT_CONTROL_2_8021Q_DISABLED; |
| 1835 | int ret; |
| 1836 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1837 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1838 | return -EOPNOTSUPP; |
| 1839 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1840 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1841 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1842 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1843 | if (ret < 0) |
| 1844 | goto unlock; |
| 1845 | |
| 1846 | old = ret & PORT_CONTROL_2_8021Q_MASK; |
| 1847 | |
Vivien Didelot | 5220ef1 | 2016-03-07 18:24:52 -0500 | [diff] [blame] | 1848 | if (new != old) { |
| 1849 | ret &= ~PORT_CONTROL_2_8021Q_MASK; |
| 1850 | ret |= new & PORT_CONTROL_2_8021Q_MASK; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1851 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1852 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2, |
Vivien Didelot | 5220ef1 | 2016-03-07 18:24:52 -0500 | [diff] [blame] | 1853 | ret); |
| 1854 | if (ret < 0) |
| 1855 | goto unlock; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1856 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1857 | netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n", |
Vivien Didelot | 5220ef1 | 2016-03-07 18:24:52 -0500 | [diff] [blame] | 1858 | mv88e6xxx_port_8021q_mode_names[new], |
| 1859 | mv88e6xxx_port_8021q_mode_names[old]); |
| 1860 | } |
| 1861 | |
| 1862 | ret = 0; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1863 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1864 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1865 | |
| 1866 | return ret; |
| 1867 | } |
| 1868 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1869 | static int |
| 1870 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
| 1871 | const struct switchdev_obj_port_vlan *vlan, |
| 1872 | struct switchdev_trans *trans) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1873 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1874 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1875 | int err; |
| 1876 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1877 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1878 | return -EOPNOTSUPP; |
| 1879 | |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1880 | /* If the requested port doesn't belong to the same bridge as the VLAN |
| 1881 | * members, do not support it (yet) and fallback to software VLAN. |
| 1882 | */ |
| 1883 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, |
| 1884 | vlan->vid_end); |
| 1885 | if (err) |
| 1886 | return err; |
| 1887 | |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1888 | /* We don't need any dynamic resource from the kernel (yet), |
| 1889 | * so skip the prepare phase. |
| 1890 | */ |
| 1891 | return 0; |
| 1892 | } |
| 1893 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1894 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1895 | u16 vid, bool untagged) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1896 | { |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1897 | struct mv88e6xxx_vtu_stu_entry vlan; |
| 1898 | int err; |
| 1899 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1900 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
Vivien Didelot | 36d04ba1 | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1901 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1902 | return err; |
Vivien Didelot | 36d04ba1 | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1903 | |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1904 | vlan.data[port] = untagged ? |
| 1905 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : |
| 1906 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; |
| 1907 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1908 | return _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1909 | } |
| 1910 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1911 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
| 1912 | const struct switchdev_obj_port_vlan *vlan, |
| 1913 | struct switchdev_trans *trans) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1914 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1915 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1916 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
| 1917 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; |
| 1918 | u16 vid; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1919 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1920 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1921 | return; |
| 1922 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1923 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1924 | |
Vivien Didelot | 4d5770b | 2016-04-06 11:55:05 -0400 | [diff] [blame] | 1925 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1926 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1927 | netdev_err(ds->ports[port].netdev, |
| 1928 | "failed to add VLAN %d%c\n", |
Vivien Didelot | 4d5770b | 2016-04-06 11:55:05 -0400 | [diff] [blame] | 1929 | vid, untagged ? 'u' : 't'); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1930 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1931 | if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1932 | netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", |
Vivien Didelot | 4d5770b | 2016-04-06 11:55:05 -0400 | [diff] [blame] | 1933 | vlan->vid_end); |
| 1934 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1935 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1936 | } |
| 1937 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1938 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1939 | int port, u16 vid) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1940 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1941 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1942 | struct mv88e6xxx_vtu_stu_entry vlan; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1943 | int i, err; |
| 1944 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1945 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
Vivien Didelot | 36d04ba1 | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1946 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1947 | return err; |
Vivien Didelot | 36d04ba1 | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1948 | |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1949 | /* Tell switchdev if this VLAN is handled in software */ |
| 1950 | if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
Vivien Didelot | 3c06f08 | 2016-02-05 14:04:39 -0500 | [diff] [blame] | 1951 | return -EOPNOTSUPP; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1952 | |
| 1953 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
| 1954 | |
| 1955 | /* keep the VLAN unless all ports are excluded */ |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 1956 | vlan.valid = false; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1957 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | 3d131f0 | 2015-11-03 10:52:52 -0500 | [diff] [blame] | 1958 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1959 | continue; |
| 1960 | |
| 1961 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 1962 | vlan.valid = true; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1963 | break; |
| 1964 | } |
| 1965 | } |
| 1966 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1967 | err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1968 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1969 | return err; |
| 1970 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1971 | return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1972 | } |
| 1973 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1974 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
| 1975 | const struct switchdev_obj_port_vlan *vlan) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1976 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1977 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1978 | u16 pvid, vid; |
| 1979 | int err = 0; |
| 1980 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1981 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1982 | return -EOPNOTSUPP; |
| 1983 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1984 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1985 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1986 | err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1987 | if (err) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1988 | goto unlock; |
| 1989 | |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1990 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1991 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1992 | if (err) |
| 1993 | goto unlock; |
| 1994 | |
| 1995 | if (vid == pvid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1996 | err = _mv88e6xxx_port_pvid_set(chip, port, 0); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1997 | if (err) |
| 1998 | goto unlock; |
| 1999 | } |
| 2000 | } |
| 2001 | |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2002 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2003 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2004 | |
| 2005 | return err; |
| 2006 | } |
| 2007 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2008 | static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | c5723ac | 2015-08-10 09:09:48 -0400 | [diff] [blame] | 2009 | const unsigned char *addr) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2010 | { |
| 2011 | int i, ret; |
| 2012 | |
| 2013 | for (i = 0; i < 3; i++) { |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 2014 | ret = _mv88e6xxx_reg_write( |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2015 | chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 2016 | (addr[i * 2] << 8) | addr[i * 2 + 1]); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2017 | if (ret < 0) |
| 2018 | return ret; |
| 2019 | } |
| 2020 | |
| 2021 | return 0; |
| 2022 | } |
| 2023 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2024 | static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 2025 | unsigned char *addr) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2026 | { |
| 2027 | int i, ret; |
| 2028 | |
| 2029 | for (i = 0; i < 3; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2030 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 2031 | GLOBAL_ATU_MAC_01 + i); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2032 | if (ret < 0) |
| 2033 | return ret; |
| 2034 | addr[i * 2] = ret >> 8; |
| 2035 | addr[i * 2 + 1] = ret & 0xff; |
| 2036 | } |
| 2037 | |
| 2038 | return 0; |
| 2039 | } |
| 2040 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2041 | static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2042 | struct mv88e6xxx_atu_entry *entry) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2043 | { |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2044 | int ret; |
| 2045 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2046 | ret = _mv88e6xxx_atu_wait(chip); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2047 | if (ret < 0) |
| 2048 | return ret; |
| 2049 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2050 | ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2051 | if (ret < 0) |
| 2052 | return ret; |
| 2053 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2054 | ret = _mv88e6xxx_atu_data_write(chip, entry); |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2055 | if (ret < 0) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2056 | return ret; |
| 2057 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2058 | return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2059 | } |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2060 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2061 | static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port, |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2062 | const unsigned char *addr, u16 vid, |
| 2063 | u8 state) |
| 2064 | { |
| 2065 | struct mv88e6xxx_atu_entry entry = { 0 }; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 2066 | struct mv88e6xxx_vtu_stu_entry vlan; |
| 2067 | int err; |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2068 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2069 | /* Null VLAN ID corresponds to the port private database */ |
| 2070 | if (vid == 0) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2071 | err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2072 | else |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2073 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 2074 | if (err) |
| 2075 | return err; |
| 2076 | |
| 2077 | entry.fid = vlan.fid; |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2078 | entry.state = state; |
| 2079 | ether_addr_copy(entry.mac, addr); |
| 2080 | if (state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
| 2081 | entry.trunk = false; |
| 2082 | entry.portv_trunkid = BIT(port); |
| 2083 | } |
| 2084 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2085 | return _mv88e6xxx_atu_load(chip, &entry); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2086 | } |
| 2087 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2088 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
| 2089 | const struct switchdev_obj_port_fdb *fdb, |
| 2090 | struct switchdev_trans *trans) |
Vivien Didelot | 146a320 | 2015-10-08 11:35:12 -0400 | [diff] [blame] | 2091 | { |
| 2092 | /* We don't need any dynamic resource from the kernel (yet), |
| 2093 | * so skip the prepare phase. |
| 2094 | */ |
| 2095 | return 0; |
| 2096 | } |
| 2097 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2098 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
| 2099 | const struct switchdev_obj_port_fdb *fdb, |
| 2100 | struct switchdev_trans *trans) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2101 | { |
Vivien Didelot | 1f36faf | 2015-10-08 11:35:13 -0400 | [diff] [blame] | 2102 | int state = is_multicast_ether_addr(fdb->addr) ? |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2103 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
| 2104 | GLOBAL_ATU_DATA_STATE_UC_STATIC; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2105 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | 6630e23 | 2015-08-06 01:44:07 -0400 | [diff] [blame] | 2106 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2107 | mutex_lock(&chip->reg_lock); |
| 2108 | if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 2109 | netdev_err(ds->ports[port].netdev, |
| 2110 | "failed to load MAC address\n"); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2111 | mutex_unlock(&chip->reg_lock); |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2112 | } |
| 2113 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2114 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
| 2115 | const struct switchdev_obj_port_fdb *fdb) |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2116 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2117 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2118 | int ret; |
| 2119 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2120 | mutex_lock(&chip->reg_lock); |
| 2121 | ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2122 | GLOBAL_ATU_DATA_STATE_UNUSED); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2123 | mutex_unlock(&chip->reg_lock); |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2124 | |
| 2125 | return ret; |
| 2126 | } |
| 2127 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2128 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2129 | struct mv88e6xxx_atu_entry *entry) |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2130 | { |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2131 | struct mv88e6xxx_atu_entry next = { 0 }; |
| 2132 | int ret; |
| 2133 | |
| 2134 | next.fid = fid; |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2135 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2136 | ret = _mv88e6xxx_atu_wait(chip); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2137 | if (ret < 0) |
| 2138 | return ret; |
| 2139 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2140 | ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2141 | if (ret < 0) |
| 2142 | return ret; |
| 2143 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2144 | ret = _mv88e6xxx_atu_mac_read(chip, next.mac); |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2145 | if (ret < 0) |
| 2146 | return ret; |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2147 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2148 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA); |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2149 | if (ret < 0) |
| 2150 | return ret; |
| 2151 | |
| 2152 | next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
| 2153 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
| 2154 | unsigned int mask, shift; |
| 2155 | |
| 2156 | if (ret & GLOBAL_ATU_DATA_TRUNK) { |
| 2157 | next.trunk = true; |
| 2158 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; |
| 2159 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; |
| 2160 | } else { |
| 2161 | next.trunk = false; |
| 2162 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; |
| 2163 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; |
| 2164 | } |
| 2165 | |
| 2166 | next.portv_trunkid = (ret & mask) >> shift; |
| 2167 | } |
| 2168 | |
| 2169 | *entry = next; |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2170 | return 0; |
| 2171 | } |
| 2172 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2173 | static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 2174 | u16 fid, u16 vid, int port, |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2175 | struct switchdev_obj_port_fdb *fdb, |
| 2176 | int (*cb)(struct switchdev_obj *obj)) |
| 2177 | { |
| 2178 | struct mv88e6xxx_atu_entry addr = { |
| 2179 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, |
| 2180 | }; |
| 2181 | int err; |
| 2182 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2183 | err = _mv88e6xxx_atu_mac_write(chip, addr.mac); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2184 | if (err) |
| 2185 | return err; |
| 2186 | |
| 2187 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2188 | err = _mv88e6xxx_atu_getnext(chip, fid, &addr); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2189 | if (err) |
| 2190 | break; |
| 2191 | |
| 2192 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) |
| 2193 | break; |
| 2194 | |
| 2195 | if (!addr.trunk && addr.portv_trunkid & BIT(port)) { |
| 2196 | bool is_static = addr.state == |
| 2197 | (is_multicast_ether_addr(addr.mac) ? |
| 2198 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
| 2199 | GLOBAL_ATU_DATA_STATE_UC_STATIC); |
| 2200 | |
| 2201 | fdb->vid = vid; |
| 2202 | ether_addr_copy(fdb->addr, addr.mac); |
| 2203 | fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; |
| 2204 | |
| 2205 | err = cb(&fdb->obj); |
| 2206 | if (err) |
| 2207 | break; |
| 2208 | } |
| 2209 | } while (!is_broadcast_ether_addr(addr.mac)); |
| 2210 | |
| 2211 | return err; |
| 2212 | } |
| 2213 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2214 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
| 2215 | struct switchdev_obj_port_fdb *fdb, |
| 2216 | int (*cb)(struct switchdev_obj *obj)) |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2217 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2218 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2219 | struct mv88e6xxx_vtu_stu_entry vlan = { |
| 2220 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ |
| 2221 | }; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2222 | u16 fid; |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2223 | int err; |
| 2224 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2225 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2226 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2227 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2228 | err = _mv88e6xxx_port_fid_get(chip, port, &fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2229 | if (err) |
| 2230 | goto unlock; |
| 2231 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2232 | err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2233 | if (err) |
| 2234 | goto unlock; |
| 2235 | |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2236 | /* Dump VLANs' Filtering Information Databases */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2237 | err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2238 | if (err) |
| 2239 | goto unlock; |
| 2240 | |
| 2241 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2242 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2243 | if (err) |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2244 | break; |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2245 | |
| 2246 | if (!vlan.valid) |
| 2247 | break; |
| 2248 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2249 | err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid, |
| 2250 | port, fdb, cb); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2251 | if (err) |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2252 | break; |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2253 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
| 2254 | |
| 2255 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2256 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2257 | |
| 2258 | return err; |
| 2259 | } |
| 2260 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2261 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
| 2262 | struct net_device *bridge) |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2263 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2264 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Colin Ian King | 1d9619d | 2016-04-25 23:11:22 +0100 | [diff] [blame] | 2265 | int i, err = 0; |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2266 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2267 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2268 | |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2269 | /* Assign the bridge and remap each port's VLANTable */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2270 | chip->ports[port].bridge_dev = bridge; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2271 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2272 | for (i = 0; i < chip->info->num_ports; ++i) { |
| 2273 | if (chip->ports[i].bridge_dev == bridge) { |
| 2274 | err = _mv88e6xxx_port_based_vlan_map(chip, i); |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2275 | if (err) |
| 2276 | break; |
| 2277 | } |
| 2278 | } |
| 2279 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2280 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | a669275 | 2016-02-12 12:09:39 -0500 | [diff] [blame] | 2281 | |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2282 | return err; |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2283 | } |
| 2284 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2285 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2286 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2287 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 2288 | struct net_device *bridge = chip->ports[port].bridge_dev; |
Vivien Didelot | 16bfa70 | 2016-03-13 16:21:33 -0400 | [diff] [blame] | 2289 | int i; |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2290 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2291 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2292 | |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2293 | /* Unassign the bridge and remap each port's VLANTable */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2294 | chip->ports[port].bridge_dev = NULL; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2295 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2296 | for (i = 0; i < chip->info->num_ports; ++i) |
| 2297 | if (i == port || chip->ports[i].bridge_dev == bridge) |
| 2298 | if (_mv88e6xxx_port_based_vlan_map(chip, i)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 2299 | netdev_warn(ds->ports[i].netdev, |
| 2300 | "failed to remap\n"); |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2301 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2302 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 66d9cd0 | 2016-02-05 14:07:14 -0500 | [diff] [blame] | 2303 | } |
| 2304 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2305 | static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 2306 | int port, int page, int reg, int val) |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2307 | { |
| 2308 | int ret; |
| 2309 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2310 | ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2311 | if (ret < 0) |
| 2312 | goto restore_page_0; |
| 2313 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2314 | ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2315 | restore_page_0: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2316 | mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2317 | |
| 2318 | return ret; |
| 2319 | } |
| 2320 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2321 | static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 2322 | int port, int page, int reg) |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2323 | { |
| 2324 | int ret; |
| 2325 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2326 | ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2327 | if (ret < 0) |
| 2328 | goto restore_page_0; |
| 2329 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2330 | ret = mv88e6xxx_mdio_read_indirect(chip, port, reg); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2331 | restore_page_0: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2332 | mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 2333 | |
| 2334 | return ret; |
| 2335 | } |
| 2336 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2337 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2338 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2339 | bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2340 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2341 | struct gpio_desc *gpiod = chip->reset; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2342 | unsigned long timeout; |
| 2343 | int ret; |
| 2344 | int i; |
| 2345 | |
| 2346 | /* Set all ports to the disabled state. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2347 | for (i = 0; i < chip->info->num_ports; i++) { |
| 2348 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2349 | if (ret < 0) |
| 2350 | return ret; |
| 2351 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2352 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL, |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2353 | ret & 0xfffc); |
| 2354 | if (ret) |
| 2355 | return ret; |
| 2356 | } |
| 2357 | |
| 2358 | /* Wait for transmit queues to drain. */ |
| 2359 | usleep_range(2000, 4000); |
| 2360 | |
| 2361 | /* If there is a gpio connected to the reset pin, toggle it */ |
| 2362 | if (gpiod) { |
| 2363 | gpiod_set_value_cansleep(gpiod, 1); |
| 2364 | usleep_range(10000, 20000); |
| 2365 | gpiod_set_value_cansleep(gpiod, 0); |
| 2366 | usleep_range(10000, 20000); |
| 2367 | } |
| 2368 | |
| 2369 | /* Reset the switch. Keep the PPU active if requested. The PPU |
| 2370 | * needs to be active to support indirect phy register access |
| 2371 | * through global registers 0x18 and 0x19. |
| 2372 | */ |
| 2373 | if (ppu_active) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2374 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2375 | else |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2376 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2377 | if (ret) |
| 2378 | return ret; |
| 2379 | |
| 2380 | /* Wait up to one second for reset to complete. */ |
| 2381 | timeout = jiffies + 1 * HZ; |
| 2382 | while (time_before(jiffies, timeout)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2383 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2384 | if (ret < 0) |
| 2385 | return ret; |
| 2386 | |
| 2387 | if ((ret & is_reset) == is_reset) |
| 2388 | break; |
| 2389 | usleep_range(1000, 2000); |
| 2390 | } |
| 2391 | if (time_after(jiffies, timeout)) |
| 2392 | ret = -ETIMEDOUT; |
| 2393 | else |
| 2394 | ret = 0; |
| 2395 | |
| 2396 | return ret; |
| 2397 | } |
| 2398 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2399 | static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip) |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2400 | { |
| 2401 | int ret; |
| 2402 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2403 | ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 2404 | PAGE_FIBER_SERDES, MII_BMCR); |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2405 | if (ret < 0) |
| 2406 | return ret; |
| 2407 | |
| 2408 | if (ret & BMCR_PDOWN) { |
| 2409 | ret &= ~BMCR_PDOWN; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2410 | ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 2411 | PAGE_FIBER_SERDES, MII_BMCR, |
| 2412 | ret); |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2413 | } |
| 2414 | |
| 2415 | return ret; |
| 2416 | } |
| 2417 | |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 2418 | static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, |
| 2419 | int reg, u16 *val) |
| 2420 | { |
| 2421 | int addr = chip->info->port_base_addr + port; |
| 2422 | |
| 2423 | if (port >= chip->info->num_ports) |
| 2424 | return -EINVAL; |
| 2425 | |
| 2426 | return mv88e6xxx_read(chip, addr, reg, val); |
| 2427 | } |
| 2428 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2429 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2430 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2431 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 2432 | int ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2433 | u16 reg; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2434 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2435 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2436 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2437 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || |
| 2438 | mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2439 | /* MAC Forcing register: don't force link, speed, |
| 2440 | * duplex or flow control state to any particular |
| 2441 | * values on physical ports, but force the CPU port |
| 2442 | * and all DSA ports to their maximum bandwidth and |
| 2443 | * full duplex. |
| 2444 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2445 | reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL); |
Andrew Lunn | 60045cb | 2015-08-17 23:52:51 +0200 | [diff] [blame] | 2446 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
Russell King | 53adc9e | 2015-09-21 21:42:59 +0100 | [diff] [blame] | 2447 | reg &= ~PORT_PCS_CTRL_UNFORCED; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2448 | reg |= PORT_PCS_CTRL_FORCE_LINK | |
| 2449 | PORT_PCS_CTRL_LINK_UP | |
| 2450 | PORT_PCS_CTRL_DUPLEX_FULL | |
| 2451 | PORT_PCS_CTRL_FORCE_DUPLEX; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2452 | if (mv88e6xxx_6065_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2453 | reg |= PORT_PCS_CTRL_100; |
| 2454 | else |
| 2455 | reg |= PORT_PCS_CTRL_1000; |
| 2456 | } else { |
| 2457 | reg |= PORT_PCS_CTRL_UNFORCED; |
| 2458 | } |
| 2459 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2460 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2461 | PORT_PCS_CTRL, reg); |
| 2462 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2463 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2464 | } |
| 2465 | |
| 2466 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
| 2467 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
| 2468 | * tunneling, determine priority by looking at 802.1p and IP |
| 2469 | * priority fields (IP prio has precedence), and set STP state |
| 2470 | * to Forwarding. |
| 2471 | * |
| 2472 | * If this is the CPU link, use DSA or EDSA tagging depending |
| 2473 | * on which tagging mode was configured. |
| 2474 | * |
| 2475 | * If this is a link to another switch, use DSA tagging mode. |
| 2476 | * |
| 2477 | * If this is the upstream port for this switch, enable |
| 2478 | * forwarding of unknown unicasts and multicasts. |
| 2479 | */ |
| 2480 | reg = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2481 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2482 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2483 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) || |
| 2484 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2485 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
| 2486 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | |
| 2487 | PORT_CONTROL_STATE_FORWARDING; |
| 2488 | if (dsa_is_cpu_port(ds, port)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2489 | if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2490 | reg |= PORT_CONTROL_DSA_TAG; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2491 | if (mv88e6xxx_6352_family(chip) || |
| 2492 | mv88e6xxx_6351_family(chip) || |
| 2493 | mv88e6xxx_6165_family(chip) || |
| 2494 | mv88e6xxx_6097_family(chip) || |
| 2495 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 5377b80 | 2016-06-04 21:17:02 +0200 | [diff] [blame] | 2496 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | |
| 2497 | PORT_CONTROL_FORWARD_UNKNOWN | |
Andrew Lunn | c047a1f | 2015-09-29 01:50:56 +0200 | [diff] [blame] | 2498 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2499 | } |
| 2500 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2501 | if (mv88e6xxx_6352_family(chip) || |
| 2502 | mv88e6xxx_6351_family(chip) || |
| 2503 | mv88e6xxx_6165_family(chip) || |
| 2504 | mv88e6xxx_6097_family(chip) || |
| 2505 | mv88e6xxx_6095_family(chip) || |
| 2506 | mv88e6xxx_6065_family(chip) || |
| 2507 | mv88e6xxx_6185_family(chip) || |
| 2508 | mv88e6xxx_6320_family(chip)) { |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 2509 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2510 | } |
| 2511 | } |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2512 | if (dsa_is_dsa_port(ds, port)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2513 | if (mv88e6xxx_6095_family(chip) || |
| 2514 | mv88e6xxx_6185_family(chip)) |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2515 | reg |= PORT_CONTROL_DSA_TAG; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2516 | if (mv88e6xxx_6352_family(chip) || |
| 2517 | mv88e6xxx_6351_family(chip) || |
| 2518 | mv88e6xxx_6165_family(chip) || |
| 2519 | mv88e6xxx_6097_family(chip) || |
| 2520 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2521 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2522 | } |
| 2523 | |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2524 | if (port == dsa_upstream_port(ds)) |
| 2525 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | |
| 2526 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
| 2527 | } |
| 2528 | if (reg) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2529 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2530 | PORT_CONTROL, reg); |
| 2531 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2532 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2533 | } |
| 2534 | |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2535 | /* If this port is connected to a SerDes, make sure the SerDes is not |
| 2536 | * powered down. |
| 2537 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2538 | if (mv88e6xxx_6352_family(chip)) { |
| 2539 | ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS); |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2540 | if (ret < 0) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2541 | return ret; |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2542 | ret &= PORT_STATUS_CMODE_MASK; |
| 2543 | if ((ret == PORT_STATUS_CMODE_100BASE_X) || |
| 2544 | (ret == PORT_STATUS_CMODE_1000BASE_X) || |
| 2545 | (ret == PORT_STATUS_CMODE_SGMII)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2546 | ret = mv88e6xxx_power_on_serdes(chip); |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2547 | if (ret < 0) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2548 | return ret; |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2549 | } |
| 2550 | } |
| 2551 | |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2552 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
Vivien Didelot | 46fbe5e | 2016-02-26 13:16:07 -0500 | [diff] [blame] | 2553 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2554 | * untagged frames on this port, do a destination address lookup on all |
| 2555 | * received packets as usual, disable ARP mirroring and don't send a |
| 2556 | * copy of all transmitted/received frames on this port to the CPU. |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2557 | */ |
| 2558 | reg = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2559 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2560 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2561 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || |
| 2562 | mv88e6xxx_6185_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2563 | reg = PORT_CONTROL_2_MAP_DA; |
| 2564 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2565 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2566 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2567 | reg |= PORT_CONTROL_2_JUMBO_10240; |
| 2568 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2569 | if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2570 | /* Set the upstream port this port should use */ |
| 2571 | reg |= dsa_upstream_port(ds); |
| 2572 | /* enable forwarding of unknown multicast addresses to |
| 2573 | * the upstream port |
| 2574 | */ |
| 2575 | if (port == dsa_upstream_port(ds)) |
| 2576 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; |
| 2577 | } |
| 2578 | |
Vivien Didelot | 46fbe5e | 2016-02-26 13:16:07 -0500 | [diff] [blame] | 2579 | reg |= PORT_CONTROL_2_8021Q_DISABLED; |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2580 | |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2581 | if (reg) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2582 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2583 | PORT_CONTROL_2, reg); |
| 2584 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2585 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2586 | } |
| 2587 | |
| 2588 | /* Port Association Vector: when learning source addresses |
| 2589 | * of packets, add the address to the address database using |
| 2590 | * a port bitmap that has only the bit for this port set and |
| 2591 | * the other bits clear. |
| 2592 | */ |
Andrew Lunn | 4c7ea3c | 2015-11-03 10:52:36 -0500 | [diff] [blame] | 2593 | reg = 1 << port; |
Vivien Didelot | 996ecb8 | 2016-04-14 14:42:08 -0400 | [diff] [blame] | 2594 | /* Disable learning for CPU port */ |
| 2595 | if (dsa_is_cpu_port(ds, port)) |
Vivien Didelot | 65fa402 | 2016-04-14 14:42:07 -0400 | [diff] [blame] | 2596 | reg = 0; |
Andrew Lunn | 4c7ea3c | 2015-11-03 10:52:36 -0500 | [diff] [blame] | 2597 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2598 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR, |
| 2599 | reg); |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2600 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2601 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2602 | |
| 2603 | /* Egress rate control 2: disable egress rate control. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2604 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2, |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2605 | 0x0000); |
| 2606 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2607 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2608 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2609 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2610 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2611 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2612 | /* Do not limit the period of time that this port can |
| 2613 | * be paused for by the remote end or the period of |
| 2614 | * time that this port can pause the remote end. |
| 2615 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2616 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2617 | PORT_PAUSE_CTRL, 0x0000); |
| 2618 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2619 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2620 | |
| 2621 | /* Port ATU control: disable limiting the number of |
| 2622 | * address database entries that this port is allowed |
| 2623 | * to use. |
| 2624 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2625 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2626 | PORT_ATU_CONTROL, 0x0000); |
| 2627 | /* Priority Override: disable DA, SA and VTU priority |
| 2628 | * override. |
| 2629 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2630 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2631 | PORT_PRI_OVERRIDE, 0x0000); |
| 2632 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2633 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2634 | |
| 2635 | /* Port Ethertype: use the Ethertype DSA Ethertype |
| 2636 | * value. |
| 2637 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2638 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2639 | PORT_ETH_TYPE, ETH_P_EDSA); |
| 2640 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2641 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2642 | /* Tag Remap: use an identity 802.1p prio -> switch |
| 2643 | * prio mapping. |
| 2644 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2645 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2646 | PORT_TAG_REGMAP_0123, 0x3210); |
| 2647 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2648 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2649 | |
| 2650 | /* Tag Remap 2: use an identity 802.1p prio -> switch |
| 2651 | * prio mapping. |
| 2652 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2653 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2654 | PORT_TAG_REGMAP_4567, 0x7654); |
| 2655 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2656 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2657 | } |
| 2658 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2659 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2660 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2661 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || |
| 2662 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2663 | /* Rate Control: disable ingress rate limiting. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2664 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2665 | PORT_RATE_CONTROL, 0x0001); |
| 2666 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2667 | return ret; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2668 | } |
| 2669 | |
Guenter Roeck | 366f0a0 | 2015-03-26 18:36:30 -0700 | [diff] [blame] | 2670 | /* Port Control 1: disable trunking, disable sending |
| 2671 | * learning messages to this port. |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2672 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2673 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1, |
| 2674 | 0x0000); |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2675 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2676 | return ret; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2677 | |
Vivien Didelot | 207afda | 2016-04-14 14:42:09 -0400 | [diff] [blame] | 2678 | /* Port based VLAN map: give each port the same default address |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2679 | * database, and allow bidirectional communication between the |
| 2680 | * CPU and DSA port(s), and the other ports. |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2681 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2682 | ret = _mv88e6xxx_port_fid_set(chip, port, 0); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2683 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2684 | return ret; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2685 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2686 | ret = _mv88e6xxx_port_based_vlan_map(chip, port); |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2687 | if (ret) |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2688 | return ret; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2689 | |
| 2690 | /* Default VLAN ID and priority: don't set a default VLAN |
| 2691 | * ID, and set the default packet priority to zero. |
| 2692 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2693 | ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN, |
Vivien Didelot | 47cf1e6 | 2015-04-20 17:43:26 -0400 | [diff] [blame] | 2694 | 0x0000); |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2695 | if (ret) |
| 2696 | return ret; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2697 | |
Andrew Lunn | dbde9e6 | 2015-05-06 01:09:48 +0200 | [diff] [blame] | 2698 | return 0; |
| 2699 | } |
| 2700 | |
Vivien Didelot | 3b4caa1 | 2016-07-18 20:45:34 -0400 | [diff] [blame] | 2701 | static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) |
| 2702 | { |
| 2703 | int err; |
| 2704 | |
| 2705 | err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01, |
| 2706 | (addr[0] << 8) | addr[1]); |
| 2707 | if (err) |
| 2708 | return err; |
| 2709 | |
| 2710 | err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23, |
| 2711 | (addr[2] << 8) | addr[3]); |
| 2712 | if (err) |
| 2713 | return err; |
| 2714 | |
| 2715 | return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45, |
| 2716 | (addr[4] << 8) | addr[5]); |
| 2717 | } |
| 2718 | |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2719 | static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, |
| 2720 | unsigned int msecs) |
| 2721 | { |
| 2722 | const unsigned int coeff = chip->info->age_time_coeff; |
| 2723 | const unsigned int min = 0x01 * coeff; |
| 2724 | const unsigned int max = 0xff * coeff; |
| 2725 | u8 age_time; |
| 2726 | u16 val; |
| 2727 | int err; |
| 2728 | |
| 2729 | if (msecs < min || msecs > max) |
| 2730 | return -ERANGE; |
| 2731 | |
| 2732 | /* Round to nearest multiple of coeff */ |
| 2733 | age_time = (msecs + coeff / 2) / coeff; |
| 2734 | |
| 2735 | err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val); |
| 2736 | if (err) |
| 2737 | return err; |
| 2738 | |
| 2739 | /* AgeTime is 11:4 bits */ |
| 2740 | val &= ~0xff0; |
| 2741 | val |= age_time << 4; |
| 2742 | |
| 2743 | return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val); |
| 2744 | } |
| 2745 | |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 2746 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
| 2747 | unsigned int ageing_time) |
| 2748 | { |
| 2749 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 2750 | int err; |
| 2751 | |
| 2752 | mutex_lock(&chip->reg_lock); |
| 2753 | err = mv88e6xxx_g1_set_age_time(chip, ageing_time); |
| 2754 | mutex_unlock(&chip->reg_lock); |
| 2755 | |
| 2756 | return err; |
| 2757 | } |
| 2758 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2759 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2760 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2761 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | b0745e87 | 2016-05-09 13:22:53 -0400 | [diff] [blame] | 2762 | u32 upstream_port = dsa_upstream_port(ds); |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2763 | u16 reg; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2764 | int err; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2765 | |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2766 | /* Enable the PHY Polling Unit if present, don't discard any packets, |
| 2767 | * and mask all interrupt sources. |
| 2768 | */ |
| 2769 | reg = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2770 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || |
| 2771 | mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2772 | reg |= GLOBAL_CONTROL_PPU_ENABLE; |
| 2773 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2774 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg); |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2775 | if (err) |
| 2776 | return err; |
| 2777 | |
Vivien Didelot | b0745e87 | 2016-05-09 13:22:53 -0400 | [diff] [blame] | 2778 | /* Configure the upstream port, and configure it as the port to which |
| 2779 | * ingress and egress and ARP monitor frames are to be sent. |
| 2780 | */ |
| 2781 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
| 2782 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | |
| 2783 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2784 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, |
| 2785 | reg); |
Vivien Didelot | b0745e87 | 2016-05-09 13:22:53 -0400 | [diff] [blame] | 2786 | if (err) |
| 2787 | return err; |
| 2788 | |
Vivien Didelot | 50484ff | 2016-05-09 13:22:54 -0400 | [diff] [blame] | 2789 | /* Disable remote management, and set the switch's DSA device number. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2790 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2, |
Vivien Didelot | 50484ff | 2016-05-09 13:22:54 -0400 | [diff] [blame] | 2791 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | |
| 2792 | (ds->index & 0x1f)); |
| 2793 | if (err) |
| 2794 | return err; |
| 2795 | |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2796 | /* Clear all the VTU and STU entries */ |
| 2797 | err = _mv88e6xxx_vtu_stu_flush(chip); |
| 2798 | if (err < 0) |
| 2799 | return err; |
| 2800 | |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2801 | /* Set the default address aging time to 5 minutes, and |
| 2802 | * enable address learn messages to be sent to all message |
| 2803 | * ports. |
| 2804 | */ |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2805 | err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
| 2806 | GLOBAL_ATU_CONTROL_LEARN2ALL); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2807 | if (err) |
| 2808 | return err; |
| 2809 | |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2810 | err = mv88e6xxx_g1_set_age_time(chip, 300000); |
| 2811 | if (err) |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2812 | return err; |
| 2813 | |
| 2814 | /* Clear all ATU entries */ |
| 2815 | err = _mv88e6xxx_atu_flush(chip, 0, true); |
| 2816 | if (err) |
| 2817 | return err; |
| 2818 | |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2819 | /* Configure the IP ToS mapping registers. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2820 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2821 | if (err) |
| 2822 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2823 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2824 | if (err) |
| 2825 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2826 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2827 | if (err) |
| 2828 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2829 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2830 | if (err) |
| 2831 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2832 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2833 | if (err) |
| 2834 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2835 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2836 | if (err) |
| 2837 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2838 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2839 | if (err) |
| 2840 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2841 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2842 | if (err) |
| 2843 | return err; |
| 2844 | |
| 2845 | /* Configure the IEEE 802.1p priority mapping register. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2846 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2847 | if (err) |
| 2848 | return err; |
| 2849 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2850 | /* Clear the statistics counters for all ports */ |
| 2851 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, |
| 2852 | GLOBAL_STATS_OP_FLUSH_ALL); |
| 2853 | if (err) |
| 2854 | return err; |
| 2855 | |
| 2856 | /* Wait for the flush to complete. */ |
| 2857 | err = _mv88e6xxx_stats_wait(chip); |
| 2858 | if (err) |
| 2859 | return err; |
| 2860 | |
| 2861 | return 0; |
| 2862 | } |
| 2863 | |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 2864 | static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, |
| 2865 | int target, int port) |
| 2866 | { |
| 2867 | u16 val = (target << 8) | (port & 0xf); |
| 2868 | |
| 2869 | return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val); |
| 2870 | } |
| 2871 | |
| 2872 | static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip) |
| 2873 | { |
| 2874 | int target, port; |
| 2875 | int err; |
| 2876 | |
| 2877 | /* Initialize the routing port to the 32 possible target devices */ |
| 2878 | for (target = 0; target < 32; ++target) { |
| 2879 | port = 0xf; |
| 2880 | |
| 2881 | if (target < DSA_MAX_SWITCHES) { |
| 2882 | port = chip->ds->rtable[target]; |
| 2883 | if (port == DSA_RTABLE_NONE) |
| 2884 | port = 0xf; |
| 2885 | } |
| 2886 | |
| 2887 | err = mv88e6xxx_g2_device_mapping_write(chip, target, port); |
| 2888 | if (err) |
| 2889 | break; |
| 2890 | } |
| 2891 | |
| 2892 | return err; |
| 2893 | } |
| 2894 | |
Vivien Didelot | 5154041 | 2016-07-18 20:45:32 -0400 | [diff] [blame] | 2895 | static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, |
| 2896 | bool hask, u16 mask) |
| 2897 | { |
| 2898 | const u16 port_mask = BIT(chip->info->num_ports) - 1; |
| 2899 | u16 val = (num << 12) | (mask & port_mask); |
| 2900 | |
| 2901 | if (hask) |
| 2902 | val |= GLOBAL2_TRUNK_MASK_HASK; |
| 2903 | |
| 2904 | return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val); |
| 2905 | } |
| 2906 | |
| 2907 | static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, |
| 2908 | u16 map) |
| 2909 | { |
| 2910 | const u16 port_mask = BIT(chip->info->num_ports) - 1; |
| 2911 | u16 val = (id << 11) | (map & port_mask); |
| 2912 | |
| 2913 | return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val); |
| 2914 | } |
| 2915 | |
| 2916 | static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip) |
| 2917 | { |
| 2918 | const u16 port_mask = BIT(chip->info->num_ports) - 1; |
| 2919 | int i, err; |
| 2920 | |
| 2921 | /* Clear all eight possible Trunk Mask vectors */ |
| 2922 | for (i = 0; i < 8; ++i) { |
| 2923 | err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask); |
| 2924 | if (err) |
| 2925 | return err; |
| 2926 | } |
| 2927 | |
| 2928 | /* Clear all sixteen possible Trunk ID routing vectors */ |
| 2929 | for (i = 0; i < 16; ++i) { |
| 2930 | err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0); |
| 2931 | if (err) |
| 2932 | return err; |
| 2933 | } |
| 2934 | |
| 2935 | return 0; |
| 2936 | } |
| 2937 | |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 2938 | static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip) |
| 2939 | { |
| 2940 | int port, err; |
| 2941 | |
| 2942 | /* Init all Ingress Rate Limit resources of all ports */ |
| 2943 | for (port = 0; port < chip->info->num_ports; ++port) { |
| 2944 | /* XXX newer chips (like 88E6390) have different 2-bit ops */ |
| 2945 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD, |
| 2946 | GLOBAL2_IRL_CMD_OP_INIT_ALL | |
| 2947 | (port << 8)); |
| 2948 | if (err) |
| 2949 | break; |
| 2950 | |
| 2951 | /* Wait for the operation to complete */ |
| 2952 | err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD, |
| 2953 | GLOBAL2_IRL_CMD_BUSY); |
| 2954 | if (err) |
| 2955 | break; |
| 2956 | } |
| 2957 | |
| 2958 | return err; |
| 2959 | } |
| 2960 | |
Vivien Didelot | 3b4caa1 | 2016-07-18 20:45:34 -0400 | [diff] [blame] | 2961 | /* Indirect write to the Switch MAC/WoL/WoF register */ |
| 2962 | static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip, |
| 2963 | unsigned int pointer, u8 data) |
| 2964 | { |
| 2965 | u16 val = (pointer << 8) | data; |
| 2966 | |
| 2967 | return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val); |
| 2968 | } |
| 2969 | |
| 2970 | static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) |
| 2971 | { |
| 2972 | int i, err; |
| 2973 | |
| 2974 | for (i = 0; i < 6; i++) { |
| 2975 | err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]); |
| 2976 | if (err) |
| 2977 | break; |
| 2978 | } |
| 2979 | |
| 2980 | return err; |
| 2981 | } |
| 2982 | |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 2983 | static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer, |
| 2984 | u8 data) |
| 2985 | { |
| 2986 | u16 val = (pointer << 8) | (data & 0x7); |
| 2987 | |
| 2988 | return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val); |
| 2989 | } |
| 2990 | |
| 2991 | static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip) |
| 2992 | { |
| 2993 | int i, err; |
| 2994 | |
| 2995 | /* Clear all sixteen possible Priority Override entries */ |
| 2996 | for (i = 0; i < 16; i++) { |
| 2997 | err = mv88e6xxx_g2_pot_write(chip, i, 0); |
| 2998 | if (err) |
| 2999 | break; |
| 3000 | } |
| 3001 | |
| 3002 | return err; |
| 3003 | } |
| 3004 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3005 | static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip) |
| 3006 | { |
| 3007 | return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, |
| 3008 | GLOBAL2_EEPROM_CMD_BUSY | |
| 3009 | GLOBAL2_EEPROM_CMD_RUNNING); |
| 3010 | } |
| 3011 | |
| 3012 | static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd) |
| 3013 | { |
| 3014 | int err; |
| 3015 | |
| 3016 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd); |
| 3017 | if (err) |
| 3018 | return err; |
| 3019 | |
| 3020 | return mv88e6xxx_g2_eeprom_wait(chip); |
| 3021 | } |
| 3022 | |
| 3023 | static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip, |
| 3024 | u8 addr, u16 *data) |
| 3025 | { |
| 3026 | u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr; |
| 3027 | int err; |
| 3028 | |
| 3029 | err = mv88e6xxx_g2_eeprom_wait(chip); |
| 3030 | if (err) |
| 3031 | return err; |
| 3032 | |
| 3033 | err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); |
| 3034 | if (err) |
| 3035 | return err; |
| 3036 | |
| 3037 | return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); |
| 3038 | } |
| 3039 | |
| 3040 | static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip, |
| 3041 | u8 addr, u16 data) |
| 3042 | { |
| 3043 | u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr; |
| 3044 | int err; |
| 3045 | |
| 3046 | err = mv88e6xxx_g2_eeprom_wait(chip); |
| 3047 | if (err) |
| 3048 | return err; |
| 3049 | |
| 3050 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); |
| 3051 | if (err) |
| 3052 | return err; |
| 3053 | |
| 3054 | return mv88e6xxx_g2_eeprom_cmd(chip, cmd); |
| 3055 | } |
| 3056 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3057 | static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) |
| 3058 | { |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 3059 | u16 reg; |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3060 | int err; |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3061 | |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 3062 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) { |
| 3063 | /* Consider the frames with reserved multicast destination |
| 3064 | * addresses matching 01:80:c2:00:00:2x as MGMT. |
| 3065 | */ |
| 3066 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, |
| 3067 | 0xffff); |
| 3068 | if (err) |
| 3069 | return err; |
| 3070 | } |
| 3071 | |
| 3072 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) { |
| 3073 | /* Consider the frames with reserved multicast destination |
| 3074 | * addresses matching 01:80:c2:00:00:0x as MGMT. |
| 3075 | */ |
| 3076 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, |
| 3077 | 0xffff); |
| 3078 | if (err) |
| 3079 | return err; |
| 3080 | } |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3081 | |
| 3082 | /* Ignore removed tag data on doubly tagged packets, disable |
| 3083 | * flow control messages, force flow control priority to the |
| 3084 | * highest, and send all special multicast frames to the CPU |
| 3085 | * port at the highest priority. |
| 3086 | */ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 3087 | reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4); |
| 3088 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) || |
| 3089 | mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) |
| 3090 | reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7; |
| 3091 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3092 | if (err) |
| 3093 | return err; |
| 3094 | |
| 3095 | /* Program the DSA routing table. */ |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 3096 | err = mv88e6xxx_g2_set_device_mapping(chip); |
| 3097 | if (err) |
| 3098 | return err; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3099 | |
Vivien Didelot | 5154041 | 2016-07-18 20:45:32 -0400 | [diff] [blame] | 3100 | /* Clear all trunk masks and mapping. */ |
| 3101 | err = mv88e6xxx_g2_clear_trunk(chip); |
| 3102 | if (err) |
| 3103 | return err; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3104 | |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 3105 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) { |
| 3106 | /* Disable ingress rate limiting by resetting all per port |
| 3107 | * ingress rate limit resources to their initial state. |
| 3108 | */ |
| 3109 | err = mv88e6xxx_g2_clear_irl(chip); |
| 3110 | if (err) |
| 3111 | return err; |
| 3112 | } |
| 3113 | |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 3114 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) { |
| 3115 | /* Initialize Cross-chip Port VLAN Table to reset defaults */ |
| 3116 | err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR, |
| 3117 | GLOBAL2_PVT_ADDR_OP_INIT_ONES); |
| 3118 | if (err) |
| 3119 | return err; |
| 3120 | } |
| 3121 | |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 3122 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) { |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3123 | /* Clear the priority override table. */ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 3124 | err = mv88e6xxx_g2_clear_pot(chip); |
| 3125 | if (err) |
| 3126 | return err; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3127 | } |
| 3128 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3129 | return 0; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 3130 | } |
| 3131 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3132 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
Guenter Roeck | acdaffc | 2015-03-26 18:36:28 -0700 | [diff] [blame] | 3133 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3134 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 3135 | int err; |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 3136 | int i; |
| 3137 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3138 | chip->ds = ds; |
| 3139 | ds->slave_mii_bus = chip->mdio_bus; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 3140 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3141 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 3142 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3143 | err = mv88e6xxx_switch_reset(chip); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 3144 | if (err) |
| 3145 | goto unlock; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 3146 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3147 | /* Setup Switch Port Registers */ |
| 3148 | for (i = 0; i < chip->info->num_ports; i++) { |
| 3149 | err = mv88e6xxx_setup_port(chip, i); |
| 3150 | if (err) |
| 3151 | goto unlock; |
| 3152 | } |
| 3153 | |
| 3154 | /* Setup Switch Global 1 Registers */ |
| 3155 | err = mv88e6xxx_g1_setup(chip); |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 3156 | if (err) |
| 3157 | goto unlock; |
| 3158 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3159 | /* Setup Switch Global 2 Registers */ |
| 3160 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { |
| 3161 | err = mv88e6xxx_g2_setup(chip); |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 3162 | if (err) |
| 3163 | goto unlock; |
| 3164 | } |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 3165 | |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 3166 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3167 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | db687a5 | 2015-06-20 21:31:29 +0200 | [diff] [blame] | 3168 | |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 3169 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 3170 | } |
| 3171 | |
Vivien Didelot | 3b4caa1 | 2016-07-18 20:45:34 -0400 | [diff] [blame] | 3172 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
| 3173 | { |
| 3174 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3175 | int err; |
| 3176 | |
| 3177 | mutex_lock(&chip->reg_lock); |
| 3178 | |
| 3179 | /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */ |
| 3180 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC)) |
| 3181 | err = mv88e6xxx_g2_set_switch_mac(chip, addr); |
| 3182 | else |
| 3183 | err = mv88e6xxx_g1_set_switch_mac(chip, addr); |
| 3184 | |
| 3185 | mutex_unlock(&chip->reg_lock); |
| 3186 | |
| 3187 | return err; |
| 3188 | } |
| 3189 | |
Arnd Bergmann | 601bbae | 2016-08-10 23:54:08 +0200 | [diff] [blame] | 3190 | #ifdef CONFIG_NET_DSA_HWMON |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 3191 | static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page, |
| 3192 | int reg) |
Andrew Lunn | 49143585 | 2015-04-02 04:06:35 +0200 | [diff] [blame] | 3193 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3194 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | 49143585 | 2015-04-02 04:06:35 +0200 | [diff] [blame] | 3195 | int ret; |
| 3196 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3197 | mutex_lock(&chip->reg_lock); |
| 3198 | ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg); |
| 3199 | mutex_unlock(&chip->reg_lock); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 3200 | |
Andrew Lunn | 49143585 | 2015-04-02 04:06:35 +0200 | [diff] [blame] | 3201 | return ret; |
| 3202 | } |
| 3203 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 3204 | static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page, |
| 3205 | int reg, int val) |
Andrew Lunn | 49143585 | 2015-04-02 04:06:35 +0200 | [diff] [blame] | 3206 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3207 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | 49143585 | 2015-04-02 04:06:35 +0200 | [diff] [blame] | 3208 | int ret; |
| 3209 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3210 | mutex_lock(&chip->reg_lock); |
| 3211 | ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val); |
| 3212 | mutex_unlock(&chip->reg_lock); |
Patrick Uiterwijk | 75baacf | 2016-03-30 01:39:40 +0000 | [diff] [blame] | 3213 | |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3214 | return ret; |
| 3215 | } |
Arnd Bergmann | 601bbae | 2016-08-10 23:54:08 +0200 | [diff] [blame] | 3216 | #endif |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3217 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3218 | static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3219 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3220 | if (port >= 0 && port < chip->info->num_ports) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3221 | return port; |
| 3222 | return -EINVAL; |
| 3223 | } |
| 3224 | |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3225 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3226 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3227 | struct mv88e6xxx_chip *chip = bus->priv; |
| 3228 | int addr = mv88e6xxx_port_to_mdio_addr(chip, port); |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3229 | int ret; |
| 3230 | |
| 3231 | if (addr < 0) |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 3232 | return 0xffff; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3233 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3234 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 3235 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3236 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
| 3237 | ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum); |
| 3238 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY)) |
| 3239 | ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum); |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 3240 | else |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3241 | ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum); |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 3242 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3243 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3244 | return ret; |
| 3245 | } |
| 3246 | |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3247 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum, |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 3248 | u16 val) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3249 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3250 | struct mv88e6xxx_chip *chip = bus->priv; |
| 3251 | int addr = mv88e6xxx_port_to_mdio_addr(chip, port); |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3252 | int ret; |
| 3253 | |
| 3254 | if (addr < 0) |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 3255 | return 0xffff; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3256 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3257 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 3258 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3259 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
| 3260 | ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val); |
| 3261 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY)) |
| 3262 | ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val); |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 3263 | else |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3264 | ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val); |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 3265 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3266 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3267 | return ret; |
| 3268 | } |
| 3269 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3270 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3271 | struct device_node *np) |
| 3272 | { |
| 3273 | static int index; |
| 3274 | struct mii_bus *bus; |
| 3275 | int err; |
| 3276 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3277 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
| 3278 | mv88e6xxx_ppu_state_init(chip); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3279 | |
| 3280 | if (np) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3281 | chip->mdio_np = of_get_child_by_name(np, "mdio"); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3282 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3283 | bus = devm_mdiobus_alloc(chip->dev); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3284 | if (!bus) |
| 3285 | return -ENOMEM; |
| 3286 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3287 | bus->priv = (void *)chip; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3288 | if (np) { |
| 3289 | bus->name = np->full_name; |
| 3290 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); |
| 3291 | } else { |
| 3292 | bus->name = "mv88e6xxx SMI"; |
| 3293 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); |
| 3294 | } |
| 3295 | |
| 3296 | bus->read = mv88e6xxx_mdio_read; |
| 3297 | bus->write = mv88e6xxx_mdio_write; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3298 | bus->parent = chip->dev; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3299 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3300 | if (chip->mdio_np) |
| 3301 | err = of_mdiobus_register(bus, chip->mdio_np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3302 | else |
| 3303 | err = mdiobus_register(bus); |
| 3304 | if (err) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3305 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3306 | goto out; |
| 3307 | } |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3308 | chip->mdio_bus = bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3309 | |
| 3310 | return 0; |
| 3311 | |
| 3312 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3313 | if (chip->mdio_np) |
| 3314 | of_node_put(chip->mdio_np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3315 | |
| 3316 | return err; |
| 3317 | } |
| 3318 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3319 | static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3320 | |
| 3321 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3322 | struct mii_bus *bus = chip->mdio_bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3323 | |
| 3324 | mdiobus_unregister(bus); |
| 3325 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3326 | if (chip->mdio_np) |
| 3327 | of_node_put(chip->mdio_np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3328 | } |
| 3329 | |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3330 | #ifdef CONFIG_NET_DSA_HWMON |
| 3331 | |
| 3332 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) |
| 3333 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3334 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3335 | int ret; |
| 3336 | int val; |
| 3337 | |
| 3338 | *temp = 0; |
| 3339 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3340 | mutex_lock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3341 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3342 | ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3343 | if (ret < 0) |
| 3344 | goto error; |
| 3345 | |
| 3346 | /* Enable temperature sensor */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3347 | ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3348 | if (ret < 0) |
| 3349 | goto error; |
| 3350 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3351 | ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5)); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3352 | if (ret < 0) |
| 3353 | goto error; |
| 3354 | |
| 3355 | /* Wait for temperature to stabilize */ |
| 3356 | usleep_range(10000, 12000); |
| 3357 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3358 | val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3359 | if (val < 0) { |
| 3360 | ret = val; |
| 3361 | goto error; |
| 3362 | } |
| 3363 | |
| 3364 | /* Disable temperature sensor */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3365 | ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5)); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3366 | if (ret < 0) |
| 3367 | goto error; |
| 3368 | |
| 3369 | *temp = ((val & 0x1f) - 5) * 5; |
| 3370 | |
| 3371 | error: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3372 | mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0); |
| 3373 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3374 | return ret; |
| 3375 | } |
| 3376 | |
| 3377 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) |
| 3378 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3379 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3380 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3381 | int ret; |
| 3382 | |
| 3383 | *temp = 0; |
| 3384 | |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 3385 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3386 | if (ret < 0) |
| 3387 | return ret; |
| 3388 | |
| 3389 | *temp = (ret & 0xff) - 25; |
| 3390 | |
| 3391 | return 0; |
| 3392 | } |
| 3393 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3394 | static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3395 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3396 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 3397 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3398 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) |
Vivien Didelot | 6594f61 | 2016-05-09 13:22:42 -0400 | [diff] [blame] | 3399 | return -EOPNOTSUPP; |
| 3400 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3401 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3402 | return mv88e63xx_get_temp(ds, temp); |
| 3403 | |
| 3404 | return mv88e61xx_get_temp(ds, temp); |
| 3405 | } |
| 3406 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3407 | static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3408 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3409 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3410 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3411 | int ret; |
| 3412 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3413 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3414 | return -EOPNOTSUPP; |
| 3415 | |
| 3416 | *temp = 0; |
| 3417 | |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 3418 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3419 | if (ret < 0) |
| 3420 | return ret; |
| 3421 | |
| 3422 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; |
| 3423 | |
| 3424 | return 0; |
| 3425 | } |
| 3426 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3427 | static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3428 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3429 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3430 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3431 | int ret; |
| 3432 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3433 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3434 | return -EOPNOTSUPP; |
| 3435 | |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 3436 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3437 | if (ret < 0) |
| 3438 | return ret; |
| 3439 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 3440 | return mv88e6xxx_mdio_page_write(ds, phy, 6, 26, |
| 3441 | (ret & 0xe0ff) | (temp << 8)); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3442 | } |
| 3443 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3444 | static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3445 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3446 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3447 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3448 | int ret; |
| 3449 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3450 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3451 | return -EOPNOTSUPP; |
| 3452 | |
| 3453 | *alarm = false; |
| 3454 | |
Andrew Lunn | 03a4a54 | 2016-06-04 21:17:05 +0200 | [diff] [blame] | 3455 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3456 | if (ret < 0) |
| 3457 | return ret; |
| 3458 | |
| 3459 | *alarm = !!(ret & 0x40); |
| 3460 | |
| 3461 | return 0; |
| 3462 | } |
| 3463 | #endif /* CONFIG_NET_DSA_HWMON */ |
| 3464 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3465 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
| 3466 | { |
| 3467 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3468 | |
| 3469 | return chip->eeprom_len; |
| 3470 | } |
| 3471 | |
| 3472 | static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip, |
| 3473 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3474 | { |
| 3475 | unsigned int offset = eeprom->offset; |
| 3476 | unsigned int len = eeprom->len; |
| 3477 | u16 val; |
| 3478 | int err; |
| 3479 | |
| 3480 | eeprom->len = 0; |
| 3481 | |
| 3482 | if (offset & 1) { |
| 3483 | err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); |
| 3484 | if (err) |
| 3485 | return err; |
| 3486 | |
| 3487 | *data++ = (val >> 8) & 0xff; |
| 3488 | |
| 3489 | offset++; |
| 3490 | len--; |
| 3491 | eeprom->len++; |
| 3492 | } |
| 3493 | |
| 3494 | while (len >= 2) { |
| 3495 | err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); |
| 3496 | if (err) |
| 3497 | return err; |
| 3498 | |
| 3499 | *data++ = val & 0xff; |
| 3500 | *data++ = (val >> 8) & 0xff; |
| 3501 | |
| 3502 | offset += 2; |
| 3503 | len -= 2; |
| 3504 | eeprom->len += 2; |
| 3505 | } |
| 3506 | |
| 3507 | if (len) { |
| 3508 | err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); |
| 3509 | if (err) |
| 3510 | return err; |
| 3511 | |
| 3512 | *data++ = val & 0xff; |
| 3513 | |
| 3514 | offset++; |
| 3515 | len--; |
| 3516 | eeprom->len++; |
| 3517 | } |
| 3518 | |
| 3519 | return 0; |
| 3520 | } |
| 3521 | |
| 3522 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
| 3523 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3524 | { |
| 3525 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3526 | int err; |
| 3527 | |
| 3528 | mutex_lock(&chip->reg_lock); |
| 3529 | |
| 3530 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16)) |
| 3531 | err = mv88e6xxx_get_eeprom16(chip, eeprom, data); |
| 3532 | else |
| 3533 | err = -EOPNOTSUPP; |
| 3534 | |
| 3535 | mutex_unlock(&chip->reg_lock); |
| 3536 | |
| 3537 | if (err) |
| 3538 | return err; |
| 3539 | |
| 3540 | eeprom->magic = 0xc3ec4951; |
| 3541 | |
| 3542 | return 0; |
| 3543 | } |
| 3544 | |
| 3545 | static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip, |
| 3546 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3547 | { |
| 3548 | unsigned int offset = eeprom->offset; |
| 3549 | unsigned int len = eeprom->len; |
| 3550 | u16 val; |
| 3551 | int err; |
| 3552 | |
| 3553 | /* Ensure the RO WriteEn bit is set */ |
| 3554 | err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val); |
| 3555 | if (err) |
| 3556 | return err; |
| 3557 | |
| 3558 | if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN)) |
| 3559 | return -EROFS; |
| 3560 | |
| 3561 | eeprom->len = 0; |
| 3562 | |
| 3563 | if (offset & 1) { |
| 3564 | err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); |
| 3565 | if (err) |
| 3566 | return err; |
| 3567 | |
| 3568 | val = (*data++ << 8) | (val & 0xff); |
| 3569 | |
| 3570 | err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); |
| 3571 | if (err) |
| 3572 | return err; |
| 3573 | |
| 3574 | offset++; |
| 3575 | len--; |
| 3576 | eeprom->len++; |
| 3577 | } |
| 3578 | |
| 3579 | while (len >= 2) { |
| 3580 | val = *data++; |
| 3581 | val |= *data++ << 8; |
| 3582 | |
| 3583 | err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); |
| 3584 | if (err) |
| 3585 | return err; |
| 3586 | |
| 3587 | offset += 2; |
| 3588 | len -= 2; |
| 3589 | eeprom->len += 2; |
| 3590 | } |
| 3591 | |
| 3592 | if (len) { |
| 3593 | err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); |
| 3594 | if (err) |
| 3595 | return err; |
| 3596 | |
| 3597 | val = (val & 0xff00) | *data++; |
| 3598 | |
| 3599 | err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); |
| 3600 | if (err) |
| 3601 | return err; |
| 3602 | |
| 3603 | offset++; |
| 3604 | len--; |
| 3605 | eeprom->len++; |
| 3606 | } |
| 3607 | |
| 3608 | return 0; |
| 3609 | } |
| 3610 | |
| 3611 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
| 3612 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3613 | { |
| 3614 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
| 3615 | int err; |
| 3616 | |
| 3617 | if (eeprom->magic != 0xc3ec4951) |
| 3618 | return -EINVAL; |
| 3619 | |
| 3620 | mutex_lock(&chip->reg_lock); |
| 3621 | |
| 3622 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16)) |
| 3623 | err = mv88e6xxx_set_eeprom16(chip, eeprom, data); |
| 3624 | else |
| 3625 | err = -EOPNOTSUPP; |
| 3626 | |
| 3627 | mutex_unlock(&chip->reg_lock); |
| 3628 | |
| 3629 | return err; |
| 3630 | } |
| 3631 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3632 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
| 3633 | [MV88E6085] = { |
| 3634 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, |
| 3635 | .family = MV88E6XXX_FAMILY_6097, |
| 3636 | .name = "Marvell 88E6085", |
| 3637 | .num_databases = 4096, |
| 3638 | .num_ports = 10, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3639 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3640 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3641 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
| 3642 | }, |
| 3643 | |
| 3644 | [MV88E6095] = { |
| 3645 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, |
| 3646 | .family = MV88E6XXX_FAMILY_6095, |
| 3647 | .name = "Marvell 88E6095/88E6095F", |
| 3648 | .num_databases = 256, |
| 3649 | .num_ports = 11, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3650 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3651 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3652 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
| 3653 | }, |
| 3654 | |
| 3655 | [MV88E6123] = { |
| 3656 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, |
| 3657 | .family = MV88E6XXX_FAMILY_6165, |
| 3658 | .name = "Marvell 88E6123", |
| 3659 | .num_databases = 4096, |
| 3660 | .num_ports = 3, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3661 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3662 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3663 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
| 3664 | }, |
| 3665 | |
| 3666 | [MV88E6131] = { |
| 3667 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, |
| 3668 | .family = MV88E6XXX_FAMILY_6185, |
| 3669 | .name = "Marvell 88E6131", |
| 3670 | .num_databases = 256, |
| 3671 | .num_ports = 8, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3672 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3673 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3674 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
| 3675 | }, |
| 3676 | |
| 3677 | [MV88E6161] = { |
| 3678 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, |
| 3679 | .family = MV88E6XXX_FAMILY_6165, |
| 3680 | .name = "Marvell 88E6161", |
| 3681 | .num_databases = 4096, |
| 3682 | .num_ports = 6, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3683 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3684 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3685 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
| 3686 | }, |
| 3687 | |
| 3688 | [MV88E6165] = { |
| 3689 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, |
| 3690 | .family = MV88E6XXX_FAMILY_6165, |
| 3691 | .name = "Marvell 88E6165", |
| 3692 | .num_databases = 4096, |
| 3693 | .num_ports = 6, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3694 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3695 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3696 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
| 3697 | }, |
| 3698 | |
| 3699 | [MV88E6171] = { |
| 3700 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, |
| 3701 | .family = MV88E6XXX_FAMILY_6351, |
| 3702 | .name = "Marvell 88E6171", |
| 3703 | .num_databases = 4096, |
| 3704 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3705 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3706 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3707 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3708 | }, |
| 3709 | |
| 3710 | [MV88E6172] = { |
| 3711 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, |
| 3712 | .family = MV88E6XXX_FAMILY_6352, |
| 3713 | .name = "Marvell 88E6172", |
| 3714 | .num_databases = 4096, |
| 3715 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3716 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3717 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3718 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3719 | }, |
| 3720 | |
| 3721 | [MV88E6175] = { |
| 3722 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, |
| 3723 | .family = MV88E6XXX_FAMILY_6351, |
| 3724 | .name = "Marvell 88E6175", |
| 3725 | .num_databases = 4096, |
| 3726 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3727 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3728 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3729 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3730 | }, |
| 3731 | |
| 3732 | [MV88E6176] = { |
| 3733 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, |
| 3734 | .family = MV88E6XXX_FAMILY_6352, |
| 3735 | .name = "Marvell 88E6176", |
| 3736 | .num_databases = 4096, |
| 3737 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3738 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3739 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3740 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3741 | }, |
| 3742 | |
| 3743 | [MV88E6185] = { |
| 3744 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, |
| 3745 | .family = MV88E6XXX_FAMILY_6185, |
| 3746 | .name = "Marvell 88E6185", |
| 3747 | .num_databases = 256, |
| 3748 | .num_ports = 10, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3749 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3750 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3751 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
| 3752 | }, |
| 3753 | |
| 3754 | [MV88E6240] = { |
| 3755 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, |
| 3756 | .family = MV88E6XXX_FAMILY_6352, |
| 3757 | .name = "Marvell 88E6240", |
| 3758 | .num_databases = 4096, |
| 3759 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3760 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3761 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3762 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3763 | }, |
| 3764 | |
| 3765 | [MV88E6320] = { |
| 3766 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, |
| 3767 | .family = MV88E6XXX_FAMILY_6320, |
| 3768 | .name = "Marvell 88E6320", |
| 3769 | .num_databases = 4096, |
| 3770 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3771 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3772 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3773 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
| 3774 | }, |
| 3775 | |
| 3776 | [MV88E6321] = { |
| 3777 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, |
| 3778 | .family = MV88E6XXX_FAMILY_6320, |
| 3779 | .name = "Marvell 88E6321", |
| 3780 | .num_databases = 4096, |
| 3781 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3782 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3783 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3784 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
| 3785 | }, |
| 3786 | |
| 3787 | [MV88E6350] = { |
| 3788 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, |
| 3789 | .family = MV88E6XXX_FAMILY_6351, |
| 3790 | .name = "Marvell 88E6350", |
| 3791 | .num_databases = 4096, |
| 3792 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3793 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3794 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3795 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3796 | }, |
| 3797 | |
| 3798 | [MV88E6351] = { |
| 3799 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, |
| 3800 | .family = MV88E6XXX_FAMILY_6351, |
| 3801 | .name = "Marvell 88E6351", |
| 3802 | .num_databases = 4096, |
| 3803 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3804 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3805 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3806 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3807 | }, |
| 3808 | |
| 3809 | [MV88E6352] = { |
| 3810 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, |
| 3811 | .family = MV88E6XXX_FAMILY_6352, |
| 3812 | .name = "Marvell 88E6352", |
| 3813 | .num_databases = 4096, |
| 3814 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3815 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3816 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3817 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3818 | }, |
| 3819 | }; |
| 3820 | |
Vivien Didelot | 5f7c036 | 2016-06-20 13:14:04 -0400 | [diff] [blame] | 3821 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3822 | { |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3823 | int i; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3824 | |
Vivien Didelot | 5f7c036 | 2016-06-20 13:14:04 -0400 | [diff] [blame] | 3825 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
| 3826 | if (mv88e6xxx_table[i].prod_num == prod_num) |
| 3827 | return &mv88e6xxx_table[i]; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3828 | |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3829 | return NULL; |
| 3830 | } |
| 3831 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3832 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3833 | { |
| 3834 | const struct mv88e6xxx_info *info; |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 3835 | unsigned int prod_num, rev; |
| 3836 | u16 id; |
| 3837 | int err; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3838 | |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 3839 | mutex_lock(&chip->reg_lock); |
| 3840 | err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); |
| 3841 | mutex_unlock(&chip->reg_lock); |
| 3842 | if (err) |
| 3843 | return err; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3844 | |
| 3845 | prod_num = (id & 0xfff0) >> 4; |
| 3846 | rev = id & 0x000f; |
| 3847 | |
| 3848 | info = mv88e6xxx_lookup_info(prod_num); |
| 3849 | if (!info) |
| 3850 | return -ENODEV; |
| 3851 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3852 | /* Update the compatible info with the probed one */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3853 | chip->info = info; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3854 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3855 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
| 3856 | chip->info->prod_num, chip->info->name, rev); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3857 | |
| 3858 | return 0; |
| 3859 | } |
| 3860 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3861 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3862 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3863 | struct mv88e6xxx_chip *chip; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3864 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3865 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
| 3866 | if (!chip) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3867 | return NULL; |
| 3868 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3869 | chip->dev = dev; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3870 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3871 | mutex_init(&chip->reg_lock); |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3872 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3873 | return chip; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3874 | } |
| 3875 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3876 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3877 | struct mii_bus *bus, int sw_addr) |
| 3878 | { |
| 3879 | /* ADDR[0] pin is unavailable externally and considered zero */ |
| 3880 | if (sw_addr & 0x1) |
| 3881 | return -EINVAL; |
| 3882 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 3883 | if (sw_addr == 0) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3884 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
| 3885 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP)) |
| 3886 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 3887 | else |
| 3888 | return -EINVAL; |
| 3889 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3890 | chip->bus = bus; |
| 3891 | chip->sw_addr = sw_addr; |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3892 | |
| 3893 | return 0; |
| 3894 | } |
| 3895 | |
Andrew Lunn | fcdce7d | 2016-05-10 23:27:20 +0200 | [diff] [blame] | 3896 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
| 3897 | struct device *host_dev, int sw_addr, |
| 3898 | void **priv) |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 3899 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3900 | struct mv88e6xxx_chip *chip; |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3901 | struct mii_bus *bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3902 | int err; |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 3903 | |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3904 | bus = dsa_host_dev_to_mii_bus(host_dev); |
Andrew Lunn | c156913 | 2016-04-13 02:40:45 +0200 | [diff] [blame] | 3905 | if (!bus) |
| 3906 | return NULL; |
| 3907 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3908 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
| 3909 | if (!chip) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3910 | return NULL; |
| 3911 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3912 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3913 | chip->info = &mv88e6xxx_table[MV88E6085]; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3914 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3915 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3916 | if (err) |
| 3917 | goto free; |
| 3918 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3919 | err = mv88e6xxx_detect(chip); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3920 | if (err) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3921 | goto free; |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3922 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3923 | err = mv88e6xxx_mdio_register(chip, NULL); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3924 | if (err) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3925 | goto free; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3926 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3927 | *priv = chip; |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3928 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3929 | return chip->info->name; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3930 | free: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3931 | devm_kfree(dsa_dev, chip); |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3932 | |
| 3933 | return NULL; |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 3934 | } |
| 3935 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 3936 | static struct dsa_switch_driver mv88e6xxx_switch_driver = { |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3937 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
Andrew Lunn | fcdce7d | 2016-05-10 23:27:20 +0200 | [diff] [blame] | 3938 | .probe = mv88e6xxx_drv_probe, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3939 | .setup = mv88e6xxx_setup, |
| 3940 | .set_addr = mv88e6xxx_set_addr, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3941 | .adjust_link = mv88e6xxx_adjust_link, |
| 3942 | .get_strings = mv88e6xxx_get_strings, |
| 3943 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, |
| 3944 | .get_sset_count = mv88e6xxx_get_sset_count, |
| 3945 | .set_eee = mv88e6xxx_set_eee, |
| 3946 | .get_eee = mv88e6xxx_get_eee, |
| 3947 | #ifdef CONFIG_NET_DSA_HWMON |
| 3948 | .get_temp = mv88e6xxx_get_temp, |
| 3949 | .get_temp_limit = mv88e6xxx_get_temp_limit, |
| 3950 | .set_temp_limit = mv88e6xxx_set_temp_limit, |
| 3951 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, |
| 3952 | #endif |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 3953 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3954 | .get_eeprom = mv88e6xxx_get_eeprom, |
| 3955 | .set_eeprom = mv88e6xxx_set_eeprom, |
| 3956 | .get_regs_len = mv88e6xxx_get_regs_len, |
| 3957 | .get_regs = mv88e6xxx_get_regs, |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 3958 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3959 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
| 3960 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, |
| 3961 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, |
| 3962 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
| 3963 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, |
| 3964 | .port_vlan_add = mv88e6xxx_port_vlan_add, |
| 3965 | .port_vlan_del = mv88e6xxx_port_vlan_del, |
| 3966 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, |
| 3967 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, |
| 3968 | .port_fdb_add = mv88e6xxx_port_fdb_add, |
| 3969 | .port_fdb_del = mv88e6xxx_port_fdb_del, |
| 3970 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, |
| 3971 | }; |
| 3972 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3973 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3974 | struct device_node *np) |
| 3975 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3976 | struct device *dev = chip->dev; |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3977 | struct dsa_switch *ds; |
| 3978 | |
| 3979 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); |
| 3980 | if (!ds) |
| 3981 | return -ENOMEM; |
| 3982 | |
| 3983 | ds->dev = dev; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3984 | ds->priv = chip; |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3985 | ds->drv = &mv88e6xxx_switch_driver; |
| 3986 | |
| 3987 | dev_set_drvdata(dev, ds); |
| 3988 | |
| 3989 | return dsa_register_switch(ds, np); |
| 3990 | } |
| 3991 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3992 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3993 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3994 | dsa_unregister_switch(chip->ds); |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3995 | } |
| 3996 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 3997 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3998 | { |
| 3999 | struct device *dev = &mdiodev->dev; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 4000 | struct device_node *np = dev->of_node; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 4001 | const struct mv88e6xxx_info *compat_info; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4002 | struct mv88e6xxx_chip *chip; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 4003 | u32 eeprom_len; |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 4004 | int err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4005 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 4006 | compat_info = of_device_get_match_data(dev); |
| 4007 | if (!compat_info) |
| 4008 | return -EINVAL; |
| 4009 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4010 | chip = mv88e6xxx_alloc_chip(dev); |
| 4011 | if (!chip) |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4012 | return -ENOMEM; |
| 4013 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4014 | chip->info = compat_info; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 4015 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4016 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 4017 | if (err) |
| 4018 | return err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4019 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4020 | err = mv88e6xxx_detect(chip); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 4021 | if (err) |
| 4022 | return err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4023 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4024 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); |
| 4025 | if (IS_ERR(chip->reset)) |
| 4026 | return PTR_ERR(chip->reset); |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 4027 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 4028 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) && |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 4029 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4030 | chip->eeprom_len = eeprom_len; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 4031 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4032 | err = mv88e6xxx_mdio_register(chip, np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 4033 | if (err) |
| 4034 | return err; |
| 4035 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4036 | err = mv88e6xxx_register_switch(chip, np); |
Andrew Lunn | 83c0afa | 2016-06-04 21:17:07 +0200 | [diff] [blame] | 4037 | if (err) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4038 | mv88e6xxx_mdio_unregister(chip); |
Andrew Lunn | 83c0afa | 2016-06-04 21:17:07 +0200 | [diff] [blame] | 4039 | return err; |
| 4040 | } |
| 4041 | |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4042 | return 0; |
| 4043 | } |
| 4044 | |
| 4045 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) |
| 4046 | { |
| 4047 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4048 | struct mv88e6xxx_chip *chip = ds_to_priv(ds); |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4049 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 4050 | mv88e6xxx_unregister_switch(chip); |
| 4051 | mv88e6xxx_mdio_unregister(chip); |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4052 | } |
| 4053 | |
| 4054 | static const struct of_device_id mv88e6xxx_of_match[] = { |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 4055 | { |
| 4056 | .compatible = "marvell,mv88e6085", |
| 4057 | .data = &mv88e6xxx_table[MV88E6085], |
| 4058 | }, |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4059 | { /* sentinel */ }, |
| 4060 | }; |
| 4061 | |
| 4062 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); |
| 4063 | |
| 4064 | static struct mdio_driver mv88e6xxx_driver = { |
| 4065 | .probe = mv88e6xxx_probe, |
| 4066 | .remove = mv88e6xxx_remove, |
| 4067 | .mdiodrv.driver = { |
| 4068 | .name = "mv88e6085", |
| 4069 | .of_match_table = mv88e6xxx_of_match, |
| 4070 | }, |
| 4071 | }; |
| 4072 | |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 4073 | static int __init mv88e6xxx_init(void) |
| 4074 | { |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4075 | register_switch_driver(&mv88e6xxx_switch_driver); |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4076 | return mdio_driver_register(&mv88e6xxx_driver); |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 4077 | } |
| 4078 | module_init(mv88e6xxx_init); |
| 4079 | |
| 4080 | static void __exit mv88e6xxx_cleanup(void) |
| 4081 | { |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 4082 | mdio_driver_unregister(&mv88e6xxx_driver); |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4083 | unregister_switch_driver(&mv88e6xxx_switch_driver); |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 4084 | } |
| 4085 | module_exit(mv88e6xxx_cleanup); |
Ben Hutchings | 3d825ed | 2011-11-25 14:37:16 +0000 | [diff] [blame] | 4086 | |
| 4087 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); |
| 4088 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); |
| 4089 | MODULE_LICENSE("GPL"); |