Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $ |
| 2 | * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters. |
| 3 | * |
| 4 | * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com) |
| 5 | */ |
| 6 | |
| 7 | #include <linux/module.h> |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/types.h> |
| 11 | #include <linux/fcntl.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/ioport.h> |
| 14 | #include <linux/in.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <linux/string.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/crc32.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/ethtool.h> |
| 22 | #include <linux/netdevice.h> |
| 23 | #include <linux/etherdevice.h> |
| 24 | #include <linux/skbuff.h> |
| 25 | #include <linux/bitops.h> |
| 26 | |
| 27 | #include <asm/auxio.h> |
| 28 | #include <asm/byteorder.h> |
| 29 | #include <asm/dma.h> |
| 30 | #include <asm/idprom.h> |
| 31 | #include <asm/io.h> |
| 32 | #include <asm/openprom.h> |
| 33 | #include <asm/oplib.h> |
| 34 | #include <asm/pgtable.h> |
| 35 | #include <asm/sbus.h> |
| 36 | #include <asm/system.h> |
| 37 | |
| 38 | #include "sunbmac.h" |
| 39 | |
Tom 'spot' Callaway | 1015828 | 2005-04-24 20:35:20 -0700 | [diff] [blame] | 40 | #define DRV_NAME "sunbmac" |
| 41 | #define DRV_VERSION "2.0" |
| 42 | #define DRV_RELDATE "11/24/03" |
| 43 | #define DRV_AUTHOR "David S. Miller (davem@redhat.com)" |
| 44 | |
Ben Collins | b48194b | 2006-10-17 19:11:31 -0700 | [diff] [blame] | 45 | static char version[] = |
Tom 'spot' Callaway | 1015828 | 2005-04-24 20:35:20 -0700 | [diff] [blame] | 46 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n"; |
| 47 | |
| 48 | MODULE_VERSION(DRV_VERSION); |
| 49 | MODULE_AUTHOR(DRV_AUTHOR); |
| 50 | MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver"); |
| 51 | MODULE_LICENSE("GPL"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | |
| 53 | #undef DEBUG_PROBE |
| 54 | #undef DEBUG_TX |
| 55 | #undef DEBUG_IRQ |
| 56 | |
| 57 | #ifdef DEBUG_PROBE |
| 58 | #define DP(x) printk x |
| 59 | #else |
| 60 | #define DP(x) |
| 61 | #endif |
| 62 | |
| 63 | #ifdef DEBUG_TX |
| 64 | #define DTX(x) printk x |
| 65 | #else |
| 66 | #define DTX(x) |
| 67 | #endif |
| 68 | |
| 69 | #ifdef DEBUG_IRQ |
| 70 | #define DIRQ(x) printk x |
| 71 | #else |
| 72 | #define DIRQ(x) |
| 73 | #endif |
| 74 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | #define DEFAULT_JAMSIZE 4 /* Toe jam */ |
| 76 | |
| 77 | #define QEC_RESET_TRIES 200 |
| 78 | |
| 79 | static int qec_global_reset(void __iomem *gregs) |
| 80 | { |
| 81 | int tries = QEC_RESET_TRIES; |
| 82 | |
| 83 | sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL); |
| 84 | while (--tries) { |
| 85 | if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) { |
| 86 | udelay(20); |
| 87 | continue; |
| 88 | } |
| 89 | break; |
| 90 | } |
| 91 | if (tries) |
| 92 | return 0; |
| 93 | printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n"); |
| 94 | return -1; |
| 95 | } |
| 96 | |
| 97 | static void qec_init(struct bigmac *bp) |
| 98 | { |
| 99 | void __iomem *gregs = bp->gregs; |
| 100 | struct sbus_dev *qec_sdev = bp->qec_sdev; |
| 101 | u8 bsizes = bp->bigmac_bursts; |
| 102 | u32 regval; |
| 103 | |
| 104 | /* 64byte bursts do not work at the moment, do |
| 105 | * not even try to enable them. -DaveM |
| 106 | */ |
| 107 | if (bsizes & DMA_BURST32) |
| 108 | regval = GLOB_CTRL_B32; |
| 109 | else |
| 110 | regval = GLOB_CTRL_B16; |
| 111 | sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL); |
| 112 | sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE); |
| 113 | |
| 114 | /* All of memsize is given to bigmac. */ |
| 115 | sbus_writel(qec_sdev->reg_addrs[1].reg_size, |
| 116 | gregs + GLOB_MSIZE); |
| 117 | |
| 118 | /* Half to the transmitter, half to the receiver. */ |
| 119 | sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1, |
| 120 | gregs + GLOB_TSIZE); |
| 121 | sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1, |
| 122 | gregs + GLOB_RSIZE); |
| 123 | } |
| 124 | |
| 125 | #define TX_RESET_TRIES 32 |
| 126 | #define RX_RESET_TRIES 32 |
| 127 | |
| 128 | static void bigmac_tx_reset(void __iomem *bregs) |
| 129 | { |
| 130 | int tries = TX_RESET_TRIES; |
| 131 | |
| 132 | sbus_writel(0, bregs + BMAC_TXCFG); |
| 133 | |
| 134 | /* The fifo threshold bit is read-only and does |
| 135 | * not clear. -DaveM |
| 136 | */ |
| 137 | while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 && |
| 138 | --tries != 0) |
| 139 | udelay(20); |
| 140 | |
| 141 | if (!tries) { |
| 142 | printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n"); |
| 143 | printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n", |
| 144 | sbus_readl(bregs + BMAC_TXCFG)); |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | static void bigmac_rx_reset(void __iomem *bregs) |
| 149 | { |
| 150 | int tries = RX_RESET_TRIES; |
| 151 | |
| 152 | sbus_writel(0, bregs + BMAC_RXCFG); |
| 153 | while (sbus_readl(bregs + BMAC_RXCFG) && --tries) |
| 154 | udelay(20); |
| 155 | |
| 156 | if (!tries) { |
| 157 | printk(KERN_ERR "BIGMAC: Receiver will not reset.\n"); |
| 158 | printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n", |
| 159 | sbus_readl(bregs + BMAC_RXCFG)); |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | /* Reset the transmitter and receiver. */ |
| 164 | static void bigmac_stop(struct bigmac *bp) |
| 165 | { |
| 166 | bigmac_tx_reset(bp->bregs); |
| 167 | bigmac_rx_reset(bp->bregs); |
| 168 | } |
| 169 | |
| 170 | static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs) |
| 171 | { |
| 172 | struct net_device_stats *stats = &bp->enet_stats; |
| 173 | |
| 174 | stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR); |
| 175 | sbus_writel(0, bregs + BMAC_RCRCECTR); |
| 176 | |
| 177 | stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR); |
| 178 | sbus_writel(0, bregs + BMAC_UNALECTR); |
| 179 | |
| 180 | stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR); |
| 181 | sbus_writel(0, bregs + BMAC_GLECTR); |
| 182 | |
| 183 | stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR); |
| 184 | |
| 185 | stats->collisions += |
| 186 | (sbus_readl(bregs + BMAC_EXCTR) + |
| 187 | sbus_readl(bregs + BMAC_LTCTR)); |
| 188 | sbus_writel(0, bregs + BMAC_EXCTR); |
| 189 | sbus_writel(0, bregs + BMAC_LTCTR); |
| 190 | } |
| 191 | |
| 192 | static void bigmac_clean_rings(struct bigmac *bp) |
| 193 | { |
| 194 | int i; |
| 195 | |
| 196 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 197 | if (bp->rx_skbs[i] != NULL) { |
| 198 | dev_kfree_skb_any(bp->rx_skbs[i]); |
| 199 | bp->rx_skbs[i] = NULL; |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 204 | if (bp->tx_skbs[i] != NULL) { |
| 205 | dev_kfree_skb_any(bp->tx_skbs[i]); |
| 206 | bp->tx_skbs[i] = NULL; |
| 207 | } |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | static void bigmac_init_rings(struct bigmac *bp, int from_irq) |
| 212 | { |
| 213 | struct bmac_init_block *bb = bp->bmac_block; |
| 214 | struct net_device *dev = bp->dev; |
Al Viro | 9e24974 | 2005-10-21 03:22:29 -0400 | [diff] [blame] | 215 | int i; |
| 216 | gfp_t gfp_flags = GFP_KERNEL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | |
| 218 | if (from_irq || in_interrupt()) |
| 219 | gfp_flags = GFP_ATOMIC; |
| 220 | |
| 221 | bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0; |
| 222 | |
| 223 | /* Free any skippy bufs left around in the rings. */ |
| 224 | bigmac_clean_rings(bp); |
| 225 | |
| 226 | /* Now get new skbufs for the receive ring. */ |
| 227 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 228 | struct sk_buff *skb; |
| 229 | |
| 230 | skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags); |
| 231 | if (!skb) |
| 232 | continue; |
| 233 | |
| 234 | bp->rx_skbs[i] = skb; |
| 235 | skb->dev = dev; |
| 236 | |
| 237 | /* Because we reserve afterwards. */ |
| 238 | skb_put(skb, ETH_FRAME_LEN); |
| 239 | skb_reserve(skb, 34); |
| 240 | |
| 241 | bb->be_rxd[i].rx_addr = |
| 242 | sbus_map_single(bp->bigmac_sdev, skb->data, |
| 243 | RX_BUF_ALLOC_SIZE - 34, |
| 244 | SBUS_DMA_FROMDEVICE); |
| 245 | bb->be_rxd[i].rx_flags = |
| 246 | (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); |
| 247 | } |
| 248 | |
| 249 | for (i = 0; i < TX_RING_SIZE; i++) |
| 250 | bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0; |
| 251 | } |
| 252 | |
| 253 | #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK) |
| 254 | #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB) |
| 255 | |
| 256 | static void idle_transceiver(void __iomem *tregs) |
| 257 | { |
| 258 | int i = 20; |
| 259 | |
| 260 | while (i--) { |
| 261 | sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL); |
| 262 | sbus_readl(tregs + TCVR_MPAL); |
| 263 | sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL); |
| 264 | sbus_readl(tregs + TCVR_MPAL); |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit) |
| 269 | { |
| 270 | if (bp->tcvr_type == internal) { |
| 271 | bit = (bit & 1) << 3; |
| 272 | sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO), |
| 273 | tregs + TCVR_MPAL); |
| 274 | sbus_readl(tregs + TCVR_MPAL); |
| 275 | sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, |
| 276 | tregs + TCVR_MPAL); |
| 277 | sbus_readl(tregs + TCVR_MPAL); |
| 278 | } else if (bp->tcvr_type == external) { |
| 279 | bit = (bit & 1) << 2; |
| 280 | sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB, |
| 281 | tregs + TCVR_MPAL); |
| 282 | sbus_readl(tregs + TCVR_MPAL); |
| 283 | sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK, |
| 284 | tregs + TCVR_MPAL); |
| 285 | sbus_readl(tregs + TCVR_MPAL); |
| 286 | } else { |
| 287 | printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n"); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs) |
| 292 | { |
| 293 | int retval = 0; |
| 294 | |
| 295 | if (bp->tcvr_type == internal) { |
| 296 | sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); |
| 297 | sbus_readl(tregs + TCVR_MPAL); |
| 298 | sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, |
| 299 | tregs + TCVR_MPAL); |
| 300 | sbus_readl(tregs + TCVR_MPAL); |
| 301 | retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3; |
| 302 | } else if (bp->tcvr_type == external) { |
| 303 | sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL); |
| 304 | sbus_readl(tregs + TCVR_MPAL); |
| 305 | sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); |
| 306 | sbus_readl(tregs + TCVR_MPAL); |
| 307 | retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2; |
| 308 | } else { |
| 309 | printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n"); |
| 310 | } |
| 311 | return retval; |
| 312 | } |
| 313 | |
| 314 | static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs) |
| 315 | { |
| 316 | int retval = 0; |
| 317 | |
| 318 | if (bp->tcvr_type == internal) { |
| 319 | sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); |
| 320 | sbus_readl(tregs + TCVR_MPAL); |
| 321 | retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3; |
| 322 | sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); |
| 323 | sbus_readl(tregs + TCVR_MPAL); |
| 324 | } else if (bp->tcvr_type == external) { |
| 325 | sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL); |
| 326 | sbus_readl(tregs + TCVR_MPAL); |
| 327 | retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2; |
| 328 | sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); |
| 329 | sbus_readl(tregs + TCVR_MPAL); |
| 330 | } else { |
| 331 | printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n"); |
| 332 | } |
| 333 | return retval; |
| 334 | } |
| 335 | |
| 336 | static void put_tcvr_byte(struct bigmac *bp, |
| 337 | void __iomem *tregs, |
| 338 | unsigned int byte) |
| 339 | { |
| 340 | int shift = 4; |
| 341 | |
| 342 | do { |
| 343 | write_tcvr_bit(bp, tregs, ((byte >> shift) & 1)); |
| 344 | shift -= 1; |
| 345 | } while (shift >= 0); |
| 346 | } |
| 347 | |
| 348 | static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs, |
| 349 | int reg, unsigned short val) |
| 350 | { |
| 351 | int shift; |
| 352 | |
| 353 | reg &= 0xff; |
| 354 | val &= 0xffff; |
| 355 | switch(bp->tcvr_type) { |
| 356 | case internal: |
| 357 | case external: |
| 358 | break; |
| 359 | |
| 360 | default: |
| 361 | printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n"); |
| 362 | return; |
| 363 | }; |
| 364 | |
| 365 | idle_transceiver(tregs); |
| 366 | write_tcvr_bit(bp, tregs, 0); |
| 367 | write_tcvr_bit(bp, tregs, 1); |
| 368 | write_tcvr_bit(bp, tregs, 0); |
| 369 | write_tcvr_bit(bp, tregs, 1); |
| 370 | |
| 371 | put_tcvr_byte(bp, tregs, |
| 372 | ((bp->tcvr_type == internal) ? |
| 373 | BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL)); |
| 374 | |
| 375 | put_tcvr_byte(bp, tregs, reg); |
| 376 | |
| 377 | write_tcvr_bit(bp, tregs, 1); |
| 378 | write_tcvr_bit(bp, tregs, 0); |
| 379 | |
| 380 | shift = 15; |
| 381 | do { |
| 382 | write_tcvr_bit(bp, tregs, (val >> shift) & 1); |
| 383 | shift -= 1; |
| 384 | } while (shift >= 0); |
| 385 | } |
| 386 | |
| 387 | static unsigned short bigmac_tcvr_read(struct bigmac *bp, |
| 388 | void __iomem *tregs, |
| 389 | int reg) |
| 390 | { |
| 391 | unsigned short retval = 0; |
| 392 | |
| 393 | reg &= 0xff; |
| 394 | switch(bp->tcvr_type) { |
| 395 | case internal: |
| 396 | case external: |
| 397 | break; |
| 398 | |
| 399 | default: |
| 400 | printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n"); |
| 401 | return 0xffff; |
| 402 | }; |
| 403 | |
| 404 | idle_transceiver(tregs); |
| 405 | write_tcvr_bit(bp, tregs, 0); |
| 406 | write_tcvr_bit(bp, tregs, 1); |
| 407 | write_tcvr_bit(bp, tregs, 1); |
| 408 | write_tcvr_bit(bp, tregs, 0); |
| 409 | |
| 410 | put_tcvr_byte(bp, tregs, |
| 411 | ((bp->tcvr_type == internal) ? |
| 412 | BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL)); |
| 413 | |
| 414 | put_tcvr_byte(bp, tregs, reg); |
| 415 | |
| 416 | if (bp->tcvr_type == external) { |
| 417 | int shift = 15; |
| 418 | |
| 419 | (void) read_tcvr_bit2(bp, tregs); |
| 420 | (void) read_tcvr_bit2(bp, tregs); |
| 421 | |
| 422 | do { |
| 423 | int tmp; |
| 424 | |
| 425 | tmp = read_tcvr_bit2(bp, tregs); |
| 426 | retval |= ((tmp & 1) << shift); |
| 427 | shift -= 1; |
| 428 | } while (shift >= 0); |
| 429 | |
| 430 | (void) read_tcvr_bit2(bp, tregs); |
| 431 | (void) read_tcvr_bit2(bp, tregs); |
| 432 | (void) read_tcvr_bit2(bp, tregs); |
| 433 | } else { |
| 434 | int shift = 15; |
| 435 | |
| 436 | (void) read_tcvr_bit(bp, tregs); |
| 437 | (void) read_tcvr_bit(bp, tregs); |
| 438 | |
| 439 | do { |
| 440 | int tmp; |
| 441 | |
| 442 | tmp = read_tcvr_bit(bp, tregs); |
| 443 | retval |= ((tmp & 1) << shift); |
| 444 | shift -= 1; |
| 445 | } while (shift >= 0); |
| 446 | |
| 447 | (void) read_tcvr_bit(bp, tregs); |
| 448 | (void) read_tcvr_bit(bp, tregs); |
| 449 | (void) read_tcvr_bit(bp, tregs); |
| 450 | } |
| 451 | return retval; |
| 452 | } |
| 453 | |
| 454 | static void bigmac_tcvr_init(struct bigmac *bp) |
| 455 | { |
| 456 | void __iomem *tregs = bp->tregs; |
| 457 | u32 mpal; |
| 458 | |
| 459 | idle_transceiver(tregs); |
| 460 | sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, |
| 461 | tregs + TCVR_MPAL); |
| 462 | sbus_readl(tregs + TCVR_MPAL); |
| 463 | |
| 464 | /* Only the bit for the present transceiver (internal or |
| 465 | * external) will stick, set them both and see what stays. |
| 466 | */ |
| 467 | sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); |
| 468 | sbus_readl(tregs + TCVR_MPAL); |
| 469 | udelay(20); |
| 470 | |
| 471 | mpal = sbus_readl(tregs + TCVR_MPAL); |
| 472 | if (mpal & MGMT_PAL_EXT_MDIO) { |
| 473 | bp->tcvr_type = external; |
| 474 | sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE), |
| 475 | tregs + TCVR_TPAL); |
| 476 | sbus_readl(tregs + TCVR_TPAL); |
| 477 | } else if (mpal & MGMT_PAL_INT_MDIO) { |
| 478 | bp->tcvr_type = internal; |
| 479 | sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK | |
| 480 | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE), |
| 481 | tregs + TCVR_TPAL); |
| 482 | sbus_readl(tregs + TCVR_TPAL); |
| 483 | } else { |
| 484 | printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor " |
| 485 | "external MDIO available!\n"); |
| 486 | printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n", |
| 487 | sbus_readl(tregs + TCVR_MPAL), |
| 488 | sbus_readl(tregs + TCVR_TPAL)); |
| 489 | } |
| 490 | } |
| 491 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 492 | static int bigmac_init_hw(struct bigmac *, int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | |
| 494 | static int try_next_permutation(struct bigmac *bp, void __iomem *tregs) |
| 495 | { |
| 496 | if (bp->sw_bmcr & BMCR_SPEED100) { |
| 497 | int timeout; |
| 498 | |
| 499 | /* Reset the PHY. */ |
| 500 | bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK); |
| 501 | bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr); |
| 502 | bp->sw_bmcr = (BMCR_RESET); |
| 503 | bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr); |
| 504 | |
| 505 | timeout = 64; |
| 506 | while (--timeout) { |
| 507 | bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR); |
| 508 | if ((bp->sw_bmcr & BMCR_RESET) == 0) |
| 509 | break; |
| 510 | udelay(20); |
| 511 | } |
| 512 | if (timeout == 0) |
| 513 | printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name); |
| 514 | |
| 515 | bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR); |
| 516 | |
| 517 | /* Now we try 10baseT. */ |
| 518 | bp->sw_bmcr &= ~(BMCR_SPEED100); |
| 519 | bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr); |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | /* We've tried them all. */ |
| 524 | return -1; |
| 525 | } |
| 526 | |
| 527 | static void bigmac_timer(unsigned long data) |
| 528 | { |
| 529 | struct bigmac *bp = (struct bigmac *) data; |
| 530 | void __iomem *tregs = bp->tregs; |
| 531 | int restart_timer = 0; |
| 532 | |
| 533 | bp->timer_ticks++; |
| 534 | if (bp->timer_state == ltrywait) { |
| 535 | bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR); |
| 536 | bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR); |
| 537 | if (bp->sw_bmsr & BMSR_LSTATUS) { |
| 538 | printk(KERN_INFO "%s: Link is now up at %s.\n", |
| 539 | bp->dev->name, |
| 540 | (bp->sw_bmcr & BMCR_SPEED100) ? |
| 541 | "100baseT" : "10baseT"); |
| 542 | bp->timer_state = asleep; |
| 543 | restart_timer = 0; |
| 544 | } else { |
| 545 | if (bp->timer_ticks >= 4) { |
| 546 | int ret; |
| 547 | |
| 548 | ret = try_next_permutation(bp, tregs); |
| 549 | if (ret == -1) { |
| 550 | printk(KERN_ERR "%s: Link down, cable problem?\n", |
| 551 | bp->dev->name); |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 552 | ret = bigmac_init_hw(bp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | if (ret) { |
| 554 | printk(KERN_ERR "%s: Error, cannot re-init the " |
| 555 | "BigMAC.\n", bp->dev->name); |
| 556 | } |
| 557 | return; |
| 558 | } |
| 559 | bp->timer_ticks = 0; |
| 560 | restart_timer = 1; |
| 561 | } else { |
| 562 | restart_timer = 1; |
| 563 | } |
| 564 | } |
| 565 | } else { |
| 566 | /* Can't happens.... */ |
| 567 | printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n", |
| 568 | bp->dev->name); |
| 569 | restart_timer = 0; |
| 570 | bp->timer_ticks = 0; |
| 571 | bp->timer_state = asleep; /* foo on you */ |
| 572 | } |
| 573 | |
| 574 | if (restart_timer != 0) { |
| 575 | bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */ |
| 576 | add_timer(&bp->bigmac_timer); |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | /* Well, really we just force the chip into 100baseT then |
| 581 | * 10baseT, each time checking for a link status. |
| 582 | */ |
| 583 | static void bigmac_begin_auto_negotiation(struct bigmac *bp) |
| 584 | { |
| 585 | void __iomem *tregs = bp->tregs; |
| 586 | int timeout; |
| 587 | |
| 588 | /* Grab new software copies of PHY registers. */ |
| 589 | bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR); |
| 590 | bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR); |
| 591 | |
| 592 | /* Reset the PHY. */ |
| 593 | bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK); |
| 594 | bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr); |
| 595 | bp->sw_bmcr = (BMCR_RESET); |
| 596 | bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr); |
| 597 | |
| 598 | timeout = 64; |
| 599 | while (--timeout) { |
| 600 | bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR); |
| 601 | if ((bp->sw_bmcr & BMCR_RESET) == 0) |
| 602 | break; |
| 603 | udelay(20); |
| 604 | } |
| 605 | if (timeout == 0) |
| 606 | printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name); |
| 607 | |
| 608 | bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR); |
| 609 | |
| 610 | /* First we try 100baseT. */ |
| 611 | bp->sw_bmcr |= BMCR_SPEED100; |
| 612 | bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr); |
| 613 | |
| 614 | bp->timer_state = ltrywait; |
| 615 | bp->timer_ticks = 0; |
| 616 | bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10; |
| 617 | bp->bigmac_timer.data = (unsigned long) bp; |
| 618 | bp->bigmac_timer.function = &bigmac_timer; |
| 619 | add_timer(&bp->bigmac_timer); |
| 620 | } |
| 621 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 622 | static int bigmac_init_hw(struct bigmac *bp, int from_irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | { |
| 624 | void __iomem *gregs = bp->gregs; |
| 625 | void __iomem *cregs = bp->creg; |
| 626 | void __iomem *bregs = bp->bregs; |
| 627 | unsigned char *e = &bp->dev->dev_addr[0]; |
| 628 | |
| 629 | /* Latch current counters into statistics. */ |
| 630 | bigmac_get_counters(bp, bregs); |
| 631 | |
| 632 | /* Reset QEC. */ |
| 633 | qec_global_reset(gregs); |
| 634 | |
| 635 | /* Init QEC. */ |
| 636 | qec_init(bp); |
| 637 | |
| 638 | /* Alloc and reset the tx/rx descriptor chains. */ |
| 639 | bigmac_init_rings(bp, from_irq); |
| 640 | |
| 641 | /* Initialize the PHY. */ |
| 642 | bigmac_tcvr_init(bp); |
| 643 | |
| 644 | /* Stop transmitter and receiver. */ |
| 645 | bigmac_stop(bp); |
| 646 | |
| 647 | /* Set hardware ethernet address. */ |
| 648 | sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2); |
| 649 | sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1); |
| 650 | sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0); |
| 651 | |
| 652 | /* Clear the hash table until mc upload occurs. */ |
| 653 | sbus_writel(0, bregs + BMAC_HTABLE3); |
| 654 | sbus_writel(0, bregs + BMAC_HTABLE2); |
| 655 | sbus_writel(0, bregs + BMAC_HTABLE1); |
| 656 | sbus_writel(0, bregs + BMAC_HTABLE0); |
| 657 | |
| 658 | /* Enable Big Mac hash table filter. */ |
| 659 | sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO, |
| 660 | bregs + BMAC_RXCFG); |
| 661 | udelay(20); |
| 662 | |
| 663 | /* Ok, configure the Big Mac transmitter. */ |
| 664 | sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG); |
| 665 | |
| 666 | /* The HME docs recommend to use the 10LSB of our MAC here. */ |
| 667 | sbus_writel(((e[5] | e[4] << 8) & 0x3ff), |
| 668 | bregs + BMAC_RSEED); |
| 669 | |
| 670 | /* Enable the output drivers no matter what. */ |
| 671 | sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV, |
| 672 | bregs + BMAC_XIFCFG); |
| 673 | |
| 674 | /* Tell the QEC where the ring descriptors are. */ |
| 675 | sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0), |
| 676 | cregs + CREG_RXDS); |
| 677 | sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0), |
| 678 | cregs + CREG_TXDS); |
| 679 | |
| 680 | /* Setup the FIFO pointers into QEC local memory. */ |
| 681 | sbus_writel(0, cregs + CREG_RXRBUFPTR); |
| 682 | sbus_writel(0, cregs + CREG_RXWBUFPTR); |
| 683 | sbus_writel(sbus_readl(gregs + GLOB_RSIZE), |
| 684 | cregs + CREG_TXRBUFPTR); |
| 685 | sbus_writel(sbus_readl(gregs + GLOB_RSIZE), |
| 686 | cregs + CREG_TXWBUFPTR); |
| 687 | |
| 688 | /* Tell bigmac what interrupts we don't want to hear about. */ |
| 689 | sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME, |
| 690 | bregs + BMAC_IMASK); |
| 691 | |
| 692 | /* Enable the various other irq's. */ |
| 693 | sbus_writel(0, cregs + CREG_RIMASK); |
| 694 | sbus_writel(0, cregs + CREG_TIMASK); |
| 695 | sbus_writel(0, cregs + CREG_QMASK); |
| 696 | sbus_writel(0, cregs + CREG_BMASK); |
| 697 | |
| 698 | /* Set jam size to a reasonable default. */ |
| 699 | sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE); |
| 700 | |
| 701 | /* Clear collision counter. */ |
| 702 | sbus_writel(0, cregs + CREG_CCNT); |
| 703 | |
| 704 | /* Enable transmitter and receiver. */ |
| 705 | sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE, |
| 706 | bregs + BMAC_TXCFG); |
| 707 | sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE, |
| 708 | bregs + BMAC_RXCFG); |
| 709 | |
| 710 | /* Ok, start detecting link speed/duplex. */ |
| 711 | bigmac_begin_auto_negotiation(bp); |
| 712 | |
| 713 | /* Success. */ |
| 714 | return 0; |
| 715 | } |
| 716 | |
| 717 | /* Error interrupts get sent here. */ |
| 718 | static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status) |
| 719 | { |
| 720 | printk(KERN_ERR "bigmac_is_medium_rare: "); |
| 721 | if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) { |
| 722 | if (qec_status & GLOB_STAT_ER) |
| 723 | printk("QEC_ERROR, "); |
| 724 | if (qec_status & GLOB_STAT_BM) |
| 725 | printk("QEC_BMAC_ERROR, "); |
| 726 | } |
| 727 | if (bmac_status & CREG_STAT_ERRORS) { |
| 728 | if (bmac_status & CREG_STAT_BERROR) |
| 729 | printk("BMAC_ERROR, "); |
| 730 | if (bmac_status & CREG_STAT_TXDERROR) |
| 731 | printk("TXD_ERROR, "); |
| 732 | if (bmac_status & CREG_STAT_TXLERR) |
| 733 | printk("TX_LATE_ERROR, "); |
| 734 | if (bmac_status & CREG_STAT_TXPERR) |
| 735 | printk("TX_PARITY_ERROR, "); |
| 736 | if (bmac_status & CREG_STAT_TXSERR) |
| 737 | printk("TX_SBUS_ERROR, "); |
| 738 | |
| 739 | if (bmac_status & CREG_STAT_RXDROP) |
| 740 | printk("RX_DROP_ERROR, "); |
| 741 | |
| 742 | if (bmac_status & CREG_STAT_RXSMALL) |
| 743 | printk("RX_SMALL_ERROR, "); |
| 744 | if (bmac_status & CREG_STAT_RXLERR) |
| 745 | printk("RX_LATE_ERROR, "); |
| 746 | if (bmac_status & CREG_STAT_RXPERR) |
| 747 | printk("RX_PARITY_ERROR, "); |
| 748 | if (bmac_status & CREG_STAT_RXSERR) |
| 749 | printk("RX_SBUS_ERROR, "); |
| 750 | } |
| 751 | |
| 752 | printk(" RESET\n"); |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 753 | bigmac_init_hw(bp, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | } |
| 755 | |
| 756 | /* BigMAC transmit complete service routines. */ |
| 757 | static void bigmac_tx(struct bigmac *bp) |
| 758 | { |
| 759 | struct be_txd *txbase = &bp->bmac_block->be_txd[0]; |
| 760 | struct net_device *dev = bp->dev; |
| 761 | int elem; |
| 762 | |
| 763 | spin_lock(&bp->lock); |
| 764 | |
| 765 | elem = bp->tx_old; |
| 766 | DTX(("bigmac_tx: tx_old[%d] ", elem)); |
| 767 | while (elem != bp->tx_new) { |
| 768 | struct sk_buff *skb; |
| 769 | struct be_txd *this = &txbase[elem]; |
| 770 | |
| 771 | DTX(("this(%p) [flags(%08x)addr(%08x)]", |
| 772 | this, this->tx_flags, this->tx_addr)); |
| 773 | |
| 774 | if (this->tx_flags & TXD_OWN) |
| 775 | break; |
| 776 | skb = bp->tx_skbs[elem]; |
| 777 | bp->enet_stats.tx_packets++; |
| 778 | bp->enet_stats.tx_bytes += skb->len; |
| 779 | sbus_unmap_single(bp->bigmac_sdev, |
| 780 | this->tx_addr, skb->len, |
| 781 | SBUS_DMA_TODEVICE); |
| 782 | |
| 783 | DTX(("skb(%p) ", skb)); |
| 784 | bp->tx_skbs[elem] = NULL; |
| 785 | dev_kfree_skb_irq(skb); |
| 786 | |
| 787 | elem = NEXT_TX(elem); |
| 788 | } |
| 789 | DTX((" DONE, tx_old=%d\n", elem)); |
| 790 | bp->tx_old = elem; |
| 791 | |
| 792 | if (netif_queue_stopped(dev) && |
| 793 | TX_BUFFS_AVAIL(bp) > 0) |
| 794 | netif_wake_queue(bp->dev); |
| 795 | |
| 796 | spin_unlock(&bp->lock); |
| 797 | } |
| 798 | |
| 799 | /* BigMAC receive complete service routines. */ |
| 800 | static void bigmac_rx(struct bigmac *bp) |
| 801 | { |
| 802 | struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0]; |
| 803 | struct be_rxd *this; |
| 804 | int elem = bp->rx_new, drops = 0; |
| 805 | u32 flags; |
| 806 | |
| 807 | this = &rxbase[elem]; |
| 808 | while (!((flags = this->rx_flags) & RXD_OWN)) { |
| 809 | struct sk_buff *skb; |
| 810 | int len = (flags & RXD_LENGTH); /* FCS not included */ |
| 811 | |
| 812 | /* Check for errors. */ |
| 813 | if (len < ETH_ZLEN) { |
| 814 | bp->enet_stats.rx_errors++; |
| 815 | bp->enet_stats.rx_length_errors++; |
| 816 | |
| 817 | drop_it: |
| 818 | /* Return it to the BigMAC. */ |
| 819 | bp->enet_stats.rx_dropped++; |
| 820 | this->rx_flags = |
| 821 | (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); |
| 822 | goto next; |
| 823 | } |
| 824 | skb = bp->rx_skbs[elem]; |
| 825 | if (len > RX_COPY_THRESHOLD) { |
| 826 | struct sk_buff *new_skb; |
| 827 | |
| 828 | /* Now refill the entry, if we can. */ |
| 829 | new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); |
| 830 | if (new_skb == NULL) { |
| 831 | drops++; |
| 832 | goto drop_it; |
| 833 | } |
| 834 | sbus_unmap_single(bp->bigmac_sdev, |
| 835 | this->rx_addr, |
| 836 | RX_BUF_ALLOC_SIZE - 34, |
| 837 | SBUS_DMA_FROMDEVICE); |
| 838 | bp->rx_skbs[elem] = new_skb; |
| 839 | new_skb->dev = bp->dev; |
| 840 | skb_put(new_skb, ETH_FRAME_LEN); |
| 841 | skb_reserve(new_skb, 34); |
| 842 | this->rx_addr = sbus_map_single(bp->bigmac_sdev, |
| 843 | new_skb->data, |
| 844 | RX_BUF_ALLOC_SIZE - 34, |
| 845 | SBUS_DMA_FROMDEVICE); |
| 846 | this->rx_flags = |
| 847 | (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); |
| 848 | |
| 849 | /* Trim the original skb for the netif. */ |
| 850 | skb_trim(skb, len); |
| 851 | } else { |
| 852 | struct sk_buff *copy_skb = dev_alloc_skb(len + 2); |
| 853 | |
| 854 | if (copy_skb == NULL) { |
| 855 | drops++; |
| 856 | goto drop_it; |
| 857 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | skb_reserve(copy_skb, 2); |
| 859 | skb_put(copy_skb, len); |
| 860 | sbus_dma_sync_single_for_cpu(bp->bigmac_sdev, |
| 861 | this->rx_addr, len, |
| 862 | SBUS_DMA_FROMDEVICE); |
David S. Miller | 8c7b7fa | 2007-07-10 22:08:12 -0700 | [diff] [blame] | 863 | skb_copy_to_linear_data(copy_skb, (unsigned char *)skb->data, len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | sbus_dma_sync_single_for_device(bp->bigmac_sdev, |
| 865 | this->rx_addr, len, |
| 866 | SBUS_DMA_FROMDEVICE); |
| 867 | |
| 868 | /* Reuse original ring buffer. */ |
| 869 | this->rx_flags = |
| 870 | (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); |
| 871 | |
| 872 | skb = copy_skb; |
| 873 | } |
| 874 | |
| 875 | /* No checksums done by the BigMAC ;-( */ |
| 876 | skb->protocol = eth_type_trans(skb, bp->dev); |
| 877 | netif_rx(skb); |
| 878 | bp->dev->last_rx = jiffies; |
| 879 | bp->enet_stats.rx_packets++; |
| 880 | bp->enet_stats.rx_bytes += len; |
| 881 | next: |
| 882 | elem = NEXT_RX(elem); |
| 883 | this = &rxbase[elem]; |
| 884 | } |
| 885 | bp->rx_new = elem; |
| 886 | if (drops) |
| 887 | printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name); |
| 888 | } |
| 889 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 890 | static irqreturn_t bigmac_interrupt(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | { |
| 892 | struct bigmac *bp = (struct bigmac *) dev_id; |
| 893 | u32 qec_status, bmac_status; |
| 894 | |
| 895 | DIRQ(("bigmac_interrupt: ")); |
| 896 | |
| 897 | /* Latch status registers now. */ |
| 898 | bmac_status = sbus_readl(bp->creg + CREG_STAT); |
| 899 | qec_status = sbus_readl(bp->gregs + GLOB_STAT); |
| 900 | |
| 901 | DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status)); |
| 902 | if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) || |
| 903 | (bmac_status & CREG_STAT_ERRORS)) |
| 904 | bigmac_is_medium_rare(bp, qec_status, bmac_status); |
| 905 | |
| 906 | if (bmac_status & CREG_STAT_TXIRQ) |
| 907 | bigmac_tx(bp); |
| 908 | |
| 909 | if (bmac_status & CREG_STAT_RXIRQ) |
| 910 | bigmac_rx(bp); |
| 911 | |
| 912 | return IRQ_HANDLED; |
| 913 | } |
| 914 | |
| 915 | static int bigmac_open(struct net_device *dev) |
| 916 | { |
| 917 | struct bigmac *bp = (struct bigmac *) dev->priv; |
| 918 | int ret; |
| 919 | |
Thomas Gleixner | 1fb9df5 | 2006-07-01 19:29:39 -0700 | [diff] [blame] | 920 | ret = request_irq(dev->irq, &bigmac_interrupt, IRQF_SHARED, dev->name, bp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | if (ret) { |
| 922 | printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq); |
| 923 | return ret; |
| 924 | } |
| 925 | init_timer(&bp->bigmac_timer); |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 926 | ret = bigmac_init_hw(bp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | if (ret) |
| 928 | free_irq(dev->irq, bp); |
| 929 | return ret; |
| 930 | } |
| 931 | |
| 932 | static int bigmac_close(struct net_device *dev) |
| 933 | { |
| 934 | struct bigmac *bp = (struct bigmac *) dev->priv; |
| 935 | |
| 936 | del_timer(&bp->bigmac_timer); |
| 937 | bp->timer_state = asleep; |
| 938 | bp->timer_ticks = 0; |
| 939 | |
| 940 | bigmac_stop(bp); |
| 941 | bigmac_clean_rings(bp); |
| 942 | free_irq(dev->irq, bp); |
| 943 | return 0; |
| 944 | } |
| 945 | |
| 946 | static void bigmac_tx_timeout(struct net_device *dev) |
| 947 | { |
| 948 | struct bigmac *bp = (struct bigmac *) dev->priv; |
| 949 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 950 | bigmac_init_hw(bp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | netif_wake_queue(dev); |
| 952 | } |
| 953 | |
| 954 | /* Put a packet on the wire. */ |
| 955 | static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 956 | { |
| 957 | struct bigmac *bp = (struct bigmac *) dev->priv; |
| 958 | int len, entry; |
| 959 | u32 mapping; |
| 960 | |
| 961 | len = skb->len; |
| 962 | mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE); |
| 963 | |
| 964 | /* Avoid a race... */ |
| 965 | spin_lock_irq(&bp->lock); |
| 966 | entry = bp->tx_new; |
| 967 | DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry)); |
| 968 | bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE; |
| 969 | bp->tx_skbs[entry] = skb; |
| 970 | bp->bmac_block->be_txd[entry].tx_addr = mapping; |
| 971 | bp->bmac_block->be_txd[entry].tx_flags = |
| 972 | (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH)); |
| 973 | bp->tx_new = NEXT_TX(entry); |
| 974 | if (TX_BUFFS_AVAIL(bp) <= 0) |
| 975 | netif_stop_queue(dev); |
| 976 | spin_unlock_irq(&bp->lock); |
| 977 | |
| 978 | /* Get it going. */ |
| 979 | sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL); |
| 980 | |
| 981 | |
| 982 | dev->trans_start = jiffies; |
| 983 | |
| 984 | return 0; |
| 985 | } |
| 986 | |
| 987 | static struct net_device_stats *bigmac_get_stats(struct net_device *dev) |
| 988 | { |
| 989 | struct bigmac *bp = (struct bigmac *) dev->priv; |
| 990 | |
| 991 | bigmac_get_counters(bp, bp->bregs); |
| 992 | return &bp->enet_stats; |
| 993 | } |
| 994 | |
| 995 | static void bigmac_set_multicast(struct net_device *dev) |
| 996 | { |
| 997 | struct bigmac *bp = (struct bigmac *) dev->priv; |
| 998 | void __iomem *bregs = bp->bregs; |
| 999 | struct dev_mc_list *dmi = dev->mc_list; |
| 1000 | char *addrs; |
| 1001 | int i; |
| 1002 | u32 tmp, crc; |
| 1003 | |
| 1004 | /* Disable the receiver. The bit self-clears when |
| 1005 | * the operation is complete. |
| 1006 | */ |
| 1007 | tmp = sbus_readl(bregs + BMAC_RXCFG); |
| 1008 | tmp &= ~(BIGMAC_RXCFG_ENABLE); |
| 1009 | sbus_writel(tmp, bregs + BMAC_RXCFG); |
| 1010 | while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0) |
| 1011 | udelay(20); |
| 1012 | |
| 1013 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) { |
| 1014 | sbus_writel(0xffff, bregs + BMAC_HTABLE0); |
| 1015 | sbus_writel(0xffff, bregs + BMAC_HTABLE1); |
| 1016 | sbus_writel(0xffff, bregs + BMAC_HTABLE2); |
| 1017 | sbus_writel(0xffff, bregs + BMAC_HTABLE3); |
| 1018 | } else if (dev->flags & IFF_PROMISC) { |
| 1019 | tmp = sbus_readl(bregs + BMAC_RXCFG); |
| 1020 | tmp |= BIGMAC_RXCFG_PMISC; |
| 1021 | sbus_writel(tmp, bregs + BMAC_RXCFG); |
| 1022 | } else { |
| 1023 | u16 hash_table[4]; |
| 1024 | |
| 1025 | for (i = 0; i < 4; i++) |
| 1026 | hash_table[i] = 0; |
| 1027 | |
| 1028 | for (i = 0; i < dev->mc_count; i++) { |
| 1029 | addrs = dmi->dmi_addr; |
| 1030 | dmi = dmi->next; |
| 1031 | |
| 1032 | if (!(*addrs & 1)) |
| 1033 | continue; |
| 1034 | |
| 1035 | crc = ether_crc_le(6, addrs); |
| 1036 | crc >>= 26; |
| 1037 | hash_table[crc >> 4] |= 1 << (crc & 0xf); |
| 1038 | } |
| 1039 | sbus_writel(hash_table[0], bregs + BMAC_HTABLE0); |
| 1040 | sbus_writel(hash_table[1], bregs + BMAC_HTABLE1); |
| 1041 | sbus_writel(hash_table[2], bregs + BMAC_HTABLE2); |
| 1042 | sbus_writel(hash_table[3], bregs + BMAC_HTABLE3); |
| 1043 | } |
| 1044 | |
| 1045 | /* Re-enable the receiver. */ |
| 1046 | tmp = sbus_readl(bregs + BMAC_RXCFG); |
| 1047 | tmp |= BIGMAC_RXCFG_ENABLE; |
| 1048 | sbus_writel(tmp, bregs + BMAC_RXCFG); |
| 1049 | } |
| 1050 | |
| 1051 | /* Ethtool support... */ |
| 1052 | static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
| 1053 | { |
| 1054 | struct bigmac *bp = dev->priv; |
| 1055 | |
| 1056 | strcpy(info->driver, "sunbmac"); |
| 1057 | strcpy(info->version, "2.0"); |
| 1058 | sprintf(info->bus_info, "SBUS:%d", |
| 1059 | bp->qec_sdev->slot); |
| 1060 | } |
| 1061 | |
| 1062 | static u32 bigmac_get_link(struct net_device *dev) |
| 1063 | { |
| 1064 | struct bigmac *bp = dev->priv; |
| 1065 | |
| 1066 | spin_lock_irq(&bp->lock); |
| 1067 | bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR); |
| 1068 | spin_unlock_irq(&bp->lock); |
| 1069 | |
| 1070 | return (bp->sw_bmsr & BMSR_LSTATUS); |
| 1071 | } |
| 1072 | |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 1073 | static const struct ethtool_ops bigmac_ethtool_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1074 | .get_drvinfo = bigmac_get_drvinfo, |
| 1075 | .get_link = bigmac_get_link, |
| 1076 | }; |
| 1077 | |
| 1078 | static int __init bigmac_ether_init(struct sbus_dev *qec_sdev) |
| 1079 | { |
| 1080 | struct net_device *dev; |
| 1081 | static int version_printed; |
| 1082 | struct bigmac *bp; |
| 1083 | u8 bsizes, bsizes_more; |
| 1084 | int i; |
Joe Perches | 0795af5 | 2007-10-03 17:59:30 -0700 | [diff] [blame^] | 1085 | DECLARE_MAC_BUF(mac); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | |
| 1087 | /* Get a new device struct for this interface. */ |
| 1088 | dev = alloc_etherdev(sizeof(struct bigmac)); |
| 1089 | if (!dev) |
| 1090 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | |
| 1092 | if (version_printed++ == 0) |
| 1093 | printk(KERN_INFO "%s", version); |
| 1094 | |
| 1095 | dev->base_addr = (long) qec_sdev; |
| 1096 | for (i = 0; i < 6; i++) |
| 1097 | dev->dev_addr[i] = idprom->id_ethaddr[i]; |
| 1098 | |
| 1099 | /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */ |
| 1100 | bp = dev->priv; |
| 1101 | bp->qec_sdev = qec_sdev; |
| 1102 | bp->bigmac_sdev = qec_sdev->child; |
| 1103 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1104 | SET_NETDEV_DEV(dev, &bp->bigmac_sdev->ofdev.dev); |
| 1105 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1106 | spin_lock_init(&bp->lock); |
| 1107 | |
| 1108 | /* Verify the registers we expect, are actually there. */ |
| 1109 | if ((bp->bigmac_sdev->num_registers != 3) || |
| 1110 | (bp->qec_sdev->num_registers != 2)) { |
| 1111 | printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n", |
| 1112 | bp->qec_sdev->num_registers, |
| 1113 | bp->bigmac_sdev->num_registers); |
| 1114 | printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n"); |
| 1115 | goto fail_and_cleanup; |
| 1116 | } |
| 1117 | |
| 1118 | /* Map in QEC global control registers. */ |
| 1119 | bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0, |
| 1120 | GLOB_REG_SIZE, "BigMAC QEC GLobal Regs"); |
| 1121 | if (!bp->gregs) { |
| 1122 | printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n"); |
| 1123 | goto fail_and_cleanup; |
| 1124 | } |
| 1125 | |
| 1126 | /* Make sure QEC is in BigMAC mode. */ |
| 1127 | if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) { |
| 1128 | printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n"); |
| 1129 | goto fail_and_cleanup; |
| 1130 | } |
| 1131 | |
| 1132 | /* Reset the QEC. */ |
| 1133 | if (qec_global_reset(bp->gregs)) |
| 1134 | goto fail_and_cleanup; |
| 1135 | |
| 1136 | /* Get supported SBUS burst sizes. */ |
| 1137 | bsizes = prom_getintdefault(bp->qec_sdev->prom_node, |
| 1138 | "burst-sizes", |
| 1139 | 0xff); |
| 1140 | |
| 1141 | bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node, |
| 1142 | "burst-sizes", |
| 1143 | 0xff); |
| 1144 | |
| 1145 | bsizes &= 0xff; |
| 1146 | if (bsizes_more != 0xff) |
| 1147 | bsizes &= bsizes_more; |
| 1148 | if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 || |
| 1149 | (bsizes & DMA_BURST32) == 0) |
| 1150 | bsizes = (DMA_BURST32 - 1); |
| 1151 | bp->bigmac_bursts = bsizes; |
| 1152 | |
| 1153 | /* Perform QEC initialization. */ |
| 1154 | qec_init(bp); |
| 1155 | |
| 1156 | /* Map in the BigMAC channel registers. */ |
| 1157 | bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0, |
| 1158 | CREG_REG_SIZE, "BigMAC QEC Channel Regs"); |
| 1159 | if (!bp->creg) { |
| 1160 | printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n"); |
| 1161 | goto fail_and_cleanup; |
| 1162 | } |
| 1163 | |
| 1164 | /* Map in the BigMAC control registers. */ |
| 1165 | bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0, |
| 1166 | BMAC_REG_SIZE, "BigMAC Primary Regs"); |
| 1167 | if (!bp->bregs) { |
| 1168 | printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n"); |
| 1169 | goto fail_and_cleanup; |
| 1170 | } |
| 1171 | |
| 1172 | /* Map in the BigMAC transceiver registers, this is how you poke at |
| 1173 | * the BigMAC's PHY. |
| 1174 | */ |
| 1175 | bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0, |
| 1176 | TCVR_REG_SIZE, "BigMAC Transceiver Regs"); |
| 1177 | if (!bp->tregs) { |
| 1178 | printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n"); |
| 1179 | goto fail_and_cleanup; |
| 1180 | } |
| 1181 | |
| 1182 | /* Stop the BigMAC. */ |
| 1183 | bigmac_stop(bp); |
| 1184 | |
| 1185 | /* Allocate transmit/receive descriptor DVMA block. */ |
| 1186 | bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev, |
| 1187 | PAGE_SIZE, |
| 1188 | &bp->bblock_dvma); |
| 1189 | if (bp->bmac_block == NULL || bp->bblock_dvma == 0) { |
| 1190 | printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n"); |
| 1191 | goto fail_and_cleanup; |
| 1192 | } |
| 1193 | |
| 1194 | /* Get the board revision of this BigMAC. */ |
| 1195 | bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node, |
| 1196 | "board-version", 1); |
| 1197 | |
| 1198 | /* Init auto-negotiation timer state. */ |
| 1199 | init_timer(&bp->bigmac_timer); |
| 1200 | bp->timer_state = asleep; |
| 1201 | bp->timer_ticks = 0; |
| 1202 | |
| 1203 | /* Backlink to generic net device struct. */ |
| 1204 | bp->dev = dev; |
| 1205 | |
| 1206 | /* Set links to our BigMAC open and close routines. */ |
| 1207 | dev->open = &bigmac_open; |
| 1208 | dev->stop = &bigmac_close; |
| 1209 | dev->hard_start_xmit = &bigmac_start_xmit; |
| 1210 | dev->ethtool_ops = &bigmac_ethtool_ops; |
| 1211 | |
| 1212 | /* Set links to BigMAC statistic and multi-cast loading code. */ |
| 1213 | dev->get_stats = &bigmac_get_stats; |
| 1214 | dev->set_multicast_list = &bigmac_set_multicast; |
| 1215 | |
| 1216 | dev->tx_timeout = &bigmac_tx_timeout; |
| 1217 | dev->watchdog_timeo = 5*HZ; |
| 1218 | |
| 1219 | /* Finish net device registration. */ |
| 1220 | dev->irq = bp->bigmac_sdev->irqs[0]; |
| 1221 | dev->dma = 0; |
| 1222 | |
| 1223 | if (register_netdev(dev)) { |
| 1224 | printk(KERN_ERR "BIGMAC: Cannot register device.\n"); |
| 1225 | goto fail_and_cleanup; |
| 1226 | } |
| 1227 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1228 | dev_set_drvdata(&bp->bigmac_sdev->ofdev.dev, bp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | |
Joe Perches | 0795af5 | 2007-10-03 17:59:30 -0700 | [diff] [blame^] | 1230 | printk(KERN_INFO "%s: BigMAC 100baseT Ethernet %s\n", |
| 1231 | dev->name, print_mac(mac, dev->dev_addr)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1232 | |
| 1233 | return 0; |
| 1234 | |
| 1235 | fail_and_cleanup: |
| 1236 | /* Something went wrong, undo whatever we did so far. */ |
| 1237 | /* Free register mappings if any. */ |
| 1238 | if (bp->gregs) |
| 1239 | sbus_iounmap(bp->gregs, GLOB_REG_SIZE); |
| 1240 | if (bp->creg) |
| 1241 | sbus_iounmap(bp->creg, CREG_REG_SIZE); |
| 1242 | if (bp->bregs) |
| 1243 | sbus_iounmap(bp->bregs, BMAC_REG_SIZE); |
| 1244 | if (bp->tregs) |
| 1245 | sbus_iounmap(bp->tregs, TCVR_REG_SIZE); |
| 1246 | |
| 1247 | if (bp->bmac_block) |
| 1248 | sbus_free_consistent(bp->bigmac_sdev, |
| 1249 | PAGE_SIZE, |
| 1250 | bp->bmac_block, |
| 1251 | bp->bblock_dvma); |
| 1252 | |
| 1253 | /* This also frees the co-located 'dev->priv' */ |
| 1254 | free_netdev(dev); |
| 1255 | return -ENODEV; |
| 1256 | } |
| 1257 | |
| 1258 | /* QEC can be the parent of either QuadEthernet or |
| 1259 | * a BigMAC. We want the latter. |
| 1260 | */ |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1261 | static int __devinit bigmac_sbus_probe(struct of_device *dev, const struct of_device_id *match) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | { |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1263 | struct sbus_dev *sdev = to_sbus_device(&dev->dev); |
| 1264 | struct device_node *dp = dev->node; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1266 | if (!strcmp(dp->name, "be")) |
| 1267 | sdev = sdev->parent; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1269 | return bigmac_ether_init(sdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1270 | } |
| 1271 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1272 | static int __devexit bigmac_sbus_remove(struct of_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1273 | { |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1274 | struct bigmac *bp = dev_get_drvdata(&dev->dev); |
| 1275 | struct net_device *net_dev = bp->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1277 | unregister_netdevice(net_dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1279 | sbus_iounmap(bp->gregs, GLOB_REG_SIZE); |
| 1280 | sbus_iounmap(bp->creg, CREG_REG_SIZE); |
| 1281 | sbus_iounmap(bp->bregs, BMAC_REG_SIZE); |
| 1282 | sbus_iounmap(bp->tregs, TCVR_REG_SIZE); |
| 1283 | sbus_free_consistent(bp->bigmac_sdev, |
| 1284 | PAGE_SIZE, |
| 1285 | bp->bmac_block, |
| 1286 | bp->bblock_dvma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1288 | free_netdev(net_dev); |
| 1289 | |
| 1290 | dev_set_drvdata(&dev->dev, NULL); |
| 1291 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1292 | return 0; |
| 1293 | } |
| 1294 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1295 | static struct of_device_id bigmac_sbus_match[] = { |
| 1296 | { |
| 1297 | .name = "qec", |
| 1298 | }, |
| 1299 | { |
| 1300 | .name = "be", |
| 1301 | }, |
| 1302 | {}, |
| 1303 | }; |
| 1304 | |
| 1305 | MODULE_DEVICE_TABLE(of, bigmac_sbus_match); |
| 1306 | |
| 1307 | static struct of_platform_driver bigmac_sbus_driver = { |
| 1308 | .name = "sunbmac", |
| 1309 | .match_table = bigmac_sbus_match, |
| 1310 | .probe = bigmac_sbus_probe, |
| 1311 | .remove = __devexit_p(bigmac_sbus_remove), |
| 1312 | }; |
| 1313 | |
| 1314 | static int __init bigmac_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1315 | { |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1316 | return of_register_driver(&bigmac_sbus_driver, &sbus_bus_type); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | } |
| 1318 | |
David S. Miller | 52a34c7 | 2006-06-23 18:48:04 -0700 | [diff] [blame] | 1319 | static void __exit bigmac_exit(void) |
| 1320 | { |
| 1321 | of_unregister_driver(&bigmac_sbus_driver); |
| 1322 | } |
| 1323 | |
| 1324 | module_init(bigmac_init); |
| 1325 | module_exit(bigmac_exit); |