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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Code to handle IP32 IRQs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2001 Keith M Wesolowski
10 */
11#include <linux/init.h>
12#include <linux/kernel_stat.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/bitops.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/mm.h>
20#include <linux/random.h>
21#include <linux/sched.h>
22
23#include <asm/mipsregs.h>
24#include <asm/signal.h>
25#include <asm/system.h>
26#include <asm/time.h>
27#include <asm/ip32/crime.h>
28#include <asm/ip32/mace.h>
29#include <asm/ip32/ip32_ints.h>
30
31/* issue a PIO read to make sure no PIO writes are pending */
32static void inline flush_crime_bus(void)
33{
Ralf Baechleb6d7c7a2006-05-30 02:13:16 +010034 crime->control;
Linus Torvalds1da177e2005-04-16 15:20:36 -070035}
36
37static void inline flush_mace_bus(void)
38{
Ralf Baechleb6d7c7a2006-05-30 02:13:16 +010039 mace->perif.ctrl.misc;
Linus Torvalds1da177e2005-04-16 15:20:36 -070040}
41
42#undef DEBUG_IRQ
43#ifdef DEBUG_IRQ
44#define DBG(x...) printk(x)
45#else
46#define DBG(x...)
47#endif
48
49/* O2 irq map
50 *
51 * IP0 -> software (ignored)
52 * IP1 -> software (ignored)
53 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
54 * IP3 -> (irq1) X unknown
55 * IP4 -> (irq2) X unknown
56 * IP5 -> (irq3) X unknown
57 * IP6 -> (irq4) X unknown
58 * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
59 *
60 * crime: (C)
61 *
62 * CRIME_INT_STAT 31:0:
63 *
64 * 0 -> 1 Video in 1
65 * 1 -> 2 Video in 2
66 * 2 -> 3 Video out
67 * 3 -> 4 Mace ethernet
68 * 4 -> S SuperIO sub-interrupt
69 * 5 -> M Miscellaneous sub-interrupt
70 * 6 -> A Audio sub-interrupt
71 * 7 -> 8 PCI bridge errors
72 * 8 -> 9 PCI SCSI aic7xxx 0
73 * 9 -> 10 PCI SCSI aic7xxx 1
74 * 10 -> 11 PCI slot 0
75 * 11 -> 12 unused (PCI slot 1)
76 * 12 -> 13 unused (PCI slot 2)
77 * 13 -> 14 unused (PCI shared 0)
78 * 14 -> 15 unused (PCI shared 1)
79 * 15 -> 16 unused (PCI shared 2)
80 * 16 -> 17 GBE0 (E)
81 * 17 -> 18 GBE1 (E)
82 * 18 -> 19 GBE2 (E)
83 * 19 -> 20 GBE3 (E)
84 * 20 -> 21 CPU errors
85 * 21 -> 22 Memory errors
86 * 22 -> 23 RE empty edge (E)
87 * 23 -> 24 RE full edge (E)
88 * 24 -> 25 RE idle edge (E)
89 * 25 -> 26 RE empty level
90 * 26 -> 27 RE full level
91 * 27 -> 28 RE idle level
92 * 28 -> 29 unused (software 0) (E)
93 * 29 -> 30 unused (software 1) (E)
94 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
95 * 31 -> 32 VICE
96 *
97 * S, M, A: Use the MACE ISA interrupt register
98 * MACE_ISA_INT_STAT 31:0
99 *
100 * 0-7 -> 33-40 Audio
101 * 8 -> 41 RTC
102 * 9 -> 42 Keyboard
103 * 10 -> X Keyboard polled
104 * 11 -> 44 Mouse
105 * 12 -> X Mouse polled
106 * 13-15 -> 46-48 Count/compare timers
107 * 16-19 -> 49-52 Parallel (16 E)
108 * 20-25 -> 53-58 Serial 1 (22 E)
109 * 26-31 -> 59-64 Serial 2 (28 E)
110 *
111 * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
112 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
113 * is quite different anyway.
114 */
115
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116/* Some initial interrupts to set up */
Ralf Baechle937a8012006-10-07 19:44:33 +0100117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
Thomas Gleixnerf40298f2006-07-01 19:29:20 -0700120struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
Thomas Gleixnerf40298f2006-07-01 19:29:20 -0700122struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
124
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125/*
126 * For interrupts wired from a single device to the CPU. Only the clock
127 * uses this it seems, which is IRQ 0 and IP7.
128 */
129
130static void enable_cpu_irq(unsigned int irq)
131{
132 set_c0_status(STATUSF_IP7);
133}
134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135static void disable_cpu_irq(unsigned int irq)
136{
137 clear_c0_status(STATUSF_IP7);
138}
139
140static void end_cpu_irq(unsigned int irq)
141{
142 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
143 enable_cpu_irq (irq);
144}
145
Ralf Baechle94dee172006-07-02 14:41:42 +0100146static struct irq_chip ip32_cpu_interrupt = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900147 .name = "IP32 CPU",
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900148 .ack = disable_cpu_irq,
149 .mask = disable_cpu_irq,
150 .mask_ack = disable_cpu_irq,
151 .unmask = enable_cpu_irq,
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000152 .end = end_cpu_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153};
154
155/*
156 * This is for pure CRIME interrupts - ie not MACE. The advantage?
157 * We get to split the register in half and do faster lookups.
158 */
159
160static uint64_t crime_mask;
161
162static void enable_crime_irq(unsigned int irq)
163{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 crime_mask |= 1 << (irq - 1);
165 crime->imask = crime_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166}
167
168static void disable_crime_irq(unsigned int irq)
169{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 crime_mask &= ~(1 << (irq - 1));
171 crime->imask = crime_mask;
172 flush_crime_bus();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173}
174
175static void mask_and_ack_crime_irq(unsigned int irq)
176{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 /* Edge triggered interrupts must be cleared. */
178 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
179 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
180 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
181 uint64_t crime_int;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 crime_int = crime->hard_int;
183 crime_int &= ~(1 << (irq - 1));
184 crime->hard_int = crime_int;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 }
186 disable_crime_irq(irq);
187}
188
189static void end_crime_irq(unsigned int irq)
190{
191 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
192 enable_crime_irq(irq);
193}
194
Ralf Baechle94dee172006-07-02 14:41:42 +0100195static struct irq_chip ip32_crime_interrupt = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900196 .name = "IP32 CRIME",
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000197 .ack = mask_and_ack_crime_irq,
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900198 .mask = disable_crime_irq,
199 .mask_ack = mask_and_ack_crime_irq,
200 .unmask = enable_crime_irq,
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000201 .end = end_crime_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202};
203
204/*
205 * This is for MACE PCI interrupts. We can decrease bus traffic by masking
206 * as close to the source as possible. This also means we can take the
207 * next chunk of the CRIME register in one piece.
208 */
209
210static unsigned long macepci_mask;
211
212static void enable_macepci_irq(unsigned int irq)
213{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
215 mace->pci.control = macepci_mask;
216 crime_mask |= 1 << (irq - 1);
217 crime->imask = crime_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218}
219
220static void disable_macepci_irq(unsigned int irq)
221{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 crime_mask &= ~(1 << (irq - 1));
223 crime->imask = crime_mask;
224 flush_crime_bus();
225 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
226 mace->pci.control = macepci_mask;
227 flush_mace_bus();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228}
229
230static void end_macepci_irq(unsigned int irq)
231{
232 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
233 enable_macepci_irq(irq);
234}
235
Ralf Baechle94dee172006-07-02 14:41:42 +0100236static struct irq_chip ip32_macepci_interrupt = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900237 .name = "IP32 MACE PCI",
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900238 .ack = disable_macepci_irq,
239 .mask = disable_macepci_irq,
240 .mask_ack = disable_macepci_irq,
241 .unmask = enable_macepci_irq,
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000242 .end = end_macepci_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243};
244
245/* This is used for MACE ISA interrupts. That means bits 4-6 in the
246 * CRIME register.
247 */
248
249#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \
250 MACEISA_AUDIO_SC_INT | \
251 MACEISA_AUDIO1_DMAT_INT | \
252 MACEISA_AUDIO1_OF_INT | \
253 MACEISA_AUDIO2_DMAT_INT | \
254 MACEISA_AUDIO2_MERR_INT | \
255 MACEISA_AUDIO3_DMAT_INT | \
256 MACEISA_AUDIO3_MERR_INT)
257#define MACEISA_MISC_INT (MACEISA_RTC_INT | \
258 MACEISA_KEYB_INT | \
259 MACEISA_KEYB_POLL_INT | \
260 MACEISA_MOUSE_INT | \
261 MACEISA_MOUSE_POLL_INT | \
Thiemo Seufercfbae5d2006-07-05 18:43:29 +0100262 MACEISA_TIMER0_INT | \
263 MACEISA_TIMER1_INT | \
264 MACEISA_TIMER2_INT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \
266 MACEISA_PAR_CTXA_INT | \
267 MACEISA_PAR_CTXB_INT | \
268 MACEISA_PAR_MERR_INT | \
269 MACEISA_SERIAL1_INT | \
270 MACEISA_SERIAL1_TDMAT_INT | \
271 MACEISA_SERIAL1_TDMAPR_INT | \
272 MACEISA_SERIAL1_TDMAME_INT | \
273 MACEISA_SERIAL1_RDMAT_INT | \
274 MACEISA_SERIAL1_RDMAOR_INT | \
275 MACEISA_SERIAL2_INT | \
276 MACEISA_SERIAL2_TDMAT_INT | \
277 MACEISA_SERIAL2_TDMAPR_INT | \
278 MACEISA_SERIAL2_TDMAME_INT | \
279 MACEISA_SERIAL2_RDMAT_INT | \
280 MACEISA_SERIAL2_RDMAOR_INT)
281
282static unsigned long maceisa_mask;
283
284static void enable_maceisa_irq (unsigned int irq)
285{
286 unsigned int crime_int = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
288 DBG ("maceisa enable: %u\n", irq);
289
290 switch (irq) {
291 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
292 crime_int = MACE_AUDIO_INT;
293 break;
Thiemo Seufercfbae5d2006-07-05 18:43:29 +0100294 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 crime_int = MACE_MISC_INT;
296 break;
297 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
298 crime_int = MACE_SUPERIO_INT;
299 break;
300 }
301 DBG ("crime_int %08x enabled\n", crime_int);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302 crime_mask |= crime_int;
303 crime->imask = crime_mask;
304 maceisa_mask |= 1 << (irq - 33);
305 mace->perif.ctrl.imask = maceisa_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306}
307
308static void disable_maceisa_irq(unsigned int irq)
309{
310 unsigned int crime_int = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 maceisa_mask &= ~(1 << (irq - 33));
313 if(!(maceisa_mask & MACEISA_AUDIO_INT))
314 crime_int |= MACE_AUDIO_INT;
315 if(!(maceisa_mask & MACEISA_MISC_INT))
316 crime_int |= MACE_MISC_INT;
317 if(!(maceisa_mask & MACEISA_SUPERIO_INT))
318 crime_int |= MACE_SUPERIO_INT;
319 crime_mask &= ~crime_int;
320 crime->imask = crime_mask;
321 flush_crime_bus();
322 mace->perif.ctrl.imask = maceisa_mask;
323 flush_mace_bus();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324}
325
326static void mask_and_ack_maceisa_irq(unsigned int irq)
327{
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900328 unsigned long mace_int;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329
330 switch (irq) {
331 case MACEISA_PARALLEL_IRQ:
332 case MACEISA_SERIAL1_TDMAPR_IRQ:
333 case MACEISA_SERIAL2_TDMAPR_IRQ:
334 /* edge triggered */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 mace_int = mace->perif.ctrl.istat;
336 mace_int &= ~(1 << (irq - 33));
337 mace->perif.ctrl.istat = mace_int;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 break;
339 }
340 disable_maceisa_irq(irq);
341}
342
343static void end_maceisa_irq(unsigned irq)
344{
345 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
346 enable_maceisa_irq(irq);
347}
348
Ralf Baechle94dee172006-07-02 14:41:42 +0100349static struct irq_chip ip32_maceisa_interrupt = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900350 .name = "IP32 MACE ISA",
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000351 .ack = mask_and_ack_maceisa_irq,
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900352 .mask = disable_maceisa_irq,
353 .mask_ack = mask_and_ack_maceisa_irq,
354 .unmask = enable_maceisa_irq,
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000355 .end = end_maceisa_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356};
357
358/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
359 * bits 0-3 and 7 in the CRIME register.
360 */
361
362static void enable_mace_irq(unsigned int irq)
363{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 crime_mask |= 1 << (irq - 1);
365 crime->imask = crime_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366}
367
368static void disable_mace_irq(unsigned int irq)
369{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 crime_mask &= ~(1 << (irq - 1));
371 crime->imask = crime_mask;
372 flush_crime_bus();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373}
374
375static void end_mace_irq(unsigned int irq)
376{
377 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
378 enable_mace_irq(irq);
379}
380
Ralf Baechle94dee172006-07-02 14:41:42 +0100381static struct irq_chip ip32_mace_interrupt = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900382 .name = "IP32 MACE",
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900383 .ack = disable_mace_irq,
384 .mask = disable_mace_irq,
385 .mask_ack = disable_mace_irq,
386 .unmask = enable_mace_irq,
Ralf Baechle8ab00b92005-02-28 13:39:57 +0000387 .end = end_mace_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388};
389
Ralf Baechle937a8012006-10-07 19:44:33 +0100390static void ip32_unknown_interrupt(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391{
392 printk ("Unknown interrupt occurred!\n");
393 printk ("cp0_status: %08x\n", read_c0_status());
394 printk ("cp0_cause: %08x\n", read_c0_cause());
395 printk ("CRIME intr mask: %016lx\n", crime->imask);
396 printk ("CRIME intr status: %016lx\n", crime->istat);
397 printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
398 printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
399 printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
400 printk ("MACE PCI control register: %08x\n", mace->pci.control);
401
402 printk("Register dump:\n");
Ralf Baechle937a8012006-10-07 19:44:33 +0100403 show_regs(get_irq_regs());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
405 printk("Please mail this report to linux-mips@linux-mips.org\n");
406 printk("Spinning...");
407 while(1) ;
408}
409
410/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
411/* change this to loop over all edge-triggered irqs, exception masked out ones */
Ralf Baechle937a8012006-10-07 19:44:33 +0100412static void ip32_irq0(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413{
414 uint64_t crime_int;
415 int irq = 0;
416
417 crime_int = crime->istat & crime_mask;
Atsushi Nemoto6f8782c2006-04-17 21:24:49 +0900418 irq = __ffs(crime_int);
419 crime_int = 1 << irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421 if (crime_int & CRIME_MACEISA_INT_MASK) {
422 unsigned long mace_int = mace->perif.ctrl.istat;
Atsushi Nemoto6f8782c2006-04-17 21:24:49 +0900423 irq = __ffs(mace_int & maceisa_mask) + 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 }
Atsushi Nemoto6f8782c2006-04-17 21:24:49 +0900425 irq++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 DBG("*irq %u*\n", irq);
Ralf Baechle937a8012006-10-07 19:44:33 +0100427 do_IRQ(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428}
429
Ralf Baechle937a8012006-10-07 19:44:33 +0100430static void ip32_irq1(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431{
Ralf Baechle937a8012006-10-07 19:44:33 +0100432 ip32_unknown_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433}
434
Ralf Baechle937a8012006-10-07 19:44:33 +0100435static void ip32_irq2(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436{
Ralf Baechle937a8012006-10-07 19:44:33 +0100437 ip32_unknown_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438}
439
Ralf Baechle937a8012006-10-07 19:44:33 +0100440static void ip32_irq3(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441{
Ralf Baechle937a8012006-10-07 19:44:33 +0100442 ip32_unknown_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443}
444
Ralf Baechle937a8012006-10-07 19:44:33 +0100445static void ip32_irq4(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446{
Ralf Baechle937a8012006-10-07 19:44:33 +0100447 ip32_unknown_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448}
449
Ralf Baechle937a8012006-10-07 19:44:33 +0100450static void ip32_irq5(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451{
Ralf Baechle937a8012006-10-07 19:44:33 +0100452 ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453}
454
Ralf Baechle937a8012006-10-07 19:44:33 +0100455asmlinkage void plat_irq_dispatch(void)
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100456{
Thiemo Seufer119537c2007-03-19 00:13:37 +0000457 unsigned int pending = read_c0_status() & read_c0_cause();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100458
459 if (likely(pending & IE_IRQ0))
Ralf Baechle937a8012006-10-07 19:44:33 +0100460 ip32_irq0();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100461 else if (unlikely(pending & IE_IRQ1))
Ralf Baechle937a8012006-10-07 19:44:33 +0100462 ip32_irq1();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100463 else if (unlikely(pending & IE_IRQ2))
Ralf Baechle937a8012006-10-07 19:44:33 +0100464 ip32_irq2();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100465 else if (unlikely(pending & IE_IRQ3))
Ralf Baechle937a8012006-10-07 19:44:33 +0100466 ip32_irq3();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100467 else if (unlikely(pending & IE_IRQ4))
Ralf Baechle937a8012006-10-07 19:44:33 +0100468 ip32_irq4();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100469 else if (likely(pending & IE_IRQ5))
Ralf Baechle937a8012006-10-07 19:44:33 +0100470 ip32_irq5();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100471}
472
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473void __init arch_init_irq(void)
474{
475 unsigned int irq;
476
477 /* Install our interrupt handler, then clear and disable all
478 * CRIME and MACE interrupts. */
479 crime->imask = 0;
480 crime->hard_int = 0;
481 crime->soft_int = 0;
482 mace->perif.ctrl.istat = 0;
483 mace->perif.ctrl.imask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484
485 for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
Ralf Baechle94dee172006-07-02 14:41:42 +0100486 struct irq_chip *controller;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487
488 if (irq == IP32_R4K_TIMER_IRQ)
489 controller = &ip32_cpu_interrupt;
490 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
491 controller = &ip32_mace_interrupt;
492 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
493 controller = &ip32_macepci_interrupt;
494 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
495 controller = &ip32_crime_interrupt;
496 else
497 controller = &ip32_maceisa_interrupt;
498
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900499 set_irq_chip(irq, controller);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 }
501 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
502 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
503
504#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
505 change_c0_status(ST0_IM, ALLINTS);
506}