Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1 | /* |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 2 | * PCIe host controller driver for Tegra SoCs |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2010, CompuLab, Ltd. |
| 5 | * Author: Mike Rapoport <mike@compulab.co.il> |
| 6 | * |
| 7 | * Based on NVIDIA PCIe driver |
| 8 | * Copyright (c) 2008-2009, NVIDIA Corporation. |
| 9 | * |
| 10 | * Bits taken from arch/arm/mach-dove/pcie.c |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 18 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 20 | * more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License along |
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 24 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 25 | */ |
| 26 | |
| 27 | #include <linux/clk.h> |
Thierry Reding | 2cb989f | 2014-07-22 12:30:46 -0600 | [diff] [blame] | 28 | #include <linux/debugfs.h> |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 29 | #include <linux/delay.h> |
| 30 | #include <linux/export.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/irq.h> |
| 33 | #include <linux/irqdomain.h> |
| 34 | #include <linux/kernel.h> |
| 35 | #include <linux/module.h> |
| 36 | #include <linux/msi.h> |
| 37 | #include <linux/of_address.h> |
| 38 | #include <linux/of_pci.h> |
| 39 | #include <linux/of_platform.h> |
| 40 | #include <linux/pci.h> |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 41 | #include <linux/phy/phy.h> |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 42 | #include <linux/platform_device.h> |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 43 | #include <linux/reset.h> |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 44 | #include <linux/sizes.h> |
| 45 | #include <linux/slab.h> |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 46 | #include <linux/vmalloc.h> |
| 47 | #include <linux/regulator/consumer.h> |
| 48 | |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 49 | #include <soc/tegra/cpuidle.h> |
Thierry Reding | 7232398 | 2014-07-11 13:19:06 +0200 | [diff] [blame] | 50 | #include <soc/tegra/pmc.h> |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 51 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 52 | #include <asm/mach/irq.h> |
| 53 | #include <asm/mach/map.h> |
| 54 | #include <asm/mach/pci.h> |
| 55 | |
| 56 | #define INT_PCI_MSI_NR (8 * 32) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 57 | |
| 58 | /* register definitions */ |
| 59 | |
| 60 | #define AFI_AXI_BAR0_SZ 0x00 |
| 61 | #define AFI_AXI_BAR1_SZ 0x04 |
| 62 | #define AFI_AXI_BAR2_SZ 0x08 |
| 63 | #define AFI_AXI_BAR3_SZ 0x0c |
| 64 | #define AFI_AXI_BAR4_SZ 0x10 |
| 65 | #define AFI_AXI_BAR5_SZ 0x14 |
| 66 | |
| 67 | #define AFI_AXI_BAR0_START 0x18 |
| 68 | #define AFI_AXI_BAR1_START 0x1c |
| 69 | #define AFI_AXI_BAR2_START 0x20 |
| 70 | #define AFI_AXI_BAR3_START 0x24 |
| 71 | #define AFI_AXI_BAR4_START 0x28 |
| 72 | #define AFI_AXI_BAR5_START 0x2c |
| 73 | |
| 74 | #define AFI_FPCI_BAR0 0x30 |
| 75 | #define AFI_FPCI_BAR1 0x34 |
| 76 | #define AFI_FPCI_BAR2 0x38 |
| 77 | #define AFI_FPCI_BAR3 0x3c |
| 78 | #define AFI_FPCI_BAR4 0x40 |
| 79 | #define AFI_FPCI_BAR5 0x44 |
| 80 | |
| 81 | #define AFI_CACHE_BAR0_SZ 0x48 |
| 82 | #define AFI_CACHE_BAR0_ST 0x4c |
| 83 | #define AFI_CACHE_BAR1_SZ 0x50 |
| 84 | #define AFI_CACHE_BAR1_ST 0x54 |
| 85 | |
| 86 | #define AFI_MSI_BAR_SZ 0x60 |
| 87 | #define AFI_MSI_FPCI_BAR_ST 0x64 |
| 88 | #define AFI_MSI_AXI_BAR_ST 0x68 |
| 89 | |
| 90 | #define AFI_MSI_VEC0 0x6c |
| 91 | #define AFI_MSI_VEC1 0x70 |
| 92 | #define AFI_MSI_VEC2 0x74 |
| 93 | #define AFI_MSI_VEC3 0x78 |
| 94 | #define AFI_MSI_VEC4 0x7c |
| 95 | #define AFI_MSI_VEC5 0x80 |
| 96 | #define AFI_MSI_VEC6 0x84 |
| 97 | #define AFI_MSI_VEC7 0x88 |
| 98 | |
| 99 | #define AFI_MSI_EN_VEC0 0x8c |
| 100 | #define AFI_MSI_EN_VEC1 0x90 |
| 101 | #define AFI_MSI_EN_VEC2 0x94 |
| 102 | #define AFI_MSI_EN_VEC3 0x98 |
| 103 | #define AFI_MSI_EN_VEC4 0x9c |
| 104 | #define AFI_MSI_EN_VEC5 0xa0 |
| 105 | #define AFI_MSI_EN_VEC6 0xa4 |
| 106 | #define AFI_MSI_EN_VEC7 0xa8 |
| 107 | |
| 108 | #define AFI_CONFIGURATION 0xac |
| 109 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) |
| 110 | |
| 111 | #define AFI_FPCI_ERROR_MASKS 0xb0 |
| 112 | |
| 113 | #define AFI_INTR_MASK 0xb4 |
| 114 | #define AFI_INTR_MASK_INT_MASK (1 << 0) |
| 115 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) |
| 116 | |
| 117 | #define AFI_INTR_CODE 0xb8 |
| 118 | #define AFI_INTR_CODE_MASK 0xf |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 119 | #define AFI_INTR_INI_SLAVE_ERROR 1 |
| 120 | #define AFI_INTR_INI_DECODE_ERROR 2 |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 121 | #define AFI_INTR_TARGET_ABORT 3 |
| 122 | #define AFI_INTR_MASTER_ABORT 4 |
| 123 | #define AFI_INTR_INVALID_WRITE 5 |
| 124 | #define AFI_INTR_LEGACY 6 |
| 125 | #define AFI_INTR_FPCI_DECODE_ERROR 7 |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 126 | #define AFI_INTR_AXI_DECODE_ERROR 8 |
| 127 | #define AFI_INTR_FPCI_TIMEOUT 9 |
| 128 | #define AFI_INTR_PE_PRSNT_SENSE 10 |
| 129 | #define AFI_INTR_PE_CLKREQ_SENSE 11 |
| 130 | #define AFI_INTR_CLKCLAMP_SENSE 12 |
| 131 | #define AFI_INTR_RDY4PD_SENSE 13 |
| 132 | #define AFI_INTR_P2P_ERROR 14 |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 133 | |
| 134 | #define AFI_INTR_SIGNATURE 0xbc |
| 135 | #define AFI_UPPER_FPCI_ADDRESS 0xc0 |
| 136 | #define AFI_SM_INTR_ENABLE 0xc4 |
| 137 | #define AFI_SM_INTR_INTA_ASSERT (1 << 0) |
| 138 | #define AFI_SM_INTR_INTB_ASSERT (1 << 1) |
| 139 | #define AFI_SM_INTR_INTC_ASSERT (1 << 2) |
| 140 | #define AFI_SM_INTR_INTD_ASSERT (1 << 3) |
| 141 | #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) |
| 142 | #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) |
| 143 | #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) |
| 144 | #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) |
| 145 | |
| 146 | #define AFI_AFI_INTR_ENABLE 0xc8 |
| 147 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) |
| 148 | #define AFI_INTR_EN_INI_DECERR (1 << 1) |
| 149 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) |
| 150 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) |
| 151 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) |
| 152 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) |
| 153 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) |
| 154 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 155 | #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 156 | |
| 157 | #define AFI_PCIE_CONFIG 0x0f8 |
| 158 | #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) |
| 159 | #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe |
| 160 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) |
| 161 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 162 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 163 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 164 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 165 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 166 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 167 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 168 | |
| 169 | #define AFI_FUSE 0x104 |
| 170 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) |
| 171 | |
| 172 | #define AFI_PEX0_CTRL 0x110 |
| 173 | #define AFI_PEX1_CTRL 0x118 |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 174 | #define AFI_PEX2_CTRL 0x128 |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 175 | #define AFI_PEX_CTRL_RST (1 << 0) |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 176 | #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 177 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 178 | #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) |
| 179 | |
| 180 | #define AFI_PLLE_CONTROL 0x160 |
| 181 | #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) |
| 182 | #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 183 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 184 | #define AFI_PEXBIAS_CTRL_0 0x168 |
| 185 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 186 | #define RP_VEND_XP 0x00000F00 |
| 187 | #define RP_VEND_XP_DL_UP (1 << 30) |
| 188 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 189 | #define RP_PRIV_MISC 0x00000FE0 |
| 190 | #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) |
| 191 | #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) |
| 192 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 193 | #define RP_LINK_CONTROL_STATUS 0x00000090 |
| 194 | #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 |
| 195 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 |
| 196 | |
| 197 | #define PADS_CTL_SEL 0x0000009C |
| 198 | |
| 199 | #define PADS_CTL 0x000000A0 |
| 200 | #define PADS_CTL_IDDQ_1L (1 << 0) |
| 201 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) |
| 202 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) |
| 203 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 204 | #define PADS_PLL_CTL_TEGRA20 0x000000B8 |
| 205 | #define PADS_PLL_CTL_TEGRA30 0x000000B4 |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 206 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) |
| 207 | #define PADS_PLL_CTL_LOCKDET (1 << 8) |
| 208 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) |
| 209 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) |
| 210 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) |
| 211 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) |
| 212 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) |
| 213 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) |
| 214 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 215 | #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) |
| 216 | |
| 217 | #define PADS_REFCLK_CFG0 0x000000C8 |
| 218 | #define PADS_REFCLK_CFG1 0x000000CC |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 219 | #define PADS_REFCLK_BIAS 0x000000D0 |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 220 | |
Stephen Warren | b02b07a | 2013-08-09 16:49:25 +0200 | [diff] [blame] | 221 | /* |
| 222 | * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit |
| 223 | * entries, one entry per PCIe port. These field definitions and desired |
| 224 | * values aren't in the TRM, but do come from NVIDIA. |
| 225 | */ |
| 226 | #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ |
| 227 | #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 |
| 228 | #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ |
| 229 | #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ |
| 230 | |
| 231 | /* Default value provided by HW engineering is 0xfa5c */ |
| 232 | #define PADS_REFCLK_CFG_VALUE \ |
| 233 | ( \ |
| 234 | (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ |
| 235 | (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ |
| 236 | (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ |
| 237 | (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ |
| 238 | ) |
| 239 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 240 | struct tegra_msi { |
| 241 | struct msi_chip chip; |
| 242 | DECLARE_BITMAP(used, INT_PCI_MSI_NR); |
| 243 | struct irq_domain *domain; |
| 244 | unsigned long pages; |
| 245 | struct mutex lock; |
| 246 | int irq; |
| 247 | }; |
| 248 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 249 | /* used to differentiate between Tegra SoC generations */ |
| 250 | struct tegra_pcie_soc_data { |
| 251 | unsigned int num_ports; |
| 252 | unsigned int msi_base_shift; |
| 253 | u32 pads_pll_ctl; |
| 254 | u32 tx_ref_sel; |
| 255 | bool has_pex_clkreq_en; |
| 256 | bool has_pex_bias_ctrl; |
| 257 | bool has_intr_prsnt_sense; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 258 | bool has_cml_clk; |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 259 | bool has_gen2; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 260 | }; |
| 261 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 262 | static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip) |
| 263 | { |
| 264 | return container_of(chip, struct tegra_msi, chip); |
| 265 | } |
| 266 | |
| 267 | struct tegra_pcie { |
| 268 | struct device *dev; |
| 269 | |
| 270 | void __iomem *pads; |
| 271 | void __iomem *afi; |
| 272 | int irq; |
| 273 | |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 274 | struct list_head buses; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 275 | struct resource *cs; |
| 276 | |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 277 | struct resource all; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 278 | struct resource io; |
| 279 | struct resource mem; |
| 280 | struct resource prefetch; |
| 281 | struct resource busn; |
| 282 | |
| 283 | struct clk *pex_clk; |
| 284 | struct clk *afi_clk; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 285 | struct clk *pll_e; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 286 | struct clk *cml_clk; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 287 | |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 288 | struct reset_control *pex_rst; |
| 289 | struct reset_control *afi_rst; |
| 290 | struct reset_control *pcie_xrst; |
| 291 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 292 | struct phy *phy; |
| 293 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 294 | struct tegra_msi msi; |
| 295 | |
| 296 | struct list_head ports; |
| 297 | unsigned int num_ports; |
| 298 | u32 xbar_config; |
| 299 | |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 300 | struct regulator_bulk_data *supplies; |
| 301 | unsigned int num_supplies; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 302 | |
| 303 | const struct tegra_pcie_soc_data *soc_data; |
Thierry Reding | 2cb989f | 2014-07-22 12:30:46 -0600 | [diff] [blame] | 304 | struct dentry *debugfs; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 305 | }; |
| 306 | |
| 307 | struct tegra_pcie_port { |
| 308 | struct tegra_pcie *pcie; |
| 309 | struct list_head list; |
| 310 | struct resource regs; |
| 311 | void __iomem *base; |
| 312 | unsigned int index; |
| 313 | unsigned int lanes; |
| 314 | }; |
| 315 | |
| 316 | struct tegra_pcie_bus { |
| 317 | struct vm_struct *area; |
| 318 | struct list_head list; |
| 319 | unsigned int nr; |
| 320 | }; |
| 321 | |
| 322 | static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys) |
| 323 | { |
| 324 | return sys->private_data; |
| 325 | } |
| 326 | |
| 327 | static inline void afi_writel(struct tegra_pcie *pcie, u32 value, |
| 328 | unsigned long offset) |
| 329 | { |
| 330 | writel(value, pcie->afi + offset); |
| 331 | } |
| 332 | |
| 333 | static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) |
| 334 | { |
| 335 | return readl(pcie->afi + offset); |
| 336 | } |
| 337 | |
| 338 | static inline void pads_writel(struct tegra_pcie *pcie, u32 value, |
| 339 | unsigned long offset) |
| 340 | { |
| 341 | writel(value, pcie->pads + offset); |
| 342 | } |
| 343 | |
| 344 | static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) |
| 345 | { |
| 346 | return readl(pcie->pads + offset); |
| 347 | } |
| 348 | |
| 349 | /* |
| 350 | * The configuration space mapping on Tegra is somewhat similar to the ECAM |
| 351 | * defined by PCIe. However it deviates a bit in how the 4 bits for extended |
| 352 | * register accesses are mapped: |
| 353 | * |
| 354 | * [27:24] extended register number |
| 355 | * [23:16] bus number |
| 356 | * [15:11] device number |
| 357 | * [10: 8] function number |
| 358 | * [ 7: 0] register number |
| 359 | * |
| 360 | * Mapping the whole extended configuration space would require 256 MiB of |
| 361 | * virtual address space, only a small part of which will actually be used. |
| 362 | * To work around this, a 1 MiB of virtual addresses are allocated per bus |
| 363 | * when the bus is first accessed. When the physical range is mapped, the |
| 364 | * the bus number bits are hidden so that the extended register number bits |
| 365 | * appear as bits [19:16]. Therefore the virtual mapping looks like this: |
| 366 | * |
| 367 | * [19:16] extended register number |
| 368 | * [15:11] device number |
| 369 | * [10: 8] function number |
| 370 | * [ 7: 0] register number |
| 371 | * |
| 372 | * This is achieved by stitching together 16 chunks of 64 KiB of physical |
| 373 | * address space via the MMU. |
| 374 | */ |
| 375 | static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where) |
| 376 | { |
| 377 | return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) | |
| 378 | (PCI_FUNC(devfn) << 8) | (where & 0xfc); |
| 379 | } |
| 380 | |
| 381 | static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, |
| 382 | unsigned int busnr) |
| 383 | { |
| 384 | pgprot_t prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN | |
| 385 | L_PTE_MT_DEV_SHARED | L_PTE_SHARED; |
| 386 | phys_addr_t cs = pcie->cs->start; |
| 387 | struct tegra_pcie_bus *bus; |
| 388 | unsigned int i; |
| 389 | int err; |
| 390 | |
| 391 | bus = kzalloc(sizeof(*bus), GFP_KERNEL); |
| 392 | if (!bus) |
| 393 | return ERR_PTR(-ENOMEM); |
| 394 | |
| 395 | INIT_LIST_HEAD(&bus->list); |
| 396 | bus->nr = busnr; |
| 397 | |
| 398 | /* allocate 1 MiB of virtual addresses */ |
| 399 | bus->area = get_vm_area(SZ_1M, VM_IOREMAP); |
| 400 | if (!bus->area) { |
| 401 | err = -ENOMEM; |
| 402 | goto free; |
| 403 | } |
| 404 | |
| 405 | /* map each of the 16 chunks of 64 KiB each */ |
| 406 | for (i = 0; i < 16; i++) { |
| 407 | unsigned long virt = (unsigned long)bus->area->addr + |
| 408 | i * SZ_64K; |
Peter Daifuku | 8d41794 | 2014-08-26 17:11:36 +0200 | [diff] [blame] | 409 | phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 410 | |
| 411 | err = ioremap_page_range(virt, virt + SZ_64K, phys, prot); |
| 412 | if (err < 0) { |
| 413 | dev_err(pcie->dev, "ioremap_page_range() failed: %d\n", |
| 414 | err); |
| 415 | goto unmap; |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | return bus; |
| 420 | |
| 421 | unmap: |
| 422 | vunmap(bus->area->addr); |
| 423 | free: |
| 424 | kfree(bus); |
| 425 | return ERR_PTR(err); |
| 426 | } |
| 427 | |
| 428 | /* |
| 429 | * Look up a virtual address mapping for the specified bus number. If no such |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 430 | * mapping exists, try to create one. |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 431 | */ |
| 432 | static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie, |
| 433 | unsigned int busnr) |
| 434 | { |
| 435 | struct tegra_pcie_bus *bus; |
| 436 | |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 437 | list_for_each_entry(bus, &pcie->buses, list) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 438 | if (bus->nr == busnr) |
Jingoo Han | 1e65249 | 2013-09-25 16:40:54 -0600 | [diff] [blame] | 439 | return (void __iomem *)bus->area->addr; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 440 | |
| 441 | bus = tegra_pcie_bus_alloc(pcie, busnr); |
| 442 | if (IS_ERR(bus)) |
| 443 | return NULL; |
| 444 | |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 445 | list_add_tail(&bus->list, &pcie->buses); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 446 | |
Jingoo Han | 1e65249 | 2013-09-25 16:40:54 -0600 | [diff] [blame] | 447 | return (void __iomem *)bus->area->addr; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus, |
| 451 | unsigned int devfn, |
| 452 | int where) |
| 453 | { |
| 454 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); |
| 455 | void __iomem *addr = NULL; |
| 456 | |
| 457 | if (bus->number == 0) { |
| 458 | unsigned int slot = PCI_SLOT(devfn); |
| 459 | struct tegra_pcie_port *port; |
| 460 | |
| 461 | list_for_each_entry(port, &pcie->ports, list) { |
| 462 | if (port->index + 1 == slot) { |
| 463 | addr = port->base + (where & ~3); |
| 464 | break; |
| 465 | } |
| 466 | } |
| 467 | } else { |
| 468 | addr = tegra_pcie_bus_map(pcie, bus->number); |
| 469 | if (!addr) { |
| 470 | dev_err(pcie->dev, |
| 471 | "failed to map cfg. space for bus %u\n", |
| 472 | bus->number); |
| 473 | return NULL; |
| 474 | } |
| 475 | |
| 476 | addr += tegra_pcie_conf_offset(devfn, where); |
| 477 | } |
| 478 | |
| 479 | return addr; |
| 480 | } |
| 481 | |
| 482 | static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, |
| 483 | int where, int size, u32 *value) |
| 484 | { |
| 485 | void __iomem *addr; |
| 486 | |
| 487 | addr = tegra_pcie_conf_address(bus, devfn, where); |
| 488 | if (!addr) { |
| 489 | *value = 0xffffffff; |
| 490 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 491 | } |
| 492 | |
| 493 | *value = readl(addr); |
| 494 | |
| 495 | if (size == 1) |
| 496 | *value = (*value >> (8 * (where & 3))) & 0xff; |
| 497 | else if (size == 2) |
| 498 | *value = (*value >> (8 * (where & 3))) & 0xffff; |
| 499 | |
| 500 | return PCIBIOS_SUCCESSFUL; |
| 501 | } |
| 502 | |
| 503 | static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, |
| 504 | int where, int size, u32 value) |
| 505 | { |
| 506 | void __iomem *addr; |
| 507 | u32 mask, tmp; |
| 508 | |
| 509 | addr = tegra_pcie_conf_address(bus, devfn, where); |
| 510 | if (!addr) |
| 511 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 512 | |
| 513 | if (size == 4) { |
| 514 | writel(value, addr); |
| 515 | return PCIBIOS_SUCCESSFUL; |
| 516 | } |
| 517 | |
| 518 | if (size == 2) |
| 519 | mask = ~(0xffff << ((where & 0x3) * 8)); |
| 520 | else if (size == 1) |
| 521 | mask = ~(0xff << ((where & 0x3) * 8)); |
| 522 | else |
| 523 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 524 | |
| 525 | tmp = readl(addr) & mask; |
| 526 | tmp |= value << ((where & 0x3) * 8); |
| 527 | writel(tmp, addr); |
| 528 | |
| 529 | return PCIBIOS_SUCCESSFUL; |
| 530 | } |
| 531 | |
| 532 | static struct pci_ops tegra_pcie_ops = { |
| 533 | .read = tegra_pcie_read_conf, |
| 534 | .write = tegra_pcie_write_conf, |
| 535 | }; |
| 536 | |
| 537 | static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) |
| 538 | { |
| 539 | unsigned long ret = 0; |
| 540 | |
| 541 | switch (port->index) { |
| 542 | case 0: |
| 543 | ret = AFI_PEX0_CTRL; |
| 544 | break; |
| 545 | |
| 546 | case 1: |
| 547 | ret = AFI_PEX1_CTRL; |
| 548 | break; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 549 | |
| 550 | case 2: |
| 551 | ret = AFI_PEX2_CTRL; |
| 552 | break; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | return ret; |
| 556 | } |
| 557 | |
| 558 | static void tegra_pcie_port_reset(struct tegra_pcie_port *port) |
| 559 | { |
| 560 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
| 561 | unsigned long value; |
| 562 | |
| 563 | /* pulse reset signal */ |
| 564 | value = afi_readl(port->pcie, ctrl); |
| 565 | value &= ~AFI_PEX_CTRL_RST; |
| 566 | afi_writel(port->pcie, value, ctrl); |
| 567 | |
| 568 | usleep_range(1000, 2000); |
| 569 | |
| 570 | value = afi_readl(port->pcie, ctrl); |
| 571 | value |= AFI_PEX_CTRL_RST; |
| 572 | afi_writel(port->pcie, value, ctrl); |
| 573 | } |
| 574 | |
| 575 | static void tegra_pcie_port_enable(struct tegra_pcie_port *port) |
| 576 | { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 577 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 578 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
| 579 | unsigned long value; |
| 580 | |
| 581 | /* enable reference clock */ |
| 582 | value = afi_readl(port->pcie, ctrl); |
| 583 | value |= AFI_PEX_CTRL_REFCLK_EN; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 584 | |
| 585 | if (soc->has_pex_clkreq_en) |
| 586 | value |= AFI_PEX_CTRL_CLKREQ_EN; |
| 587 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 588 | value |= AFI_PEX_CTRL_OVERRIDE_EN; |
| 589 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 590 | afi_writel(port->pcie, value, ctrl); |
| 591 | |
| 592 | tegra_pcie_port_reset(port); |
| 593 | } |
| 594 | |
| 595 | static void tegra_pcie_port_disable(struct tegra_pcie_port *port) |
| 596 | { |
Thierry Reding | 0d20d62 | 2014-08-26 17:11:35 +0200 | [diff] [blame] | 597 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 598 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
| 599 | unsigned long value; |
| 600 | |
| 601 | /* assert port reset */ |
| 602 | value = afi_readl(port->pcie, ctrl); |
| 603 | value &= ~AFI_PEX_CTRL_RST; |
| 604 | afi_writel(port->pcie, value, ctrl); |
| 605 | |
| 606 | /* disable reference clock */ |
| 607 | value = afi_readl(port->pcie, ctrl); |
Thierry Reding | 0d20d62 | 2014-08-26 17:11:35 +0200 | [diff] [blame] | 608 | |
| 609 | if (soc->has_pex_clkreq_en) |
| 610 | value &= ~AFI_PEX_CTRL_CLKREQ_EN; |
| 611 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 612 | value &= ~AFI_PEX_CTRL_REFCLK_EN; |
| 613 | afi_writel(port->pcie, value, ctrl); |
| 614 | } |
| 615 | |
| 616 | static void tegra_pcie_port_free(struct tegra_pcie_port *port) |
| 617 | { |
| 618 | struct tegra_pcie *pcie = port->pcie; |
| 619 | |
| 620 | devm_iounmap(pcie->dev, port->base); |
| 621 | devm_release_mem_region(pcie->dev, port->regs.start, |
| 622 | resource_size(&port->regs)); |
| 623 | list_del(&port->list); |
| 624 | devm_kfree(pcie->dev, port); |
| 625 | } |
| 626 | |
| 627 | static void tegra_pcie_fixup_bridge(struct pci_dev *dev) |
| 628 | { |
| 629 | u16 reg; |
| 630 | |
| 631 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { |
| 632 | pci_read_config_word(dev, PCI_COMMAND, ®); |
| 633 | reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 634 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); |
| 635 | pci_write_config_word(dev, PCI_COMMAND, reg); |
| 636 | } |
| 637 | } |
| 638 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); |
| 639 | |
| 640 | /* Tegra PCIE root complex wrongly reports device class */ |
| 641 | static void tegra_pcie_fixup_class(struct pci_dev *dev) |
| 642 | { |
| 643 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
| 644 | } |
| 645 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); |
| 646 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 647 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class); |
| 648 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 649 | |
| 650 | /* Tegra PCIE requires relaxed ordering */ |
| 651 | static void tegra_pcie_relax_enable(struct pci_dev *dev) |
| 652 | { |
| 653 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); |
| 654 | } |
| 655 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); |
| 656 | |
| 657 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) |
| 658 | { |
| 659 | struct tegra_pcie *pcie = sys_to_pcie(sys); |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 660 | int err; |
| 661 | |
| 662 | err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem); |
| 663 | if (err < 0) |
| 664 | return err; |
| 665 | |
| 666 | err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch); |
| 667 | if (err) |
| 668 | return err; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 669 | |
| 670 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); |
| 671 | pci_add_resource_offset(&sys->resources, &pcie->prefetch, |
| 672 | sys->mem_offset); |
| 673 | pci_add_resource(&sys->resources, &pcie->busn); |
| 674 | |
| 675 | pci_ioremap_io(nr * SZ_64K, pcie->io.start); |
| 676 | |
| 677 | return 1; |
| 678 | } |
| 679 | |
| 680 | static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) |
| 681 | { |
| 682 | struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata); |
Lucas Stach | f5d3352 | 2014-04-16 10:24:32 -0600 | [diff] [blame] | 683 | int irq; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 684 | |
Stephen Warren | b4f1737 | 2013-05-06 14:19:19 -0600 | [diff] [blame] | 685 | tegra_cpuidle_pcie_irqs_in_use(); |
| 686 | |
Lucas Stach | f5d3352 | 2014-04-16 10:24:32 -0600 | [diff] [blame] | 687 | irq = of_irq_parse_and_map_pci(pdev, slot, pin); |
| 688 | if (!irq) |
| 689 | irq = pcie->irq; |
| 690 | |
| 691 | return irq; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | static void tegra_pcie_add_bus(struct pci_bus *bus) |
| 695 | { |
| 696 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| 697 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); |
| 698 | |
| 699 | bus->msi = &pcie->msi.chip; |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys) |
| 704 | { |
| 705 | struct tegra_pcie *pcie = sys_to_pcie(sys); |
| 706 | struct pci_bus *bus; |
| 707 | |
| 708 | bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys, |
| 709 | &sys->resources); |
| 710 | if (!bus) |
| 711 | return NULL; |
| 712 | |
| 713 | pci_scan_child_bus(bus); |
| 714 | |
| 715 | return bus; |
| 716 | } |
| 717 | |
| 718 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) |
| 719 | { |
| 720 | const char *err_msg[] = { |
| 721 | "Unknown", |
| 722 | "AXI slave error", |
| 723 | "AXI decode error", |
| 724 | "Target abort", |
| 725 | "Master abort", |
| 726 | "Invalid write", |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 727 | "Legacy interrupt", |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 728 | "Response decoding error", |
| 729 | "AXI response decoding error", |
| 730 | "Transaction timeout", |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 731 | "Slot present pin change", |
| 732 | "Slot clock request change", |
| 733 | "TMS clock ramp change", |
| 734 | "TMS ready for power down", |
| 735 | "Peer2Peer error", |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 736 | }; |
| 737 | struct tegra_pcie *pcie = arg; |
| 738 | u32 code, signature; |
| 739 | |
| 740 | code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; |
| 741 | signature = afi_readl(pcie, AFI_INTR_SIGNATURE); |
| 742 | afi_writel(pcie, 0, AFI_INTR_CODE); |
| 743 | |
| 744 | if (code == AFI_INTR_LEGACY) |
| 745 | return IRQ_NONE; |
| 746 | |
| 747 | if (code >= ARRAY_SIZE(err_msg)) |
| 748 | code = 0; |
| 749 | |
| 750 | /* |
| 751 | * do not pollute kernel log with master abort reports since they |
| 752 | * happen a lot during enumeration |
| 753 | */ |
| 754 | if (code == AFI_INTR_MASTER_ABORT) |
| 755 | dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code], |
| 756 | signature); |
| 757 | else |
| 758 | dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code], |
| 759 | signature); |
| 760 | |
| 761 | if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT || |
| 762 | code == AFI_INTR_FPCI_DECODE_ERROR) { |
| 763 | u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff; |
| 764 | u64 address = (u64)fpci << 32 | (signature & 0xfffffffc); |
| 765 | |
| 766 | if (code == AFI_INTR_MASTER_ABORT) |
| 767 | dev_dbg(pcie->dev, " FPCI address: %10llx\n", address); |
| 768 | else |
| 769 | dev_err(pcie->dev, " FPCI address: %10llx\n", address); |
| 770 | } |
| 771 | |
| 772 | return IRQ_HANDLED; |
| 773 | } |
| 774 | |
| 775 | /* |
| 776 | * FPCI map is as follows: |
| 777 | * - 0xfdfc000000: I/O space |
| 778 | * - 0xfdfe000000: type 0 configuration space |
| 779 | * - 0xfdff000000: type 1 configuration space |
| 780 | * - 0xfe00000000: type 0 extended configuration space |
| 781 | * - 0xfe10000000: type 1 extended configuration space |
| 782 | */ |
| 783 | static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) |
| 784 | { |
| 785 | u32 fpci_bar, size, axi_address; |
| 786 | |
| 787 | /* Bar 0: type 1 extended configuration space */ |
| 788 | fpci_bar = 0xfe100000; |
| 789 | size = resource_size(pcie->cs); |
| 790 | axi_address = pcie->cs->start; |
| 791 | afi_writel(pcie, axi_address, AFI_AXI_BAR0_START); |
| 792 | afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); |
| 793 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0); |
| 794 | |
| 795 | /* Bar 1: downstream IO bar */ |
| 796 | fpci_bar = 0xfdfc0000; |
| 797 | size = resource_size(&pcie->io); |
| 798 | axi_address = pcie->io.start; |
| 799 | afi_writel(pcie, axi_address, AFI_AXI_BAR1_START); |
| 800 | afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); |
| 801 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1); |
| 802 | |
| 803 | /* Bar 2: prefetchable memory BAR */ |
| 804 | fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; |
| 805 | size = resource_size(&pcie->prefetch); |
| 806 | axi_address = pcie->prefetch.start; |
| 807 | afi_writel(pcie, axi_address, AFI_AXI_BAR2_START); |
| 808 | afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); |
| 809 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2); |
| 810 | |
| 811 | /* Bar 3: non prefetchable memory BAR */ |
| 812 | fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; |
| 813 | size = resource_size(&pcie->mem); |
| 814 | axi_address = pcie->mem.start; |
| 815 | afi_writel(pcie, axi_address, AFI_AXI_BAR3_START); |
| 816 | afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); |
| 817 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3); |
| 818 | |
| 819 | /* NULL out the remaining BARs as they are not used */ |
| 820 | afi_writel(pcie, 0, AFI_AXI_BAR4_START); |
| 821 | afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); |
| 822 | afi_writel(pcie, 0, AFI_FPCI_BAR4); |
| 823 | |
| 824 | afi_writel(pcie, 0, AFI_AXI_BAR5_START); |
| 825 | afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); |
| 826 | afi_writel(pcie, 0, AFI_FPCI_BAR5); |
| 827 | |
| 828 | /* map all upstream transactions as uncached */ |
| 829 | afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST); |
| 830 | afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); |
| 831 | afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); |
| 832 | afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); |
| 833 | |
| 834 | /* MSI translations are setup only when needed */ |
| 835 | afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); |
| 836 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); |
| 837 | afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); |
| 838 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); |
| 839 | } |
| 840 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 841 | static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 842 | { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 843 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 844 | u32 value; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 845 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 846 | timeout = jiffies + msecs_to_jiffies(timeout); |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 847 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 848 | while (time_before(jiffies, timeout)) { |
| 849 | value = pads_readl(pcie, soc->pads_pll_ctl); |
| 850 | if (value & PADS_PLL_CTL_LOCKDET) |
| 851 | return 0; |
| 852 | } |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 853 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 854 | return -ETIMEDOUT; |
| 855 | } |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 856 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 857 | static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) |
| 858 | { |
| 859 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
| 860 | u32 value; |
| 861 | int err; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 862 | |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 863 | /* initialize internal PHY, enable up to 16 PCIE lanes */ |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 864 | pads_writel(pcie, 0x0, PADS_CTL_SEL); |
| 865 | |
| 866 | /* override IDDQ to 1 on all 4 lanes */ |
| 867 | value = pads_readl(pcie, PADS_CTL); |
| 868 | value |= PADS_CTL_IDDQ_1L; |
| 869 | pads_writel(pcie, value, PADS_CTL); |
| 870 | |
| 871 | /* |
| 872 | * Set up PHY PLL inputs select PLLE output as refclock, |
| 873 | * set TX ref sel to div10 (not div5). |
| 874 | */ |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 875 | value = pads_readl(pcie, soc->pads_pll_ctl); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 876 | value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 877 | value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; |
| 878 | pads_writel(pcie, value, soc->pads_pll_ctl); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 879 | |
Eric Yuen | ec73276 | 2014-08-26 17:11:37 +0200 | [diff] [blame] | 880 | /* reset PLL */ |
| 881 | value = pads_readl(pcie, soc->pads_pll_ctl); |
| 882 | value &= ~PADS_PLL_CTL_RST_B4SM; |
| 883 | pads_writel(pcie, value, soc->pads_pll_ctl); |
| 884 | |
| 885 | usleep_range(20, 100); |
| 886 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 887 | /* take PLL out of reset */ |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 888 | value = pads_readl(pcie, soc->pads_pll_ctl); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 889 | value |= PADS_PLL_CTL_RST_B4SM; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 890 | pads_writel(pcie, value, soc->pads_pll_ctl); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 891 | |
Stephen Warren | b02b07a | 2013-08-09 16:49:25 +0200 | [diff] [blame] | 892 | /* Configure the reference clock driver */ |
| 893 | value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); |
| 894 | pads_writel(pcie, value, PADS_REFCLK_CFG0); |
| 895 | if (soc->num_ports > 2) |
| 896 | pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 897 | |
| 898 | /* wait for the PLL to lock */ |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 899 | err = tegra_pcie_pll_wait(pcie, 500); |
| 900 | if (err < 0) { |
| 901 | dev_err(pcie->dev, "PLL failed to lock: %d\n", err); |
| 902 | return err; |
| 903 | } |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 904 | |
| 905 | /* turn off IDDQ override */ |
| 906 | value = pads_readl(pcie, PADS_CTL); |
| 907 | value &= ~PADS_CTL_IDDQ_1L; |
| 908 | pads_writel(pcie, value, PADS_CTL); |
| 909 | |
| 910 | /* enable TX/RX data */ |
| 911 | value = pads_readl(pcie, PADS_CTL); |
| 912 | value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; |
| 913 | pads_writel(pcie, value, PADS_CTL); |
| 914 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 915 | return 0; |
| 916 | } |
| 917 | |
| 918 | static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) |
| 919 | { |
| 920 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
| 921 | struct tegra_pcie_port *port; |
| 922 | unsigned long value; |
| 923 | int err; |
| 924 | |
| 925 | /* enable PLL power down */ |
| 926 | if (pcie->phy) { |
| 927 | value = afi_readl(pcie, AFI_PLLE_CONTROL); |
| 928 | value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; |
| 929 | value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; |
| 930 | afi_writel(pcie, value, AFI_PLLE_CONTROL); |
| 931 | } |
| 932 | |
| 933 | /* power down PCIe slot clock bias pad */ |
| 934 | if (soc->has_pex_bias_ctrl) |
| 935 | afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); |
| 936 | |
| 937 | /* configure mode and disable all ports */ |
| 938 | value = afi_readl(pcie, AFI_PCIE_CONFIG); |
| 939 | value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; |
| 940 | value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; |
| 941 | |
| 942 | list_for_each_entry(port, &pcie->ports, list) |
| 943 | value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); |
| 944 | |
| 945 | afi_writel(pcie, value, AFI_PCIE_CONFIG); |
| 946 | |
| 947 | if (soc->has_gen2) { |
| 948 | value = afi_readl(pcie, AFI_FUSE); |
| 949 | value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; |
| 950 | afi_writel(pcie, value, AFI_FUSE); |
| 951 | } else { |
| 952 | value = afi_readl(pcie, AFI_FUSE); |
| 953 | value |= AFI_FUSE_PCIE_T0_GEN2_DIS; |
| 954 | afi_writel(pcie, value, AFI_FUSE); |
| 955 | } |
| 956 | |
| 957 | if (!pcie->phy) |
| 958 | err = tegra_pcie_phy_enable(pcie); |
| 959 | else |
| 960 | err = phy_power_on(pcie->phy); |
| 961 | |
| 962 | if (err < 0) { |
| 963 | dev_err(pcie->dev, "failed to power on PHY: %d\n", err); |
| 964 | return err; |
| 965 | } |
| 966 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 967 | /* take the PCIe interface module out of reset */ |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 968 | reset_control_deassert(pcie->pcie_xrst); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 969 | |
| 970 | /* finally enable PCIe */ |
| 971 | value = afi_readl(pcie, AFI_CONFIGURATION); |
| 972 | value |= AFI_CONFIGURATION_EN_FPCI; |
| 973 | afi_writel(pcie, value, AFI_CONFIGURATION); |
| 974 | |
| 975 | value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | |
| 976 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | |
| 977 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR; |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 978 | |
| 979 | if (soc->has_intr_prsnt_sense) |
| 980 | value |= AFI_INTR_EN_PRSNT_SENSE; |
| 981 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 982 | afi_writel(pcie, value, AFI_AFI_INTR_ENABLE); |
| 983 | afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE); |
| 984 | |
| 985 | /* don't enable MSI for now, only when needed */ |
| 986 | afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); |
| 987 | |
| 988 | /* disable all exceptions */ |
| 989 | afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); |
| 990 | |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | static void tegra_pcie_power_off(struct tegra_pcie *pcie) |
| 995 | { |
| 996 | int err; |
| 997 | |
| 998 | /* TODO: disable and unprepare clocks? */ |
| 999 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1000 | err = phy_power_off(pcie->phy); |
| 1001 | if (err < 0) |
| 1002 | dev_warn(pcie->dev, "failed to power off PHY: %d\n", err); |
| 1003 | |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 1004 | reset_control_assert(pcie->pcie_xrst); |
| 1005 | reset_control_assert(pcie->afi_rst); |
| 1006 | reset_control_assert(pcie->pex_rst); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1007 | |
| 1008 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); |
| 1009 | |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1010 | err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1011 | if (err < 0) |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1012 | dev_warn(pcie->dev, "failed to disable regulators: %d\n", err); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1013 | } |
| 1014 | |
| 1015 | static int tegra_pcie_power_on(struct tegra_pcie *pcie) |
| 1016 | { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1017 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1018 | int err; |
| 1019 | |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 1020 | reset_control_assert(pcie->pcie_xrst); |
| 1021 | reset_control_assert(pcie->afi_rst); |
| 1022 | reset_control_assert(pcie->pex_rst); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1023 | |
| 1024 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); |
| 1025 | |
| 1026 | /* enable regulators */ |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1027 | err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); |
| 1028 | if (err < 0) |
| 1029 | dev_err(pcie->dev, "failed to enable regulators: %d\n", err); |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1030 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1031 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, |
Stephen Warren | 80b2879 | 2013-11-06 15:45:46 -0700 | [diff] [blame] | 1032 | pcie->pex_clk, |
| 1033 | pcie->pex_rst); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1034 | if (err) { |
| 1035 | dev_err(pcie->dev, "powerup sequence failed: %d\n", err); |
| 1036 | return err; |
| 1037 | } |
| 1038 | |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 1039 | reset_control_deassert(pcie->afi_rst); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1040 | |
| 1041 | err = clk_prepare_enable(pcie->afi_clk); |
| 1042 | if (err < 0) { |
| 1043 | dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err); |
| 1044 | return err; |
| 1045 | } |
| 1046 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1047 | if (soc->has_cml_clk) { |
| 1048 | err = clk_prepare_enable(pcie->cml_clk); |
| 1049 | if (err < 0) { |
| 1050 | dev_err(pcie->dev, "failed to enable CML clock: %d\n", |
| 1051 | err); |
| 1052 | return err; |
| 1053 | } |
| 1054 | } |
| 1055 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1056 | err = clk_prepare_enable(pcie->pll_e); |
| 1057 | if (err < 0) { |
| 1058 | dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err); |
| 1059 | return err; |
| 1060 | } |
| 1061 | |
| 1062 | return 0; |
| 1063 | } |
| 1064 | |
| 1065 | static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) |
| 1066 | { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1067 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
| 1068 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1069 | pcie->pex_clk = devm_clk_get(pcie->dev, "pex"); |
| 1070 | if (IS_ERR(pcie->pex_clk)) |
| 1071 | return PTR_ERR(pcie->pex_clk); |
| 1072 | |
| 1073 | pcie->afi_clk = devm_clk_get(pcie->dev, "afi"); |
| 1074 | if (IS_ERR(pcie->afi_clk)) |
| 1075 | return PTR_ERR(pcie->afi_clk); |
| 1076 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1077 | pcie->pll_e = devm_clk_get(pcie->dev, "pll_e"); |
| 1078 | if (IS_ERR(pcie->pll_e)) |
| 1079 | return PTR_ERR(pcie->pll_e); |
| 1080 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1081 | if (soc->has_cml_clk) { |
| 1082 | pcie->cml_clk = devm_clk_get(pcie->dev, "cml"); |
| 1083 | if (IS_ERR(pcie->cml_clk)) |
| 1084 | return PTR_ERR(pcie->cml_clk); |
| 1085 | } |
| 1086 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1087 | return 0; |
| 1088 | } |
| 1089 | |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 1090 | static int tegra_pcie_resets_get(struct tegra_pcie *pcie) |
| 1091 | { |
| 1092 | pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex"); |
| 1093 | if (IS_ERR(pcie->pex_rst)) |
| 1094 | return PTR_ERR(pcie->pex_rst); |
| 1095 | |
| 1096 | pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi"); |
| 1097 | if (IS_ERR(pcie->afi_rst)) |
| 1098 | return PTR_ERR(pcie->afi_rst); |
| 1099 | |
| 1100 | pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x"); |
| 1101 | if (IS_ERR(pcie->pcie_xrst)) |
| 1102 | return PTR_ERR(pcie->pcie_xrst); |
| 1103 | |
| 1104 | return 0; |
| 1105 | } |
| 1106 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1107 | static int tegra_pcie_get_resources(struct tegra_pcie *pcie) |
| 1108 | { |
| 1109 | struct platform_device *pdev = to_platform_device(pcie->dev); |
| 1110 | struct resource *pads, *afi, *res; |
| 1111 | int err; |
| 1112 | |
| 1113 | err = tegra_pcie_clocks_get(pcie); |
| 1114 | if (err) { |
| 1115 | dev_err(&pdev->dev, "failed to get clocks: %d\n", err); |
| 1116 | return err; |
| 1117 | } |
| 1118 | |
Stephen Warren | 3127a6b | 2013-11-06 15:56:58 -0700 | [diff] [blame] | 1119 | err = tegra_pcie_resets_get(pcie); |
| 1120 | if (err) { |
| 1121 | dev_err(&pdev->dev, "failed to get resets: %d\n", err); |
| 1122 | return err; |
| 1123 | } |
| 1124 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1125 | pcie->phy = devm_phy_optional_get(pcie->dev, "pcie"); |
| 1126 | if (IS_ERR(pcie->phy)) { |
| 1127 | err = PTR_ERR(pcie->phy); |
| 1128 | dev_err(&pdev->dev, "failed to get PHY: %d\n", err); |
| 1129 | return err; |
| 1130 | } |
| 1131 | |
| 1132 | err = phy_init(pcie->phy); |
| 1133 | if (err < 0) { |
| 1134 | dev_err(&pdev->dev, "failed to initialize PHY: %d\n", err); |
| 1135 | return err; |
| 1136 | } |
| 1137 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1138 | err = tegra_pcie_power_on(pcie); |
| 1139 | if (err) { |
| 1140 | dev_err(&pdev->dev, "failed to power up: %d\n", err); |
| 1141 | return err; |
| 1142 | } |
| 1143 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1144 | pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); |
Julia Lawall | dc05ee3 | 2013-08-26 11:11:09 +0200 | [diff] [blame] | 1145 | pcie->pads = devm_ioremap_resource(&pdev->dev, pads); |
| 1146 | if (IS_ERR(pcie->pads)) { |
| 1147 | err = PTR_ERR(pcie->pads); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1148 | goto poweroff; |
| 1149 | } |
| 1150 | |
| 1151 | afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); |
Julia Lawall | dc05ee3 | 2013-08-26 11:11:09 +0200 | [diff] [blame] | 1152 | pcie->afi = devm_ioremap_resource(&pdev->dev, afi); |
| 1153 | if (IS_ERR(pcie->afi)) { |
| 1154 | err = PTR_ERR(pcie->afi); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1155 | goto poweroff; |
| 1156 | } |
| 1157 | |
Julia Lawall | dc05ee3 | 2013-08-26 11:11:09 +0200 | [diff] [blame] | 1158 | /* request configuration space, but remap later, on demand */ |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1159 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); |
| 1160 | if (!res) { |
| 1161 | err = -EADDRNOTAVAIL; |
| 1162 | goto poweroff; |
| 1163 | } |
| 1164 | |
| 1165 | pcie->cs = devm_request_mem_region(pcie->dev, res->start, |
| 1166 | resource_size(res), res->name); |
| 1167 | if (!pcie->cs) { |
| 1168 | err = -EADDRNOTAVAIL; |
| 1169 | goto poweroff; |
| 1170 | } |
| 1171 | |
| 1172 | /* request interrupt */ |
| 1173 | err = platform_get_irq_byname(pdev, "intr"); |
| 1174 | if (err < 0) { |
| 1175 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); |
| 1176 | goto poweroff; |
| 1177 | } |
| 1178 | |
| 1179 | pcie->irq = err; |
| 1180 | |
| 1181 | err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); |
| 1182 | if (err) { |
| 1183 | dev_err(&pdev->dev, "failed to register IRQ: %d\n", err); |
| 1184 | goto poweroff; |
| 1185 | } |
| 1186 | |
| 1187 | return 0; |
| 1188 | |
| 1189 | poweroff: |
| 1190 | tegra_pcie_power_off(pcie); |
| 1191 | return err; |
| 1192 | } |
| 1193 | |
| 1194 | static int tegra_pcie_put_resources(struct tegra_pcie *pcie) |
| 1195 | { |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1196 | int err; |
| 1197 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1198 | if (pcie->irq > 0) |
| 1199 | free_irq(pcie->irq, pcie); |
| 1200 | |
| 1201 | tegra_pcie_power_off(pcie); |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1202 | |
| 1203 | err = phy_exit(pcie->phy); |
| 1204 | if (err < 0) |
| 1205 | dev_err(pcie->dev, "failed to teardown PHY: %d\n", err); |
| 1206 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1207 | return 0; |
| 1208 | } |
| 1209 | |
| 1210 | static int tegra_msi_alloc(struct tegra_msi *chip) |
| 1211 | { |
| 1212 | int msi; |
| 1213 | |
| 1214 | mutex_lock(&chip->lock); |
| 1215 | |
| 1216 | msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); |
| 1217 | if (msi < INT_PCI_MSI_NR) |
| 1218 | set_bit(msi, chip->used); |
| 1219 | else |
| 1220 | msi = -ENOSPC; |
| 1221 | |
| 1222 | mutex_unlock(&chip->lock); |
| 1223 | |
| 1224 | return msi; |
| 1225 | } |
| 1226 | |
| 1227 | static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq) |
| 1228 | { |
| 1229 | struct device *dev = chip->chip.dev; |
| 1230 | |
| 1231 | mutex_lock(&chip->lock); |
| 1232 | |
| 1233 | if (!test_bit(irq, chip->used)) |
| 1234 | dev_err(dev, "trying to free unused MSI#%lu\n", irq); |
| 1235 | else |
| 1236 | clear_bit(irq, chip->used); |
| 1237 | |
| 1238 | mutex_unlock(&chip->lock); |
| 1239 | } |
| 1240 | |
| 1241 | static irqreturn_t tegra_pcie_msi_irq(int irq, void *data) |
| 1242 | { |
| 1243 | struct tegra_pcie *pcie = data; |
| 1244 | struct tegra_msi *msi = &pcie->msi; |
| 1245 | unsigned int i, processed = 0; |
| 1246 | |
| 1247 | for (i = 0; i < 8; i++) { |
| 1248 | unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); |
| 1249 | |
| 1250 | while (reg) { |
| 1251 | unsigned int offset = find_first_bit(®, 32); |
| 1252 | unsigned int index = i * 32 + offset; |
| 1253 | unsigned int irq; |
| 1254 | |
| 1255 | /* clear the interrupt */ |
| 1256 | afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4); |
| 1257 | |
| 1258 | irq = irq_find_mapping(msi->domain, index); |
| 1259 | if (irq) { |
| 1260 | if (test_bit(index, msi->used)) |
| 1261 | generic_handle_irq(irq); |
| 1262 | else |
| 1263 | dev_info(pcie->dev, "unhandled MSI\n"); |
| 1264 | } else { |
| 1265 | /* |
| 1266 | * that's weird who triggered this? |
| 1267 | * just clear it |
| 1268 | */ |
| 1269 | dev_info(pcie->dev, "unexpected MSI\n"); |
| 1270 | } |
| 1271 | |
| 1272 | /* see if there's any more pending in this vector */ |
| 1273 | reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); |
| 1274 | |
| 1275 | processed++; |
| 1276 | } |
| 1277 | } |
| 1278 | |
| 1279 | return processed > 0 ? IRQ_HANDLED : IRQ_NONE; |
| 1280 | } |
| 1281 | |
| 1282 | static int tegra_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, |
| 1283 | struct msi_desc *desc) |
| 1284 | { |
| 1285 | struct tegra_msi *msi = to_tegra_msi(chip); |
| 1286 | struct msi_msg msg; |
| 1287 | unsigned int irq; |
| 1288 | int hwirq; |
| 1289 | |
| 1290 | hwirq = tegra_msi_alloc(msi); |
| 1291 | if (hwirq < 0) |
| 1292 | return hwirq; |
| 1293 | |
| 1294 | irq = irq_create_mapping(msi->domain, hwirq); |
Jisheng Zhang | 019fa46 | 2014-07-29 09:33:30 +0800 | [diff] [blame] | 1295 | if (!irq) { |
| 1296 | tegra_msi_free(msi, hwirq); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1297 | return -EINVAL; |
Jisheng Zhang | 019fa46 | 2014-07-29 09:33:30 +0800 | [diff] [blame] | 1298 | } |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1299 | |
| 1300 | irq_set_msi_desc(irq, desc); |
| 1301 | |
| 1302 | msg.address_lo = virt_to_phys((void *)msi->pages); |
| 1303 | /* 32 bit address only */ |
| 1304 | msg.address_hi = 0; |
| 1305 | msg.data = hwirq; |
| 1306 | |
| 1307 | write_msi_msg(irq, &msg); |
| 1308 | |
| 1309 | return 0; |
| 1310 | } |
| 1311 | |
| 1312 | static void tegra_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) |
| 1313 | { |
| 1314 | struct tegra_msi *msi = to_tegra_msi(chip); |
| 1315 | struct irq_data *d = irq_get_irq_data(irq); |
Jisheng Zhang | 019fa46 | 2014-07-29 09:33:30 +0800 | [diff] [blame] | 1316 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1317 | |
Jisheng Zhang | 019fa46 | 2014-07-29 09:33:30 +0800 | [diff] [blame] | 1318 | irq_dispose_mapping(irq); |
| 1319 | tegra_msi_free(msi, hwirq); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1320 | } |
| 1321 | |
| 1322 | static struct irq_chip tegra_msi_irq_chip = { |
| 1323 | .name = "Tegra PCIe MSI", |
| 1324 | .irq_enable = unmask_msi_irq, |
| 1325 | .irq_disable = mask_msi_irq, |
| 1326 | .irq_mask = mask_msi_irq, |
| 1327 | .irq_unmask = unmask_msi_irq, |
| 1328 | }; |
| 1329 | |
| 1330 | static int tegra_msi_map(struct irq_domain *domain, unsigned int irq, |
| 1331 | irq_hw_number_t hwirq) |
| 1332 | { |
| 1333 | irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq); |
| 1334 | irq_set_chip_data(irq, domain->host_data); |
| 1335 | set_irq_flags(irq, IRQF_VALID); |
| 1336 | |
Stephen Warren | b4f1737 | 2013-05-06 14:19:19 -0600 | [diff] [blame] | 1337 | tegra_cpuidle_pcie_irqs_in_use(); |
| 1338 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1339 | return 0; |
| 1340 | } |
| 1341 | |
| 1342 | static const struct irq_domain_ops msi_domain_ops = { |
| 1343 | .map = tegra_msi_map, |
| 1344 | }; |
| 1345 | |
| 1346 | static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) |
| 1347 | { |
| 1348 | struct platform_device *pdev = to_platform_device(pcie->dev); |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1349 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1350 | struct tegra_msi *msi = &pcie->msi; |
| 1351 | unsigned long base; |
| 1352 | int err; |
| 1353 | u32 reg; |
| 1354 | |
| 1355 | mutex_init(&msi->lock); |
| 1356 | |
| 1357 | msi->chip.dev = pcie->dev; |
| 1358 | msi->chip.setup_irq = tegra_msi_setup_irq; |
| 1359 | msi->chip.teardown_irq = tegra_msi_teardown_irq; |
| 1360 | |
| 1361 | msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR, |
| 1362 | &msi_domain_ops, &msi->chip); |
| 1363 | if (!msi->domain) { |
| 1364 | dev_err(&pdev->dev, "failed to create IRQ domain\n"); |
| 1365 | return -ENOMEM; |
| 1366 | } |
| 1367 | |
| 1368 | err = platform_get_irq_byname(pdev, "msi"); |
| 1369 | if (err < 0) { |
| 1370 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); |
| 1371 | goto err; |
| 1372 | } |
| 1373 | |
| 1374 | msi->irq = err; |
| 1375 | |
| 1376 | err = request_irq(msi->irq, tegra_pcie_msi_irq, 0, |
| 1377 | tegra_msi_irq_chip.name, pcie); |
| 1378 | if (err < 0) { |
| 1379 | dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); |
| 1380 | goto err; |
| 1381 | } |
| 1382 | |
| 1383 | /* setup AFI/FPCI range */ |
| 1384 | msi->pages = __get_free_pages(GFP_KERNEL, 0); |
| 1385 | base = virt_to_phys((void *)msi->pages); |
| 1386 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1387 | afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1388 | afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST); |
| 1389 | /* this register is in 4K increments */ |
| 1390 | afi_writel(pcie, 1, AFI_MSI_BAR_SZ); |
| 1391 | |
| 1392 | /* enable all MSI vectors */ |
| 1393 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0); |
| 1394 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1); |
| 1395 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2); |
| 1396 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3); |
| 1397 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4); |
| 1398 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5); |
| 1399 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6); |
| 1400 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7); |
| 1401 | |
| 1402 | /* and unmask the MSI interrupt */ |
| 1403 | reg = afi_readl(pcie, AFI_INTR_MASK); |
| 1404 | reg |= AFI_INTR_MASK_MSI_MASK; |
| 1405 | afi_writel(pcie, reg, AFI_INTR_MASK); |
| 1406 | |
| 1407 | return 0; |
| 1408 | |
| 1409 | err: |
| 1410 | irq_domain_remove(msi->domain); |
| 1411 | return err; |
| 1412 | } |
| 1413 | |
| 1414 | static int tegra_pcie_disable_msi(struct tegra_pcie *pcie) |
| 1415 | { |
| 1416 | struct tegra_msi *msi = &pcie->msi; |
| 1417 | unsigned int i, irq; |
| 1418 | u32 value; |
| 1419 | |
| 1420 | /* mask the MSI interrupt */ |
| 1421 | value = afi_readl(pcie, AFI_INTR_MASK); |
| 1422 | value &= ~AFI_INTR_MASK_MSI_MASK; |
| 1423 | afi_writel(pcie, value, AFI_INTR_MASK); |
| 1424 | |
| 1425 | /* disable all MSI vectors */ |
| 1426 | afi_writel(pcie, 0, AFI_MSI_EN_VEC0); |
| 1427 | afi_writel(pcie, 0, AFI_MSI_EN_VEC1); |
| 1428 | afi_writel(pcie, 0, AFI_MSI_EN_VEC2); |
| 1429 | afi_writel(pcie, 0, AFI_MSI_EN_VEC3); |
| 1430 | afi_writel(pcie, 0, AFI_MSI_EN_VEC4); |
| 1431 | afi_writel(pcie, 0, AFI_MSI_EN_VEC5); |
| 1432 | afi_writel(pcie, 0, AFI_MSI_EN_VEC6); |
| 1433 | afi_writel(pcie, 0, AFI_MSI_EN_VEC7); |
| 1434 | |
| 1435 | free_pages(msi->pages, 0); |
| 1436 | |
| 1437 | if (msi->irq > 0) |
| 1438 | free_irq(msi->irq, pcie); |
| 1439 | |
| 1440 | for (i = 0; i < INT_PCI_MSI_NR; i++) { |
| 1441 | irq = irq_find_mapping(msi->domain, i); |
| 1442 | if (irq > 0) |
| 1443 | irq_dispose_mapping(irq); |
| 1444 | } |
| 1445 | |
| 1446 | irq_domain_remove(msi->domain); |
| 1447 | |
| 1448 | return 0; |
| 1449 | } |
| 1450 | |
| 1451 | static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, |
| 1452 | u32 *xbar) |
| 1453 | { |
| 1454 | struct device_node *np = pcie->dev->of_node; |
| 1455 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1456 | if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { |
| 1457 | switch (lanes) { |
| 1458 | case 0x0000104: |
| 1459 | dev_info(pcie->dev, "4x1, 1x1 configuration\n"); |
| 1460 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; |
| 1461 | return 0; |
| 1462 | |
| 1463 | case 0x0000102: |
| 1464 | dev_info(pcie->dev, "2x1, 1x1 configuration\n"); |
| 1465 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; |
| 1466 | return 0; |
| 1467 | } |
| 1468 | } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1469 | switch (lanes) { |
| 1470 | case 0x00000204: |
| 1471 | dev_info(pcie->dev, "4x1, 2x1 configuration\n"); |
| 1472 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; |
| 1473 | return 0; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1474 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1475 | case 0x00020202: |
| 1476 | dev_info(pcie->dev, "2x3 configuration\n"); |
| 1477 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; |
| 1478 | return 0; |
| 1479 | |
| 1480 | case 0x00010104: |
| 1481 | dev_info(pcie->dev, "4x1, 1x2 configuration\n"); |
| 1482 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; |
| 1483 | return 0; |
| 1484 | } |
| 1485 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { |
| 1486 | switch (lanes) { |
| 1487 | case 0x00000004: |
| 1488 | dev_info(pcie->dev, "single-mode configuration\n"); |
| 1489 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; |
| 1490 | return 0; |
| 1491 | |
| 1492 | case 0x00000202: |
| 1493 | dev_info(pcie->dev, "dual-mode configuration\n"); |
| 1494 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; |
| 1495 | return 0; |
| 1496 | } |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1497 | } |
| 1498 | |
| 1499 | return -EINVAL; |
| 1500 | } |
| 1501 | |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1502 | /* |
| 1503 | * Check whether a given set of supplies is available in a device tree node. |
| 1504 | * This is used to check whether the new or the legacy device tree bindings |
| 1505 | * should be used. |
| 1506 | */ |
| 1507 | static bool of_regulator_bulk_available(struct device_node *np, |
| 1508 | struct regulator_bulk_data *supplies, |
| 1509 | unsigned int num_supplies) |
| 1510 | { |
| 1511 | char property[32]; |
| 1512 | unsigned int i; |
| 1513 | |
| 1514 | for (i = 0; i < num_supplies; i++) { |
| 1515 | snprintf(property, 32, "%s-supply", supplies[i].supply); |
| 1516 | |
| 1517 | if (of_find_property(np, property, NULL) == NULL) |
| 1518 | return false; |
| 1519 | } |
| 1520 | |
| 1521 | return true; |
| 1522 | } |
| 1523 | |
| 1524 | /* |
| 1525 | * Old versions of the device tree binding for this device used a set of power |
| 1526 | * supplies that didn't match the hardware inputs. This happened to work for a |
| 1527 | * number of cases but is not future proof. However to preserve backwards- |
| 1528 | * compatibility with old device trees, this function will try to use the old |
| 1529 | * set of supplies. |
| 1530 | */ |
| 1531 | static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie) |
| 1532 | { |
| 1533 | struct device_node *np = pcie->dev->of_node; |
| 1534 | |
| 1535 | if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) |
| 1536 | pcie->num_supplies = 3; |
| 1537 | else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) |
| 1538 | pcie->num_supplies = 2; |
| 1539 | |
| 1540 | if (pcie->num_supplies == 0) { |
| 1541 | dev_err(pcie->dev, "device %s not supported in legacy mode\n", |
| 1542 | np->full_name); |
| 1543 | return -ENODEV; |
| 1544 | } |
| 1545 | |
| 1546 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, |
| 1547 | sizeof(*pcie->supplies), |
| 1548 | GFP_KERNEL); |
| 1549 | if (!pcie->supplies) |
| 1550 | return -ENOMEM; |
| 1551 | |
| 1552 | pcie->supplies[0].supply = "pex-clk"; |
| 1553 | pcie->supplies[1].supply = "vdd"; |
| 1554 | |
| 1555 | if (pcie->num_supplies > 2) |
| 1556 | pcie->supplies[2].supply = "avdd"; |
| 1557 | |
| 1558 | return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, |
| 1559 | pcie->supplies); |
| 1560 | } |
| 1561 | |
| 1562 | /* |
| 1563 | * Obtains the list of regulators required for a particular generation of the |
| 1564 | * IP block. |
| 1565 | * |
| 1566 | * This would've been nice to do simply by providing static tables for use |
| 1567 | * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky |
| 1568 | * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB) |
| 1569 | * and either seems to be optional depending on which ports are being used. |
| 1570 | */ |
| 1571 | static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) |
| 1572 | { |
| 1573 | struct device_node *np = pcie->dev->of_node; |
| 1574 | unsigned int i = 0; |
| 1575 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1576 | if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { |
| 1577 | pcie->num_supplies = 7; |
| 1578 | |
| 1579 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, |
| 1580 | sizeof(*pcie->supplies), |
| 1581 | GFP_KERNEL); |
| 1582 | if (!pcie->supplies) |
| 1583 | return -ENOMEM; |
| 1584 | |
| 1585 | pcie->supplies[i++].supply = "avddio-pex"; |
| 1586 | pcie->supplies[i++].supply = "dvddio-pex"; |
| 1587 | pcie->supplies[i++].supply = "avdd-pex-pll"; |
| 1588 | pcie->supplies[i++].supply = "hvdd-pex"; |
| 1589 | pcie->supplies[i++].supply = "hvdd-pex-pll-e"; |
| 1590 | pcie->supplies[i++].supply = "vddio-pex-ctl"; |
| 1591 | pcie->supplies[i++].supply = "avdd-pll-erefe"; |
| 1592 | } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1593 | bool need_pexa = false, need_pexb = false; |
| 1594 | |
| 1595 | /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */ |
| 1596 | if (lane_mask & 0x0f) |
| 1597 | need_pexa = true; |
| 1598 | |
| 1599 | /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */ |
| 1600 | if (lane_mask & 0x30) |
| 1601 | need_pexb = true; |
| 1602 | |
| 1603 | pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + |
| 1604 | (need_pexb ? 2 : 0); |
| 1605 | |
| 1606 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, |
| 1607 | sizeof(*pcie->supplies), |
| 1608 | GFP_KERNEL); |
| 1609 | if (!pcie->supplies) |
| 1610 | return -ENOMEM; |
| 1611 | |
| 1612 | pcie->supplies[i++].supply = "avdd-pex-pll"; |
| 1613 | pcie->supplies[i++].supply = "hvdd-pex"; |
| 1614 | pcie->supplies[i++].supply = "vddio-pex-ctl"; |
| 1615 | pcie->supplies[i++].supply = "avdd-plle"; |
| 1616 | |
| 1617 | if (need_pexa) { |
| 1618 | pcie->supplies[i++].supply = "avdd-pexa"; |
| 1619 | pcie->supplies[i++].supply = "vdd-pexa"; |
| 1620 | } |
| 1621 | |
| 1622 | if (need_pexb) { |
| 1623 | pcie->supplies[i++].supply = "avdd-pexb"; |
| 1624 | pcie->supplies[i++].supply = "vdd-pexb"; |
| 1625 | } |
| 1626 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { |
| 1627 | pcie->num_supplies = 5; |
| 1628 | |
| 1629 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, |
| 1630 | sizeof(*pcie->supplies), |
| 1631 | GFP_KERNEL); |
| 1632 | if (!pcie->supplies) |
| 1633 | return -ENOMEM; |
| 1634 | |
| 1635 | pcie->supplies[0].supply = "avdd-pex"; |
| 1636 | pcie->supplies[1].supply = "vdd-pex"; |
| 1637 | pcie->supplies[2].supply = "avdd-pex-pll"; |
| 1638 | pcie->supplies[3].supply = "avdd-plle"; |
| 1639 | pcie->supplies[4].supply = "vddio-pex-clk"; |
| 1640 | } |
| 1641 | |
| 1642 | if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies, |
| 1643 | pcie->num_supplies)) |
| 1644 | return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, |
| 1645 | pcie->supplies); |
| 1646 | |
| 1647 | /* |
| 1648 | * If not all regulators are available for this new scheme, assume |
| 1649 | * that the device tree complies with an older version of the device |
| 1650 | * tree binding. |
| 1651 | */ |
| 1652 | dev_info(pcie->dev, "using legacy DT binding for power supplies\n"); |
| 1653 | |
| 1654 | devm_kfree(pcie->dev, pcie->supplies); |
| 1655 | pcie->num_supplies = 0; |
| 1656 | |
| 1657 | return tegra_pcie_get_legacy_regulators(pcie); |
| 1658 | } |
| 1659 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1660 | static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) |
| 1661 | { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1662 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1663 | struct device_node *np = pcie->dev->of_node, *port; |
| 1664 | struct of_pci_range_parser parser; |
| 1665 | struct of_pci_range range; |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1666 | u32 lanes = 0, mask = 0; |
| 1667 | unsigned int lane = 0; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1668 | struct resource res; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1669 | int err; |
| 1670 | |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 1671 | memset(&pcie->all, 0, sizeof(pcie->all)); |
| 1672 | pcie->all.flags = IORESOURCE_MEM; |
| 1673 | pcie->all.name = np->full_name; |
| 1674 | pcie->all.start = ~0; |
| 1675 | pcie->all.end = 0; |
| 1676 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1677 | if (of_pci_range_parser_init(&parser, np)) { |
| 1678 | dev_err(pcie->dev, "missing \"ranges\" property\n"); |
| 1679 | return -EINVAL; |
| 1680 | } |
| 1681 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1682 | for_each_of_pci_range(&parser, &range) { |
| 1683 | of_pci_range_to_resource(&range, np, &res); |
| 1684 | |
| 1685 | switch (res.flags & IORESOURCE_TYPE_BITS) { |
| 1686 | case IORESOURCE_IO: |
| 1687 | memcpy(&pcie->io, &res, sizeof(res)); |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 1688 | pcie->io.name = np->full_name; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1689 | break; |
| 1690 | |
| 1691 | case IORESOURCE_MEM: |
| 1692 | if (res.flags & IORESOURCE_PREFETCH) { |
| 1693 | memcpy(&pcie->prefetch, &res, sizeof(res)); |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 1694 | pcie->prefetch.name = "prefetchable"; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1695 | } else { |
| 1696 | memcpy(&pcie->mem, &res, sizeof(res)); |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 1697 | pcie->mem.name = "non-prefetchable"; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1698 | } |
| 1699 | break; |
| 1700 | } |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 1701 | |
| 1702 | if (res.start <= pcie->all.start) |
| 1703 | pcie->all.start = res.start; |
| 1704 | |
| 1705 | if (res.end >= pcie->all.end) |
| 1706 | pcie->all.end = res.end; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1707 | } |
| 1708 | |
Thierry Reding | 41534e5 | 2014-08-01 14:15:11 +0200 | [diff] [blame] | 1709 | err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all); |
| 1710 | if (err < 0) |
| 1711 | return err; |
| 1712 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1713 | err = of_pci_parse_bus_range(np, &pcie->busn); |
| 1714 | if (err < 0) { |
| 1715 | dev_err(pcie->dev, "failed to parse ranges property: %d\n", |
| 1716 | err); |
| 1717 | pcie->busn.name = np->name; |
| 1718 | pcie->busn.start = 0; |
| 1719 | pcie->busn.end = 0xff; |
| 1720 | pcie->busn.flags = IORESOURCE_BUS; |
| 1721 | } |
| 1722 | |
| 1723 | /* parse root ports */ |
| 1724 | for_each_child_of_node(np, port) { |
| 1725 | struct tegra_pcie_port *rp; |
| 1726 | unsigned int index; |
| 1727 | u32 value; |
| 1728 | |
| 1729 | err = of_pci_get_devfn(port); |
| 1730 | if (err < 0) { |
| 1731 | dev_err(pcie->dev, "failed to parse address: %d\n", |
| 1732 | err); |
| 1733 | return err; |
| 1734 | } |
| 1735 | |
| 1736 | index = PCI_SLOT(err); |
| 1737 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1738 | if (index < 1 || index > soc->num_ports) { |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1739 | dev_err(pcie->dev, "invalid port number: %d\n", index); |
| 1740 | return -EINVAL; |
| 1741 | } |
| 1742 | |
| 1743 | index--; |
| 1744 | |
| 1745 | err = of_property_read_u32(port, "nvidia,num-lanes", &value); |
| 1746 | if (err < 0) { |
| 1747 | dev_err(pcie->dev, "failed to parse # of lanes: %d\n", |
| 1748 | err); |
| 1749 | return err; |
| 1750 | } |
| 1751 | |
| 1752 | if (value > 16) { |
| 1753 | dev_err(pcie->dev, "invalid # of lanes: %u\n", value); |
| 1754 | return -EINVAL; |
| 1755 | } |
| 1756 | |
| 1757 | lanes |= value << (index << 3); |
| 1758 | |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1759 | if (!of_device_is_available(port)) { |
| 1760 | lane += value; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1761 | continue; |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1762 | } |
| 1763 | |
| 1764 | mask |= ((1 << value) - 1) << lane; |
| 1765 | lane += value; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1766 | |
| 1767 | rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL); |
| 1768 | if (!rp) |
| 1769 | return -ENOMEM; |
| 1770 | |
| 1771 | err = of_address_to_resource(port, 0, &rp->regs); |
| 1772 | if (err < 0) { |
| 1773 | dev_err(pcie->dev, "failed to parse address: %d\n", |
| 1774 | err); |
| 1775 | return err; |
| 1776 | } |
| 1777 | |
| 1778 | INIT_LIST_HEAD(&rp->list); |
| 1779 | rp->index = index; |
| 1780 | rp->lanes = value; |
| 1781 | rp->pcie = pcie; |
| 1782 | |
Julia Lawall | dc05ee3 | 2013-08-26 11:11:09 +0200 | [diff] [blame] | 1783 | rp->base = devm_ioremap_resource(pcie->dev, &rp->regs); |
| 1784 | if (IS_ERR(rp->base)) |
| 1785 | return PTR_ERR(rp->base); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1786 | |
| 1787 | list_add_tail(&rp->list, &pcie->ports); |
| 1788 | } |
| 1789 | |
| 1790 | err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); |
| 1791 | if (err < 0) { |
| 1792 | dev_err(pcie->dev, "invalid lane configuration\n"); |
| 1793 | return err; |
| 1794 | } |
| 1795 | |
Thierry Reding | 077fb15 | 2014-05-28 16:49:13 +0200 | [diff] [blame] | 1796 | err = tegra_pcie_get_regulators(pcie, mask); |
| 1797 | if (err < 0) |
| 1798 | return err; |
| 1799 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1800 | return 0; |
| 1801 | } |
| 1802 | |
| 1803 | /* |
| 1804 | * FIXME: If there are no PCIe cards attached, then calling this function |
| 1805 | * can result in the increase of the bootup time as there are big timeout |
| 1806 | * loops. |
| 1807 | */ |
| 1808 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ |
| 1809 | static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) |
| 1810 | { |
| 1811 | unsigned int retries = 3; |
| 1812 | unsigned long value; |
| 1813 | |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1814 | /* override presence detection */ |
| 1815 | value = readl(port->base + RP_PRIV_MISC); |
| 1816 | value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; |
| 1817 | value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; |
| 1818 | writel(value, port->base + RP_PRIV_MISC); |
| 1819 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 1820 | do { |
| 1821 | unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT; |
| 1822 | |
| 1823 | do { |
| 1824 | value = readl(port->base + RP_VEND_XP); |
| 1825 | |
| 1826 | if (value & RP_VEND_XP_DL_UP) |
| 1827 | break; |
| 1828 | |
| 1829 | usleep_range(1000, 2000); |
| 1830 | } while (--timeout); |
| 1831 | |
| 1832 | if (!timeout) { |
| 1833 | dev_err(port->pcie->dev, "link %u down, retrying\n", |
| 1834 | port->index); |
| 1835 | goto retry; |
| 1836 | } |
| 1837 | |
| 1838 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; |
| 1839 | |
| 1840 | do { |
| 1841 | value = readl(port->base + RP_LINK_CONTROL_STATUS); |
| 1842 | |
| 1843 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) |
| 1844 | return true; |
| 1845 | |
| 1846 | usleep_range(1000, 2000); |
| 1847 | } while (--timeout); |
| 1848 | |
| 1849 | retry: |
| 1850 | tegra_pcie_port_reset(port); |
| 1851 | } while (--retries); |
| 1852 | |
| 1853 | return false; |
| 1854 | } |
| 1855 | |
| 1856 | static int tegra_pcie_enable(struct tegra_pcie *pcie) |
| 1857 | { |
| 1858 | struct tegra_pcie_port *port, *tmp; |
| 1859 | struct hw_pci hw; |
| 1860 | |
| 1861 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { |
| 1862 | dev_info(pcie->dev, "probing port %u, using %u lanes\n", |
| 1863 | port->index, port->lanes); |
| 1864 | |
| 1865 | tegra_pcie_port_enable(port); |
| 1866 | |
| 1867 | if (tegra_pcie_port_check_link(port)) |
| 1868 | continue; |
| 1869 | |
| 1870 | dev_info(pcie->dev, "link %u down, ignoring\n", port->index); |
| 1871 | |
| 1872 | tegra_pcie_port_disable(port); |
| 1873 | tegra_pcie_port_free(port); |
| 1874 | } |
| 1875 | |
| 1876 | memset(&hw, 0, sizeof(hw)); |
| 1877 | |
| 1878 | hw.nr_controllers = 1; |
| 1879 | hw.private_data = (void **)&pcie; |
| 1880 | hw.setup = tegra_pcie_setup; |
| 1881 | hw.map_irq = tegra_pcie_map_irq; |
| 1882 | hw.add_bus = tegra_pcie_add_bus; |
| 1883 | hw.scan = tegra_pcie_scan_bus; |
| 1884 | hw.ops = &tegra_pcie_ops; |
| 1885 | |
| 1886 | pci_common_init_dev(pcie->dev, &hw); |
| 1887 | |
| 1888 | return 0; |
| 1889 | } |
| 1890 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1891 | static const struct tegra_pcie_soc_data tegra20_pcie_data = { |
| 1892 | .num_ports = 2, |
| 1893 | .msi_base_shift = 0, |
| 1894 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, |
| 1895 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, |
| 1896 | .has_pex_clkreq_en = false, |
| 1897 | .has_pex_bias_ctrl = false, |
| 1898 | .has_intr_prsnt_sense = false, |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1899 | .has_cml_clk = false, |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1900 | .has_gen2 = false, |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1901 | }; |
| 1902 | |
| 1903 | static const struct tegra_pcie_soc_data tegra30_pcie_data = { |
| 1904 | .num_ports = 3, |
| 1905 | .msi_base_shift = 8, |
| 1906 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, |
| 1907 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, |
| 1908 | .has_pex_clkreq_en = true, |
| 1909 | .has_pex_bias_ctrl = true, |
| 1910 | .has_intr_prsnt_sense = true, |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1911 | .has_cml_clk = true, |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1912 | .has_gen2 = false, |
| 1913 | }; |
| 1914 | |
| 1915 | static const struct tegra_pcie_soc_data tegra124_pcie_data = { |
| 1916 | .num_ports = 2, |
| 1917 | .msi_base_shift = 8, |
| 1918 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, |
| 1919 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, |
| 1920 | .has_pex_clkreq_en = true, |
| 1921 | .has_pex_bias_ctrl = true, |
| 1922 | .has_intr_prsnt_sense = true, |
| 1923 | .has_cml_clk = true, |
| 1924 | .has_gen2 = true, |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1925 | }; |
| 1926 | |
| 1927 | static const struct of_device_id tegra_pcie_of_match[] = { |
Thierry Reding | 7f1f054 | 2014-08-26 17:11:38 +0200 | [diff] [blame] | 1928 | { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data }, |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 1929 | { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data }, |
| 1930 | { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data }, |
| 1931 | { }, |
| 1932 | }; |
| 1933 | MODULE_DEVICE_TABLE(of, tegra_pcie_of_match); |
| 1934 | |
Thierry Reding | 2cb989f | 2014-07-22 12:30:46 -0600 | [diff] [blame] | 1935 | static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos) |
| 1936 | { |
| 1937 | struct tegra_pcie *pcie = s->private; |
| 1938 | |
| 1939 | if (list_empty(&pcie->ports)) |
| 1940 | return NULL; |
| 1941 | |
| 1942 | seq_printf(s, "Index Status\n"); |
| 1943 | |
| 1944 | return seq_list_start(&pcie->ports, *pos); |
| 1945 | } |
| 1946 | |
| 1947 | static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos) |
| 1948 | { |
| 1949 | struct tegra_pcie *pcie = s->private; |
| 1950 | |
| 1951 | return seq_list_next(v, &pcie->ports, pos); |
| 1952 | } |
| 1953 | |
| 1954 | static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v) |
| 1955 | { |
| 1956 | } |
| 1957 | |
| 1958 | static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v) |
| 1959 | { |
| 1960 | bool up = false, active = false; |
| 1961 | struct tegra_pcie_port *port; |
| 1962 | unsigned int value; |
| 1963 | |
| 1964 | port = list_entry(v, struct tegra_pcie_port, list); |
| 1965 | |
| 1966 | value = readl(port->base + RP_VEND_XP); |
| 1967 | |
| 1968 | if (value & RP_VEND_XP_DL_UP) |
| 1969 | up = true; |
| 1970 | |
| 1971 | value = readl(port->base + RP_LINK_CONTROL_STATUS); |
| 1972 | |
| 1973 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) |
| 1974 | active = true; |
| 1975 | |
| 1976 | seq_printf(s, "%2u ", port->index); |
| 1977 | |
| 1978 | if (up) |
| 1979 | seq_printf(s, "up"); |
| 1980 | |
| 1981 | if (active) { |
| 1982 | if (up) |
| 1983 | seq_printf(s, ", "); |
| 1984 | |
| 1985 | seq_printf(s, "active"); |
| 1986 | } |
| 1987 | |
| 1988 | seq_printf(s, "\n"); |
| 1989 | return 0; |
| 1990 | } |
| 1991 | |
| 1992 | static const struct seq_operations tegra_pcie_ports_seq_ops = { |
| 1993 | .start = tegra_pcie_ports_seq_start, |
| 1994 | .next = tegra_pcie_ports_seq_next, |
| 1995 | .stop = tegra_pcie_ports_seq_stop, |
| 1996 | .show = tegra_pcie_ports_seq_show, |
| 1997 | }; |
| 1998 | |
| 1999 | static int tegra_pcie_ports_open(struct inode *inode, struct file *file) |
| 2000 | { |
| 2001 | struct tegra_pcie *pcie = inode->i_private; |
| 2002 | struct seq_file *s; |
| 2003 | int err; |
| 2004 | |
| 2005 | err = seq_open(file, &tegra_pcie_ports_seq_ops); |
| 2006 | if (err) |
| 2007 | return err; |
| 2008 | |
| 2009 | s = file->private_data; |
| 2010 | s->private = pcie; |
| 2011 | |
| 2012 | return 0; |
| 2013 | } |
| 2014 | |
| 2015 | static const struct file_operations tegra_pcie_ports_ops = { |
| 2016 | .owner = THIS_MODULE, |
| 2017 | .open = tegra_pcie_ports_open, |
| 2018 | .read = seq_read, |
| 2019 | .llseek = seq_lseek, |
| 2020 | .release = seq_release, |
| 2021 | }; |
| 2022 | |
| 2023 | static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) |
| 2024 | { |
| 2025 | struct dentry *file; |
| 2026 | |
| 2027 | pcie->debugfs = debugfs_create_dir("pcie", NULL); |
| 2028 | if (!pcie->debugfs) |
| 2029 | return -ENOMEM; |
| 2030 | |
| 2031 | file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, |
| 2032 | pcie, &tegra_pcie_ports_ops); |
| 2033 | if (!file) |
| 2034 | goto remove; |
| 2035 | |
| 2036 | return 0; |
| 2037 | |
| 2038 | remove: |
| 2039 | debugfs_remove_recursive(pcie->debugfs); |
| 2040 | pcie->debugfs = NULL; |
| 2041 | return -ENOMEM; |
| 2042 | } |
| 2043 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2044 | static int tegra_pcie_probe(struct platform_device *pdev) |
| 2045 | { |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 2046 | const struct of_device_id *match; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2047 | struct tegra_pcie *pcie; |
| 2048 | int err; |
| 2049 | |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 2050 | match = of_match_device(tegra_pcie_of_match, &pdev->dev); |
| 2051 | if (!match) |
| 2052 | return -ENODEV; |
| 2053 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2054 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); |
| 2055 | if (!pcie) |
| 2056 | return -ENOMEM; |
| 2057 | |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 2058 | INIT_LIST_HEAD(&pcie->buses); |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2059 | INIT_LIST_HEAD(&pcie->ports); |
Jay Agarwal | 94716cd | 2013-08-09 16:49:24 +0200 | [diff] [blame] | 2060 | pcie->soc_data = match->data; |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2061 | pcie->dev = &pdev->dev; |
| 2062 | |
| 2063 | err = tegra_pcie_parse_dt(pcie); |
| 2064 | if (err < 0) |
| 2065 | return err; |
| 2066 | |
| 2067 | pcibios_min_mem = 0; |
| 2068 | |
| 2069 | err = tegra_pcie_get_resources(pcie); |
| 2070 | if (err < 0) { |
| 2071 | dev_err(&pdev->dev, "failed to request resources: %d\n", err); |
| 2072 | return err; |
| 2073 | } |
| 2074 | |
| 2075 | err = tegra_pcie_enable_controller(pcie); |
| 2076 | if (err) |
| 2077 | goto put_resources; |
| 2078 | |
| 2079 | /* setup the AFI address translations */ |
| 2080 | tegra_pcie_setup_translations(pcie); |
| 2081 | |
| 2082 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| 2083 | err = tegra_pcie_enable_msi(pcie); |
| 2084 | if (err < 0) { |
| 2085 | dev_err(&pdev->dev, |
| 2086 | "failed to enable MSI support: %d\n", |
| 2087 | err); |
| 2088 | goto put_resources; |
| 2089 | } |
| 2090 | } |
| 2091 | |
| 2092 | err = tegra_pcie_enable(pcie); |
| 2093 | if (err < 0) { |
| 2094 | dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err); |
| 2095 | goto disable_msi; |
| 2096 | } |
| 2097 | |
Thierry Reding | 2cb989f | 2014-07-22 12:30:46 -0600 | [diff] [blame] | 2098 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
| 2099 | err = tegra_pcie_debugfs_init(pcie); |
| 2100 | if (err < 0) |
| 2101 | dev_err(&pdev->dev, "failed to setup debugfs: %d\n", |
| 2102 | err); |
| 2103 | } |
| 2104 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2105 | platform_set_drvdata(pdev, pcie); |
| 2106 | return 0; |
| 2107 | |
| 2108 | disable_msi: |
| 2109 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
| 2110 | tegra_pcie_disable_msi(pcie); |
| 2111 | put_resources: |
| 2112 | tegra_pcie_put_resources(pcie); |
| 2113 | return err; |
| 2114 | } |
| 2115 | |
Thierry Reding | d1523b5 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 2116 | static struct platform_driver tegra_pcie_driver = { |
| 2117 | .driver = { |
| 2118 | .name = "tegra-pcie", |
| 2119 | .owner = THIS_MODULE, |
| 2120 | .of_match_table = tegra_pcie_of_match, |
| 2121 | .suppress_bind_attrs = true, |
| 2122 | }, |
| 2123 | .probe = tegra_pcie_probe, |
| 2124 | }; |
| 2125 | module_platform_driver(tegra_pcie_driver); |
| 2126 | |
| 2127 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); |
| 2128 | MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver"); |
Thierry Reding | d975cb5 | 2014-07-11 08:58:58 +0200 | [diff] [blame] | 2129 | MODULE_LICENSE("GPL v2"); |