Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2010 Intel Corporation |
| 3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Eric Anholt <eric@anholt.net> |
| 26 | * Dave Airlie <airlied@linux.ie> |
| 27 | * Jesse Barnes <jesse.barnes@intel.com> |
| 28 | * Chris Wilson <chris@chris-wilson.co.uk> |
| 29 | */ |
| 30 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 32 | |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 33 | #include <linux/moduleparam.h> |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
| 35 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 36 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ |
| 37 | |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 38 | void |
Ville Syrjälä | 4c6df4b | 2013-09-02 21:13:39 +0300 | [diff] [blame] | 39 | intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 40 | struct drm_display_mode *adjusted_mode) |
| 41 | { |
Ville Syrjälä | 4c6df4b | 2013-09-02 21:13:39 +0300 | [diff] [blame] | 42 | drm_mode_copy(adjusted_mode, fixed_mode); |
Imre Deak | a52690e | 2013-08-27 12:24:09 +0300 | [diff] [blame] | 43 | |
| 44 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | /* adjusted_mode has been preset to be the panel's fixed mode */ |
| 48 | void |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 49 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
| 50 | struct intel_crtc_config *pipe_config, |
| 51 | int fitting_mode) |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 52 | { |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 53 | struct drm_display_mode *adjusted_mode; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 54 | int x, y, width, height; |
| 55 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 56 | adjusted_mode = &pipe_config->adjusted_mode; |
| 57 | |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 58 | x = y = width = height = 0; |
| 59 | |
| 60 | /* Native modes don't need fitting */ |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 61 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
| 62 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 63 | goto done; |
| 64 | |
| 65 | switch (fitting_mode) { |
| 66 | case DRM_MODE_SCALE_CENTER: |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 67 | width = pipe_config->pipe_src_w; |
| 68 | height = pipe_config->pipe_src_h; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 69 | x = (adjusted_mode->hdisplay - width + 1)/2; |
| 70 | y = (adjusted_mode->vdisplay - height + 1)/2; |
| 71 | break; |
| 72 | |
| 73 | case DRM_MODE_SCALE_ASPECT: |
| 74 | /* Scale but preserve the aspect ratio */ |
| 75 | { |
Daniel Vetter | 9084e7d | 2013-09-16 23:43:45 +0200 | [diff] [blame] | 76 | u32 scaled_width = adjusted_mode->hdisplay |
| 77 | * pipe_config->pipe_src_h; |
| 78 | u32 scaled_height = pipe_config->pipe_src_w |
| 79 | * adjusted_mode->vdisplay; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 80 | if (scaled_width > scaled_height) { /* pillar */ |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 81 | width = scaled_height / pipe_config->pipe_src_h; |
Adam Jackson | 302983e | 2011-07-13 16:32:32 -0400 | [diff] [blame] | 82 | if (width & 1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 83 | width++; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 84 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
| 85 | y = 0; |
| 86 | height = adjusted_mode->vdisplay; |
| 87 | } else if (scaled_width < scaled_height) { /* letter */ |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 88 | height = scaled_width / pipe_config->pipe_src_w; |
Adam Jackson | 302983e | 2011-07-13 16:32:32 -0400 | [diff] [blame] | 89 | if (height & 1) |
| 90 | height++; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 91 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
| 92 | x = 0; |
| 93 | width = adjusted_mode->hdisplay; |
| 94 | } else { |
| 95 | x = y = 0; |
| 96 | width = adjusted_mode->hdisplay; |
| 97 | height = adjusted_mode->vdisplay; |
| 98 | } |
| 99 | } |
| 100 | break; |
| 101 | |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 102 | case DRM_MODE_SCALE_FULLSCREEN: |
| 103 | x = y = 0; |
| 104 | width = adjusted_mode->hdisplay; |
| 105 | height = adjusted_mode->vdisplay; |
| 106 | break; |
Jesse Barnes | ab3e67f | 2013-04-25 12:55:03 -0700 | [diff] [blame] | 107 | |
| 108 | default: |
| 109 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); |
| 110 | return; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | done: |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 114 | pipe_config->pch_pfit.pos = (x << 16) | y; |
| 115 | pipe_config->pch_pfit.size = (width << 16) | height; |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 116 | pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 117 | } |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 118 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 119 | static void |
| 120 | centre_horizontally(struct drm_display_mode *mode, |
| 121 | int width) |
| 122 | { |
| 123 | u32 border, sync_pos, blank_width, sync_width; |
| 124 | |
| 125 | /* keep the hsync and hblank widths constant */ |
| 126 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 127 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 128 | sync_pos = (blank_width - sync_width + 1) / 2; |
| 129 | |
| 130 | border = (mode->hdisplay - width + 1) / 2; |
| 131 | border += border & 1; /* make the border even */ |
| 132 | |
| 133 | mode->crtc_hdisplay = width; |
| 134 | mode->crtc_hblank_start = width + border; |
| 135 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; |
| 136 | |
| 137 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; |
| 138 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; |
| 139 | } |
| 140 | |
| 141 | static void |
| 142 | centre_vertically(struct drm_display_mode *mode, |
| 143 | int height) |
| 144 | { |
| 145 | u32 border, sync_pos, blank_width, sync_width; |
| 146 | |
| 147 | /* keep the vsync and vblank widths constant */ |
| 148 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 149 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 150 | sync_pos = (blank_width - sync_width + 1) / 2; |
| 151 | |
| 152 | border = (mode->vdisplay - height + 1) / 2; |
| 153 | |
| 154 | mode->crtc_vdisplay = height; |
| 155 | mode->crtc_vblank_start = height + border; |
| 156 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; |
| 157 | |
| 158 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; |
| 159 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; |
| 160 | } |
| 161 | |
| 162 | static inline u32 panel_fitter_scaling(u32 source, u32 target) |
| 163 | { |
| 164 | /* |
| 165 | * Floating point operation is not supported. So the FACTOR |
| 166 | * is defined, which can avoid the floating point computation |
| 167 | * when calculating the panel ratio. |
| 168 | */ |
| 169 | #define ACCURACY 12 |
| 170 | #define FACTOR (1 << ACCURACY) |
| 171 | u32 ratio = source * FACTOR / target; |
| 172 | return (FACTOR * ratio + FACTOR/2) / FACTOR; |
| 173 | } |
| 174 | |
Daniel Vetter | 9084e7d | 2013-09-16 23:43:45 +0200 | [diff] [blame] | 175 | static void i965_scale_aspect(struct intel_crtc_config *pipe_config, |
| 176 | u32 *pfit_control) |
| 177 | { |
| 178 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
| 179 | u32 scaled_width = adjusted_mode->hdisplay * |
| 180 | pipe_config->pipe_src_h; |
| 181 | u32 scaled_height = pipe_config->pipe_src_w * |
| 182 | adjusted_mode->vdisplay; |
| 183 | |
| 184 | /* 965+ is easy, it does everything in hw */ |
| 185 | if (scaled_width > scaled_height) |
| 186 | *pfit_control |= PFIT_ENABLE | |
| 187 | PFIT_SCALING_PILLAR; |
| 188 | else if (scaled_width < scaled_height) |
| 189 | *pfit_control |= PFIT_ENABLE | |
| 190 | PFIT_SCALING_LETTER; |
| 191 | else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w) |
| 192 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; |
| 193 | } |
| 194 | |
| 195 | static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config, |
| 196 | u32 *pfit_control, u32 *pfit_pgm_ratios, |
| 197 | u32 *border) |
| 198 | { |
| 199 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
| 200 | u32 scaled_width = adjusted_mode->hdisplay * |
| 201 | pipe_config->pipe_src_h; |
| 202 | u32 scaled_height = pipe_config->pipe_src_w * |
| 203 | adjusted_mode->vdisplay; |
| 204 | u32 bits; |
| 205 | |
| 206 | /* |
| 207 | * For earlier chips we have to calculate the scaling |
| 208 | * ratio by hand and program it into the |
| 209 | * PFIT_PGM_RATIO register |
| 210 | */ |
| 211 | if (scaled_width > scaled_height) { /* pillar */ |
| 212 | centre_horizontally(adjusted_mode, |
| 213 | scaled_height / |
| 214 | pipe_config->pipe_src_h); |
| 215 | |
| 216 | *border = LVDS_BORDER_ENABLE; |
| 217 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) { |
| 218 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, |
| 219 | adjusted_mode->vdisplay); |
| 220 | |
| 221 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | |
| 222 | bits << PFIT_VERT_SCALE_SHIFT); |
| 223 | *pfit_control |= (PFIT_ENABLE | |
| 224 | VERT_INTERP_BILINEAR | |
| 225 | HORIZ_INTERP_BILINEAR); |
| 226 | } |
| 227 | } else if (scaled_width < scaled_height) { /* letter */ |
| 228 | centre_vertically(adjusted_mode, |
| 229 | scaled_width / |
| 230 | pipe_config->pipe_src_w); |
| 231 | |
| 232 | *border = LVDS_BORDER_ENABLE; |
| 233 | if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) { |
| 234 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, |
| 235 | adjusted_mode->hdisplay); |
| 236 | |
| 237 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | |
| 238 | bits << PFIT_VERT_SCALE_SHIFT); |
| 239 | *pfit_control |= (PFIT_ENABLE | |
| 240 | VERT_INTERP_BILINEAR | |
| 241 | HORIZ_INTERP_BILINEAR); |
| 242 | } |
| 243 | } else { |
| 244 | /* Aspects match, Let hw scale both directions */ |
| 245 | *pfit_control |= (PFIT_ENABLE | |
| 246 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | |
| 247 | VERT_INTERP_BILINEAR | |
| 248 | HORIZ_INTERP_BILINEAR); |
| 249 | } |
| 250 | } |
| 251 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 252 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, |
| 253 | struct intel_crtc_config *pipe_config, |
| 254 | int fitting_mode) |
| 255 | { |
| 256 | struct drm_device *dev = intel_crtc->base.dev; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 257 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 258 | struct drm_display_mode *adjusted_mode; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 259 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 260 | adjusted_mode = &pipe_config->adjusted_mode; |
| 261 | |
| 262 | /* Native modes don't need fitting */ |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 263 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
| 264 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 265 | goto out; |
| 266 | |
| 267 | switch (fitting_mode) { |
| 268 | case DRM_MODE_SCALE_CENTER: |
| 269 | /* |
| 270 | * For centered modes, we have to calculate border widths & |
| 271 | * heights and modify the values programmed into the CRTC. |
| 272 | */ |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 273 | centre_horizontally(adjusted_mode, pipe_config->pipe_src_w); |
| 274 | centre_vertically(adjusted_mode, pipe_config->pipe_src_h); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 275 | border = LVDS_BORDER_ENABLE; |
| 276 | break; |
| 277 | case DRM_MODE_SCALE_ASPECT: |
| 278 | /* Scale but preserve the aspect ratio */ |
Daniel Vetter | 9084e7d | 2013-09-16 23:43:45 +0200 | [diff] [blame] | 279 | if (INTEL_INFO(dev)->gen >= 4) |
| 280 | i965_scale_aspect(pipe_config, &pfit_control); |
| 281 | else |
| 282 | i9xx_scale_aspect(pipe_config, &pfit_control, |
| 283 | &pfit_pgm_ratios, &border); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 284 | break; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 285 | case DRM_MODE_SCALE_FULLSCREEN: |
| 286 | /* |
| 287 | * Full scaling, even if it changes the aspect ratio. |
| 288 | * Fortunately this is all done for us in hw. |
| 289 | */ |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 290 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay || |
| 291 | pipe_config->pipe_src_w != adjusted_mode->hdisplay) { |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 292 | pfit_control |= PFIT_ENABLE; |
| 293 | if (INTEL_INFO(dev)->gen >= 4) |
| 294 | pfit_control |= PFIT_SCALING_AUTO; |
| 295 | else |
| 296 | pfit_control |= (VERT_AUTO_SCALE | |
| 297 | VERT_INTERP_BILINEAR | |
| 298 | HORIZ_AUTO_SCALE | |
| 299 | HORIZ_INTERP_BILINEAR); |
| 300 | } |
| 301 | break; |
Jesse Barnes | ab3e67f | 2013-04-25 12:55:03 -0700 | [diff] [blame] | 302 | default: |
| 303 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); |
| 304 | return; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* 965+ wants fuzzy fitting */ |
| 308 | /* FIXME: handle multiple panels by failing gracefully */ |
| 309 | if (INTEL_INFO(dev)->gen >= 4) |
| 310 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
| 311 | PFIT_FILTER_FUZZY); |
| 312 | |
| 313 | out: |
| 314 | if ((pfit_control & PFIT_ENABLE) == 0) { |
| 315 | pfit_control = 0; |
| 316 | pfit_pgm_ratios = 0; |
| 317 | } |
| 318 | |
| 319 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ |
| 320 | if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) |
| 321 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
| 322 | |
Daniel Vetter | 2deefda | 2013-04-25 22:52:17 +0200 | [diff] [blame] | 323 | pipe_config->gmch_pfit.control = pfit_control; |
| 324 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; |
Daniel Vetter | 68fc874 | 2013-04-25 22:52:16 +0200 | [diff] [blame] | 325 | pipe_config->gmch_pfit.lvds_border_bits = border; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 326 | } |
| 327 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 328 | static int is_backlight_combination_mode(struct drm_device *dev) |
| 329 | { |
| 330 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 331 | |
Jani Nikula | d9c638d | 2013-09-24 16:44:39 +0300 | [diff] [blame] | 332 | if (IS_GEN4(dev)) |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 333 | return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; |
| 334 | |
| 335 | if (IS_GEN2(dev)) |
| 336 | return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; |
| 337 | |
| 338 | return 0; |
| 339 | } |
| 340 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 341 | /* XXX: query mode clock or hardware clock and program max PWM appropriately |
| 342 | * when it's 0. |
| 343 | */ |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 344 | static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe) |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 345 | { |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 346 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 347 | u32 val; |
| 348 | |
Ville Syrjälä | df0a679 | 2013-05-22 11:36:40 +0300 | [diff] [blame] | 349 | WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock)); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 350 | |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 351 | /* Restore the CTL value if it lost, e.g. GPU reset */ |
| 352 | |
| 353 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 354 | val = I915_READ(BLC_PWM_PCH_CTL2); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 355 | if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { |
| 356 | dev_priv->regfile.saveBLC_PWM_CTL2 = val; |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 357 | } else if (val == 0) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 358 | val = dev_priv->regfile.saveBLC_PWM_CTL2; |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 359 | I915_WRITE(BLC_PWM_PCH_CTL2, val); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 360 | } |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 361 | } else if (IS_VALLEYVIEW(dev)) { |
| 362 | val = I915_READ(VLV_BLC_PWM_CTL(pipe)); |
| 363 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { |
| 364 | dev_priv->regfile.saveBLC_PWM_CTL = val; |
| 365 | dev_priv->regfile.saveBLC_PWM_CTL2 = |
| 366 | I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
| 367 | } else if (val == 0) { |
| 368 | val = dev_priv->regfile.saveBLC_PWM_CTL; |
| 369 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), val); |
| 370 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), |
| 371 | dev_priv->regfile.saveBLC_PWM_CTL2); |
| 372 | } |
| 373 | |
| 374 | if (!val) |
| 375 | val = 0x0f42ffff; |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 376 | } else { |
| 377 | val = I915_READ(BLC_PWM_CTL); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 378 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { |
| 379 | dev_priv->regfile.saveBLC_PWM_CTL = val; |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 380 | if (INTEL_INFO(dev)->gen >= 4) |
| 381 | dev_priv->regfile.saveBLC_PWM_CTL2 = |
| 382 | I915_READ(BLC_PWM_CTL2); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 383 | } else if (val == 0) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 384 | val = dev_priv->regfile.saveBLC_PWM_CTL; |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 385 | I915_WRITE(BLC_PWM_CTL, val); |
| 386 | if (INTEL_INFO(dev)->gen >= 4) |
| 387 | I915_WRITE(BLC_PWM_CTL2, |
| 388 | dev_priv->regfile.saveBLC_PWM_CTL2); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 389 | } |
| 390 | } |
| 391 | |
| 392 | return val; |
| 393 | } |
| 394 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 395 | static u32 intel_panel_get_max_backlight(struct drm_device *dev, |
| 396 | enum pipe pipe) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 397 | { |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 398 | u32 max; |
| 399 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 400 | max = i915_read_blc_pwm_ctl(dev, pipe); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 401 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 402 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 403 | max >>= 16; |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 404 | } else { |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 405 | if (INTEL_INFO(dev)->gen < 4) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 406 | max >>= 17; |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 407 | else |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 408 | max >>= 16; |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 409 | |
| 410 | if (is_backlight_combination_mode(dev)) |
| 411 | max *= 0xff; |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 412 | } |
| 413 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 414 | DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 415 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 416 | return max; |
| 417 | } |
| 418 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 419 | static int i915_panel_invert_brightness; |
| 420 | MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness " |
| 421 | "(-1 force normal, 0 machine defaults, 1 force inversion), please " |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 422 | "report PCI device ID, subsystem vendor and subsystem device ID " |
| 423 | "to dri-devel@lists.freedesktop.org, if your machine needs it. " |
| 424 | "It will then be included in an upcoming module version."); |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 425 | module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 426 | static u32 intel_panel_compute_brightness(struct drm_device *dev, |
| 427 | enum pipe pipe, u32 val) |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 428 | { |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 429 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 430 | |
| 431 | if (i915_panel_invert_brightness < 0) |
| 432 | return val; |
| 433 | |
| 434 | if (i915_panel_invert_brightness > 0 || |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 435 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 436 | u32 max = intel_panel_get_max_backlight(dev, pipe); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 437 | if (max) |
| 438 | return max - val; |
| 439 | } |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 440 | |
| 441 | return val; |
| 442 | } |
| 443 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 444 | static u32 intel_panel_get_backlight(struct drm_device *dev, |
| 445 | enum pipe pipe) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 446 | { |
| 447 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 448 | u32 val; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 449 | unsigned long flags; |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 450 | int reg; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 451 | |
| 452 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 453 | |
| 454 | if (HAS_PCH_SPLIT(dev)) { |
| 455 | val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
| 456 | } else { |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 457 | if (IS_VALLEYVIEW(dev)) |
| 458 | reg = VLV_BLC_PWM_CTL(pipe); |
| 459 | else |
| 460 | reg = BLC_PWM_CTL; |
| 461 | |
| 462 | val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK; |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 463 | if (INTEL_INFO(dev)->gen < 4) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 464 | val >>= 1; |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 465 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 466 | if (is_backlight_combination_mode(dev)) { |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 467 | u8 lbpc; |
| 468 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 469 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
| 470 | val *= lbpc; |
| 471 | } |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 472 | } |
| 473 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 474 | val = intel_panel_compute_brightness(dev, pipe, val); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 475 | |
| 476 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
| 477 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 478 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
| 479 | return val; |
| 480 | } |
| 481 | |
| 482 | static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) |
| 483 | { |
| 484 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 485 | u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
| 486 | I915_WRITE(BLC_PWM_CPU_CTL, val | level); |
| 487 | } |
| 488 | |
Daniel Vetter | 9084e7d | 2013-09-16 23:43:45 +0200 | [diff] [blame] | 489 | static void intel_panel_actually_set_backlight(struct drm_device *dev, |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 490 | enum pipe pipe, u32 level) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 491 | { |
| 492 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 493 | u32 tmp; |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 494 | int reg; |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 495 | |
| 496 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 497 | level = intel_panel_compute_brightness(dev, pipe, level); |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 498 | |
| 499 | if (HAS_PCH_SPLIT(dev)) |
| 500 | return intel_pch_panel_set_backlight(dev, level); |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 501 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 502 | if (is_backlight_combination_mode(dev)) { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 503 | u32 max = intel_panel_get_max_backlight(dev, pipe); |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 504 | u8 lbpc; |
| 505 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 506 | /* we're screwed, but keep behaviour backwards compatible */ |
| 507 | if (!max) |
| 508 | max = 1; |
| 509 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 510 | lbpc = level * 0xfe / max + 1; |
| 511 | level /= lbpc; |
| 512 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); |
| 513 | } |
| 514 | |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 515 | if (IS_VALLEYVIEW(dev)) |
| 516 | reg = VLV_BLC_PWM_CTL(pipe); |
| 517 | else |
| 518 | reg = BLC_PWM_CTL; |
| 519 | |
| 520 | tmp = I915_READ(reg); |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 521 | if (INTEL_INFO(dev)->gen < 4) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 522 | level <<= 1; |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 523 | tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 524 | I915_WRITE(reg, tmp | level); |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 525 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 526 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 527 | /* set backlight brightness to level in range [0..max] */ |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 528 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
| 529 | u32 max) |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 530 | { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 531 | struct drm_device *dev = connector->base.dev; |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 532 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 533 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 534 | u32 freq; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 535 | unsigned long flags; |
| 536 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 537 | if (pipe == INVALID_PIPE) |
| 538 | return; |
| 539 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 540 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 541 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 542 | freq = intel_panel_get_max_backlight(dev, pipe); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 543 | if (!freq) { |
| 544 | /* we are screwed, bail out */ |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 545 | goto out; |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 546 | } |
| 547 | |
Aaron Lu | 22505b8 | 2013-08-02 09:16:03 +0800 | [diff] [blame] | 548 | /* scale to hardware, but be careful to not overflow */ |
| 549 | if (freq < max) |
| 550 | level = level * freq / max; |
| 551 | else |
| 552 | level = freq / max * level; |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 553 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 554 | dev_priv->backlight.level = level; |
| 555 | if (dev_priv->backlight.device) |
| 556 | dev_priv->backlight.device->props.brightness = level; |
Jani Nikula | b6b3ba5 | 2013-03-12 11:44:15 +0200 | [diff] [blame] | 557 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 558 | if (dev_priv->backlight.enabled) |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 559 | intel_panel_actually_set_backlight(dev, pipe, level); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 560 | out: |
| 561 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 562 | } |
| 563 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 564 | void intel_panel_disable_backlight(struct intel_connector *connector) |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 565 | { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 566 | struct drm_device *dev = connector->base.dev; |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 567 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 568 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 569 | unsigned long flags; |
| 570 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 571 | if (pipe == INVALID_PIPE) |
| 572 | return; |
| 573 | |
Jani Nikula | 3f57757 | 2013-07-25 14:31:30 +0300 | [diff] [blame] | 574 | /* |
| 575 | * Do not disable backlight on the vgaswitcheroo path. When switching |
| 576 | * away from i915, the other client may depend on i915 to handle the |
| 577 | * backlight. This will leave the backlight on unnecessarily when |
| 578 | * another client is not activated. |
| 579 | */ |
| 580 | if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) { |
| 581 | DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); |
| 582 | return; |
| 583 | } |
| 584 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 585 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 586 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 587 | dev_priv->backlight.enabled = false; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 588 | intel_panel_actually_set_backlight(dev, pipe, 0); |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 589 | |
| 590 | if (INTEL_INFO(dev)->gen >= 4) { |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 591 | uint32_t reg, tmp; |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 592 | |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 593 | if (HAS_PCH_SPLIT(dev)) |
| 594 | reg = BLC_PWM_CPU_CTL2; |
| 595 | else if (IS_VALLEYVIEW(dev)) |
| 596 | reg = VLV_BLC_PWM_CTL2(pipe); |
| 597 | else |
| 598 | reg = BLC_PWM_CTL2; |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 599 | |
| 600 | I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 601 | |
| 602 | if (HAS_PCH_SPLIT(dev)) { |
| 603 | tmp = I915_READ(BLC_PWM_PCH_CTL1); |
| 604 | tmp &= ~BLM_PCH_PWM_ENABLE; |
| 605 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); |
| 606 | } |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 607 | } |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 608 | |
| 609 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 610 | } |
| 611 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 612 | void intel_panel_enable_backlight(struct intel_connector *connector) |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 613 | { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 614 | struct drm_device *dev = connector->base.dev; |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 615 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 616 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
Jani Nikula | 35ffda4 | 2013-04-25 16:49:25 +0300 | [diff] [blame] | 617 | enum transcoder cpu_transcoder = |
| 618 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 619 | unsigned long flags; |
| 620 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 621 | if (pipe == INVALID_PIPE) |
| 622 | return; |
| 623 | |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 624 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
Chris Wilson | 540b5d0 | 2013-10-13 12:56:31 +0100 | [diff] [blame] | 625 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 626 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 627 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 628 | if (dev_priv->backlight.level == 0) { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 629 | dev_priv->backlight.level = intel_panel_get_max_backlight(dev, |
| 630 | pipe); |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 631 | if (dev_priv->backlight.device) |
| 632 | dev_priv->backlight.device->props.brightness = |
| 633 | dev_priv->backlight.level; |
Jani Nikula | b6b3ba5 | 2013-03-12 11:44:15 +0200 | [diff] [blame] | 634 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 635 | |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 636 | if (INTEL_INFO(dev)->gen >= 4) { |
| 637 | uint32_t reg, tmp; |
| 638 | |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 639 | if (HAS_PCH_SPLIT(dev)) |
| 640 | reg = BLC_PWM_CPU_CTL2; |
| 641 | else if (IS_VALLEYVIEW(dev)) |
| 642 | reg = VLV_BLC_PWM_CTL2(pipe); |
| 643 | else |
| 644 | reg = BLC_PWM_CTL2; |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 645 | |
| 646 | tmp = I915_READ(reg); |
| 647 | |
| 648 | /* Note that this can also get called through dpms changes. And |
| 649 | * we don't track the backlight dpms state, hence check whether |
| 650 | * we have to do anything first. */ |
| 651 | if (tmp & BLM_PWM_ENABLE) |
Takashi Iwai | 770c123 | 2012-08-11 08:56:42 +0200 | [diff] [blame] | 652 | goto set_level; |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 653 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 654 | if (INTEL_INFO(dev)->num_pipes == 3) |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 655 | tmp &= ~BLM_PIPE_SELECT_IVB; |
| 656 | else |
| 657 | tmp &= ~BLM_PIPE_SELECT; |
| 658 | |
Jani Nikula | 35ffda4 | 2013-04-25 16:49:25 +0300 | [diff] [blame] | 659 | if (cpu_transcoder == TRANSCODER_EDP) |
| 660 | tmp |= BLM_TRANSCODER_EDP; |
| 661 | else |
| 662 | tmp |= BLM_PIPE(cpu_transcoder); |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 663 | tmp &= ~BLM_PWM_ENABLE; |
| 664 | |
| 665 | I915_WRITE(reg, tmp); |
| 666 | POSTING_READ(reg); |
| 667 | I915_WRITE(reg, tmp | BLM_PWM_ENABLE); |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 668 | |
Kamal Mostafa | e85843b | 2013-07-19 15:02:01 -0700 | [diff] [blame] | 669 | if (HAS_PCH_SPLIT(dev) && |
| 670 | !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) { |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 671 | tmp = I915_READ(BLC_PWM_PCH_CTL1); |
| 672 | tmp |= BLM_PCH_PWM_ENABLE; |
| 673 | tmp &= ~BLM_PCH_OVERRIDE_ENABLE; |
| 674 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); |
| 675 | } |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 676 | } |
Takashi Iwai | 770c123 | 2012-08-11 08:56:42 +0200 | [diff] [blame] | 677 | |
| 678 | set_level: |
Daniel Vetter | b128937 | 2013-03-22 15:44:46 +0100 | [diff] [blame] | 679 | /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. |
| 680 | * BLC_PWM_CPU_CTL may be cleared to zero automatically when these |
| 681 | * registers are set. |
Takashi Iwai | 770c123 | 2012-08-11 08:56:42 +0200 | [diff] [blame] | 682 | */ |
Daniel Vetter | ecb135a | 2013-04-03 11:25:32 +0200 | [diff] [blame] | 683 | dev_priv->backlight.enabled = true; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 684 | intel_panel_actually_set_backlight(dev, pipe, |
| 685 | dev_priv->backlight.level); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 686 | |
| 687 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 688 | } |
| 689 | |
Jesse Barnes | afc85b9 | 2013-09-25 14:04:32 -0700 | [diff] [blame] | 690 | /* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */ |
| 691 | static void intel_panel_init_backlight_regs(struct drm_device *dev) |
| 692 | { |
| 693 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 694 | |
| 695 | if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame^] | 696 | enum pipe pipe; |
| 697 | |
| 698 | for_each_pipe(pipe) { |
| 699 | u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); |
| 700 | |
| 701 | /* Skip if the modulation freq is already set */ |
| 702 | if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) |
| 703 | continue; |
| 704 | |
| 705 | cur_val &= BACKLIGHT_DUTY_CYCLE_MASK; |
| 706 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | |
| 707 | cur_val); |
| 708 | } |
Jesse Barnes | afc85b9 | 2013-09-25 14:04:32 -0700 | [diff] [blame] | 709 | } |
| 710 | } |
| 711 | |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 712 | static void intel_panel_init_backlight(struct drm_device *dev) |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 713 | { |
| 714 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 715 | |
Jesse Barnes | afc85b9 | 2013-09-25 14:04:32 -0700 | [diff] [blame] | 716 | intel_panel_init_backlight_regs(dev); |
| 717 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 718 | dev_priv->backlight.level = intel_panel_get_backlight(dev, 0); |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 719 | dev_priv->backlight.enabled = dev_priv->backlight.level != 0; |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 720 | } |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 721 | |
| 722 | enum drm_connector_status |
| 723 | intel_panel_detect(struct drm_device *dev) |
| 724 | { |
| 725 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 726 | |
| 727 | /* Assume that the BIOS does not lie through the OpRegion... */ |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 728 | if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) { |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 729 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? |
| 730 | connector_status_connected : |
| 731 | connector_status_disconnected; |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 732 | } |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 733 | |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 734 | switch (i915_panel_ignore_lid) { |
| 735 | case -2: |
| 736 | return connector_status_connected; |
| 737 | case -1: |
| 738 | return connector_status_disconnected; |
| 739 | default: |
| 740 | return connector_status_unknown; |
| 741 | } |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 742 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 743 | |
Jani Nikula | 912e8b1 | 2013-09-18 17:19:45 +0300 | [diff] [blame] | 744 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 745 | static int intel_panel_update_status(struct backlight_device *bd) |
| 746 | { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 747 | struct intel_connector *connector = bl_get_data(bd); |
| 748 | struct drm_device *dev = connector->base.dev; |
| 749 | |
| 750 | mutex_lock(&dev->mode_config.mutex); |
Chris Wilson | 540b5d0 | 2013-10-13 12:56:31 +0100 | [diff] [blame] | 751 | DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n", |
| 752 | bd->props.brightness, bd->props.max_brightness); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 753 | intel_panel_set_backlight(connector, bd->props.brightness, |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 754 | bd->props.max_brightness); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 755 | mutex_unlock(&dev->mode_config.mutex); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 756 | return 0; |
| 757 | } |
| 758 | |
| 759 | static int intel_panel_get_brightness(struct backlight_device *bd) |
| 760 | { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 761 | struct intel_connector *connector = bl_get_data(bd); |
| 762 | struct drm_device *dev = connector->base.dev; |
| 763 | enum pipe pipe; |
| 764 | |
| 765 | mutex_lock(&dev->mode_config.mutex); |
| 766 | pipe = intel_get_pipe_from_connector(connector); |
| 767 | mutex_unlock(&dev->mode_config.mutex); |
| 768 | if (pipe == INVALID_PIPE) |
| 769 | return 0; |
| 770 | |
| 771 | return intel_panel_get_backlight(connector->base.dev, pipe); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static const struct backlight_ops intel_panel_bl_ops = { |
| 775 | .update_status = intel_panel_update_status, |
| 776 | .get_brightness = intel_panel_get_brightness, |
| 777 | }; |
| 778 | |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 779 | int intel_panel_setup_backlight(struct drm_connector *connector) |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 780 | { |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 781 | struct drm_device *dev = connector->dev; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 782 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 783 | struct backlight_properties props; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 784 | unsigned long flags; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 785 | |
| 786 | intel_panel_init_backlight(dev); |
| 787 | |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 788 | if (WARN_ON(dev_priv->backlight.device)) |
| 789 | return -ENODEV; |
| 790 | |
Corentin Chary | af437cf | 2012-05-22 10:29:46 +0100 | [diff] [blame] | 791 | memset(&props, 0, sizeof(props)); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 792 | props.type = BACKLIGHT_RAW; |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 793 | props.brightness = dev_priv->backlight.level; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 794 | |
| 795 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 796 | props.max_brightness = intel_panel_get_max_backlight(dev, 0); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 797 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
| 798 | |
Jani Nikula | 28dcc2d | 2012-09-03 16:25:12 +0300 | [diff] [blame] | 799 | if (props.max_brightness == 0) { |
Jani Nikula | e86b618 | 2012-10-25 10:57:38 +0300 | [diff] [blame] | 800 | DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n"); |
Jani Nikula | 28dcc2d | 2012-09-03 16:25:12 +0300 | [diff] [blame] | 801 | return -ENODEV; |
| 802 | } |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 803 | dev_priv->backlight.device = |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 804 | backlight_device_register("intel_backlight", |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 805 | &connector->kdev, |
| 806 | to_intel_connector(connector), |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 807 | &intel_panel_bl_ops, &props); |
| 808 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 809 | if (IS_ERR(dev_priv->backlight.device)) { |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 810 | DRM_ERROR("Failed to register backlight: %ld\n", |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 811 | PTR_ERR(dev_priv->backlight.device)); |
| 812 | dev_priv->backlight.device = NULL; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 813 | return -ENODEV; |
| 814 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 815 | return 0; |
| 816 | } |
| 817 | |
| 818 | void intel_panel_destroy_backlight(struct drm_device *dev) |
| 819 | { |
| 820 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 821 | if (dev_priv->backlight.device) { |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 822 | backlight_device_unregister(dev_priv->backlight.device); |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 823 | dev_priv->backlight.device = NULL; |
| 824 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 825 | } |
| 826 | #else |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 827 | int intel_panel_setup_backlight(struct drm_connector *connector) |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 828 | { |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 829 | intel_panel_init_backlight(connector->dev); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 830 | return 0; |
| 831 | } |
| 832 | |
| 833 | void intel_panel_destroy_backlight(struct drm_device *dev) |
| 834 | { |
| 835 | return; |
| 836 | } |
| 837 | #endif |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 838 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 839 | int intel_panel_init(struct intel_panel *panel, |
| 840 | struct drm_display_mode *fixed_mode) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 841 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 842 | panel->fixed_mode = fixed_mode; |
| 843 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 844 | return 0; |
| 845 | } |
| 846 | |
| 847 | void intel_panel_fini(struct intel_panel *panel) |
| 848 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 849 | struct intel_connector *intel_connector = |
| 850 | container_of(panel, struct intel_connector, panel); |
| 851 | |
| 852 | if (panel->fixed_mode) |
| 853 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 854 | } |