blob: 4d863ebc117c0f59cce46f39fda4d191e93b9843 [file] [log] [blame]
Richard Zhaob3d99682012-07-07 22:56:47 +08001/*
Peter Chen43f36342014-08-26 10:55:17 +08002 * Copyright 2012-2014 Freescale Semiconductor, Inc.
Richard Zhaob3d99682012-07-07 22:56:47 +08003 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
4 * on behalf of DENX Software Engineering GmbH
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/usb/otg.h>
19#include <linux/stmp_device.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/io.h>
Peter Chen24007802014-02-24 10:20:54 +080023#include <linux/of_device.h>
Peter Chen0d896532014-02-24 10:20:57 +080024#include <linux/regmap.h>
25#include <linux/mfd/syscon.h>
Richard Zhaob3d99682012-07-07 22:56:47 +080026
27#define DRIVER_NAME "mxs_phy"
28
29#define HW_USBPHY_PWD 0x00
30#define HW_USBPHY_CTRL 0x30
31#define HW_USBPHY_CTRL_SET 0x34
32#define HW_USBPHY_CTRL_CLR 0x38
33
Peter Chen3f126502014-02-24 10:21:02 +080034#define HW_USBPHY_DEBUG_SET 0x54
35#define HW_USBPHY_DEBUG_CLR 0x58
36
Peter Chen22db05e2014-02-24 10:20:59 +080037#define HW_USBPHY_IP 0x90
38#define HW_USBPHY_IP_SET 0x94
39#define HW_USBPHY_IP_CLR 0x98
40
Richard Zhaob3d99682012-07-07 22:56:47 +080041#define BM_USBPHY_CTRL_SFTRST BIT(31)
42#define BM_USBPHY_CTRL_CLKGATE BIT(30)
Li Jun7b09e672015-01-16 18:28:59 +080043#define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
Peter Chen13644142014-02-24 10:20:55 +080044#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
45#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
Peter Chen3f126502014-02-24 10:21:02 +080046#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
47#define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
48#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
Peter Chen13644142014-02-24 10:20:55 +080049#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
50#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
51#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
Richard Zhaob3d99682012-07-07 22:56:47 +080052#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
53#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
54#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
55
Peter Chen22db05e2014-02-24 10:20:59 +080056#define BM_USBPHY_IP_FIX (BIT(17) | BIT(18))
57
Peter Chen3f126502014-02-24 10:21:02 +080058#define BM_USBPHY_DEBUG_CLKGATE BIT(30)
59
60/* Anatop Registers */
Peter Chenbf783432014-02-24 10:21:03 +080061#define ANADIG_ANA_MISC0 0x150
62#define ANADIG_ANA_MISC0_SET 0x154
63#define ANADIG_ANA_MISC0_CLR 0x158
64
Peter Chen3f126502014-02-24 10:21:02 +080065#define ANADIG_USB1_VBUS_DET_STAT 0x1c0
66#define ANADIG_USB2_VBUS_DET_STAT 0x220
67
68#define ANADIG_USB1_LOOPBACK_SET 0x1e4
69#define ANADIG_USB1_LOOPBACK_CLR 0x1e8
70#define ANADIG_USB2_LOOPBACK_SET 0x244
71#define ANADIG_USB2_LOOPBACK_CLR 0x248
72
Peter Chenefdbd3a2015-01-16 18:29:00 +080073#define ANADIG_USB1_MISC 0x1f0
74#define ANADIG_USB2_MISC 0x250
75
Peter Chenbf783432014-02-24 10:21:03 +080076#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
77#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
78
Peter Chen3f126502014-02-24 10:21:02 +080079#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
80#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
81
82#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
83#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
84#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
85#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
86
Peter Chenefdbd3a2015-01-16 18:29:00 +080087#define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
88#define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
89#define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
90#define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
91
Peter Chen24007802014-02-24 10:20:54 +080092#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
93
94/* Do disconnection between PHY and controller without vbus */
95#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
96
97/*
98 * The PHY will be in messy if there is a wakeup after putting
99 * bus to suspend (set portsc.suspendM) but before setting PHY to low
100 * power mode (set portsc.phcd).
101 */
102#define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1)
103
104/*
105 * The SOF sends too fast after resuming, it will cause disconnection
106 * between host and high speed device.
107 */
108#define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
109
Peter Chen22db05e2014-02-24 10:20:59 +0800110/*
111 * IC has bug fixes logic, they include
112 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
113 * which are described at above flags, the RTL will handle it
114 * according to different versions.
115 */
116#define MXS_PHY_NEED_IP_FIX BIT(3)
117
Peter Chen24007802014-02-24 10:20:54 +0800118struct mxs_phy_data {
119 unsigned int flags;
120};
121
122static const struct mxs_phy_data imx23_phy_data = {
123 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
124};
125
126static const struct mxs_phy_data imx6q_phy_data = {
127 .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
Peter Chen22db05e2014-02-24 10:20:59 +0800128 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
129 MXS_PHY_NEED_IP_FIX,
Peter Chen24007802014-02-24 10:20:54 +0800130};
131
132static const struct mxs_phy_data imx6sl_phy_data = {
Peter Chen22db05e2014-02-24 10:20:59 +0800133 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
134 MXS_PHY_NEED_IP_FIX,
Peter Chen24007802014-02-24 10:20:54 +0800135};
136
Stefan Agnerd0ee68b2014-07-28 16:57:29 +0200137static const struct mxs_phy_data vf610_phy_data = {
138 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
139 MXS_PHY_NEED_IP_FIX,
140};
141
Peter Chen43f36342014-08-26 10:55:17 +0800142static const struct mxs_phy_data imx6sx_phy_data = {
Peter Chendd811ba2015-01-16 18:28:58 +0800143 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
Peter Chen43f36342014-08-26 10:55:17 +0800144};
145
Peter Chen24007802014-02-24 10:20:54 +0800146static const struct of_device_id mxs_phy_dt_ids[] = {
Peter Chen43f36342014-08-26 10:55:17 +0800147 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
Peter Chen24007802014-02-24 10:20:54 +0800148 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
149 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
150 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
Stefan Agnerd0ee68b2014-07-28 16:57:29 +0200151 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
Peter Chen24007802014-02-24 10:20:54 +0800152 { /* sentinel */ }
153};
154MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
155
Richard Zhaob3d99682012-07-07 22:56:47 +0800156struct mxs_phy {
157 struct usb_phy phy;
158 struct clk *clk;
Peter Chen24007802014-02-24 10:20:54 +0800159 const struct mxs_phy_data *data;
Peter Chen0d896532014-02-24 10:20:57 +0800160 struct regmap *regmap_anatop;
Peter Chen83be1812014-02-24 10:21:00 +0800161 int port_id;
Richard Zhaob3d99682012-07-07 22:56:47 +0800162};
163
Peter Chenbf783432014-02-24 10:21:03 +0800164static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
165{
166 return mxs_phy->data == &imx6q_phy_data;
167}
168
169static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
170{
171 return mxs_phy->data == &imx6sl_phy_data;
172}
173
Peter Chen47d18452014-02-24 10:21:04 +0800174/*
175 * PHY needs some 32K cycles to switch from 32K clock to
176 * bus (such as AHB/AXI, etc) clock.
177 */
178static void mxs_phy_clock_switch_delay(void)
179{
180 usleep_range(300, 400);
181}
182
Fabio Estevam51e563e2013-07-03 16:34:13 -0300183static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
Richard Zhaob3d99682012-07-07 22:56:47 +0800184{
Fabio Estevam51e563e2013-07-03 16:34:13 -0300185 int ret;
Richard Zhaob3d99682012-07-07 22:56:47 +0800186 void __iomem *base = mxs_phy->phy.io_priv;
187
Fabio Estevam51e563e2013-07-03 16:34:13 -0300188 ret = stmp_reset_block(base + HW_USBPHY_CTRL);
189 if (ret)
190 return ret;
Richard Zhaob3d99682012-07-07 22:56:47 +0800191
192 /* Power up the PHY */
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100193 writel(0, base + HW_USBPHY_PWD);
Richard Zhaob3d99682012-07-07 22:56:47 +0800194
Peter Chen13644142014-02-24 10:20:55 +0800195 /*
196 * USB PHY Ctrl Setting
197 * - Auto clock/power on
198 * - Enable full/low speed support
199 */
200 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
201 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
202 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
203 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
204 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
205 BM_USBPHY_CTRL_ENUTMILEVEL2 |
206 BM_USBPHY_CTRL_ENUTMILEVEL3,
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100207 base + HW_USBPHY_CTRL_SET);
Fabio Estevam51e563e2013-07-03 16:34:13 -0300208
Peter Chen22db05e2014-02-24 10:20:59 +0800209 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
210 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
211
Fabio Estevam51e563e2013-07-03 16:34:13 -0300212 return 0;
Richard Zhaob3d99682012-07-07 22:56:47 +0800213}
214
Peter Chen3f126502014-02-24 10:21:02 +0800215/* Return true if the vbus is there */
216static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
217{
218 unsigned int vbus_value;
219
Stefan Wahren543aa482015-06-15 04:37:00 +0000220 if (!mxs_phy->regmap_anatop)
221 return false;
222
Peter Chen3f126502014-02-24 10:21:02 +0800223 if (mxs_phy->port_id == 0)
224 regmap_read(mxs_phy->regmap_anatop,
225 ANADIG_USB1_VBUS_DET_STAT,
226 &vbus_value);
227 else if (mxs_phy->port_id == 1)
228 regmap_read(mxs_phy->regmap_anatop,
229 ANADIG_USB2_VBUS_DET_STAT,
230 &vbus_value);
231
232 if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
233 return true;
234 else
235 return false;
236}
237
238static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
239{
240 void __iomem *base = mxs_phy->phy.io_priv;
241 u32 reg;
242
243 if (disconnect)
244 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
245 base + HW_USBPHY_DEBUG_CLR);
246
247 if (mxs_phy->port_id == 0) {
248 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
249 : ANADIG_USB1_LOOPBACK_CLR;
250 regmap_write(mxs_phy->regmap_anatop, reg,
251 BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
252 BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
253 } else if (mxs_phy->port_id == 1) {
254 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
255 : ANADIG_USB2_LOOPBACK_CLR;
256 regmap_write(mxs_phy->regmap_anatop, reg,
257 BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
258 BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
259 }
260
261 if (!disconnect)
262 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
263 base + HW_USBPHY_DEBUG_SET);
264
265 /* Delay some time, and let Linestate be SE0 for controller */
266 if (disconnect)
267 usleep_range(500, 1000);
268}
269
Li Jun7b09e672015-01-16 18:28:59 +0800270static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
271{
272 void __iomem *base = mxs_phy->phy.io_priv;
273 u32 phyctrl = readl(base + HW_USBPHY_CTRL);
274
275 if (IS_ENABLED(CONFIG_USB_OTG) &&
276 !(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE))
277 return true;
278
279 return false;
280}
281
Peter Chen3f126502014-02-24 10:21:02 +0800282static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
283{
284 bool vbus_is_on = false;
285
286 /* If the SoCs don't need to disconnect line without vbus, quit */
287 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
288 return;
289
290 /* If the SoCs don't have anatop, quit */
291 if (!mxs_phy->regmap_anatop)
292 return;
293
294 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
295
Li Jun7b09e672015-01-16 18:28:59 +0800296 if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy))
Peter Chen3f126502014-02-24 10:21:02 +0800297 __mxs_phy_disconnect_line(mxs_phy, true);
298 else
299 __mxs_phy_disconnect_line(mxs_phy, false);
300
301}
302
Richard Zhaob3d99682012-07-07 22:56:47 +0800303static int mxs_phy_init(struct usb_phy *phy)
304{
Fabio Estevam67c21fc2013-12-02 01:02:34 -0200305 int ret;
Richard Zhaob3d99682012-07-07 22:56:47 +0800306 struct mxs_phy *mxs_phy = to_mxs_phy(phy);
307
Peter Chen47d18452014-02-24 10:21:04 +0800308 mxs_phy_clock_switch_delay();
Fabio Estevam67c21fc2013-12-02 01:02:34 -0200309 ret = clk_prepare_enable(mxs_phy->clk);
310 if (ret)
311 return ret;
312
Fabio Estevam51e563e2013-07-03 16:34:13 -0300313 return mxs_phy_hw_init(mxs_phy);
Richard Zhaob3d99682012-07-07 22:56:47 +0800314}
315
316static void mxs_phy_shutdown(struct usb_phy *phy)
317{
318 struct mxs_phy *mxs_phy = to_mxs_phy(phy);
Peter Chenfdf80e72014-12-24 13:48:02 +0800319 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
320 BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
321 BM_USBPHY_CTRL_ENIDCHG_WKUP |
322 BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
323 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
324 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
325 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
326 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL;
327
328 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
329 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
Richard Zhaob3d99682012-07-07 22:56:47 +0800330
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100331 writel(BM_USBPHY_CTRL_CLKGATE,
332 phy->io_priv + HW_USBPHY_CTRL_SET);
Richard Zhaob3d99682012-07-07 22:56:47 +0800333
334 clk_disable_unprepare(mxs_phy->clk);
335}
336
Peter Chenefdbd3a2015-01-16 18:29:00 +0800337static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
338{
339 unsigned int line_state;
340 /* bit definition is the same for all controllers */
341 unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
342 dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
343 unsigned int reg = ANADIG_USB1_MISC;
344
345 /* If the SoCs don't have anatop, quit */
346 if (!mxs_phy->regmap_anatop)
347 return false;
348
349 if (mxs_phy->port_id == 0)
350 reg = ANADIG_USB1_MISC;
351 else if (mxs_phy->port_id == 1)
352 reg = ANADIG_USB2_MISC;
353
354 regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
355
356 if ((line_state & (dp_bit | dm_bit)) == dm_bit)
357 return true;
358 else
359 return false;
360}
361
Peter Chen04a62212013-01-10 16:35:53 +0800362static int mxs_phy_suspend(struct usb_phy *x, int suspend)
363{
Fabio Estevam67c21fc2013-12-02 01:02:34 -0200364 int ret;
Peter Chen04a62212013-01-10 16:35:53 +0800365 struct mxs_phy *mxs_phy = to_mxs_phy(x);
Peter Chenefdbd3a2015-01-16 18:29:00 +0800366 bool low_speed_connection, vbus_is_on;
367
368 low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
369 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
Peter Chen04a62212013-01-10 16:35:53 +0800370
371 if (suspend) {
Peter Chenefdbd3a2015-01-16 18:29:00 +0800372 /*
373 * FIXME: Do not power down RXPWD1PT1 bit for low speed
374 * connect. The low speed connection will have problem at
375 * very rare cases during usb suspend and resume process.
376 */
Peter Chene235f7b2015-01-16 18:29:01 +0800377 if (low_speed_connection & vbus_is_on) {
378 /*
379 * If value to be set as pwd value is not 0xffffffff,
380 * several 32Khz cycles are needed.
381 */
382 mxs_phy_clock_switch_delay();
383 writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
384 } else {
Peter Chenefdbd3a2015-01-16 18:29:00 +0800385 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
Peter Chene235f7b2015-01-16 18:29:01 +0800386 }
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100387 writel(BM_USBPHY_CTRL_CLKGATE,
388 x->io_priv + HW_USBPHY_CTRL_SET);
Peter Chen04a62212013-01-10 16:35:53 +0800389 clk_disable_unprepare(mxs_phy->clk);
390 } else {
Peter Chen47d18452014-02-24 10:21:04 +0800391 mxs_phy_clock_switch_delay();
Fabio Estevam67c21fc2013-12-02 01:02:34 -0200392 ret = clk_prepare_enable(mxs_phy->clk);
393 if (ret)
394 return ret;
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100395 writel(BM_USBPHY_CTRL_CLKGATE,
396 x->io_priv + HW_USBPHY_CTRL_CLR);
397 writel(0, x->io_priv + HW_USBPHY_PWD);
Peter Chen04a62212013-01-10 16:35:53 +0800398 }
399
400 return 0;
401}
402
Peter Chen3f126502014-02-24 10:21:02 +0800403static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
404{
405 struct mxs_phy *mxs_phy = to_mxs_phy(x);
406 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
407 BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
408 BM_USBPHY_CTRL_ENIDCHG_WKUP;
409 if (enabled) {
410 mxs_phy_disconnect_line(mxs_phy, true);
411 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
412 } else {
413 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
414 mxs_phy_disconnect_line(mxs_phy, false);
415 }
416
417 return 0;
418}
419
Peter Chenac965112012-11-09 09:44:44 +0800420static int mxs_phy_on_connect(struct usb_phy *phy,
421 enum usb_device_speed speed)
Richard Zhaob3d99682012-07-07 22:56:47 +0800422{
Peter Chenf6a15822014-02-24 10:20:58 +0800423 dev_dbg(phy->dev, "%s device has connected\n",
424 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
Richard Zhaob3d99682012-07-07 22:56:47 +0800425
Peter Chenac965112012-11-09 09:44:44 +0800426 if (speed == USB_SPEED_HIGH)
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100427 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
428 phy->io_priv + HW_USBPHY_CTRL_SET);
Richard Zhaob3d99682012-07-07 22:56:47 +0800429
430 return 0;
431}
432
Peter Chenac965112012-11-09 09:44:44 +0800433static int mxs_phy_on_disconnect(struct usb_phy *phy,
434 enum usb_device_speed speed)
Richard Zhaob3d99682012-07-07 22:56:47 +0800435{
Peter Chenf6a15822014-02-24 10:20:58 +0800436 dev_dbg(phy->dev, "%s device has disconnected\n",
437 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
Richard Zhaob3d99682012-07-07 22:56:47 +0800438
Peter Chenf78c0952014-12-24 13:48:03 +0800439 /* Sometimes, the speed is not high speed when the error occurs */
440 if (readl(phy->io_priv + HW_USBPHY_CTRL) &
441 BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
Marc Kleine-Buddeb5a726b2013-02-28 11:52:30 +0100442 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
443 phy->io_priv + HW_USBPHY_CTRL_CLR);
Richard Zhaob3d99682012-07-07 22:56:47 +0800444
445 return 0;
446}
447
448static int mxs_phy_probe(struct platform_device *pdev)
449{
450 struct resource *res;
451 void __iomem *base;
452 struct clk *clk;
453 struct mxs_phy *mxs_phy;
Sascha Hauer25df6392013-02-27 15:16:30 +0100454 int ret;
Peter Chen24007802014-02-24 10:20:54 +0800455 const struct of_device_id *of_id =
456 of_match_device(mxs_phy_dt_ids, &pdev->dev);
Peter Chen0d896532014-02-24 10:20:57 +0800457 struct device_node *np = pdev->dev.of_node;
Richard Zhaob3d99682012-07-07 22:56:47 +0800458
459 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding148e1132013-01-21 11:09:22 +0100460 base = devm_ioremap_resource(&pdev->dev, res);
461 if (IS_ERR(base))
462 return PTR_ERR(base);
Richard Zhaob3d99682012-07-07 22:56:47 +0800463
464 clk = devm_clk_get(&pdev->dev, NULL);
465 if (IS_ERR(clk)) {
466 dev_err(&pdev->dev,
467 "can't get the clock, err=%ld", PTR_ERR(clk));
468 return PTR_ERR(clk);
469 }
470
471 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
Peter Chenc62fe552014-10-14 15:56:16 +0800472 if (!mxs_phy)
Richard Zhaob3d99682012-07-07 22:56:47 +0800473 return -ENOMEM;
Richard Zhaob3d99682012-07-07 22:56:47 +0800474
Peter Chen0d896532014-02-24 10:20:57 +0800475 /* Some SoCs don't have anatop registers */
476 if (of_get_property(np, "fsl,anatop", NULL)) {
477 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
478 (np, "fsl,anatop");
479 if (IS_ERR(mxs_phy->regmap_anatop)) {
480 dev_dbg(&pdev->dev,
481 "failed to find regmap for anatop\n");
482 return PTR_ERR(mxs_phy->regmap_anatop);
483 }
484 }
485
Peter Chen83be1812014-02-24 10:21:00 +0800486 ret = of_alias_get_id(np, "usbphy");
487 if (ret < 0)
488 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
489 mxs_phy->port_id = ret;
490
Richard Zhaob3d99682012-07-07 22:56:47 +0800491 mxs_phy->phy.io_priv = base;
492 mxs_phy->phy.dev = &pdev->dev;
493 mxs_phy->phy.label = DRIVER_NAME;
494 mxs_phy->phy.init = mxs_phy_init;
495 mxs_phy->phy.shutdown = mxs_phy_shutdown;
Peter Chen04a62212013-01-10 16:35:53 +0800496 mxs_phy->phy.set_suspend = mxs_phy_suspend;
Richard Zhaob3d99682012-07-07 22:56:47 +0800497 mxs_phy->phy.notify_connect = mxs_phy_on_connect;
498 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
Michael Grzeschik4e0aa632013-05-15 15:03:14 +0200499 mxs_phy->phy.type = USB_PHY_TYPE_USB2;
Peter Chen3f126502014-02-24 10:21:02 +0800500 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup;
Richard Zhaob3d99682012-07-07 22:56:47 +0800501
Richard Zhaob3d99682012-07-07 22:56:47 +0800502 mxs_phy->clk = clk;
Peter Chen24007802014-02-24 10:20:54 +0800503 mxs_phy->data = of_id->data;
Richard Zhaob3d99682012-07-07 22:56:47 +0800504
Jisheng Zhang97a27f72013-11-07 10:55:49 +0800505 platform_set_drvdata(pdev, mxs_phy);
Richard Zhaob3d99682012-07-07 22:56:47 +0800506
Peter Chenbf783432014-02-24 10:21:03 +0800507 device_set_wakeup_capable(&pdev->dev, true);
508
Saurabh Karajgaonkar082155e2015-08-04 14:01:31 +0000509 return usb_add_phy_dev(&mxs_phy->phy);
Richard Zhaob3d99682012-07-07 22:56:47 +0800510}
511
Bill Pembertonfb4e98a2012-11-19 13:26:20 -0500512static int mxs_phy_remove(struct platform_device *pdev)
Richard Zhaob3d99682012-07-07 22:56:47 +0800513{
Sascha Hauer25df6392013-02-27 15:16:30 +0100514 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
515
516 usb_remove_phy(&mxs_phy->phy);
517
Richard Zhaob3d99682012-07-07 22:56:47 +0800518 return 0;
519}
520
Peter Chenbf783432014-02-24 10:21:03 +0800521#ifdef CONFIG_PM_SLEEP
522static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
523{
524 unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
525
526 /* If the SoCs don't have anatop, quit */
527 if (!mxs_phy->regmap_anatop)
528 return;
529
530 if (is_imx6q_phy(mxs_phy))
531 regmap_write(mxs_phy->regmap_anatop, reg,
532 BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
533 else if (is_imx6sl_phy(mxs_phy))
534 regmap_write(mxs_phy->regmap_anatop,
535 reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
536}
537
538static int mxs_phy_system_suspend(struct device *dev)
539{
540 struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
541
542 if (device_may_wakeup(dev))
543 mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
544
545 return 0;
546}
547
548static int mxs_phy_system_resume(struct device *dev)
549{
550 struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
551
552 if (device_may_wakeup(dev))
553 mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
554
555 return 0;
556}
557#endif /* CONFIG_PM_SLEEP */
558
559static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
560 mxs_phy_system_resume);
561
Richard Zhaob3d99682012-07-07 22:56:47 +0800562static struct platform_driver mxs_phy_driver = {
563 .probe = mxs_phy_probe,
Bill Pemberton76904172012-11-19 13:21:08 -0500564 .remove = mxs_phy_remove,
Richard Zhaob3d99682012-07-07 22:56:47 +0800565 .driver = {
566 .name = DRIVER_NAME,
Richard Zhaob3d99682012-07-07 22:56:47 +0800567 .of_match_table = mxs_phy_dt_ids,
Peter Chenbf783432014-02-24 10:21:03 +0800568 .pm = &mxs_phy_pm,
Richard Zhaob3d99682012-07-07 22:56:47 +0800569 },
570};
571
572static int __init mxs_phy_module_init(void)
573{
574 return platform_driver_register(&mxs_phy_driver);
575}
576postcore_initcall(mxs_phy_module_init);
577
578static void __exit mxs_phy_module_exit(void)
579{
580 platform_driver_unregister(&mxs_phy_driver);
581}
582module_exit(mxs_phy_module_exit);
583
584MODULE_ALIAS("platform:mxs-usb-phy");
585MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
586MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
587MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
588MODULE_LICENSE("GPL");