blob: 30777f9f1a439eef1ad5e8d4446017d7f3999392 [file] [log] [blame]
Georgi Djakov2b46cd22014-06-12 19:41:42 +03001/*
Stephane Viaucb2eb7d2015-08-06 16:07:50 +05302 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/module.h>
17#include <linux/regmap.h>
18#include <linux/reset-controller.h>
19
20#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
22
23#include "common.h"
24#include "clk-regmap.h"
25#include "clk-pll.h"
26#include "clk-rcg.h"
27#include "clk-branch.h"
28#include "reset.h"
Stephane Viaucb2eb7d2015-08-06 16:07:50 +053029#include "gdsc.h"
Georgi Djakov2b46cd22014-06-12 19:41:42 +030030
Georgi Djakov293d2e972015-03-20 18:30:26 +020031enum {
32 P_XO,
33 P_MMPLL0,
34 P_EDPLINK,
35 P_MMPLL1,
36 P_HDMIPLL,
37 P_GPLL0,
38 P_EDPVCO,
39 P_MMPLL4,
40 P_DSI0PLL,
41 P_DSI0PLL_BYTE,
42 P_MMPLL2,
43 P_MMPLL3,
44 P_GPLL1,
45 P_DSI1PLL,
46 P_DSI1PLL_BYTE,
47 P_MMSLEEP,
48};
Georgi Djakov2b46cd22014-06-12 19:41:42 +030049
Georgi Djakov293d2e972015-03-20 18:30:26 +020050static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
51 { P_XO, 0 },
52 { P_MMPLL0, 1 },
53 { P_MMPLL1, 2 },
54 { P_GPLL0, 5 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +030055};
56
Georgi Djakovadb11a42015-07-06 16:51:30 +030057static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +030058 "xo",
59 "mmpll0_vote",
60 "mmpll1_vote",
61 "mmss_gpll0_vote",
62};
63
Georgi Djakov293d2e972015-03-20 18:30:26 +020064static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
65 { P_XO, 0 },
66 { P_MMPLL0, 1 },
67 { P_HDMIPLL, 4 },
68 { P_GPLL0, 5 },
69 { P_DSI0PLL, 2 },
70 { P_DSI1PLL, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +030071};
72
Georgi Djakovadb11a42015-07-06 16:51:30 +030073static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +030074 "xo",
75 "mmpll0_vote",
76 "hdmipll",
77 "mmss_gpll0_vote",
78 "dsi0pll",
79 "dsi1pll",
80};
81
Georgi Djakov293d2e972015-03-20 18:30:26 +020082static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
83 { P_XO, 0 },
84 { P_MMPLL0, 1 },
85 { P_MMPLL1, 2 },
86 { P_GPLL0, 5 },
87 { P_MMPLL2, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +030088};
89
Georgi Djakovadb11a42015-07-06 16:51:30 +030090static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +030091 "xo",
92 "mmpll0_vote",
93 "mmpll1_vote",
94 "mmss_gpll0_vote",
95 "mmpll2",
96};
97
Georgi Djakov293d2e972015-03-20 18:30:26 +020098static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
99 { P_XO, 0 },
100 { P_MMPLL0, 1 },
101 { P_MMPLL1, 2 },
102 { P_GPLL0, 5 },
103 { P_MMPLL3, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300104};
105
Georgi Djakovadb11a42015-07-06 16:51:30 +0300106static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300107 "xo",
108 "mmpll0_vote",
109 "mmpll1_vote",
110 "mmss_gpll0_vote",
111 "mmpll3",
112};
113
Georgi Djakov293d2e972015-03-20 18:30:26 +0200114static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
115 { P_XO, 0 },
116 { P_EDPLINK, 4 },
117 { P_HDMIPLL, 3 },
118 { P_EDPVCO, 5 },
119 { P_DSI0PLL, 1 },
120 { P_DSI1PLL, 2 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300121};
122
Georgi Djakovadb11a42015-07-06 16:51:30 +0300123static const char * const mmcc_xo_dsi_hdmi_edp[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300124 "xo",
125 "edp_link_clk",
126 "hdmipll",
127 "edp_vco_div",
128 "dsi0pll",
129 "dsi1pll",
130};
131
Georgi Djakov293d2e972015-03-20 18:30:26 +0200132static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
133 { P_XO, 0 },
134 { P_EDPLINK, 4 },
135 { P_HDMIPLL, 3 },
136 { P_GPLL0, 5 },
137 { P_DSI0PLL, 1 },
138 { P_DSI1PLL, 2 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300139};
140
Georgi Djakovadb11a42015-07-06 16:51:30 +0300141static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300142 "xo",
143 "edp_link_clk",
144 "hdmipll",
145 "gpll0_vote",
146 "dsi0pll",
147 "dsi1pll",
148};
149
Georgi Djakov293d2e972015-03-20 18:30:26 +0200150static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
151 { P_XO, 0 },
152 { P_EDPLINK, 4 },
153 { P_HDMIPLL, 3 },
154 { P_GPLL0, 5 },
155 { P_DSI0PLL_BYTE, 1 },
156 { P_DSI1PLL_BYTE, 2 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300157};
158
Georgi Djakovadb11a42015-07-06 16:51:30 +0300159static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300160 "xo",
161 "edp_link_clk",
162 "hdmipll",
163 "gpll0_vote",
164 "dsi0pllbyte",
165 "dsi1pllbyte",
166};
167
Georgi Djakov293d2e972015-03-20 18:30:26 +0200168static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
169 { P_XO, 0 },
170 { P_MMPLL0, 1 },
171 { P_MMPLL1, 2 },
172 { P_GPLL0, 5 },
173 { P_MMPLL4, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300174};
175
Georgi Djakovadb11a42015-07-06 16:51:30 +0300176static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300177 "xo",
178 "mmpll0",
179 "mmpll1",
180 "mmpll4",
181 "gpll0",
182};
183
Georgi Djakov293d2e972015-03-20 18:30:26 +0200184static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
185 { P_XO, 0 },
186 { P_MMPLL0, 1 },
187 { P_MMPLL1, 2 },
188 { P_MMPLL4, 3 },
189 { P_GPLL0, 5 },
190 { P_GPLL1, 4 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300191};
192
Georgi Djakovadb11a42015-07-06 16:51:30 +0300193static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300194 "xo",
195 "mmpll0",
196 "mmpll1",
197 "mmpll4",
198 "gpll1",
199 "gpll0",
200};
201
Georgi Djakov293d2e972015-03-20 18:30:26 +0200202static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
203 { P_XO, 0 },
204 { P_MMPLL0, 1 },
205 { P_MMPLL1, 2 },
206 { P_MMPLL4, 3 },
207 { P_GPLL0, 5 },
208 { P_GPLL1, 4 },
209 { P_MMSLEEP, 6 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300210};
211
Georgi Djakovadb11a42015-07-06 16:51:30 +0300212static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300213 "xo",
214 "mmpll0",
215 "mmpll1",
216 "mmpll4",
217 "gpll1",
218 "gpll0",
219 "sleep_clk_src",
220};
221
222#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
223
224static struct clk_pll mmpll0 = {
225 .l_reg = 0x0004,
226 .m_reg = 0x0008,
227 .n_reg = 0x000c,
228 .config_reg = 0x0014,
229 .mode_reg = 0x0000,
230 .status_reg = 0x001c,
231 .status_bit = 17,
232 .clkr.hw.init = &(struct clk_init_data){
233 .name = "mmpll0",
234 .parent_names = (const char *[]){ "xo" },
235 .num_parents = 1,
236 .ops = &clk_pll_ops,
237 },
238};
239
240static struct clk_regmap mmpll0_vote = {
241 .enable_reg = 0x0100,
242 .enable_mask = BIT(0),
243 .hw.init = &(struct clk_init_data){
244 .name = "mmpll0_vote",
245 .parent_names = (const char *[]){ "mmpll0" },
246 .num_parents = 1,
247 .ops = &clk_pll_vote_ops,
248 },
249};
250
251static struct clk_pll mmpll1 = {
252 .l_reg = 0x0044,
253 .m_reg = 0x0048,
254 .n_reg = 0x004c,
255 .config_reg = 0x0050,
256 .mode_reg = 0x0040,
257 .status_reg = 0x005c,
258 .status_bit = 17,
259 .clkr.hw.init = &(struct clk_init_data){
260 .name = "mmpll1",
261 .parent_names = (const char *[]){ "xo" },
262 .num_parents = 1,
263 .ops = &clk_pll_ops,
264 },
265};
266
267static struct clk_regmap mmpll1_vote = {
268 .enable_reg = 0x0100,
269 .enable_mask = BIT(1),
270 .hw.init = &(struct clk_init_data){
271 .name = "mmpll1_vote",
272 .parent_names = (const char *[]){ "mmpll1" },
273 .num_parents = 1,
274 .ops = &clk_pll_vote_ops,
275 },
276};
277
278static struct clk_pll mmpll2 = {
279 .l_reg = 0x4104,
280 .m_reg = 0x4108,
281 .n_reg = 0x410c,
282 .config_reg = 0x4110,
283 .mode_reg = 0x4100,
284 .status_reg = 0x411c,
285 .clkr.hw.init = &(struct clk_init_data){
286 .name = "mmpll2",
287 .parent_names = (const char *[]){ "xo" },
288 .num_parents = 1,
289 .ops = &clk_pll_ops,
290 },
291};
292
293static struct clk_pll mmpll3 = {
294 .l_reg = 0x0084,
295 .m_reg = 0x0088,
296 .n_reg = 0x008c,
297 .config_reg = 0x0090,
298 .mode_reg = 0x0080,
299 .status_reg = 0x009c,
300 .status_bit = 17,
301 .clkr.hw.init = &(struct clk_init_data){
302 .name = "mmpll3",
303 .parent_names = (const char *[]){ "xo" },
304 .num_parents = 1,
305 .ops = &clk_pll_ops,
306 },
307};
308
309static struct clk_pll mmpll4 = {
310 .l_reg = 0x00a4,
311 .m_reg = 0x00a8,
312 .n_reg = 0x00ac,
313 .config_reg = 0x00b0,
314 .mode_reg = 0x0080,
315 .status_reg = 0x00bc,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "mmpll4",
318 .parent_names = (const char *[]){ "xo" },
319 .num_parents = 1,
320 .ops = &clk_pll_ops,
321 },
322};
323
324static struct clk_rcg2 mmss_ahb_clk_src = {
325 .cmd_rcgr = 0x5000,
326 .hid_width = 5,
327 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
328 .clkr.hw.init = &(struct clk_init_data){
329 .name = "mmss_ahb_clk_src",
330 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
331 .num_parents = 4,
332 .ops = &clk_rcg2_ops,
333 },
334};
335
336static struct freq_tbl ftbl_mmss_axi_clk[] = {
337 F(19200000, P_XO, 1, 0, 0),
338 F(37500000, P_GPLL0, 16, 0, 0),
339 F(50000000, P_GPLL0, 12, 0, 0),
340 F(75000000, P_GPLL0, 8, 0, 0),
341 F(100000000, P_GPLL0, 6, 0, 0),
342 F(150000000, P_GPLL0, 4, 0, 0),
343 F(333430000, P_MMPLL1, 3.5, 0, 0),
344 F(400000000, P_MMPLL0, 2, 0, 0),
345 F(466800000, P_MMPLL1, 2.5, 0, 0),
346};
347
348static struct clk_rcg2 mmss_axi_clk_src = {
349 .cmd_rcgr = 0x5040,
350 .hid_width = 5,
351 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
352 .freq_tbl = ftbl_mmss_axi_clk,
353 .clkr.hw.init = &(struct clk_init_data){
354 .name = "mmss_axi_clk_src",
355 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
356 .num_parents = 4,
357 .ops = &clk_rcg2_ops,
358 },
359};
360
361static struct freq_tbl ftbl_ocmemnoc_clk[] = {
362 F(19200000, P_XO, 1, 0, 0),
363 F(37500000, P_GPLL0, 16, 0, 0),
364 F(50000000, P_GPLL0, 12, 0, 0),
365 F(75000000, P_GPLL0, 8, 0, 0),
366 F(109090000, P_GPLL0, 5.5, 0, 0),
367 F(150000000, P_GPLL0, 4, 0, 0),
368 F(228570000, P_MMPLL0, 3.5, 0, 0),
369 F(320000000, P_MMPLL0, 2.5, 0, 0),
370};
371
372static struct clk_rcg2 ocmemnoc_clk_src = {
373 .cmd_rcgr = 0x5090,
374 .hid_width = 5,
375 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
376 .freq_tbl = ftbl_ocmemnoc_clk,
377 .clkr.hw.init = &(struct clk_init_data){
378 .name = "ocmemnoc_clk_src",
379 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
380 .num_parents = 4,
381 .ops = &clk_rcg2_ops,
382 },
383};
384
385static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
386 F(100000000, P_GPLL0, 6, 0, 0),
387 F(200000000, P_MMPLL0, 4, 0, 0),
388 { }
389};
390
391static struct clk_rcg2 csi0_clk_src = {
392 .cmd_rcgr = 0x3090,
393 .hid_width = 5,
394 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
395 .freq_tbl = ftbl_camss_csi0_3_clk,
396 .clkr.hw.init = &(struct clk_init_data){
397 .name = "csi0_clk_src",
398 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
399 .num_parents = 5,
400 .ops = &clk_rcg2_ops,
401 },
402};
403
404static struct clk_rcg2 csi1_clk_src = {
405 .cmd_rcgr = 0x3100,
406 .hid_width = 5,
407 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
408 .freq_tbl = ftbl_camss_csi0_3_clk,
409 .clkr.hw.init = &(struct clk_init_data){
410 .name = "csi1_clk_src",
411 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
412 .num_parents = 5,
413 .ops = &clk_rcg2_ops,
414 },
415};
416
417static struct clk_rcg2 csi2_clk_src = {
418 .cmd_rcgr = 0x3160,
419 .hid_width = 5,
420 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
421 .freq_tbl = ftbl_camss_csi0_3_clk,
422 .clkr.hw.init = &(struct clk_init_data){
423 .name = "csi2_clk_src",
424 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
425 .num_parents = 5,
426 .ops = &clk_rcg2_ops,
427 },
428};
429
430static struct clk_rcg2 csi3_clk_src = {
431 .cmd_rcgr = 0x31c0,
432 .hid_width = 5,
433 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
434 .freq_tbl = ftbl_camss_csi0_3_clk,
435 .clkr.hw.init = &(struct clk_init_data){
436 .name = "csi3_clk_src",
437 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
438 .num_parents = 5,
439 .ops = &clk_rcg2_ops,
440 },
441};
442
443static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
444 F(37500000, P_GPLL0, 16, 0, 0),
445 F(50000000, P_GPLL0, 12, 0, 0),
446 F(60000000, P_GPLL0, 10, 0, 0),
447 F(80000000, P_GPLL0, 7.5, 0, 0),
448 F(100000000, P_GPLL0, 6, 0, 0),
449 F(109090000, P_GPLL0, 5.5, 0, 0),
450 F(133330000, P_GPLL0, 4.5, 0, 0),
451 F(200000000, P_GPLL0, 3, 0, 0),
452 F(228570000, P_MMPLL0, 3.5, 0, 0),
453 F(266670000, P_MMPLL0, 3, 0, 0),
454 F(320000000, P_MMPLL0, 2.5, 0, 0),
455 F(465000000, P_MMPLL4, 2, 0, 0),
456 F(600000000, P_GPLL0, 1, 0, 0),
457 { }
458};
459
460static struct clk_rcg2 vfe0_clk_src = {
461 .cmd_rcgr = 0x3600,
462 .hid_width = 5,
463 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
464 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
465 .clkr.hw.init = &(struct clk_init_data){
466 .name = "vfe0_clk_src",
467 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
468 .num_parents = 5,
469 .ops = &clk_rcg2_ops,
470 },
471};
472
473static struct clk_rcg2 vfe1_clk_src = {
474 .cmd_rcgr = 0x3620,
475 .hid_width = 5,
476 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
477 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "vfe1_clk_src",
480 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
481 .num_parents = 5,
482 .ops = &clk_rcg2_ops,
483 },
484};
485
486static struct freq_tbl ftbl_mdss_mdp_clk[] = {
487 F(37500000, P_GPLL0, 16, 0, 0),
488 F(60000000, P_GPLL0, 10, 0, 0),
489 F(75000000, P_GPLL0, 8, 0, 0),
490 F(85710000, P_GPLL0, 7, 0, 0),
491 F(100000000, P_GPLL0, 6, 0, 0),
492 F(150000000, P_GPLL0, 4, 0, 0),
493 F(160000000, P_MMPLL0, 5, 0, 0),
494 F(200000000, P_MMPLL0, 4, 0, 0),
495 F(228570000, P_MMPLL0, 3.5, 0, 0),
496 F(300000000, P_GPLL0, 2, 0, 0),
497 F(320000000, P_MMPLL0, 2.5, 0, 0),
498 { }
499};
500
501static struct clk_rcg2 mdp_clk_src = {
502 .cmd_rcgr = 0x2040,
503 .hid_width = 5,
504 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
505 .freq_tbl = ftbl_mdss_mdp_clk,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "mdp_clk_src",
508 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
509 .num_parents = 6,
510 .ops = &clk_rcg2_ops,
511 },
512};
513
514static struct clk_rcg2 gfx3d_clk_src = {
515 .cmd_rcgr = 0x4000,
516 .hid_width = 5,
517 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
518 .clkr.hw.init = &(struct clk_init_data){
519 .name = "gfx3d_clk_src",
520 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
521 .num_parents = 5,
522 .ops = &clk_rcg2_ops,
523 },
524};
525
526static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
527 F(75000000, P_GPLL0, 8, 0, 0),
528 F(133330000, P_GPLL0, 4.5, 0, 0),
529 F(200000000, P_GPLL0, 3, 0, 0),
530 F(228570000, P_MMPLL0, 3.5, 0, 0),
531 F(266670000, P_MMPLL0, 3, 0, 0),
532 F(320000000, P_MMPLL0, 2.5, 0, 0),
533 { }
534};
535
536static struct clk_rcg2 jpeg0_clk_src = {
537 .cmd_rcgr = 0x3500,
538 .hid_width = 5,
539 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
540 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
541 .clkr.hw.init = &(struct clk_init_data){
542 .name = "jpeg0_clk_src",
543 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
544 .num_parents = 5,
545 .ops = &clk_rcg2_ops,
546 },
547};
548
549static struct clk_rcg2 jpeg1_clk_src = {
550 .cmd_rcgr = 0x3520,
551 .hid_width = 5,
552 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
553 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
554 .clkr.hw.init = &(struct clk_init_data){
555 .name = "jpeg1_clk_src",
556 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
557 .num_parents = 5,
558 .ops = &clk_rcg2_ops,
559 },
560};
561
562static struct clk_rcg2 jpeg2_clk_src = {
563 .cmd_rcgr = 0x3540,
564 .hid_width = 5,
565 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
566 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "jpeg2_clk_src",
569 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
570 .num_parents = 5,
571 .ops = &clk_rcg2_ops,
572 },
573};
574
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300575static struct clk_rcg2 pclk0_clk_src = {
576 .cmd_rcgr = 0x2000,
577 .mnd_width = 8,
578 .hid_width = 5,
579 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "pclk0_clk_src",
582 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
583 .num_parents = 6,
584 .ops = &clk_pixel_ops,
585 .flags = CLK_SET_RATE_PARENT,
586 },
587};
588
589static struct clk_rcg2 pclk1_clk_src = {
590 .cmd_rcgr = 0x2020,
591 .mnd_width = 8,
592 .hid_width = 5,
593 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "pclk1_clk_src",
596 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
597 .num_parents = 6,
598 .ops = &clk_pixel_ops,
599 .flags = CLK_SET_RATE_PARENT,
600 },
601};
602
603static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
604 F(50000000, P_GPLL0, 12, 0, 0),
605 F(100000000, P_GPLL0, 6, 0, 0),
606 F(133330000, P_GPLL0, 4.5, 0, 0),
607 F(200000000, P_MMPLL0, 4, 0, 0),
608 F(266670000, P_MMPLL0, 3, 0, 0),
609 F(465000000, P_MMPLL3, 2, 0, 0),
610 { }
611};
612
613static struct clk_rcg2 vcodec0_clk_src = {
614 .cmd_rcgr = 0x1000,
615 .mnd_width = 8,
616 .hid_width = 5,
617 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
618 .freq_tbl = ftbl_venus0_vcodec0_clk,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "vcodec0_clk_src",
621 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
622 .num_parents = 5,
623 .ops = &clk_rcg2_ops,
624 },
625};
626
627static struct freq_tbl ftbl_avsync_vp_clk[] = {
628 F(150000000, P_GPLL0, 4, 0, 0),
629 F(320000000, P_MMPLL0, 2.5, 0, 0),
630 { }
631};
632
633static struct clk_rcg2 vp_clk_src = {
634 .cmd_rcgr = 0x2430,
635 .hid_width = 5,
636 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
637 .freq_tbl = ftbl_avsync_vp_clk,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "vp_clk_src",
640 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
641 .num_parents = 4,
642 .ops = &clk_rcg2_ops,
643 },
644};
645
646static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
647 F(19200000, P_XO, 1, 0, 0),
648 { }
649};
650
651static struct clk_rcg2 cci_clk_src = {
652 .cmd_rcgr = 0x3300,
653 .mnd_width = 8,
654 .hid_width = 5,
655 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
656 .freq_tbl = ftbl_camss_cci_cci_clk,
657 .clkr.hw.init = &(struct clk_init_data){
658 .name = "cci_clk_src",
659 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
660 .num_parents = 6,
661 .ops = &clk_rcg2_ops,
662 },
663};
664
665static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
666 F(10000, P_XO, 16, 1, 120),
667 F(24000, P_XO, 16, 1, 50),
668 F(6000000, P_GPLL0, 10, 1, 10),
669 F(12000000, P_GPLL0, 10, 1, 5),
670 F(13000000, P_GPLL0, 4, 13, 150),
671 F(24000000, P_GPLL0, 5, 1, 5),
672 { }
673};
674
675static struct clk_rcg2 camss_gp0_clk_src = {
676 .cmd_rcgr = 0x3420,
677 .mnd_width = 8,
678 .hid_width = 5,
679 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
680 .freq_tbl = ftbl_camss_gp0_1_clk,
681 .clkr.hw.init = &(struct clk_init_data){
682 .name = "camss_gp0_clk_src",
683 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
684 .num_parents = 7,
685 .ops = &clk_rcg2_ops,
686 },
687};
688
689static struct clk_rcg2 camss_gp1_clk_src = {
690 .cmd_rcgr = 0x3450,
691 .mnd_width = 8,
692 .hid_width = 5,
693 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
694 .freq_tbl = ftbl_camss_gp0_1_clk,
695 .clkr.hw.init = &(struct clk_init_data){
696 .name = "camss_gp1_clk_src",
697 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
698 .num_parents = 7,
699 .ops = &clk_rcg2_ops,
700 },
701};
702
703static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
704 F(4800000, P_XO, 4, 0, 0),
705 F(6000000, P_GPLL0, 10, 1, 10),
706 F(8000000, P_GPLL0, 15, 1, 5),
707 F(9600000, P_XO, 2, 0, 0),
708 F(16000000, P_MMPLL0, 10, 1, 5),
709 F(19200000, P_XO, 1, 0, 0),
710 F(24000000, P_GPLL0, 5, 1, 5),
711 F(32000000, P_MMPLL0, 5, 1, 5),
712 F(48000000, P_GPLL0, 12.5, 0, 0),
713 F(64000000, P_MMPLL0, 12.5, 0, 0),
714 { }
715};
716
717static struct clk_rcg2 mclk0_clk_src = {
718 .cmd_rcgr = 0x3360,
719 .mnd_width = 8,
720 .hid_width = 5,
721 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
722 .freq_tbl = ftbl_camss_mclk0_3_clk,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "mclk0_clk_src",
725 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
726 .num_parents = 6,
727 .ops = &clk_rcg2_ops,
728 },
729};
730
731static struct clk_rcg2 mclk1_clk_src = {
732 .cmd_rcgr = 0x3390,
733 .mnd_width = 8,
734 .hid_width = 5,
735 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
736 .freq_tbl = ftbl_camss_mclk0_3_clk,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "mclk1_clk_src",
739 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
740 .num_parents = 6,
741 .ops = &clk_rcg2_ops,
742 },
743};
744
745static struct clk_rcg2 mclk2_clk_src = {
746 .cmd_rcgr = 0x33c0,
747 .mnd_width = 8,
748 .hid_width = 5,
749 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
750 .freq_tbl = ftbl_camss_mclk0_3_clk,
751 .clkr.hw.init = &(struct clk_init_data){
752 .name = "mclk2_clk_src",
753 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
754 .num_parents = 6,
755 .ops = &clk_rcg2_ops,
756 },
757};
758
759static struct clk_rcg2 mclk3_clk_src = {
760 .cmd_rcgr = 0x33f0,
761 .mnd_width = 8,
762 .hid_width = 5,
763 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
764 .freq_tbl = ftbl_camss_mclk0_3_clk,
765 .clkr.hw.init = &(struct clk_init_data){
766 .name = "mclk3_clk_src",
767 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
768 .num_parents = 6,
769 .ops = &clk_rcg2_ops,
770 },
771};
772
773static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
774 F(100000000, P_GPLL0, 6, 0, 0),
775 F(200000000, P_MMPLL0, 4, 0, 0),
776 { }
777};
778
779static struct clk_rcg2 csi0phytimer_clk_src = {
780 .cmd_rcgr = 0x3000,
781 .hid_width = 5,
782 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
783 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
784 .clkr.hw.init = &(struct clk_init_data){
785 .name = "csi0phytimer_clk_src",
786 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
787 .num_parents = 5,
788 .ops = &clk_rcg2_ops,
789 },
790};
791
792static struct clk_rcg2 csi1phytimer_clk_src = {
793 .cmd_rcgr = 0x3030,
794 .hid_width = 5,
795 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
796 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
797 .clkr.hw.init = &(struct clk_init_data){
798 .name = "csi1phytimer_clk_src",
799 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
800 .num_parents = 5,
801 .ops = &clk_rcg2_ops,
802 },
803};
804
805static struct clk_rcg2 csi2phytimer_clk_src = {
806 .cmd_rcgr = 0x3060,
807 .hid_width = 5,
808 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
809 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
810 .clkr.hw.init = &(struct clk_init_data){
811 .name = "csi2phytimer_clk_src",
812 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
813 .num_parents = 5,
814 .ops = &clk_rcg2_ops,
815 },
816};
817
818static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
819 F(133330000, P_GPLL0, 4.5, 0, 0),
820 F(266670000, P_MMPLL0, 3, 0, 0),
821 F(320000000, P_MMPLL0, 2.5, 0, 0),
822 F(372000000, P_MMPLL4, 2.5, 0, 0),
823 F(465000000, P_MMPLL4, 2, 0, 0),
824 F(600000000, P_GPLL0, 1, 0, 0),
825 { }
826};
827
828static struct clk_rcg2 cpp_clk_src = {
829 .cmd_rcgr = 0x3640,
830 .hid_width = 5,
831 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
832 .freq_tbl = ftbl_camss_vfe_cpp_clk,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "cpp_clk_src",
835 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
836 .num_parents = 5,
837 .ops = &clk_rcg2_ops,
838 },
839};
840
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300841static struct clk_rcg2 byte0_clk_src = {
842 .cmd_rcgr = 0x2120,
843 .hid_width = 5,
844 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300845 .clkr.hw.init = &(struct clk_init_data){
846 .name = "byte0_clk_src",
847 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
848 .num_parents = 6,
Stephen Boyd8ee9c7d2015-04-09 23:02:02 -0700849 .ops = &clk_byte2_ops,
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300850 .flags = CLK_SET_RATE_PARENT,
851 },
852};
853
854static struct clk_rcg2 byte1_clk_src = {
855 .cmd_rcgr = 0x2140,
856 .hid_width = 5,
857 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "byte1_clk_src",
860 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
861 .num_parents = 6,
Stephen Boyd8ee9c7d2015-04-09 23:02:02 -0700862 .ops = &clk_byte2_ops,
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300863 .flags = CLK_SET_RATE_PARENT,
864 },
865};
866
867static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
868 F(19200000, P_XO, 1, 0, 0),
869 { }
870};
871
872static struct clk_rcg2 edpaux_clk_src = {
873 .cmd_rcgr = 0x20e0,
874 .hid_width = 5,
875 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
876 .freq_tbl = ftbl_mdss_edpaux_clk,
877 .clkr.hw.init = &(struct clk_init_data){
878 .name = "edpaux_clk_src",
879 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
880 .num_parents = 4,
881 .ops = &clk_rcg2_ops,
882 },
883};
884
885static struct freq_tbl ftbl_mdss_edplink_clk[] = {
886 F(135000000, P_EDPLINK, 2, 0, 0),
887 F(270000000, P_EDPLINK, 11, 0, 0),
888 { }
889};
890
891static struct clk_rcg2 edplink_clk_src = {
892 .cmd_rcgr = 0x20c0,
893 .hid_width = 5,
894 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
895 .freq_tbl = ftbl_mdss_edplink_clk,
896 .clkr.hw.init = &(struct clk_init_data){
897 .name = "edplink_clk_src",
898 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
899 .num_parents = 6,
900 .ops = &clk_rcg2_ops,
901 .flags = CLK_SET_RATE_PARENT,
902 },
903};
904
905static struct freq_tbl edp_pixel_freq_tbl[] = {
906 { .src = P_EDPVCO },
907 { }
908};
909
910static struct clk_rcg2 edppixel_clk_src = {
911 .cmd_rcgr = 0x20a0,
912 .mnd_width = 8,
913 .hid_width = 5,
914 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
915 .freq_tbl = edp_pixel_freq_tbl,
916 .clkr.hw.init = &(struct clk_init_data){
917 .name = "edppixel_clk_src",
918 .parent_names = mmcc_xo_dsi_hdmi_edp,
919 .num_parents = 6,
920 .ops = &clk_edp_pixel_ops,
921 },
922};
923
924static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
925 F(19200000, P_XO, 1, 0, 0),
926 { }
927};
928
929static struct clk_rcg2 esc0_clk_src = {
930 .cmd_rcgr = 0x2160,
931 .hid_width = 5,
932 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
933 .freq_tbl = ftbl_mdss_esc0_1_clk,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "esc0_clk_src",
936 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
937 .num_parents = 6,
938 .ops = &clk_rcg2_ops,
939 },
940};
941
942static struct clk_rcg2 esc1_clk_src = {
943 .cmd_rcgr = 0x2180,
944 .hid_width = 5,
945 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
946 .freq_tbl = ftbl_mdss_esc0_1_clk,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "esc1_clk_src",
949 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
950 .num_parents = 6,
951 .ops = &clk_rcg2_ops,
952 },
953};
954
955static struct freq_tbl extpclk_freq_tbl[] = {
956 { .src = P_HDMIPLL },
957 { }
958};
959
960static struct clk_rcg2 extpclk_clk_src = {
961 .cmd_rcgr = 0x2060,
962 .hid_width = 5,
963 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
964 .freq_tbl = extpclk_freq_tbl,
965 .clkr.hw.init = &(struct clk_init_data){
966 .name = "extpclk_clk_src",
967 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
968 .num_parents = 6,
969 .ops = &clk_byte_ops,
970 .flags = CLK_SET_RATE_PARENT,
971 },
972};
973
974static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
975 F(19200000, P_XO, 1, 0, 0),
976 { }
977};
978
979static struct clk_rcg2 hdmi_clk_src = {
980 .cmd_rcgr = 0x2100,
981 .hid_width = 5,
982 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
983 .freq_tbl = ftbl_mdss_hdmi_clk,
984 .clkr.hw.init = &(struct clk_init_data){
985 .name = "hdmi_clk_src",
986 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
987 .num_parents = 4,
988 .ops = &clk_rcg2_ops,
989 },
990};
991
992static struct freq_tbl ftbl_mdss_vsync_clk[] = {
993 F(19200000, P_XO, 1, 0, 0),
994 { }
995};
996
997static struct clk_rcg2 vsync_clk_src = {
998 .cmd_rcgr = 0x2080,
999 .hid_width = 5,
1000 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1001 .freq_tbl = ftbl_mdss_vsync_clk,
1002 .clkr.hw.init = &(struct clk_init_data){
1003 .name = "vsync_clk_src",
1004 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1005 .num_parents = 4,
1006 .ops = &clk_rcg2_ops,
1007 },
1008};
1009
1010static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1011 F(50000000, P_GPLL0, 12, 0, 0),
1012 { }
1013};
1014
1015static struct clk_rcg2 rbcpr_clk_src = {
1016 .cmd_rcgr = 0x4060,
1017 .hid_width = 5,
1018 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1019 .freq_tbl = ftbl_mmss_rbcpr_clk,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "rbcpr_clk_src",
1022 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1023 .num_parents = 4,
1024 .ops = &clk_rcg2_ops,
1025 },
1026};
1027
1028static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1029 F(19200000, P_XO, 1, 0, 0),
1030 { }
1031};
1032
1033static struct clk_rcg2 rbbmtimer_clk_src = {
1034 .cmd_rcgr = 0x4090,
1035 .hid_width = 5,
1036 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1037 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1038 .clkr.hw.init = &(struct clk_init_data){
1039 .name = "rbbmtimer_clk_src",
1040 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1041 .num_parents = 4,
1042 .ops = &clk_rcg2_ops,
1043 },
1044};
1045
1046static struct freq_tbl ftbl_vpu_maple_clk[] = {
1047 F(50000000, P_GPLL0, 12, 0, 0),
1048 F(100000000, P_GPLL0, 6, 0, 0),
1049 F(133330000, P_GPLL0, 4.5, 0, 0),
1050 F(200000000, P_MMPLL0, 4, 0, 0),
1051 F(266670000, P_MMPLL0, 3, 0, 0),
1052 F(465000000, P_MMPLL3, 2, 0, 0),
1053 { }
1054};
1055
1056static struct clk_rcg2 maple_clk_src = {
1057 .cmd_rcgr = 0x1320,
1058 .hid_width = 5,
1059 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1060 .freq_tbl = ftbl_vpu_maple_clk,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "maple_clk_src",
1063 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1064 .num_parents = 4,
1065 .ops = &clk_rcg2_ops,
1066 },
1067};
1068
1069static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1070 F(50000000, P_GPLL0, 12, 0, 0),
1071 F(100000000, P_GPLL0, 6, 0, 0),
1072 F(200000000, P_MMPLL0, 4, 0, 0),
1073 F(320000000, P_MMPLL0, 2.5, 0, 0),
1074 F(400000000, P_MMPLL0, 2, 0, 0),
1075 { }
1076};
1077
1078static struct clk_rcg2 vdp_clk_src = {
1079 .cmd_rcgr = 0x1300,
1080 .hid_width = 5,
1081 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1082 .freq_tbl = ftbl_vpu_vdp_clk,
1083 .clkr.hw.init = &(struct clk_init_data){
1084 .name = "vdp_clk_src",
1085 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1086 .num_parents = 4,
1087 .ops = &clk_rcg2_ops,
1088 },
1089};
1090
1091static struct freq_tbl ftbl_vpu_bus_clk[] = {
1092 F(40000000, P_GPLL0, 15, 0, 0),
1093 F(80000000, P_MMPLL0, 10, 0, 0),
1094 { }
1095};
1096
1097static struct clk_rcg2 vpu_bus_clk_src = {
1098 .cmd_rcgr = 0x1340,
1099 .hid_width = 5,
1100 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1101 .freq_tbl = ftbl_vpu_bus_clk,
1102 .clkr.hw.init = &(struct clk_init_data){
1103 .name = "vpu_bus_clk_src",
1104 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1105 .num_parents = 4,
1106 .ops = &clk_rcg2_ops,
1107 },
1108};
1109
1110static struct clk_branch mmss_cxo_clk = {
1111 .halt_reg = 0x5104,
1112 .clkr = {
1113 .enable_reg = 0x5104,
1114 .enable_mask = BIT(0),
1115 .hw.init = &(struct clk_init_data){
1116 .name = "mmss_cxo_clk",
1117 .parent_names = (const char *[]){ "xo" },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123};
1124
1125static struct clk_branch mmss_sleepclk_clk = {
1126 .halt_reg = 0x5100,
1127 .clkr = {
1128 .enable_reg = 0x5100,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "mmss_sleepclk_clk",
1132 .parent_names = (const char *[]){
1133 "sleep_clk_src",
1134 },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140};
1141
1142static struct clk_branch avsync_ahb_clk = {
1143 .halt_reg = 0x2414,
1144 .clkr = {
1145 .enable_reg = 0x2414,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "avsync_ahb_clk",
1149 .parent_names = (const char *[]){
1150 "mmss_ahb_clk_src",
1151 },
1152 .num_parents = 1,
1153 .flags = CLK_SET_RATE_PARENT,
1154 .ops = &clk_branch2_ops,
1155 },
1156 },
1157};
1158
1159static struct clk_branch avsync_edppixel_clk = {
1160 .halt_reg = 0x2418,
1161 .clkr = {
1162 .enable_reg = 0x2418,
1163 .enable_mask = BIT(0),
1164 .hw.init = &(struct clk_init_data){
1165 .name = "avsync_edppixel_clk",
1166 .parent_names = (const char *[]){
1167 "edppixel_clk_src",
1168 },
1169 .num_parents = 1,
1170 .flags = CLK_SET_RATE_PARENT,
1171 .ops = &clk_branch2_ops,
1172 },
1173 },
1174};
1175
1176static struct clk_branch avsync_extpclk_clk = {
1177 .halt_reg = 0x2410,
1178 .clkr = {
1179 .enable_reg = 0x2410,
1180 .enable_mask = BIT(0),
1181 .hw.init = &(struct clk_init_data){
1182 .name = "avsync_extpclk_clk",
1183 .parent_names = (const char *[]){
1184 "extpclk_clk_src",
1185 },
1186 .num_parents = 1,
1187 .flags = CLK_SET_RATE_PARENT,
1188 .ops = &clk_branch2_ops,
1189 },
1190 },
1191};
1192
1193static struct clk_branch avsync_pclk0_clk = {
1194 .halt_reg = 0x241c,
1195 .clkr = {
1196 .enable_reg = 0x241c,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data){
1199 .name = "avsync_pclk0_clk",
1200 .parent_names = (const char *[]){
1201 "pclk0_clk_src",
1202 },
1203 .num_parents = 1,
1204 .flags = CLK_SET_RATE_PARENT,
1205 .ops = &clk_branch2_ops,
1206 },
1207 },
1208};
1209
1210static struct clk_branch avsync_pclk1_clk = {
1211 .halt_reg = 0x2420,
1212 .clkr = {
1213 .enable_reg = 0x2420,
1214 .enable_mask = BIT(0),
1215 .hw.init = &(struct clk_init_data){
1216 .name = "avsync_pclk1_clk",
1217 .parent_names = (const char *[]){
1218 "pclk1_clk_src",
1219 },
1220 .num_parents = 1,
1221 .flags = CLK_SET_RATE_PARENT,
1222 .ops = &clk_branch2_ops,
1223 },
1224 },
1225};
1226
1227static struct clk_branch avsync_vp_clk = {
1228 .halt_reg = 0x2404,
1229 .clkr = {
1230 .enable_reg = 0x2404,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data){
1233 .name = "avsync_vp_clk",
1234 .parent_names = (const char *[]){
1235 "vp_clk_src",
1236 },
1237 .num_parents = 1,
1238 .flags = CLK_SET_RATE_PARENT,
1239 .ops = &clk_branch2_ops,
1240 },
1241 },
1242};
1243
1244static struct clk_branch camss_ahb_clk = {
1245 .halt_reg = 0x348c,
1246 .clkr = {
1247 .enable_reg = 0x348c,
1248 .enable_mask = BIT(0),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "camss_ahb_clk",
1251 .parent_names = (const char *[]){
1252 "mmss_ahb_clk_src",
1253 },
1254 .num_parents = 1,
1255 .flags = CLK_SET_RATE_PARENT,
1256 .ops = &clk_branch2_ops,
1257 },
1258 },
1259};
1260
1261static struct clk_branch camss_cci_cci_ahb_clk = {
1262 .halt_reg = 0x3348,
1263 .clkr = {
1264 .enable_reg = 0x3348,
1265 .enable_mask = BIT(0),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "camss_cci_cci_ahb_clk",
1268 .parent_names = (const char *[]){
1269 "mmss_ahb_clk_src",
1270 },
1271 .num_parents = 1,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275};
1276
1277static struct clk_branch camss_cci_cci_clk = {
1278 .halt_reg = 0x3344,
1279 .clkr = {
1280 .enable_reg = 0x3344,
1281 .enable_mask = BIT(0),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "camss_cci_cci_clk",
1284 .parent_names = (const char *[]){
1285 "cci_clk_src",
1286 },
1287 .num_parents = 1,
1288 .flags = CLK_SET_RATE_PARENT,
1289 .ops = &clk_branch2_ops,
1290 },
1291 },
1292};
1293
1294static struct clk_branch camss_csi0_ahb_clk = {
1295 .halt_reg = 0x30bc,
1296 .clkr = {
1297 .enable_reg = 0x30bc,
1298 .enable_mask = BIT(0),
1299 .hw.init = &(struct clk_init_data){
1300 .name = "camss_csi0_ahb_clk",
1301 .parent_names = (const char *[]){
1302 "mmss_ahb_clk_src",
1303 },
1304 .num_parents = 1,
1305 .ops = &clk_branch2_ops,
1306 },
1307 },
1308};
1309
1310static struct clk_branch camss_csi0_clk = {
1311 .halt_reg = 0x30b4,
1312 .clkr = {
1313 .enable_reg = 0x30b4,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi0_clk",
1317 .parent_names = (const char *[]){
1318 "csi0_clk_src",
1319 },
1320 .num_parents = 1,
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1323 },
1324 },
1325};
1326
1327static struct clk_branch camss_csi0phy_clk = {
1328 .halt_reg = 0x30c4,
1329 .clkr = {
1330 .enable_reg = 0x30c4,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "camss_csi0phy_clk",
1334 .parent_names = (const char *[]){
1335 "csi0_clk_src",
1336 },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static struct clk_branch camss_csi0pix_clk = {
1345 .halt_reg = 0x30e4,
1346 .clkr = {
1347 .enable_reg = 0x30e4,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "camss_csi0pix_clk",
1351 .parent_names = (const char *[]){
1352 "csi0_clk_src",
1353 },
1354 .num_parents = 1,
1355 .flags = CLK_SET_RATE_PARENT,
1356 .ops = &clk_branch2_ops,
1357 },
1358 },
1359};
1360
1361static struct clk_branch camss_csi0rdi_clk = {
1362 .halt_reg = 0x30d4,
1363 .clkr = {
1364 .enable_reg = 0x30d4,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_csi0rdi_clk",
1368 .parent_names = (const char *[]){
1369 "csi0_clk_src",
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 .ops = &clk_branch2_ops,
1374 },
1375 },
1376};
1377
1378static struct clk_branch camss_csi1_ahb_clk = {
1379 .halt_reg = 0x3128,
1380 .clkr = {
1381 .enable_reg = 0x3128,
1382 .enable_mask = BIT(0),
1383 .hw.init = &(struct clk_init_data){
1384 .name = "camss_csi1_ahb_clk",
1385 .parent_names = (const char *[]){
1386 "mmss_ahb_clk_src",
1387 },
1388 .num_parents = 1,
1389 .flags = CLK_SET_RATE_PARENT,
1390 .ops = &clk_branch2_ops,
1391 },
1392 },
1393};
1394
1395static struct clk_branch camss_csi1_clk = {
1396 .halt_reg = 0x3124,
1397 .clkr = {
1398 .enable_reg = 0x3124,
1399 .enable_mask = BIT(0),
1400 .hw.init = &(struct clk_init_data){
1401 .name = "camss_csi1_clk",
1402 .parent_names = (const char *[]){
1403 "csi1_clk_src",
1404 },
1405 .num_parents = 1,
1406 .flags = CLK_SET_RATE_PARENT,
1407 .ops = &clk_branch2_ops,
1408 },
1409 },
1410};
1411
1412static struct clk_branch camss_csi1phy_clk = {
1413 .halt_reg = 0x3134,
1414 .clkr = {
1415 .enable_reg = 0x3134,
1416 .enable_mask = BIT(0),
1417 .hw.init = &(struct clk_init_data){
1418 .name = "camss_csi1phy_clk",
1419 .parent_names = (const char *[]){
1420 "csi1_clk_src",
1421 },
1422 .num_parents = 1,
1423 .flags = CLK_SET_RATE_PARENT,
1424 .ops = &clk_branch2_ops,
1425 },
1426 },
1427};
1428
1429static struct clk_branch camss_csi1pix_clk = {
1430 .halt_reg = 0x3154,
1431 .clkr = {
1432 .enable_reg = 0x3154,
1433 .enable_mask = BIT(0),
1434 .hw.init = &(struct clk_init_data){
1435 .name = "camss_csi1pix_clk",
1436 .parent_names = (const char *[]){
1437 "csi1_clk_src",
1438 },
1439 .num_parents = 1,
1440 .flags = CLK_SET_RATE_PARENT,
1441 .ops = &clk_branch2_ops,
1442 },
1443 },
1444};
1445
1446static struct clk_branch camss_csi1rdi_clk = {
1447 .halt_reg = 0x3144,
1448 .clkr = {
1449 .enable_reg = 0x3144,
1450 .enable_mask = BIT(0),
1451 .hw.init = &(struct clk_init_data){
1452 .name = "camss_csi1rdi_clk",
1453 .parent_names = (const char *[]){
1454 "csi1_clk_src",
1455 },
1456 .num_parents = 1,
1457 .flags = CLK_SET_RATE_PARENT,
1458 .ops = &clk_branch2_ops,
1459 },
1460 },
1461};
1462
1463static struct clk_branch camss_csi2_ahb_clk = {
1464 .halt_reg = 0x3188,
1465 .clkr = {
1466 .enable_reg = 0x3188,
1467 .enable_mask = BIT(0),
1468 .hw.init = &(struct clk_init_data){
1469 .name = "camss_csi2_ahb_clk",
1470 .parent_names = (const char *[]){
1471 "mmss_ahb_clk_src",
1472 },
1473 .num_parents = 1,
1474 .ops = &clk_branch2_ops,
1475 },
1476 },
1477};
1478
1479static struct clk_branch camss_csi2_clk = {
1480 .halt_reg = 0x3184,
1481 .clkr = {
1482 .enable_reg = 0x3184,
1483 .enable_mask = BIT(0),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "camss_csi2_clk",
1486 .parent_names = (const char *[]){
1487 "csi2_clk_src",
1488 },
1489 .num_parents = 1,
1490 .flags = CLK_SET_RATE_PARENT,
1491 .ops = &clk_branch2_ops,
1492 },
1493 },
1494};
1495
1496static struct clk_branch camss_csi2phy_clk = {
1497 .halt_reg = 0x3194,
1498 .clkr = {
1499 .enable_reg = 0x3194,
1500 .enable_mask = BIT(0),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "camss_csi2phy_clk",
1503 .parent_names = (const char *[]){
1504 "csi2_clk_src",
1505 },
1506 .num_parents = 1,
1507 .flags = CLK_SET_RATE_PARENT,
1508 .ops = &clk_branch2_ops,
1509 },
1510 },
1511};
1512
1513static struct clk_branch camss_csi2pix_clk = {
1514 .halt_reg = 0x31b4,
1515 .clkr = {
1516 .enable_reg = 0x31b4,
1517 .enable_mask = BIT(0),
1518 .hw.init = &(struct clk_init_data){
1519 .name = "camss_csi2pix_clk",
1520 .parent_names = (const char *[]){
1521 "csi2_clk_src",
1522 },
1523 .num_parents = 1,
1524 .flags = CLK_SET_RATE_PARENT,
1525 .ops = &clk_branch2_ops,
1526 },
1527 },
1528};
1529
1530static struct clk_branch camss_csi2rdi_clk = {
1531 .halt_reg = 0x31a4,
1532 .clkr = {
1533 .enable_reg = 0x31a4,
1534 .enable_mask = BIT(0),
1535 .hw.init = &(struct clk_init_data){
1536 .name = "camss_csi2rdi_clk",
1537 .parent_names = (const char *[]){
1538 "csi2_clk_src",
1539 },
1540 .num_parents = 1,
1541 .flags = CLK_SET_RATE_PARENT,
1542 .ops = &clk_branch2_ops,
1543 },
1544 },
1545};
1546
1547static struct clk_branch camss_csi3_ahb_clk = {
1548 .halt_reg = 0x31e8,
1549 .clkr = {
1550 .enable_reg = 0x31e8,
1551 .enable_mask = BIT(0),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "camss_csi3_ahb_clk",
1554 .parent_names = (const char *[]){
1555 "mmss_ahb_clk_src",
1556 },
1557 .num_parents = 1,
1558 .ops = &clk_branch2_ops,
1559 },
1560 },
1561};
1562
1563static struct clk_branch camss_csi3_clk = {
1564 .halt_reg = 0x31e4,
1565 .clkr = {
1566 .enable_reg = 0x31e4,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "camss_csi3_clk",
1570 .parent_names = (const char *[]){
1571 "csi3_clk_src",
1572 },
1573 .num_parents = 1,
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1576 },
1577 },
1578};
1579
1580static struct clk_branch camss_csi3phy_clk = {
1581 .halt_reg = 0x31f4,
1582 .clkr = {
1583 .enable_reg = 0x31f4,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "camss_csi3phy_clk",
1587 .parent_names = (const char *[]){
1588 "csi3_clk_src",
1589 },
1590 .num_parents = 1,
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1593 },
1594 },
1595};
1596
1597static struct clk_branch camss_csi3pix_clk = {
1598 .halt_reg = 0x3214,
1599 .clkr = {
1600 .enable_reg = 0x3214,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "camss_csi3pix_clk",
1604 .parent_names = (const char *[]){
1605 "csi3_clk_src",
1606 },
1607 .num_parents = 1,
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1610 },
1611 },
1612};
1613
1614static struct clk_branch camss_csi3rdi_clk = {
1615 .halt_reg = 0x3204,
1616 .clkr = {
1617 .enable_reg = 0x3204,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "camss_csi3rdi_clk",
1621 .parent_names = (const char *[]){
1622 "csi3_clk_src",
1623 },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch camss_csi_vfe0_clk = {
1632 .halt_reg = 0x3704,
1633 .clkr = {
1634 .enable_reg = 0x3704,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "camss_csi_vfe0_clk",
1638 .parent_names = (const char *[]){
1639 "vfe0_clk_src",
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646};
1647
1648static struct clk_branch camss_csi_vfe1_clk = {
1649 .halt_reg = 0x3714,
1650 .clkr = {
1651 .enable_reg = 0x3714,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "camss_csi_vfe1_clk",
1655 .parent_names = (const char *[]){
1656 "vfe1_clk_src",
1657 },
1658 .num_parents = 1,
1659 .flags = CLK_SET_RATE_PARENT,
1660 .ops = &clk_branch2_ops,
1661 },
1662 },
1663};
1664
1665static struct clk_branch camss_gp0_clk = {
1666 .halt_reg = 0x3444,
1667 .clkr = {
1668 .enable_reg = 0x3444,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "camss_gp0_clk",
1672 .parent_names = (const char *[]){
1673 "camss_gp0_clk_src",
1674 },
1675 .num_parents = 1,
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680};
1681
1682static struct clk_branch camss_gp1_clk = {
1683 .halt_reg = 0x3474,
1684 .clkr = {
1685 .enable_reg = 0x3474,
1686 .enable_mask = BIT(0),
1687 .hw.init = &(struct clk_init_data){
1688 .name = "camss_gp1_clk",
1689 .parent_names = (const char *[]){
1690 "camss_gp1_clk_src",
1691 },
1692 .num_parents = 1,
1693 .flags = CLK_SET_RATE_PARENT,
1694 .ops = &clk_branch2_ops,
1695 },
1696 },
1697};
1698
1699static struct clk_branch camss_ispif_ahb_clk = {
1700 .halt_reg = 0x3224,
1701 .clkr = {
1702 .enable_reg = 0x3224,
1703 .enable_mask = BIT(0),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "camss_ispif_ahb_clk",
1706 .parent_names = (const char *[]){
1707 "mmss_ahb_clk_src",
1708 },
1709 .num_parents = 1,
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch camss_jpeg_jpeg0_clk = {
1717 .halt_reg = 0x35a8,
1718 .clkr = {
1719 .enable_reg = 0x35a8,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "camss_jpeg_jpeg0_clk",
1723 .parent_names = (const char *[]){
1724 "jpeg0_clk_src",
1725 },
1726 .num_parents = 1,
1727 .flags = CLK_SET_RATE_PARENT,
1728 .ops = &clk_branch2_ops,
1729 },
1730 },
1731};
1732
1733static struct clk_branch camss_jpeg_jpeg1_clk = {
1734 .halt_reg = 0x35ac,
1735 .clkr = {
1736 .enable_reg = 0x35ac,
1737 .enable_mask = BIT(0),
1738 .hw.init = &(struct clk_init_data){
1739 .name = "camss_jpeg_jpeg1_clk",
1740 .parent_names = (const char *[]){
1741 "jpeg1_clk_src",
1742 },
1743 .num_parents = 1,
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_branch2_ops,
1746 },
1747 },
1748};
1749
1750static struct clk_branch camss_jpeg_jpeg2_clk = {
1751 .halt_reg = 0x35b0,
1752 .clkr = {
1753 .enable_reg = 0x35b0,
1754 .enable_mask = BIT(0),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "camss_jpeg_jpeg2_clk",
1757 .parent_names = (const char *[]){
1758 "jpeg2_clk_src",
1759 },
1760 .num_parents = 1,
1761 .flags = CLK_SET_RATE_PARENT,
1762 .ops = &clk_branch2_ops,
1763 },
1764 },
1765};
1766
1767static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1768 .halt_reg = 0x35b4,
1769 .clkr = {
1770 .enable_reg = 0x35b4,
1771 .enable_mask = BIT(0),
1772 .hw.init = &(struct clk_init_data){
1773 .name = "camss_jpeg_jpeg_ahb_clk",
1774 .parent_names = (const char *[]){
1775 "mmss_ahb_clk_src",
1776 },
1777 .num_parents = 1,
1778 .ops = &clk_branch2_ops,
1779 },
1780 },
1781};
1782
1783static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1784 .halt_reg = 0x35b8,
1785 .clkr = {
1786 .enable_reg = 0x35b8,
1787 .enable_mask = BIT(0),
1788 .hw.init = &(struct clk_init_data){
1789 .name = "camss_jpeg_jpeg_axi_clk",
1790 .parent_names = (const char *[]){
1791 "mmss_axi_clk_src",
1792 },
1793 .num_parents = 1,
1794 .ops = &clk_branch2_ops,
1795 },
1796 },
1797};
1798
1799static struct clk_branch camss_mclk0_clk = {
1800 .halt_reg = 0x3384,
1801 .clkr = {
1802 .enable_reg = 0x3384,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "camss_mclk0_clk",
1806 .parent_names = (const char *[]){
1807 "mclk0_clk_src",
1808 },
1809 .num_parents = 1,
1810 .flags = CLK_SET_RATE_PARENT,
1811 .ops = &clk_branch2_ops,
1812 },
1813 },
1814};
1815
1816static struct clk_branch camss_mclk1_clk = {
1817 .halt_reg = 0x33b4,
1818 .clkr = {
1819 .enable_reg = 0x33b4,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "camss_mclk1_clk",
1823 .parent_names = (const char *[]){
1824 "mclk1_clk_src",
1825 },
1826 .num_parents = 1,
1827 .flags = CLK_SET_RATE_PARENT,
1828 .ops = &clk_branch2_ops,
1829 },
1830 },
1831};
1832
1833static struct clk_branch camss_mclk2_clk = {
1834 .halt_reg = 0x33e4,
1835 .clkr = {
1836 .enable_reg = 0x33e4,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "camss_mclk2_clk",
1840 .parent_names = (const char *[]){
1841 "mclk2_clk_src",
1842 },
1843 .num_parents = 1,
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1846 },
1847 },
1848};
1849
1850static struct clk_branch camss_mclk3_clk = {
1851 .halt_reg = 0x3414,
1852 .clkr = {
1853 .enable_reg = 0x3414,
1854 .enable_mask = BIT(0),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "camss_mclk3_clk",
1857 .parent_names = (const char *[]){
1858 "mclk3_clk_src",
1859 },
1860 .num_parents = 1,
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1863 },
1864 },
1865};
1866
1867static struct clk_branch camss_micro_ahb_clk = {
1868 .halt_reg = 0x3494,
1869 .clkr = {
1870 .enable_reg = 0x3494,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "camss_micro_ahb_clk",
1874 .parent_names = (const char *[]){
1875 "mmss_ahb_clk_src",
1876 },
1877 .num_parents = 1,
1878 .ops = &clk_branch2_ops,
1879 },
1880 },
1881};
1882
1883static struct clk_branch camss_phy0_csi0phytimer_clk = {
1884 .halt_reg = 0x3024,
1885 .clkr = {
1886 .enable_reg = 0x3024,
1887 .enable_mask = BIT(0),
1888 .hw.init = &(struct clk_init_data){
1889 .name = "camss_phy0_csi0phytimer_clk",
1890 .parent_names = (const char *[]){
1891 "csi0phytimer_clk_src",
1892 },
1893 .num_parents = 1,
1894 .flags = CLK_SET_RATE_PARENT,
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898};
1899
1900static struct clk_branch camss_phy1_csi1phytimer_clk = {
1901 .halt_reg = 0x3054,
1902 .clkr = {
1903 .enable_reg = 0x3054,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "camss_phy1_csi1phytimer_clk",
1907 .parent_names = (const char *[]){
1908 "csi1phytimer_clk_src",
1909 },
1910 .num_parents = 1,
1911 .flags = CLK_SET_RATE_PARENT,
1912 .ops = &clk_branch2_ops,
1913 },
1914 },
1915};
1916
1917static struct clk_branch camss_phy2_csi2phytimer_clk = {
1918 .halt_reg = 0x3084,
1919 .clkr = {
1920 .enable_reg = 0x3084,
1921 .enable_mask = BIT(0),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "camss_phy2_csi2phytimer_clk",
1924 .parent_names = (const char *[]){
1925 "csi2phytimer_clk_src",
1926 },
1927 .num_parents = 1,
1928 .flags = CLK_SET_RATE_PARENT,
1929 .ops = &clk_branch2_ops,
1930 },
1931 },
1932};
1933
1934static struct clk_branch camss_top_ahb_clk = {
1935 .halt_reg = 0x3484,
1936 .clkr = {
1937 .enable_reg = 0x3484,
1938 .enable_mask = BIT(0),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "camss_top_ahb_clk",
1941 .parent_names = (const char *[]){
1942 "mmss_ahb_clk_src",
1943 },
1944 .num_parents = 1,
1945 .flags = CLK_SET_RATE_PARENT,
1946 .ops = &clk_branch2_ops,
1947 },
1948 },
1949};
1950
1951static struct clk_branch camss_vfe_cpp_ahb_clk = {
1952 .halt_reg = 0x36b4,
1953 .clkr = {
1954 .enable_reg = 0x36b4,
1955 .enable_mask = BIT(0),
1956 .hw.init = &(struct clk_init_data){
1957 .name = "camss_vfe_cpp_ahb_clk",
1958 .parent_names = (const char *[]){
1959 "mmss_ahb_clk_src",
1960 },
1961 .num_parents = 1,
1962 .flags = CLK_SET_RATE_PARENT,
1963 .ops = &clk_branch2_ops,
1964 },
1965 },
1966};
1967
1968static struct clk_branch camss_vfe_cpp_clk = {
1969 .halt_reg = 0x36b0,
1970 .clkr = {
1971 .enable_reg = 0x36b0,
1972 .enable_mask = BIT(0),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "camss_vfe_cpp_clk",
1975 .parent_names = (const char *[]){
1976 "cpp_clk_src",
1977 },
1978 .num_parents = 1,
1979 .flags = CLK_SET_RATE_PARENT,
1980 .ops = &clk_branch2_ops,
1981 },
1982 },
1983};
1984
1985static struct clk_branch camss_vfe_vfe0_clk = {
1986 .halt_reg = 0x36a8,
1987 .clkr = {
1988 .enable_reg = 0x36a8,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "camss_vfe_vfe0_clk",
1992 .parent_names = (const char *[]){
1993 "vfe0_clk_src",
1994 },
1995 .num_parents = 1,
1996 .flags = CLK_SET_RATE_PARENT,
1997 .ops = &clk_branch2_ops,
1998 },
1999 },
2000};
2001
2002static struct clk_branch camss_vfe_vfe1_clk = {
2003 .halt_reg = 0x36ac,
2004 .clkr = {
2005 .enable_reg = 0x36ac,
2006 .enable_mask = BIT(0),
2007 .hw.init = &(struct clk_init_data){
2008 .name = "camss_vfe_vfe1_clk",
2009 .parent_names = (const char *[]){
2010 "vfe1_clk_src",
2011 },
2012 .num_parents = 1,
2013 .flags = CLK_SET_RATE_PARENT,
2014 .ops = &clk_branch2_ops,
2015 },
2016 },
2017};
2018
2019static struct clk_branch camss_vfe_vfe_ahb_clk = {
2020 .halt_reg = 0x36b8,
2021 .clkr = {
2022 .enable_reg = 0x36b8,
2023 .enable_mask = BIT(0),
2024 .hw.init = &(struct clk_init_data){
2025 .name = "camss_vfe_vfe_ahb_clk",
2026 .parent_names = (const char *[]){
2027 "mmss_ahb_clk_src",
2028 },
2029 .num_parents = 1,
2030 .flags = CLK_SET_RATE_PARENT,
2031 .ops = &clk_branch2_ops,
2032 },
2033 },
2034};
2035
2036static struct clk_branch camss_vfe_vfe_axi_clk = {
2037 .halt_reg = 0x36bc,
2038 .clkr = {
2039 .enable_reg = 0x36bc,
2040 .enable_mask = BIT(0),
2041 .hw.init = &(struct clk_init_data){
2042 .name = "camss_vfe_vfe_axi_clk",
2043 .parent_names = (const char *[]){
2044 "mmss_axi_clk_src",
2045 },
2046 .num_parents = 1,
2047 .flags = CLK_SET_RATE_PARENT,
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch mdss_ahb_clk = {
2054 .halt_reg = 0x2308,
2055 .clkr = {
2056 .enable_reg = 0x2308,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "mdss_ahb_clk",
2060 .parent_names = (const char *[]){
2061 "mmss_ahb_clk_src",
2062 },
2063 .num_parents = 1,
2064 .flags = CLK_SET_RATE_PARENT,
2065 .ops = &clk_branch2_ops,
2066 },
2067 },
2068};
2069
2070static struct clk_branch mdss_axi_clk = {
2071 .halt_reg = 0x2310,
2072 .clkr = {
2073 .enable_reg = 0x2310,
2074 .enable_mask = BIT(0),
2075 .hw.init = &(struct clk_init_data){
2076 .name = "mdss_axi_clk",
2077 .parent_names = (const char *[]){
2078 "mmss_axi_clk_src",
2079 },
2080 .num_parents = 1,
2081 .flags = CLK_SET_RATE_PARENT,
2082 .ops = &clk_branch2_ops,
2083 },
2084 },
2085};
2086
2087static struct clk_branch mdss_byte0_clk = {
2088 .halt_reg = 0x233c,
2089 .clkr = {
2090 .enable_reg = 0x233c,
2091 .enable_mask = BIT(0),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "mdss_byte0_clk",
2094 .parent_names = (const char *[]){
2095 "byte0_clk_src",
2096 },
2097 .num_parents = 1,
2098 .flags = CLK_SET_RATE_PARENT,
2099 .ops = &clk_branch2_ops,
2100 },
2101 },
2102};
2103
2104static struct clk_branch mdss_byte1_clk = {
2105 .halt_reg = 0x2340,
2106 .clkr = {
2107 .enable_reg = 0x2340,
2108 .enable_mask = BIT(0),
2109 .hw.init = &(struct clk_init_data){
2110 .name = "mdss_byte1_clk",
2111 .parent_names = (const char *[]){
2112 "byte1_clk_src",
2113 },
2114 .num_parents = 1,
2115 .flags = CLK_SET_RATE_PARENT,
2116 .ops = &clk_branch2_ops,
2117 },
2118 },
2119};
2120
2121static struct clk_branch mdss_edpaux_clk = {
2122 .halt_reg = 0x2334,
2123 .clkr = {
2124 .enable_reg = 0x2334,
2125 .enable_mask = BIT(0),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "mdss_edpaux_clk",
2128 .parent_names = (const char *[]){
2129 "edpaux_clk_src",
2130 },
2131 .num_parents = 1,
2132 .flags = CLK_SET_RATE_PARENT,
2133 .ops = &clk_branch2_ops,
2134 },
2135 },
2136};
2137
2138static struct clk_branch mdss_edplink_clk = {
2139 .halt_reg = 0x2330,
2140 .clkr = {
2141 .enable_reg = 0x2330,
2142 .enable_mask = BIT(0),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "mdss_edplink_clk",
2145 .parent_names = (const char *[]){
2146 "edplink_clk_src",
2147 },
2148 .num_parents = 1,
2149 .flags = CLK_SET_RATE_PARENT,
2150 .ops = &clk_branch2_ops,
2151 },
2152 },
2153};
2154
2155static struct clk_branch mdss_edppixel_clk = {
2156 .halt_reg = 0x232c,
2157 .clkr = {
2158 .enable_reg = 0x232c,
2159 .enable_mask = BIT(0),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "mdss_edppixel_clk",
2162 .parent_names = (const char *[]){
2163 "edppixel_clk_src",
2164 },
2165 .num_parents = 1,
2166 .flags = CLK_SET_RATE_PARENT,
2167 .ops = &clk_branch2_ops,
2168 },
2169 },
2170};
2171
2172static struct clk_branch mdss_esc0_clk = {
2173 .halt_reg = 0x2344,
2174 .clkr = {
2175 .enable_reg = 0x2344,
2176 .enable_mask = BIT(0),
2177 .hw.init = &(struct clk_init_data){
2178 .name = "mdss_esc0_clk",
2179 .parent_names = (const char *[]){
2180 "esc0_clk_src",
2181 },
2182 .num_parents = 1,
2183 .flags = CLK_SET_RATE_PARENT,
2184 .ops = &clk_branch2_ops,
2185 },
2186 },
2187};
2188
2189static struct clk_branch mdss_esc1_clk = {
2190 .halt_reg = 0x2348,
2191 .clkr = {
2192 .enable_reg = 0x2348,
2193 .enable_mask = BIT(0),
2194 .hw.init = &(struct clk_init_data){
2195 .name = "mdss_esc1_clk",
2196 .parent_names = (const char *[]){
2197 "esc1_clk_src",
2198 },
2199 .num_parents = 1,
2200 .flags = CLK_SET_RATE_PARENT,
2201 .ops = &clk_branch2_ops,
2202 },
2203 },
2204};
2205
2206static struct clk_branch mdss_extpclk_clk = {
2207 .halt_reg = 0x2324,
2208 .clkr = {
2209 .enable_reg = 0x2324,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "mdss_extpclk_clk",
2213 .parent_names = (const char *[]){
2214 "extpclk_clk_src",
2215 },
2216 .num_parents = 1,
2217 .flags = CLK_SET_RATE_PARENT,
2218 .ops = &clk_branch2_ops,
2219 },
2220 },
2221};
2222
2223static struct clk_branch mdss_hdmi_ahb_clk = {
2224 .halt_reg = 0x230c,
2225 .clkr = {
2226 .enable_reg = 0x230c,
2227 .enable_mask = BIT(0),
2228 .hw.init = &(struct clk_init_data){
2229 .name = "mdss_hdmi_ahb_clk",
2230 .parent_names = (const char *[]){
2231 "mmss_ahb_clk_src",
2232 },
2233 .num_parents = 1,
2234 .flags = CLK_SET_RATE_PARENT,
2235 .ops = &clk_branch2_ops,
2236 },
2237 },
2238};
2239
2240static struct clk_branch mdss_hdmi_clk = {
2241 .halt_reg = 0x2338,
2242 .clkr = {
2243 .enable_reg = 0x2338,
2244 .enable_mask = BIT(0),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "mdss_hdmi_clk",
2247 .parent_names = (const char *[]){
2248 "hdmi_clk_src",
2249 },
2250 .num_parents = 1,
2251 .flags = CLK_SET_RATE_PARENT,
2252 .ops = &clk_branch2_ops,
2253 },
2254 },
2255};
2256
2257static struct clk_branch mdss_mdp_clk = {
2258 .halt_reg = 0x231c,
2259 .clkr = {
2260 .enable_reg = 0x231c,
2261 .enable_mask = BIT(0),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "mdss_mdp_clk",
2264 .parent_names = (const char *[]){
2265 "mdp_clk_src",
2266 },
2267 .num_parents = 1,
2268 .flags = CLK_SET_RATE_PARENT,
2269 .ops = &clk_branch2_ops,
2270 },
2271 },
2272};
2273
2274static struct clk_branch mdss_mdp_lut_clk = {
2275 .halt_reg = 0x2320,
2276 .clkr = {
2277 .enable_reg = 0x2320,
2278 .enable_mask = BIT(0),
2279 .hw.init = &(struct clk_init_data){
2280 .name = "mdss_mdp_lut_clk",
2281 .parent_names = (const char *[]){
2282 "mdp_clk_src",
2283 },
2284 .num_parents = 1,
2285 .flags = CLK_SET_RATE_PARENT,
2286 .ops = &clk_branch2_ops,
2287 },
2288 },
2289};
2290
2291static struct clk_branch mdss_pclk0_clk = {
2292 .halt_reg = 0x2314,
2293 .clkr = {
2294 .enable_reg = 0x2314,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "mdss_pclk0_clk",
2298 .parent_names = (const char *[]){
2299 "pclk0_clk_src",
2300 },
2301 .num_parents = 1,
2302 .flags = CLK_SET_RATE_PARENT,
2303 .ops = &clk_branch2_ops,
2304 },
2305 },
2306};
2307
2308static struct clk_branch mdss_pclk1_clk = {
2309 .halt_reg = 0x2318,
2310 .clkr = {
2311 .enable_reg = 0x2318,
2312 .enable_mask = BIT(0),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "mdss_pclk1_clk",
2315 .parent_names = (const char *[]){
2316 "pclk1_clk_src",
2317 },
2318 .num_parents = 1,
2319 .flags = CLK_SET_RATE_PARENT,
2320 .ops = &clk_branch2_ops,
2321 },
2322 },
2323};
2324
2325static struct clk_branch mdss_vsync_clk = {
2326 .halt_reg = 0x2328,
2327 .clkr = {
2328 .enable_reg = 0x2328,
2329 .enable_mask = BIT(0),
2330 .hw.init = &(struct clk_init_data){
2331 .name = "mdss_vsync_clk",
2332 .parent_names = (const char *[]){
2333 "vsync_clk_src",
2334 },
2335 .num_parents = 1,
2336 .flags = CLK_SET_RATE_PARENT,
2337 .ops = &clk_branch2_ops,
2338 },
2339 },
2340};
2341
2342static struct clk_branch mmss_rbcpr_ahb_clk = {
2343 .halt_reg = 0x4088,
2344 .clkr = {
2345 .enable_reg = 0x4088,
2346 .enable_mask = BIT(0),
2347 .hw.init = &(struct clk_init_data){
2348 .name = "mmss_rbcpr_ahb_clk",
2349 .parent_names = (const char *[]){
2350 "mmss_ahb_clk_src",
2351 },
2352 .num_parents = 1,
2353 .flags = CLK_SET_RATE_PARENT,
2354 .ops = &clk_branch2_ops,
2355 },
2356 },
2357};
2358
2359static struct clk_branch mmss_rbcpr_clk = {
2360 .halt_reg = 0x4084,
2361 .clkr = {
2362 .enable_reg = 0x4084,
2363 .enable_mask = BIT(0),
2364 .hw.init = &(struct clk_init_data){
2365 .name = "mmss_rbcpr_clk",
2366 .parent_names = (const char *[]){
2367 "rbcpr_clk_src",
2368 },
2369 .num_parents = 1,
2370 .flags = CLK_SET_RATE_PARENT,
2371 .ops = &clk_branch2_ops,
2372 },
2373 },
2374};
2375
2376static struct clk_branch mmss_spdm_ahb_clk = {
2377 .halt_reg = 0x0230,
2378 .clkr = {
2379 .enable_reg = 0x0230,
2380 .enable_mask = BIT(0),
2381 .hw.init = &(struct clk_init_data){
2382 .name = "mmss_spdm_ahb_clk",
2383 .parent_names = (const char *[]){
2384 "mmss_spdm_ahb_div_clk",
2385 },
2386 .num_parents = 1,
2387 .flags = CLK_SET_RATE_PARENT,
2388 .ops = &clk_branch2_ops,
2389 },
2390 },
2391};
2392
2393static struct clk_branch mmss_spdm_axi_clk = {
2394 .halt_reg = 0x0210,
2395 .clkr = {
2396 .enable_reg = 0x0210,
2397 .enable_mask = BIT(0),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "mmss_spdm_axi_clk",
2400 .parent_names = (const char *[]){
2401 "mmss_spdm_axi_div_clk",
2402 },
2403 .num_parents = 1,
2404 .flags = CLK_SET_RATE_PARENT,
2405 .ops = &clk_branch2_ops,
2406 },
2407 },
2408};
2409
2410static struct clk_branch mmss_spdm_csi0_clk = {
2411 .halt_reg = 0x023c,
2412 .clkr = {
2413 .enable_reg = 0x023c,
2414 .enable_mask = BIT(0),
2415 .hw.init = &(struct clk_init_data){
2416 .name = "mmss_spdm_csi0_clk",
2417 .parent_names = (const char *[]){
2418 "mmss_spdm_csi0_div_clk",
2419 },
2420 .num_parents = 1,
2421 .flags = CLK_SET_RATE_PARENT,
2422 .ops = &clk_branch2_ops,
2423 },
2424 },
2425};
2426
2427static struct clk_branch mmss_spdm_gfx3d_clk = {
2428 .halt_reg = 0x022c,
2429 .clkr = {
2430 .enable_reg = 0x022c,
2431 .enable_mask = BIT(0),
2432 .hw.init = &(struct clk_init_data){
2433 .name = "mmss_spdm_gfx3d_clk",
2434 .parent_names = (const char *[]){
2435 "mmss_spdm_gfx3d_div_clk",
2436 },
2437 .num_parents = 1,
2438 .flags = CLK_SET_RATE_PARENT,
2439 .ops = &clk_branch2_ops,
2440 },
2441 },
2442};
2443
2444static struct clk_branch mmss_spdm_jpeg0_clk = {
2445 .halt_reg = 0x0204,
2446 .clkr = {
2447 .enable_reg = 0x0204,
2448 .enable_mask = BIT(0),
2449 .hw.init = &(struct clk_init_data){
2450 .name = "mmss_spdm_jpeg0_clk",
2451 .parent_names = (const char *[]){
2452 "mmss_spdm_jpeg0_div_clk",
2453 },
2454 .num_parents = 1,
2455 .flags = CLK_SET_RATE_PARENT,
2456 .ops = &clk_branch2_ops,
2457 },
2458 },
2459};
2460
2461static struct clk_branch mmss_spdm_jpeg1_clk = {
2462 .halt_reg = 0x0208,
2463 .clkr = {
2464 .enable_reg = 0x0208,
2465 .enable_mask = BIT(0),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "mmss_spdm_jpeg1_clk",
2468 .parent_names = (const char *[]){
2469 "mmss_spdm_jpeg1_div_clk",
2470 },
2471 .num_parents = 1,
2472 .flags = CLK_SET_RATE_PARENT,
2473 .ops = &clk_branch2_ops,
2474 },
2475 },
2476};
2477
2478static struct clk_branch mmss_spdm_jpeg2_clk = {
2479 .halt_reg = 0x0224,
2480 .clkr = {
2481 .enable_reg = 0x0224,
2482 .enable_mask = BIT(0),
2483 .hw.init = &(struct clk_init_data){
2484 .name = "mmss_spdm_jpeg2_clk",
2485 .parent_names = (const char *[]){
2486 "mmss_spdm_jpeg2_div_clk",
2487 },
2488 .num_parents = 1,
2489 .flags = CLK_SET_RATE_PARENT,
2490 .ops = &clk_branch2_ops,
2491 },
2492 },
2493};
2494
2495static struct clk_branch mmss_spdm_mdp_clk = {
2496 .halt_reg = 0x020c,
2497 .clkr = {
2498 .enable_reg = 0x020c,
2499 .enable_mask = BIT(0),
2500 .hw.init = &(struct clk_init_data){
2501 .name = "mmss_spdm_mdp_clk",
2502 .parent_names = (const char *[]){
2503 "mmss_spdm_mdp_div_clk",
2504 },
2505 .num_parents = 1,
2506 .flags = CLK_SET_RATE_PARENT,
2507 .ops = &clk_branch2_ops,
2508 },
2509 },
2510};
2511
2512static struct clk_branch mmss_spdm_pclk0_clk = {
2513 .halt_reg = 0x0234,
2514 .clkr = {
2515 .enable_reg = 0x0234,
2516 .enable_mask = BIT(0),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "mmss_spdm_pclk0_clk",
2519 .parent_names = (const char *[]){
2520 "mmss_spdm_pclk0_div_clk",
2521 },
2522 .num_parents = 1,
2523 .flags = CLK_SET_RATE_PARENT,
2524 .ops = &clk_branch2_ops,
2525 },
2526 },
2527};
2528
2529static struct clk_branch mmss_spdm_pclk1_clk = {
2530 .halt_reg = 0x0228,
2531 .clkr = {
2532 .enable_reg = 0x0228,
2533 .enable_mask = BIT(0),
2534 .hw.init = &(struct clk_init_data){
2535 .name = "mmss_spdm_pclk1_clk",
2536 .parent_names = (const char *[]){
2537 "mmss_spdm_pclk1_div_clk",
2538 },
2539 .num_parents = 1,
2540 .flags = CLK_SET_RATE_PARENT,
2541 .ops = &clk_branch2_ops,
2542 },
2543 },
2544};
2545
2546static struct clk_branch mmss_spdm_vcodec0_clk = {
2547 .halt_reg = 0x0214,
2548 .clkr = {
2549 .enable_reg = 0x0214,
2550 .enable_mask = BIT(0),
2551 .hw.init = &(struct clk_init_data){
2552 .name = "mmss_spdm_vcodec0_clk",
2553 .parent_names = (const char *[]){
2554 "mmss_spdm_vcodec0_div_clk",
2555 },
2556 .num_parents = 1,
2557 .flags = CLK_SET_RATE_PARENT,
2558 .ops = &clk_branch2_ops,
2559 },
2560 },
2561};
2562
2563static struct clk_branch mmss_spdm_vfe0_clk = {
2564 .halt_reg = 0x0218,
2565 .clkr = {
2566 .enable_reg = 0x0218,
2567 .enable_mask = BIT(0),
2568 .hw.init = &(struct clk_init_data){
2569 .name = "mmss_spdm_vfe0_clk",
2570 .parent_names = (const char *[]){
2571 "mmss_spdm_vfe0_div_clk",
2572 },
2573 .num_parents = 1,
2574 .flags = CLK_SET_RATE_PARENT,
2575 .ops = &clk_branch2_ops,
2576 },
2577 },
2578};
2579
2580static struct clk_branch mmss_spdm_vfe1_clk = {
2581 .halt_reg = 0x021c,
2582 .clkr = {
2583 .enable_reg = 0x021c,
2584 .enable_mask = BIT(0),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "mmss_spdm_vfe1_clk",
2587 .parent_names = (const char *[]){
2588 "mmss_spdm_vfe1_div_clk",
2589 },
2590 .num_parents = 1,
2591 .flags = CLK_SET_RATE_PARENT,
2592 .ops = &clk_branch2_ops,
2593 },
2594 },
2595};
2596
2597static struct clk_branch mmss_spdm_rm_axi_clk = {
2598 .halt_reg = 0x0304,
2599 .clkr = {
2600 .enable_reg = 0x0304,
2601 .enable_mask = BIT(0),
2602 .hw.init = &(struct clk_init_data){
2603 .name = "mmss_spdm_rm_axi_clk",
2604 .parent_names = (const char *[]){
2605 "mmss_axi_clk_src",
2606 },
2607 .num_parents = 1,
2608 .flags = CLK_SET_RATE_PARENT,
2609 .ops = &clk_branch2_ops,
2610 },
2611 },
2612};
2613
2614static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2615 .halt_reg = 0x0308,
2616 .clkr = {
2617 .enable_reg = 0x0308,
2618 .enable_mask = BIT(0),
2619 .hw.init = &(struct clk_init_data){
2620 .name = "mmss_spdm_rm_ocmemnoc_clk",
2621 .parent_names = (const char *[]){
2622 "ocmemnoc_clk_src",
2623 },
2624 .num_parents = 1,
2625 .flags = CLK_SET_RATE_PARENT,
2626 .ops = &clk_branch2_ops,
2627 },
2628 },
2629};
2630
2631
2632static struct clk_branch mmss_misc_ahb_clk = {
2633 .halt_reg = 0x502c,
2634 .clkr = {
2635 .enable_reg = 0x502c,
2636 .enable_mask = BIT(0),
2637 .hw.init = &(struct clk_init_data){
2638 .name = "mmss_misc_ahb_clk",
2639 .parent_names = (const char *[]){
2640 "mmss_ahb_clk_src",
2641 },
2642 .num_parents = 1,
2643 .flags = CLK_SET_RATE_PARENT,
2644 .ops = &clk_branch2_ops,
2645 },
2646 },
2647};
2648
2649static struct clk_branch mmss_mmssnoc_ahb_clk = {
2650 .halt_reg = 0x5024,
2651 .clkr = {
2652 .enable_reg = 0x5024,
2653 .enable_mask = BIT(0),
2654 .hw.init = &(struct clk_init_data){
2655 .name = "mmss_mmssnoc_ahb_clk",
2656 .parent_names = (const char *[]){
2657 "mmss_ahb_clk_src",
2658 },
2659 .num_parents = 1,
2660 .ops = &clk_branch2_ops,
2661 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2662 },
2663 },
2664};
2665
2666static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2667 .halt_reg = 0x5028,
2668 .clkr = {
2669 .enable_reg = 0x5028,
2670 .enable_mask = BIT(0),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "mmss_mmssnoc_bto_ahb_clk",
2673 .parent_names = (const char *[]){
2674 "mmss_ahb_clk_src",
2675 },
2676 .num_parents = 1,
2677 .ops = &clk_branch2_ops,
2678 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2679 },
2680 },
2681};
2682
2683static struct clk_branch mmss_mmssnoc_axi_clk = {
2684 .halt_reg = 0x506c,
2685 .clkr = {
2686 .enable_reg = 0x506c,
2687 .enable_mask = BIT(0),
2688 .hw.init = &(struct clk_init_data){
2689 .name = "mmss_mmssnoc_axi_clk",
2690 .parent_names = (const char *[]){
2691 "mmss_axi_clk_src",
2692 },
2693 .num_parents = 1,
2694 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2695 .ops = &clk_branch2_ops,
2696 },
2697 },
2698};
2699
2700static struct clk_branch mmss_s0_axi_clk = {
2701 .halt_reg = 0x5064,
2702 .clkr = {
2703 .enable_reg = 0x5064,
2704 .enable_mask = BIT(0),
2705 .hw.init = &(struct clk_init_data){
2706 .name = "mmss_s0_axi_clk",
2707 .parent_names = (const char *[]){
2708 "mmss_axi_clk_src",
2709 },
2710 .num_parents = 1,
2711 .ops = &clk_branch2_ops,
2712 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2713 },
2714 },
2715};
2716
2717static struct clk_branch ocmemcx_ahb_clk = {
2718 .halt_reg = 0x405c,
2719 .clkr = {
2720 .enable_reg = 0x405c,
2721 .enable_mask = BIT(0),
2722 .hw.init = &(struct clk_init_data){
2723 .name = "ocmemcx_ahb_clk",
2724 .parent_names = (const char *[]){
2725 "mmss_ahb_clk_src",
2726 },
2727 .num_parents = 1,
2728 .flags = CLK_SET_RATE_PARENT,
2729 .ops = &clk_branch2_ops,
2730 },
2731 },
2732};
2733
2734static struct clk_branch ocmemcx_ocmemnoc_clk = {
2735 .halt_reg = 0x4058,
2736 .clkr = {
2737 .enable_reg = 0x4058,
2738 .enable_mask = BIT(0),
2739 .hw.init = &(struct clk_init_data){
2740 .name = "ocmemcx_ocmemnoc_clk",
2741 .parent_names = (const char *[]){
2742 "ocmemnoc_clk_src",
2743 },
2744 .num_parents = 1,
2745 .flags = CLK_SET_RATE_PARENT,
2746 .ops = &clk_branch2_ops,
2747 },
2748 },
2749};
2750
2751static struct clk_branch oxili_ocmemgx_clk = {
2752 .halt_reg = 0x402c,
2753 .clkr = {
2754 .enable_reg = 0x402c,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(struct clk_init_data){
2757 .name = "oxili_ocmemgx_clk",
2758 .parent_names = (const char *[]){
2759 "gfx3d_clk_src",
2760 },
2761 .num_parents = 1,
2762 .flags = CLK_SET_RATE_PARENT,
2763 .ops = &clk_branch2_ops,
2764 },
2765 },
2766};
2767
2768static struct clk_branch oxili_gfx3d_clk = {
2769 .halt_reg = 0x4028,
2770 .clkr = {
2771 .enable_reg = 0x4028,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "oxili_gfx3d_clk",
2775 .parent_names = (const char *[]){
2776 "gfx3d_clk_src",
2777 },
2778 .num_parents = 1,
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2781 },
2782 },
2783};
2784
2785static struct clk_branch oxili_rbbmtimer_clk = {
2786 .halt_reg = 0x40b0,
2787 .clkr = {
2788 .enable_reg = 0x40b0,
2789 .enable_mask = BIT(0),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "oxili_rbbmtimer_clk",
2792 .parent_names = (const char *[]){
2793 "rbbmtimer_clk_src",
2794 },
2795 .num_parents = 1,
2796 .flags = CLK_SET_RATE_PARENT,
2797 .ops = &clk_branch2_ops,
2798 },
2799 },
2800};
2801
2802static struct clk_branch oxilicx_ahb_clk = {
2803 .halt_reg = 0x403c,
2804 .clkr = {
2805 .enable_reg = 0x403c,
2806 .enable_mask = BIT(0),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "oxilicx_ahb_clk",
2809 .parent_names = (const char *[]){
2810 "mmss_ahb_clk_src",
2811 },
2812 .num_parents = 1,
2813 .flags = CLK_SET_RATE_PARENT,
2814 .ops = &clk_branch2_ops,
2815 },
2816 },
2817};
2818
2819static struct clk_branch venus0_ahb_clk = {
2820 .halt_reg = 0x1030,
2821 .clkr = {
2822 .enable_reg = 0x1030,
2823 .enable_mask = BIT(0),
2824 .hw.init = &(struct clk_init_data){
2825 .name = "venus0_ahb_clk",
2826 .parent_names = (const char *[]){
2827 "mmss_ahb_clk_src",
2828 },
2829 .num_parents = 1,
2830 .flags = CLK_SET_RATE_PARENT,
2831 .ops = &clk_branch2_ops,
2832 },
2833 },
2834};
2835
2836static struct clk_branch venus0_axi_clk = {
2837 .halt_reg = 0x1034,
2838 .clkr = {
2839 .enable_reg = 0x1034,
2840 .enable_mask = BIT(0),
2841 .hw.init = &(struct clk_init_data){
2842 .name = "venus0_axi_clk",
2843 .parent_names = (const char *[]){
2844 "mmss_axi_clk_src",
2845 },
2846 .num_parents = 1,
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_branch2_ops,
2849 },
2850 },
2851};
2852
2853static struct clk_branch venus0_core0_vcodec_clk = {
2854 .halt_reg = 0x1048,
2855 .clkr = {
2856 .enable_reg = 0x1048,
2857 .enable_mask = BIT(0),
2858 .hw.init = &(struct clk_init_data){
2859 .name = "venus0_core0_vcodec_clk",
2860 .parent_names = (const char *[]){
2861 "vcodec0_clk_src",
2862 },
2863 .num_parents = 1,
2864 .flags = CLK_SET_RATE_PARENT,
2865 .ops = &clk_branch2_ops,
2866 },
2867 },
2868};
2869
2870static struct clk_branch venus0_core1_vcodec_clk = {
2871 .halt_reg = 0x104c,
2872 .clkr = {
2873 .enable_reg = 0x104c,
2874 .enable_mask = BIT(0),
2875 .hw.init = &(struct clk_init_data){
2876 .name = "venus0_core1_vcodec_clk",
2877 .parent_names = (const char *[]){
2878 "vcodec0_clk_src",
2879 },
2880 .num_parents = 1,
2881 .flags = CLK_SET_RATE_PARENT,
2882 .ops = &clk_branch2_ops,
2883 },
2884 },
2885};
2886
2887static struct clk_branch venus0_ocmemnoc_clk = {
2888 .halt_reg = 0x1038,
2889 .clkr = {
2890 .enable_reg = 0x1038,
2891 .enable_mask = BIT(0),
2892 .hw.init = &(struct clk_init_data){
2893 .name = "venus0_ocmemnoc_clk",
2894 .parent_names = (const char *[]){
2895 "ocmemnoc_clk_src",
2896 },
2897 .num_parents = 1,
2898 .flags = CLK_SET_RATE_PARENT,
2899 .ops = &clk_branch2_ops,
2900 },
2901 },
2902};
2903
2904static struct clk_branch venus0_vcodec0_clk = {
2905 .halt_reg = 0x1028,
2906 .clkr = {
2907 .enable_reg = 0x1028,
2908 .enable_mask = BIT(0),
2909 .hw.init = &(struct clk_init_data){
2910 .name = "venus0_vcodec0_clk",
2911 .parent_names = (const char *[]){
2912 "vcodec0_clk_src",
2913 },
2914 .num_parents = 1,
2915 .flags = CLK_SET_RATE_PARENT,
2916 .ops = &clk_branch2_ops,
2917 },
2918 },
2919};
2920
2921static struct clk_branch vpu_ahb_clk = {
2922 .halt_reg = 0x1430,
2923 .clkr = {
2924 .enable_reg = 0x1430,
2925 .enable_mask = BIT(0),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "vpu_ahb_clk",
2928 .parent_names = (const char *[]){
2929 "mmss_ahb_clk_src",
2930 },
2931 .num_parents = 1,
2932 .flags = CLK_SET_RATE_PARENT,
2933 .ops = &clk_branch2_ops,
2934 },
2935 },
2936};
2937
2938static struct clk_branch vpu_axi_clk = {
2939 .halt_reg = 0x143c,
2940 .clkr = {
2941 .enable_reg = 0x143c,
2942 .enable_mask = BIT(0),
2943 .hw.init = &(struct clk_init_data){
2944 .name = "vpu_axi_clk",
2945 .parent_names = (const char *[]){
2946 "mmss_axi_clk_src",
2947 },
2948 .num_parents = 1,
2949 .flags = CLK_SET_RATE_PARENT,
2950 .ops = &clk_branch2_ops,
2951 },
2952 },
2953};
2954
2955static struct clk_branch vpu_bus_clk = {
2956 .halt_reg = 0x1440,
2957 .clkr = {
2958 .enable_reg = 0x1440,
2959 .enable_mask = BIT(0),
2960 .hw.init = &(struct clk_init_data){
2961 .name = "vpu_bus_clk",
2962 .parent_names = (const char *[]){
2963 "vpu_bus_clk_src",
2964 },
2965 .num_parents = 1,
2966 .flags = CLK_SET_RATE_PARENT,
2967 .ops = &clk_branch2_ops,
2968 },
2969 },
2970};
2971
2972static struct clk_branch vpu_cxo_clk = {
2973 .halt_reg = 0x1434,
2974 .clkr = {
2975 .enable_reg = 0x1434,
2976 .enable_mask = BIT(0),
2977 .hw.init = &(struct clk_init_data){
2978 .name = "vpu_cxo_clk",
2979 .parent_names = (const char *[]){ "xo" },
2980 .num_parents = 1,
2981 .flags = CLK_SET_RATE_PARENT,
2982 .ops = &clk_branch2_ops,
2983 },
2984 },
2985};
2986
2987static struct clk_branch vpu_maple_clk = {
2988 .halt_reg = 0x142c,
2989 .clkr = {
2990 .enable_reg = 0x142c,
2991 .enable_mask = BIT(0),
2992 .hw.init = &(struct clk_init_data){
2993 .name = "vpu_maple_clk",
2994 .parent_names = (const char *[]){
2995 "maple_clk_src",
2996 },
2997 .num_parents = 1,
2998 .flags = CLK_SET_RATE_PARENT,
2999 .ops = &clk_branch2_ops,
3000 },
3001 },
3002};
3003
3004static struct clk_branch vpu_sleep_clk = {
3005 .halt_reg = 0x1438,
3006 .clkr = {
3007 .enable_reg = 0x1438,
3008 .enable_mask = BIT(0),
3009 .hw.init = &(struct clk_init_data){
3010 .name = "vpu_sleep_clk",
3011 .parent_names = (const char *[]){
3012 "sleep_clk_src",
3013 },
3014 .num_parents = 1,
3015 .flags = CLK_SET_RATE_PARENT,
3016 .ops = &clk_branch2_ops,
3017 },
3018 },
3019};
3020
3021static struct clk_branch vpu_vdp_clk = {
3022 .halt_reg = 0x1428,
3023 .clkr = {
3024 .enable_reg = 0x1428,
3025 .enable_mask = BIT(0),
3026 .hw.init = &(struct clk_init_data){
3027 .name = "vpu_vdp_clk",
3028 .parent_names = (const char *[]){
3029 "vdp_clk_src",
3030 },
3031 .num_parents = 1,
3032 .flags = CLK_SET_RATE_PARENT,
3033 .ops = &clk_branch2_ops,
3034 },
3035 },
3036};
3037
3038static const struct pll_config mmpll1_config = {
3039 .l = 60,
3040 .m = 25,
3041 .n = 32,
3042 .vco_val = 0x0,
3043 .vco_mask = 0x3 << 20,
3044 .pre_div_val = 0x0,
3045 .pre_div_mask = 0x7 << 12,
3046 .post_div_val = 0x0,
3047 .post_div_mask = 0x3 << 8,
3048 .mn_ena_mask = BIT(24),
3049 .main_output_mask = BIT(0),
3050};
3051
3052static const struct pll_config mmpll3_config = {
3053 .l = 48,
3054 .m = 7,
3055 .n = 16,
3056 .vco_val = 0x0,
3057 .vco_mask = 0x3 << 20,
3058 .pre_div_val = 0x0,
3059 .pre_div_mask = 0x7 << 12,
3060 .post_div_val = 0x0,
3061 .post_div_mask = 0x3 << 8,
3062 .mn_ena_mask = BIT(24),
3063 .main_output_mask = BIT(0),
3064 .aux_output_mask = BIT(1),
3065};
3066
Stephane Viaucb2eb7d2015-08-06 16:07:50 +05303067static struct gdsc venus0_gdsc = {
3068 .gdscr = 0x1024,
3069 .pd = {
3070 .name = "venus0",
3071 },
3072 .pwrsts = PWRSTS_OFF_ON,
3073};
3074
3075static struct gdsc venus0_core0_gdsc = {
3076 .gdscr = 0x1040,
3077 .pd = {
3078 .name = "venus0_core0",
3079 },
3080 .pwrsts = PWRSTS_OFF_ON,
3081};
3082
3083static struct gdsc venus0_core1_gdsc = {
3084 .gdscr = 0x1044,
3085 .pd = {
3086 .name = "venus0_core1",
3087 },
3088 .pwrsts = PWRSTS_OFF_ON,
3089};
3090
3091static struct gdsc mdss_gdsc = {
3092 .gdscr = 0x2304,
3093 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3094 .cxc_count = 2,
3095 .pd = {
3096 .name = "mdss",
3097 },
3098 .pwrsts = PWRSTS_OFF_ON,
3099};
3100
3101static struct gdsc camss_jpeg_gdsc = {
3102 .gdscr = 0x35a4,
3103 .pd = {
3104 .name = "camss_jpeg",
3105 },
3106 .pwrsts = PWRSTS_OFF_ON,
3107};
3108
3109static struct gdsc camss_vfe_gdsc = {
3110 .gdscr = 0x36a4,
3111 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3112 .cxc_count = 3,
3113 .pd = {
3114 .name = "camss_vfe",
3115 },
3116 .pwrsts = PWRSTS_OFF_ON,
3117};
3118
3119static struct gdsc oxili_gdsc = {
3120 .gdscr = 0x4024,
3121 .cxcs = (unsigned int []){ 0x4028 },
3122 .cxc_count = 1,
3123 .pd = {
3124 .name = "oxili",
3125 },
3126 .pwrsts = PWRSTS_OFF_ON,
3127};
3128
3129static struct gdsc oxilicx_gdsc = {
3130 .gdscr = 0x4034,
3131 .pd = {
3132 .name = "oxilicx",
3133 },
3134 .pwrsts = PWRSTS_OFF_ON,
3135};
3136
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003137static struct clk_regmap *mmcc_apq8084_clocks[] = {
3138 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3139 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3140 [MMPLL0] = &mmpll0.clkr,
3141 [MMPLL0_VOTE] = &mmpll0_vote,
3142 [MMPLL1] = &mmpll1.clkr,
3143 [MMPLL1_VOTE] = &mmpll1_vote,
3144 [MMPLL2] = &mmpll2.clkr,
3145 [MMPLL3] = &mmpll3.clkr,
3146 [MMPLL4] = &mmpll4.clkr,
3147 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3148 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3149 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3150 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3151 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3152 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3153 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3154 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3155 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3156 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3157 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3158 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3159 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3160 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3161 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3162 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3163 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3164 [VP_CLK_SRC] = &vp_clk_src.clkr,
3165 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3166 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3167 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3168 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3169 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3170 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3171 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3172 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3173 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3174 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3175 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3176 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3177 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3178 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3179 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3180 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3181 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3182 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3183 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
Georgi Djakov9a6cb702014-10-10 16:57:24 +03003184 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003185 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3186 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3187 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3188 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3189 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3190 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3191 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3192 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3193 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3194 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3195 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3196 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3197 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3198 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3199 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3200 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3201 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3202 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3203 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3204 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3205 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3206 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3207 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3208 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3209 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3210 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3211 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3212 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3213 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3214 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3215 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3216 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3217 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3218 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3219 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3220 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3221 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3222 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3223 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3224 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3225 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3226 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3227 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3228 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3229 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3230 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3231 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3232 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3233 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3234 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3235 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3236 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3237 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3238 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3239 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3240 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3241 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3242 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3243 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3244 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3245 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3246 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3247 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3248 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3249 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3250 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3251 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3252 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3253 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3254 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3255 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3256 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3257 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3258 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3259 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3260 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3261 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3262 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3263 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3264 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3265 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3266 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3267 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3268 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3269 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3270 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3271 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3272 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3273 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3274 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3275 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3276 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3277 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3278 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3279 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3280 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3281 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3282 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3283 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3284 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3285 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3286 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3287 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3288 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3289 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3290 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3291 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3292 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3293 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3294 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3295 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3296 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3297 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3298 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3299 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3300 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3301 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3302 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3303};
3304
3305static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3306 [MMSS_SPDM_RESET] = { 0x0200 },
3307 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3308 [VENUS0_RESET] = { 0x1020 },
3309 [VPU_RESET] = { 0x1400 },
3310 [MDSS_RESET] = { 0x2300 },
3311 [AVSYNC_RESET] = { 0x2400 },
3312 [CAMSS_PHY0_RESET] = { 0x3020 },
3313 [CAMSS_PHY1_RESET] = { 0x3050 },
3314 [CAMSS_PHY2_RESET] = { 0x3080 },
3315 [CAMSS_CSI0_RESET] = { 0x30b0 },
3316 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3317 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3318 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3319 [CAMSS_CSI1_RESET] = { 0x3120 },
3320 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3321 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3322 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3323 [CAMSS_CSI2_RESET] = { 0x3180 },
3324 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3325 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3326 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3327 [CAMSS_CSI3_RESET] = { 0x31e0 },
3328 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3329 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3330 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3331 [CAMSS_ISPIF_RESET] = { 0x3220 },
3332 [CAMSS_CCI_RESET] = { 0x3340 },
3333 [CAMSS_MCLK0_RESET] = { 0x3380 },
3334 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3335 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3336 [CAMSS_MCLK3_RESET] = { 0x3410 },
3337 [CAMSS_GP0_RESET] = { 0x3440 },
3338 [CAMSS_GP1_RESET] = { 0x3470 },
3339 [CAMSS_TOP_RESET] = { 0x3480 },
3340 [CAMSS_AHB_RESET] = { 0x3488 },
3341 [CAMSS_MICRO_RESET] = { 0x3490 },
3342 [CAMSS_JPEG_RESET] = { 0x35a0 },
3343 [CAMSS_VFE_RESET] = { 0x36a0 },
3344 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3345 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3346 [OXILI_RESET] = { 0x4020 },
3347 [OXILICX_RESET] = { 0x4030 },
3348 [OCMEMCX_RESET] = { 0x4050 },
3349 [MMSS_RBCRP_RESET] = { 0x4080 },
3350 [MMSSNOCAHB_RESET] = { 0x5020 },
3351 [MMSSNOCAXI_RESET] = { 0x5060 },
3352};
3353
Stephane Viaucb2eb7d2015-08-06 16:07:50 +05303354static struct gdsc *mmcc_apq8084_gdscs[] = {
3355 [VENUS0_GDSC] = &venus0_gdsc,
3356 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
3357 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
3358 [MDSS_GDSC] = &mdss_gdsc,
3359 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
3360 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
3361 [OXILI_GDSC] = &oxili_gdsc,
3362 [OXILICX_GDSC] = &oxilicx_gdsc,
3363};
3364
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003365static const struct regmap_config mmcc_apq8084_regmap_config = {
3366 .reg_bits = 32,
3367 .reg_stride = 4,
3368 .val_bits = 32,
3369 .max_register = 0x5104,
3370 .fast_io = true,
3371};
3372
3373static const struct qcom_cc_desc mmcc_apq8084_desc = {
3374 .config = &mmcc_apq8084_regmap_config,
3375 .clks = mmcc_apq8084_clocks,
3376 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3377 .resets = mmcc_apq8084_resets,
3378 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
Stephane Viaucb2eb7d2015-08-06 16:07:50 +05303379 .gdscs = mmcc_apq8084_gdscs,
3380 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003381};
3382
3383static const struct of_device_id mmcc_apq8084_match_table[] = {
3384 { .compatible = "qcom,mmcc-apq8084" },
3385 { }
3386};
3387MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3388
3389static int mmcc_apq8084_probe(struct platform_device *pdev)
3390{
3391 int ret;
3392 struct regmap *regmap;
3393
3394 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3395 if (ret)
3396 return ret;
3397
3398 regmap = dev_get_regmap(&pdev->dev, NULL);
3399 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3400 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3401
3402 return 0;
3403}
3404
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003405static struct platform_driver mmcc_apq8084_driver = {
3406 .probe = mmcc_apq8084_probe,
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003407 .driver = {
3408 .name = "mmcc-apq8084",
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003409 .of_match_table = mmcc_apq8084_match_table,
3410 },
3411};
3412module_platform_driver(mmcc_apq8084_driver);
3413
3414MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3415MODULE_LICENSE("GPL v2");
3416MODULE_ALIAS("platform:mmcc-apq8084");