blob: d7f2da127d13a452f984c63000e27b0d3c02a71a [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * Maybe PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME "pata_hpt366"
Alan Cox6ddd6862008-02-26 13:35:54 -080030#define DRV_VERSION "0.6.2"
Jeff Garzik669a5db2006-08-29 18:12:40 -040031
32struct hpt_clock {
Tejun Heo6ecb6f22009-01-08 16:29:20 -050033 u8 xfer_mode;
Jeff Garzik669a5db2006-08-29 18:12:40 -040034 u32 timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 * register access.
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
46 * register access.
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 * xfer.
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 * register access.
53 * 28 UDMA enable
54 * 29 DMA enable
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
56 * PIO.
57 * 31 FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
66
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
70
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
76 { 0, 0x0120d9d9 }
77};
78
79static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
85
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
89
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95 { 0, 0x0120a7a7 }
96};
97
98static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
104
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
108
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
114 { 0, 0x01208585 }
115};
116
117static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121 "Maxtor 90510D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125 NULL
126};
127
128static const char *bad_ata66_4[] = {
129 "IBM-DTLA-307075",
130 "IBM-DTLA-307060",
131 "IBM-DTLA-307045",
132 "IBM-DTLA-307030",
133 "IBM-DTLA-307020",
134 "IBM-DTLA-307015",
135 "IBM-DTLA-305040",
136 "IBM-DTLA-305030",
137 "IBM-DTLA-305020",
138 "IC35L010AVER07-0",
139 "IC35L020AVER07-0",
140 "IC35L030AVER07-0",
141 "IC35L040AVER07-0",
142 "IC35L060AVER07-0",
143 "WDC AC310200R",
144 NULL
145};
146
147static const char *bad_ata66_3[] = {
148 "WDC AC310200R",
149 NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900154 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 int i = 0;
156
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900159 while (list[i] != NULL) {
160 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 modestr, list[i]);
163 return 1;
164 }
165 i++;
166 }
167 return 0;
168}
169
170/**
171 * hpt366_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172 * @adev: ATA device
173 *
174 * Block UDMA on devices that cause trouble with this controller.
175 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400176
Alan Coxa76b62c2007-03-09 09:34:07 -0500177static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400178{
179 if (adev->class == ATA_DEV_ATA) {
180 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
181 mask &= ~ATA_MASK_UDMA;
182 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
Alan Cox6ddd6862008-02-26 13:35:54 -0800183 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
Alan Cox6ddd6862008-02-26 13:35:54 -0800185 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
Tejun Heo3ee89f12008-12-09 17:14:04 +0900186 } else if (adev->class == ATA_DEV_ATAPI)
187 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
188
Tejun Heo9363c382008-04-07 22:47:16 +0900189 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400190}
191
Alan Coxfecfda52007-03-08 19:34:28 +0000192static int hpt36x_cable_detect(struct ata_port *ap)
193{
Alan Coxfecfda52007-03-08 19:34:28 +0000194 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heobab5b322008-12-09 17:13:19 +0900195 u8 ata66;
Alan Coxfecfda52007-03-08 19:34:28 +0000196
Tejun Heobab5b322008-12-09 17:13:19 +0900197 /*
198 * Each channel of pata_hpt366 occupies separate PCI function
199 * as the primary channel and bit1 indicates the cable type.
200 */
Alan Coxfecfda52007-03-08 19:34:28 +0000201 pci_read_config_byte(pdev, 0x5A, &ata66);
Tejun Heobab5b322008-12-09 17:13:19 +0900202 if (ata66 & 2)
Alan Coxfecfda52007-03-08 19:34:28 +0000203 return ATA_CBL_PATA40;
204 return ATA_CBL_PATA80;
205}
206
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500207static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
208 u8 mode)
209{
210 struct hpt_clock *clocks = ap->host->private_data;
211 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
212 u32 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
213 u32 addr2 = 0x51 + 4 * ap->port_no;
214 u32 mask, reg;
215 u8 fast;
216
217 /* Fast interrupt prediction disable, hold off interrupt disable */
218 pci_read_config_byte(pdev, addr2, &fast);
219 if (fast & 0x80) {
220 fast &= ~0x80;
221 pci_write_config_byte(pdev, addr2, fast);
222 }
223
224 /* determine timing mask and find matching clock entry */
225 if (mode < XFER_MW_DMA_0)
226 mask = 0xc1f8ffff;
227 else if (mode < XFER_UDMA_0)
228 mask = 0x303800ff;
229 else
230 mask = 0x30070000;
231
232 while (clocks->xfer_mode) {
233 if (clocks->xfer_mode == mode)
234 break;
235 clocks++;
236 }
237 if (!clocks->xfer_mode)
238 BUG();
239
240 /*
241 * Combine new mode bits with old config bits and disable
242 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
243 * problems handling I/O errors later.
244 */
245 pci_read_config_dword(pdev, addr1, &reg);
246 reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
247 pci_write_config_dword(pdev, addr1, reg);
248}
249
Jeff Garzik669a5db2006-08-29 18:12:40 -0400250/**
251 * hpt366_set_piomode - PIO setup
252 * @ap: ATA interface
253 * @adev: device on the interface
254 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400255 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400256 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400257
Jeff Garzik669a5db2006-08-29 18:12:40 -0400258static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
259{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500260 hpt366_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400261}
262
263/**
264 * hpt366_set_dmamode - DMA timing setup
265 * @ap: ATA interface
266 * @adev: Device being configured
267 *
268 * Set up the channel for MWDMA or UDMA modes. Much the same as with
269 * PIO, load the mode number and then set MWDMA or UDMA flag.
270 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400271
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
273{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500274 hpt366_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400275}
276
277static struct scsi_host_template hpt36x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900278 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279};
280
281/*
282 * Configuration for HPT366/68
283 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400284
Jeff Garzik669a5db2006-08-29 18:12:40 -0400285static struct ata_port_operations hpt366_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900286 .inherits = &ata_bmdma_port_ops,
287 .cable_detect = hpt36x_cable_detect,
288 .mode_filter = hpt366_filter,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400289 .set_piomode = hpt366_set_piomode,
290 .set_dmamode = hpt366_set_dmamode,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400291};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400292
293/**
Alanaa54ab12006-11-27 16:24:15 +0000294 * hpt36x_init_chipset - common chip setup
295 * @dev: PCI device
296 *
297 * Perform the chip setup work that must be done at both init and
298 * resume time
299 */
300
301static void hpt36x_init_chipset(struct pci_dev *dev)
302{
303 u8 drive_fast;
304 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
305 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
306 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
307 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
308
309 pci_read_config_byte(dev, 0x51, &drive_fast);
310 if (drive_fast & 0x80)
311 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
312}
313
314/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400315 * hpt36x_init_one - Initialise an HPT366/368
316 * @dev: PCI device
317 * @id: Entry in match table
318 *
319 * Initialise an HPT36x device. There are some interesting complications
320 * here. Firstly the chip may report 366 and be one of several variants.
321 * Secondly all the timings depend on the clock for the chip which we must
322 * detect and look up
323 *
324 * This is the known chip mappings. It may be missing a couple of later
325 * releases.
326 *
327 * Chip version PCI Rev Notes
328 * HPT366 4 (HPT366) 0 UDMA66
329 * HPT366 4 (HPT366) 1 UDMA66
330 * HPT368 4 (HPT366) 2 UDMA66
331 * HPT37x/30x 4 (HPT366) 3+ Other driver
332 *
333 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400334
Jeff Garzik669a5db2006-08-29 18:12:40 -0400335static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
336{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200337 static const struct ata_port_info info_hpt366 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400338 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100339 .pio_mask = ATA_PIO4,
340 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400341 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400342 .port_ops = &hpt366_port_ops
343 };
Tejun Heo887125e2008-03-25 12:22:49 +0900344 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345
Tejun Heo887125e2008-03-25 12:22:49 +0900346 void *hpriv = NULL;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400347 u32 class_rev;
348 u32 reg1;
Tejun Heof08048e2008-03-25 12:22:47 +0900349 int rc;
350
351 rc = pcim_enable_device(dev);
352 if (rc)
353 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400354
355 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
356 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400357
Jeff Garzik669a5db2006-08-29 18:12:40 -0400358 /* May be a later chip in disguise. Check */
359 /* Newer chips are not in the HPT36x driver. Ignore them */
360 if (class_rev > 2)
361 return -ENODEV;
362
Alanaa54ab12006-11-27 16:24:15 +0000363 hpt36x_init_chipset(dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364
365 pci_read_config_dword(dev, 0x40, &reg1);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400366
Jeff Garzik669a5db2006-08-29 18:12:40 -0400367 /* PCI clocking determines the ATA timing values to use */
368 /* info_hpt366 is safe against re-entry so we can scribble on it */
OGAWA Hirofumi2c136ef2006-10-03 01:14:03 -0700369 switch((reg1 & 0x700) >> 8) {
Tejun Heo2456eb82008-12-08 18:48:42 +0900370 case 9:
Tejun Heo887125e2008-03-25 12:22:49 +0900371 hpriv = &hpt366_40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400372 break;
Tejun Heo2456eb82008-12-08 18:48:42 +0900373 case 5:
Tejun Heo887125e2008-03-25 12:22:49 +0900374 hpriv = &hpt366_25;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400375 break;
376 default:
Tejun Heo887125e2008-03-25 12:22:49 +0900377 hpriv = &hpt366_33;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400378 break;
379 }
380 /* Now kick off ATA set up */
Tejun Heo9363c382008-04-07 22:47:16 +0900381 return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400382}
383
Tejun Heo438ac6d2007-03-02 17:31:26 +0900384#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000385static int hpt36x_reinit_one(struct pci_dev *dev)
386{
Tejun Heof08048e2008-03-25 12:22:47 +0900387 struct ata_host *host = dev_get_drvdata(&dev->dev);
388 int rc;
389
390 rc = ata_pci_device_do_resume(dev);
391 if (rc)
392 return rc;
Alanaa54ab12006-11-27 16:24:15 +0000393 hpt36x_init_chipset(dev);
Tejun Heof08048e2008-03-25 12:22:47 +0900394 ata_host_resume(host);
395 return 0;
Alanaa54ab12006-11-27 16:24:15 +0000396}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900397#endif
Alanaa54ab12006-11-27 16:24:15 +0000398
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400399static const struct pci_device_id hpt36x[] = {
400 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400401 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400402};
403
404static struct pci_driver hpt36x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400405 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400406 .id_table = hpt36x,
407 .probe = hpt36x_init_one,
Alanaa54ab12006-11-27 16:24:15 +0000408 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900409#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000410 .suspend = ata_pci_device_suspend,
411 .resume = hpt36x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900412#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400413};
414
415static int __init hpt36x_init(void)
416{
417 return pci_register_driver(&hpt36x_pci_driver);
418}
419
Jeff Garzik669a5db2006-08-29 18:12:40 -0400420static void __exit hpt36x_exit(void)
421{
422 pci_unregister_driver(&hpt36x_pci_driver);
423}
424
Jeff Garzik669a5db2006-08-29 18:12:40 -0400425MODULE_AUTHOR("Alan Cox");
426MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
427MODULE_LICENSE("GPL");
428MODULE_DEVICE_TABLE(pci, hpt36x);
429MODULE_VERSION(DRV_VERSION);
430
431module_init(hpt36x_init);
432module_exit(hpt36x_exit);