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Colin Cross2d5cd9a2010-01-28 16:41:42 -08001/*
2 * arch/arch/mach-tegra/timer.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/init.h>
Russell King5e06b642010-12-15 19:19:25 +000021#include <linux/sched.h>
Colin Cross2d5cd9a2010-01-28 16:41:42 -080022#include <linux/time.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/clockchips.h>
26#include <linux/clocksource.h>
27#include <linux/clk.h>
28#include <linux/io.h>
Colin Cross2d5cd9a2010-01-28 16:41:42 -080029
30#include <asm/mach/time.h>
Colin Cross2d5cd9a2010-01-28 16:41:42 -080031#include <asm/localtimer.h>
Russell Kinge3f4c0a2010-12-15 21:49:42 +000032#include <asm/sched_clock.h>
Colin Cross2d5cd9a2010-01-28 16:41:42 -080033
34#include <mach/iomap.h>
35#include <mach/irqs.h>
Colin Cross2ea67fd2010-10-04 08:49:49 -070036#include <mach/suspend.h>
Colin Cross2d5cd9a2010-01-28 16:41:42 -080037
38#include "board.h"
39#include "clock.h"
40
Colin Cross09361782010-11-28 16:26:19 -080041#define RTC_SECONDS 0x08
42#define RTC_SHADOW_SECONDS 0x0c
43#define RTC_MILLISECONDS 0x10
44
Colin Cross2d5cd9a2010-01-28 16:41:42 -080045#define TIMERUS_CNTR_1US 0x10
46#define TIMERUS_USEC_CFG 0x14
47#define TIMERUS_CNTR_FREEZE 0x4c
48
49#define TIMER1_BASE 0x0
50#define TIMER2_BASE 0x8
51#define TIMER3_BASE 0x50
52#define TIMER4_BASE 0x58
53
54#define TIMER_PTV 0x0
55#define TIMER_PCR 0x4
56
Colin Cross2d5cd9a2010-01-28 16:41:42 -080057static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
Colin Cross09361782010-11-28 16:26:19 -080058static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
59
60static struct timespec persistent_ts;
61static u64 persistent_ms, last_persistent_ms;
Colin Cross2d5cd9a2010-01-28 16:41:42 -080062
63#define timer_writel(value, reg) \
64 __raw_writel(value, (u32)timer_reg_base + (reg))
65#define timer_readl(reg) \
66 __raw_readl((u32)timer_reg_base + (reg))
67
68static int tegra_timer_set_next_event(unsigned long cycles,
69 struct clock_event_device *evt)
70{
71 u32 reg;
72
73 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
74 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
75
76 return 0;
77}
78
79static void tegra_timer_set_mode(enum clock_event_mode mode,
80 struct clock_event_device *evt)
81{
82 u32 reg;
83
84 timer_writel(0, TIMER3_BASE + TIMER_PTV);
85
86 switch (mode) {
87 case CLOCK_EVT_MODE_PERIODIC:
88 reg = 0xC0000000 | ((1000000/HZ)-1);
89 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
90 break;
91 case CLOCK_EVT_MODE_ONESHOT:
92 break;
93 case CLOCK_EVT_MODE_UNUSED:
94 case CLOCK_EVT_MODE_SHUTDOWN:
95 case CLOCK_EVT_MODE_RESUME:
96 break;
97 }
98}
99
100static cycle_t tegra_clocksource_read(struct clocksource *cs)
101{
Colin Cross684e94c2010-11-17 16:20:15 -0800102 return timer_readl(TIMERUS_CNTR_1US);
Colin Cross2d5cd9a2010-01-28 16:41:42 -0800103}
104
105static struct clock_event_device tegra_clockevent = {
106 .name = "timer0",
107 .rating = 300,
108 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
109 .set_next_event = tegra_timer_set_next_event,
110 .set_mode = tegra_timer_set_mode,
111};
112
113static struct clocksource tegra_clocksource = {
114 .name = "timer_us",
115 .rating = 300,
116 .read = tegra_clocksource_read,
Colin Cross684e94c2010-11-17 16:20:15 -0800117 .mask = CLOCKSOURCE_MASK(32),
Colin Cross2d5cd9a2010-01-28 16:41:42 -0800118 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
119};
120
Russell Kinge3f4c0a2010-12-15 21:49:42 +0000121static DEFINE_CLOCK_DATA(cd);
122
123/*
124 * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
125 * This gives a resolution of about 1us and a wrap period of about 1h11min.
126 */
127#define SC_MULT 4194304000u
128#define SC_SHIFT 22
129
Russell King5e06b642010-12-15 19:19:25 +0000130unsigned long long notrace sched_clock(void)
Colin Cross2d5cd9a2010-01-28 16:41:42 -0800131{
Russell Kinge3f4c0a2010-12-15 21:49:42 +0000132 u32 cyc = timer_readl(TIMERUS_CNTR_1US);
133 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
134}
135
136static void notrace tegra_update_sched_clock(void)
137{
138 u32 cyc = timer_readl(TIMERUS_CNTR_1US);
139 update_sched_clock(&cd, cyc, (u32)~0);
Colin Cross2d5cd9a2010-01-28 16:41:42 -0800140}
141
Colin Cross09361782010-11-28 16:26:19 -0800142/*
143 * tegra_rtc_read - Reads the Tegra RTC registers
144 * Care must be taken that this funciton is not called while the
145 * tegra_rtc driver could be executing to avoid race conditions
146 * on the RTC shadow register
147 */
148u64 tegra_rtc_read_ms(void)
149{
150 u32 ms = readl(rtc_base + RTC_MILLISECONDS);
151 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
152 return (u64)s * MSEC_PER_SEC + ms;
153}
154
155/*
156 * read_persistent_clock - Return time from a persistent clock.
157 *
158 * Reads the time from a source which isn't disabled during PM, the
159 * 32k sync timer. Convert the cycles elapsed since last read into
160 * nsecs and adds to a monotonically increasing timespec.
161 * Care must be taken that this funciton is not called while the
162 * tegra_rtc driver could be executing to avoid race conditions
163 * on the RTC shadow register
164 */
165void read_persistent_clock(struct timespec *ts)
166{
167 u64 delta;
168 struct timespec *tsp = &persistent_ts;
169
170 last_persistent_ms = persistent_ms;
171 persistent_ms = tegra_rtc_read_ms();
172 delta = persistent_ms - last_persistent_ms;
173
174 timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
175 *ts = *tsp;
176}
177
Colin Cross2d5cd9a2010-01-28 16:41:42 -0800178static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
179{
180 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
181 timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
182 evt->event_handler(evt);
183 return IRQ_HANDLED;
184}
185
186static struct irqaction tegra_timer_irq = {
187 .name = "timer0",
188 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
189 .handler = tegra_timer_interrupt,
190 .dev_id = &tegra_clockevent,
191 .irq = INT_TMR3,
192};
193
194static void __init tegra_init_timer(void)
195{
196 unsigned long rate = clk_measure_input_freq();
197 int ret;
198
199#ifdef CONFIG_HAVE_ARM_TWD
200 twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
201#endif
202
203 switch (rate) {
204 case 12000000:
205 timer_writel(0x000b, TIMERUS_USEC_CFG);
206 break;
207 case 13000000:
208 timer_writel(0x000c, TIMERUS_USEC_CFG);
209 break;
210 case 19200000:
211 timer_writel(0x045f, TIMERUS_USEC_CFG);
212 break;
213 case 26000000:
214 timer_writel(0x0019, TIMERUS_USEC_CFG);
215 break;
216 default:
217 WARN(1, "Unknown clock rate");
218 }
219
Russell Kinge3f4c0a2010-12-15 21:49:42 +0000220 init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
221 1000000, SC_MULT, SC_SHIFT);
222
Colin Cross2d5cd9a2010-01-28 16:41:42 -0800223 if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
224 printk(KERN_ERR "Failed to register clocksource\n");
225 BUG();
226 }
227
228 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
229 if (ret) {
230 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
231 BUG();
232 }
233
234 clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
235 tegra_clockevent.max_delta_ns =
236 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
237 tegra_clockevent.min_delta_ns =
238 clockevent_delta2ns(0x1, &tegra_clockevent);
239 tegra_clockevent.cpumask = cpu_all_mask;
240 tegra_clockevent.irq = tegra_timer_irq.irq;
241 clockevents_register_device(&tegra_clockevent);
242
243 return;
244}
245
246struct sys_timer tegra_timer = {
247 .init = tegra_init_timer,
248};
Colin Cross09361782010-11-28 16:26:19 -0800249
250#ifdef CONFIG_PM
251static u32 usec_config;
252
253void tegra_timer_suspend(void)
254{
255 usec_config = timer_readl(TIMERUS_USEC_CFG);
256}
257
258void tegra_timer_resume(void)
259{
260 timer_writel(usec_config, TIMERUS_USEC_CFG);
261}
262#endif