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Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080012#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/slab.h>
17#include <linux/interrupt.h>
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080018#include <linux/io.h>
19#include <linux/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080020#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24/* Since we request GPIOs from ourself */
25#include <linux/pinctrl/consumer.h>
26
Alexandre Bellonic654b6b2014-10-17 11:49:40 +020027#include "pinctrl-at91.h"
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080028#include "core.h"
29
Linus Walleij94daf852013-11-05 10:30:14 +010030#define MAX_GPIO_BANKS 5
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080031#define MAX_NB_GPIO_PER_BANK 32
32
33struct at91_pinctrl_mux_ops;
34
35struct at91_gpio_chip {
36 struct gpio_chip chip;
37 struct pinctrl_gpio_range range;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */
39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq; /* PIO bank Linux virtual interrupt */
41 int pioc_idx; /* PIO bank index */
42 void __iomem *regbase; /* PIO bank virtual address */
43 struct clk *clock; /* associated clock */
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080044 struct at91_pinctrl_mux_ops *ops; /* ops */
45};
46
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080047static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
48
49static int gpio_banks;
50
Jean-Christophe PLAGNIOL-VILLARD525fae22012-10-23 18:28:00 +020051#define PULL_UP (1 << 0)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080052#define MULTI_DRIVE (1 << 1)
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +080053#define DEGLITCH (1 << 2)
54#define PULL_DOWN (1 << 3)
55#define DIS_SCHMIT (1 << 4)
Marek Roszko4334ac22014-08-23 23:12:04 -040056#define DRIVE_STRENGTH_SHIFT 5
57#define DRIVE_STRENGTH_MASK 0x3
58#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +080059#define DEBOUNCE (1 << 16)
60#define DEBOUNCE_VAL_SHIFT 17
61#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080062
63/**
Marek Roszko4334ac22014-08-23 23:12:04 -040064 * These defines will translated the dt binding settings to our internal
65 * settings. They are not necessarily the same value as the register setting.
66 * The actual drive strength current of low, medium and high must be looked up
67 * from the corresponding device datasheet. This value is different for pins
68 * that are even in the same banks. It is also dependent on VCC.
69 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
70 * strength when there is no dt config for it.
71 */
72#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
73#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
74#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
75#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
76
77/**
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080078 * struct at91_pmx_func - describes AT91 pinmux functions
79 * @name: the name of this specific function
80 * @groups: corresponding pin groups
81 * @ngroups: the number of groups
82 */
83struct at91_pmx_func {
84 const char *name;
85 const char **groups;
86 unsigned ngroups;
87};
88
89enum at91_mux {
90 AT91_MUX_GPIO = 0,
91 AT91_MUX_PERIPH_A = 1,
92 AT91_MUX_PERIPH_B = 2,
93 AT91_MUX_PERIPH_C = 3,
94 AT91_MUX_PERIPH_D = 4,
95};
96
97/**
98 * struct at91_pmx_pin - describes an At91 pin mux
99 * @bank: the bank of the pin
100 * @pin: the pin number in the @bank
101 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
102 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
103 */
104struct at91_pmx_pin {
105 uint32_t bank;
106 uint32_t pin;
107 enum at91_mux mux;
108 unsigned long conf;
109};
110
111/**
112 * struct at91_pin_group - describes an At91 pin group
113 * @name: the name of this specific pin group
114 * @pins_conf: the mux mode for each pin in this group. The size of this
115 * array is the same as pins.
116 * @pins: an array of discrete physical pins used in this group, taken
117 * from the driver-local pin enumeration space
118 * @npins: the number of pins in this group array, i.e. the number of
119 * elements in .pins so we can iterate over that array
120 */
121struct at91_pin_group {
122 const char *name;
123 struct at91_pmx_pin *pins_conf;
124 unsigned int *pins;
125 unsigned npins;
126};
127
128/**
Alexandre Bellonic2eb9e72013-12-07 14:08:52 +0100129 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800130 * on new IP with support for periph C and D the way to mux in
131 * periph A and B has changed
132 * So provide the right call back
133 * if not present means the IP does not support it
134 * @get_periph: return the periph mode configured
135 * @mux_A_periph: mux as periph A
136 * @mux_B_periph: mux as periph B
137 * @mux_C_periph: mux as periph C
138 * @mux_D_periph: mux as periph D
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800139 * @get_deglitch: get deglitch status
140 * @set_deglitch: enable/disable deglitch
141 * @get_debounce: get debounce status
142 * @set_debounce: enable/disable debounce
143 * @get_pulldown: get pulldown status
144 * @set_pulldown: enable/disable pulldown
145 * @get_schmitt_trig: get schmitt trigger status
146 * @disable_schmitt_trig: disable schmitt trigger
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800147 * @irq_type: return irq type
148 */
149struct at91_pinctrl_mux_ops {
150 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
151 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
152 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
153 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
154 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800155 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
Boris BREZILLON77966ad2013-09-13 09:45:33 +0200156 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800157 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
Boris BREZILLON77966ad2013-09-13 09:45:33 +0200158 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800159 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
Boris BREZILLON77966ad2013-09-13 09:45:33 +0200160 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800161 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
162 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
Marek Roszko4334ac22014-08-23 23:12:04 -0400163 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
164 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
165 u32 strength);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800166 /* irq */
167 int (*irq_type)(struct irq_data *d, unsigned type);
168};
169
170static int gpio_irq_type(struct irq_data *d, unsigned type);
171static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
172
173struct at91_pinctrl {
174 struct device *dev;
175 struct pinctrl_dev *pctl;
176
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +0100177 int nactive_banks;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800178
179 uint32_t *mux_mask;
180 int nmux;
181
182 struct at91_pmx_func *functions;
183 int nfunctions;
184
185 struct at91_pin_group *groups;
186 int ngroups;
187
188 struct at91_pinctrl_mux_ops *ops;
189};
190
Arnd Bergmann56411f32016-06-13 17:18:34 +0200191static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800192 const struct at91_pinctrl *info,
193 const char *name)
194{
195 const struct at91_pin_group *grp = NULL;
196 int i;
197
198 for (i = 0; i < info->ngroups; i++) {
199 if (strcmp(info->groups[i].name, name))
200 continue;
201
202 grp = &info->groups[i];
203 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
204 break;
205 }
206
207 return grp;
208}
209
210static int at91_get_groups_count(struct pinctrl_dev *pctldev)
211{
212 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
213
214 return info->ngroups;
215}
216
217static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
218 unsigned selector)
219{
220 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
221
222 return info->groups[selector].name;
223}
224
225static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
226 const unsigned **pins,
227 unsigned *npins)
228{
229 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
230
231 if (selector >= info->ngroups)
232 return -EINVAL;
233
234 *pins = info->groups[selector].pins;
235 *npins = info->groups[selector].npins;
236
237 return 0;
238}
239
240static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
241 unsigned offset)
242{
243 seq_printf(s, "%s", dev_name(pctldev->dev));
244}
245
246static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
247 struct device_node *np,
248 struct pinctrl_map **map, unsigned *num_maps)
249{
250 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
251 const struct at91_pin_group *grp;
252 struct pinctrl_map *new_map;
253 struct device_node *parent;
254 int map_num = 1;
255 int i;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800256
257 /*
Alexandre Belloni61e310a2013-10-16 16:12:33 +0200258 * first find the group of this node and check if we need to create
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800259 * config maps for pins
260 */
261 grp = at91_pinctrl_find_group_by_name(info, np->name);
262 if (!grp) {
263 dev_err(info->dev, "unable to find group for node %s\n",
264 np->name);
265 return -EINVAL;
266 }
267
268 map_num += grp->npins;
269 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
270 if (!new_map)
271 return -ENOMEM;
272
273 *map = new_map;
274 *num_maps = map_num;
275
276 /* create mux map */
277 parent = of_get_parent(np);
278 if (!parent) {
Julia Lawallc62b2b32012-12-12 15:22:44 +0100279 devm_kfree(pctldev->dev, new_map);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800280 return -EINVAL;
281 }
282 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
283 new_map[0].data.mux.function = parent->name;
284 new_map[0].data.mux.group = np->name;
285 of_node_put(parent);
286
287 /* create config map */
288 new_map++;
289 for (i = 0; i < grp->npins; i++) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800290 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
291 new_map[i].data.configs.group_or_pin =
292 pin_get_name(pctldev, grp->pins[i]);
293 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
294 new_map[i].data.configs.num_configs = 1;
295 }
296
297 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
298 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
299
300 return 0;
301}
302
303static void at91_dt_free_map(struct pinctrl_dev *pctldev,
304 struct pinctrl_map *map, unsigned num_maps)
305{
306}
307
Laurent Pinchart022ab142013-02-16 10:25:07 +0100308static const struct pinctrl_ops at91_pctrl_ops = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800309 .get_groups_count = at91_get_groups_count,
310 .get_group_name = at91_get_group_name,
311 .get_group_pins = at91_get_group_pins,
312 .pin_dbg_show = at91_pin_dbg_show,
313 .dt_node_to_map = at91_dt_node_to_map,
314 .dt_free_map = at91_dt_free_map,
315};
316
Sachin Kamat3c936002013-03-15 10:07:03 +0530317static void __iomem *pin_to_controller(struct at91_pinctrl *info,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800318 unsigned int bank)
319{
David Dueck1ab36382015-07-28 09:48:16 +0200320 if (!gpio_chips[bank])
321 return NULL;
322
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800323 return gpio_chips[bank]->regbase;
324}
325
326static inline int pin_to_bank(unsigned pin)
327{
328 return pin /= MAX_NB_GPIO_PER_BANK;
329}
330
331static unsigned pin_to_mask(unsigned int pin)
332{
333 return 1 << pin;
334}
335
Marek Roszko4334ac22014-08-23 23:12:04 -0400336static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
337{
338 /* return the shift value for a pin for "two bit" per pin registers,
339 * i.e. drive strength */
340 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
341 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
342}
343
344static unsigned sama5d3_get_drive_register(unsigned int pin)
345{
346 /* drive strength is split between two registers
347 * with two bits per pin */
348 return (pin >= MAX_NB_GPIO_PER_BANK/2)
349 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
350}
351
352static unsigned at91sam9x5_get_drive_register(unsigned int pin)
353{
354 /* drive strength is split between two registers
355 * with two bits per pin */
356 return (pin >= MAX_NB_GPIO_PER_BANK/2)
357 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
358}
359
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800360static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
361{
362 writel_relaxed(mask, pio + PIO_IDR);
363}
364
365static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
366{
Boris BREZILLON05d35342013-08-27 15:19:21 +0200367 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800368}
369
370static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
371{
Wenyou Yang3d784272014-09-11 16:40:15 +0200372 if (on)
373 writel_relaxed(mask, pio + PIO_PPDDR);
374
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800375 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
376}
377
378static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
379{
380 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
381}
382
383static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
384{
385 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
386}
387
388static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
389{
390 writel_relaxed(mask, pio + PIO_ASR);
391}
392
393static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
394{
395 writel_relaxed(mask, pio + PIO_BSR);
396}
397
398static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
399{
400
401 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
402 pio + PIO_ABCDSR1);
403 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
404 pio + PIO_ABCDSR2);
405}
406
407static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
408{
409 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
410 pio + PIO_ABCDSR1);
411 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
412 pio + PIO_ABCDSR2);
413}
414
415static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
416{
417 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
418 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
419}
420
421static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
422{
423 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
424 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
425}
426
427static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
428{
429 unsigned select;
430
431 if (readl_relaxed(pio + PIO_PSR) & mask)
432 return AT91_MUX_GPIO;
433
434 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
435 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
436
437 return select + 1;
438}
439
440static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
441{
442 unsigned select;
443
444 if (readl_relaxed(pio + PIO_PSR) & mask)
445 return AT91_MUX_GPIO;
446
447 select = readl_relaxed(pio + PIO_ABSR) & mask;
448
449 return select + 1;
450}
451
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800452static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
453{
Ben Dooksd4802392015-03-26 12:18:49 +0000454 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800455}
456
457static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
458{
Ben Dooksd4802392015-03-26 12:18:49 +0000459 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800460}
461
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200462static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
463{
Ben Dooksd4802392015-03-26 12:18:49 +0000464 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
465 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200466
467 return false;
468}
469
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800470static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
471{
472 if (is_on)
Ben Dooksd4802392015-03-26 12:18:49 +0000473 writel_relaxed(mask, pio + PIO_IFSCDR);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800474 at91_mux_set_deglitch(pio, mask, is_on);
475}
476
477static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
478{
Ben Dooksd4802392015-03-26 12:18:49 +0000479 *div = readl_relaxed(pio + PIO_SCDR);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800480
Ben Dooksd4802392015-03-26 12:18:49 +0000481 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
482 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800483}
484
485static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
486 bool is_on, u32 div)
487{
488 if (is_on) {
Ben Dooksd4802392015-03-26 12:18:49 +0000489 writel_relaxed(mask, pio + PIO_IFSCER);
490 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
491 writel_relaxed(mask, pio + PIO_IFER);
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200492 } else
Ben Dooksd4802392015-03-26 12:18:49 +0000493 writel_relaxed(mask, pio + PIO_IFSCDR);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800494}
495
496static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
497{
Ben Dooksd4802392015-03-26 12:18:49 +0000498 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800499}
500
501static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
502{
Wenyou Yang3d784272014-09-11 16:40:15 +0200503 if (is_on)
Ben Dooksd4802392015-03-26 12:18:49 +0000504 writel_relaxed(mask, pio + PIO_PUDR);
Wenyou Yang3d784272014-09-11 16:40:15 +0200505
Ben Dooksd4802392015-03-26 12:18:49 +0000506 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800507}
508
509static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
510{
Ben Dooksd4802392015-03-26 12:18:49 +0000511 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800512}
513
514static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
515{
Ben Dooksd4802392015-03-26 12:18:49 +0000516 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800517}
518
Marek Roszko4334ac22014-08-23 23:12:04 -0400519static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
520{
Ben Dooksd4802392015-03-26 12:18:49 +0000521 unsigned tmp = readl_relaxed(reg);
Marek Roszko4334ac22014-08-23 23:12:04 -0400522
523 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
524
525 return tmp & DRIVE_STRENGTH_MASK;
526}
527
528static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
529 unsigned pin)
530{
531 unsigned tmp = read_drive_strength(pio +
532 sama5d3_get_drive_register(pin), pin);
533
534 /* SAMA5 strength is 1:1 with our defines,
535 * except 0 is equivalent to low per datasheet */
536 if (!tmp)
537 tmp = DRIVE_STRENGTH_LOW;
538
539 return tmp;
540}
541
542static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
543 unsigned pin)
544{
545 unsigned tmp = read_drive_strength(pio +
546 at91sam9x5_get_drive_register(pin), pin);
547
548 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
549 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
550 tmp = DRIVE_STRENGTH_HI - tmp;
551
552 return tmp;
553}
554
555static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
556{
Ben Dooksd4802392015-03-26 12:18:49 +0000557 unsigned tmp = readl_relaxed(reg);
Marek Roszko4334ac22014-08-23 23:12:04 -0400558 unsigned shift = two_bit_pin_value_shift_amount(pin);
559
560 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
561 tmp |= strength << shift;
562
Ben Dooksd4802392015-03-26 12:18:49 +0000563 writel_relaxed(tmp, reg);
Marek Roszko4334ac22014-08-23 23:12:04 -0400564}
565
566static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
567 u32 setting)
568{
569 /* do nothing if setting is zero */
570 if (!setting)
571 return;
572
573 /* strength is 1 to 1 with setting for SAMA5 */
574 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
575}
576
577static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
578 u32 setting)
579{
580 /* do nothing if setting is zero */
581 if (!setting)
582 return;
583
584 /* strength is inverse on SAM9x5s with our defines
585 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
586 setting = DRIVE_STRENGTH_HI - setting;
587
588 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
589 setting);
590}
591
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800592static struct at91_pinctrl_mux_ops at91rm9200_ops = {
593 .get_periph = at91_mux_get_periph,
594 .mux_A_periph = at91_mux_set_A_periph,
595 .mux_B_periph = at91_mux_set_B_periph,
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800596 .get_deglitch = at91_mux_get_deglitch,
597 .set_deglitch = at91_mux_set_deglitch,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800598 .irq_type = gpio_irq_type,
599};
600
601static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
602 .get_periph = at91_mux_pio3_get_periph,
603 .mux_A_periph = at91_mux_pio3_set_A_periph,
604 .mux_B_periph = at91_mux_pio3_set_B_periph,
605 .mux_C_periph = at91_mux_pio3_set_C_periph,
606 .mux_D_periph = at91_mux_pio3_set_D_periph,
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200607 .get_deglitch = at91_mux_pio3_get_deglitch,
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800608 .set_deglitch = at91_mux_pio3_set_deglitch,
609 .get_debounce = at91_mux_pio3_get_debounce,
610 .set_debounce = at91_mux_pio3_set_debounce,
611 .get_pulldown = at91_mux_pio3_get_pulldown,
612 .set_pulldown = at91_mux_pio3_set_pulldown,
613 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
614 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
Marek Roszko4334ac22014-08-23 23:12:04 -0400615 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
616 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
617 .irq_type = alt_gpio_irq_type,
618};
619
620static struct at91_pinctrl_mux_ops sama5d3_ops = {
621 .get_periph = at91_mux_pio3_get_periph,
622 .mux_A_periph = at91_mux_pio3_set_A_periph,
623 .mux_B_periph = at91_mux_pio3_set_B_periph,
624 .mux_C_periph = at91_mux_pio3_set_C_periph,
625 .mux_D_periph = at91_mux_pio3_set_D_periph,
626 .get_deglitch = at91_mux_pio3_get_deglitch,
627 .set_deglitch = at91_mux_pio3_set_deglitch,
628 .get_debounce = at91_mux_pio3_get_debounce,
629 .set_debounce = at91_mux_pio3_set_debounce,
630 .get_pulldown = at91_mux_pio3_get_pulldown,
631 .set_pulldown = at91_mux_pio3_set_pulldown,
632 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
633 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
634 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
635 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800636 .irq_type = alt_gpio_irq_type,
637};
638
639static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
640{
641 if (pin->mux) {
Hans Wennborg4b6fe452014-08-05 21:43:16 -0700642 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800643 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
644 } else {
Hans Wennborg4b6fe452014-08-05 21:43:16 -0700645 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800646 pin->bank + 'A', pin->pin, pin->conf);
647 }
648}
649
Sachin Kamat3c936002013-03-15 10:07:03 +0530650static int pin_check_config(struct at91_pinctrl *info, const char *name,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800651 int index, const struct at91_pmx_pin *pin)
652{
653 int mux;
654
655 /* check if it's a valid config */
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +0100656 if (pin->bank >= gpio_banks) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800657 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +0100658 name, index, pin->bank, gpio_banks);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800659 return -EINVAL;
660 }
661
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +0100662 if (!gpio_chips[pin->bank]) {
663 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
664 name, index, pin->bank);
665 return -ENXIO;
666 }
667
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800668 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
669 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
670 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
671 return -EINVAL;
672 }
673
674 if (!pin->mux)
675 return 0;
676
677 mux = pin->mux - 1;
678
679 if (mux >= info->nmux) {
680 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
681 name, index, mux, info->nmux);
682 return -EINVAL;
683 }
684
685 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
686 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
687 name, index, mux, pin->bank + 'A', pin->pin);
688 return -EINVAL;
689 }
690
691 return 0;
692}
693
694static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
695{
696 writel_relaxed(mask, pio + PIO_PDR);
697}
698
699static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
700{
701 writel_relaxed(mask, pio + PIO_PER);
702 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
703}
704
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200705static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
706 unsigned group)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800707{
708 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
709 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
710 const struct at91_pmx_pin *pin;
711 uint32_t npins = info->groups[group].npins;
712 int i, ret;
713 unsigned mask;
714 void __iomem *pio;
715
716 dev_dbg(info->dev, "enable function %s group %s\n",
717 info->functions[selector].name, info->groups[group].name);
718
719 /* first check that all the pins of the group are valid with a valid
Alexandre Belloni61e310a2013-10-16 16:12:33 +0200720 * parameter */
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800721 for (i = 0; i < npins; i++) {
722 pin = &pins_conf[i];
723 ret = pin_check_config(info, info->groups[group].name, i, pin);
724 if (ret)
725 return ret;
726 }
727
728 for (i = 0; i < npins; i++) {
729 pin = &pins_conf[i];
730 at91_pin_dbg(info->dev, pin);
731 pio = pin_to_controller(info, pin->bank);
David Dueck1ab36382015-07-28 09:48:16 +0200732
733 if (!pio)
734 continue;
735
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800736 mask = pin_to_mask(pin->pin);
737 at91_mux_disable_interrupt(pio, mask);
Sachin Kamat3c936002013-03-15 10:07:03 +0530738 switch (pin->mux) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800739 case AT91_MUX_GPIO:
740 at91_mux_gpio_enable(pio, mask, 1);
741 break;
742 case AT91_MUX_PERIPH_A:
743 info->ops->mux_A_periph(pio, mask);
744 break;
745 case AT91_MUX_PERIPH_B:
746 info->ops->mux_B_periph(pio, mask);
747 break;
748 case AT91_MUX_PERIPH_C:
749 if (!info->ops->mux_C_periph)
750 return -EINVAL;
751 info->ops->mux_C_periph(pio, mask);
752 break;
753 case AT91_MUX_PERIPH_D:
754 if (!info->ops->mux_D_periph)
755 return -EINVAL;
756 info->ops->mux_D_periph(pio, mask);
757 break;
758 }
759 if (pin->mux)
760 at91_mux_gpio_disable(pio, mask);
761 }
762
763 return 0;
764}
765
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800766static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
767{
768 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
769
770 return info->nfunctions;
771}
772
773static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
774 unsigned selector)
775{
776 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
777
778 return info->functions[selector].name;
779}
780
781static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
782 const char * const **groups,
783 unsigned * const num_groups)
784{
785 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
786
787 *groups = info->functions[selector].groups;
788 *num_groups = info->functions[selector].ngroups;
789
790 return 0;
791}
792
Axel Linf6f94f62012-11-05 21:23:50 +0800793static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
794 struct pinctrl_gpio_range *range,
795 unsigned offset)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800796{
797 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
798 struct at91_gpio_chip *at91_chip;
799 struct gpio_chip *chip;
800 unsigned mask;
801
802 if (!range) {
803 dev_err(npct->dev, "invalid range\n");
804 return -EINVAL;
805 }
806 if (!range->gc) {
807 dev_err(npct->dev, "missing GPIO chip in range\n");
808 return -EINVAL;
809 }
810 chip = range->gc;
Linus Walleij370ea612015-12-08 09:27:45 +0100811 at91_chip = gpiochip_get_data(chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800812
813 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
814
815 mask = 1 << (offset - chip->base);
816
817 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
818 offset, 'A' + range->id, offset - chip->base, mask);
819
820 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
821
822 return 0;
823}
824
Axel Linf6f94f62012-11-05 21:23:50 +0800825static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
826 struct pinctrl_gpio_range *range,
827 unsigned offset)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800828{
829 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
830
831 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
832 /* Set the pin to some default state, GPIO is usually default */
833}
834
Laurent Pinchart022ab142013-02-16 10:25:07 +0100835static const struct pinmux_ops at91_pmx_ops = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800836 .get_functions_count = at91_pmx_get_funcs_count,
837 .get_function_name = at91_pmx_get_func_name,
838 .get_function_groups = at91_pmx_get_groups,
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200839 .set_mux = at91_pmx_set,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800840 .gpio_request_enable = at91_gpio_request_enable,
841 .gpio_disable_free = at91_gpio_disable_free,
842};
843
844static int at91_pinconf_get(struct pinctrl_dev *pctldev,
845 unsigned pin_id, unsigned long *config)
846{
847 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
848 void __iomem *pio;
849 unsigned pin;
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800850 int div;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800851
Alexandre Belloni1292e692013-12-07 14:08:53 +0100852 *config = 0;
853 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800854 pio = pin_to_controller(info, pin_to_bank(pin_id));
David Dueck1ab36382015-07-28 09:48:16 +0200855
856 if (!pio)
857 return -EINVAL;
858
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800859 pin = pin_id % MAX_NB_GPIO_PER_BANK;
860
861 if (at91_mux_get_multidrive(pio, pin))
862 *config |= MULTI_DRIVE;
863
864 if (at91_mux_get_pullup(pio, pin))
865 *config |= PULL_UP;
866
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800867 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
868 *config |= DEGLITCH;
869 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
870 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
871 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
872 *config |= PULL_DOWN;
873 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
874 *config |= DIS_SCHMIT;
Marek Roszko4334ac22014-08-23 23:12:04 -0400875 if (info->ops->get_drivestrength)
876 *config |= (info->ops->get_drivestrength(pio, pin)
877 << DRIVE_STRENGTH_SHIFT);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800878
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800879 return 0;
880}
881
882static int at91_pinconf_set(struct pinctrl_dev *pctldev,
Sherman Yin03b054e2013-08-27 11:32:12 -0700883 unsigned pin_id, unsigned long *configs,
884 unsigned num_configs)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800885{
886 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
887 unsigned mask;
888 void __iomem *pio;
Sherman Yin03b054e2013-08-27 11:32:12 -0700889 int i;
890 unsigned long config;
Marek Roszko4334ac22014-08-23 23:12:04 -0400891 unsigned pin;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800892
Sherman Yin03b054e2013-08-27 11:32:12 -0700893 for (i = 0; i < num_configs; i++) {
894 config = configs[i];
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800895
Sherman Yin03b054e2013-08-27 11:32:12 -0700896 dev_dbg(info->dev,
897 "%s:%d, pin_id=%d, config=0x%lx",
898 __func__, __LINE__, pin_id, config);
899 pio = pin_to_controller(info, pin_to_bank(pin_id));
David Dueck1ab36382015-07-28 09:48:16 +0200900
901 if (!pio)
902 return -EINVAL;
903
Marek Roszko4334ac22014-08-23 23:12:04 -0400904 pin = pin_id % MAX_NB_GPIO_PER_BANK;
905 mask = pin_to_mask(pin);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800906
Sherman Yin03b054e2013-08-27 11:32:12 -0700907 if (config & PULL_UP && config & PULL_DOWN)
908 return -EINVAL;
909
910 at91_mux_set_pullup(pio, mask, config & PULL_UP);
911 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
912 if (info->ops->set_deglitch)
913 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
914 if (info->ops->set_debounce)
915 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800916 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
Sherman Yin03b054e2013-08-27 11:32:12 -0700917 if (info->ops->set_pulldown)
918 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
919 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
920 info->ops->disable_schmitt_trig(pio, mask);
Marek Roszko4334ac22014-08-23 23:12:04 -0400921 if (info->ops->set_drivestrength)
922 info->ops->set_drivestrength(pio, pin,
923 (config & DRIVE_STRENGTH)
924 >> DRIVE_STRENGTH_SHIFT);
Sherman Yin03b054e2013-08-27 11:32:12 -0700925
926 } /* for each config */
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800927
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800928 return 0;
929}
930
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100931#define DBG_SHOW_FLAG(flag) do { \
932 if (config & flag) { \
933 if (num_conf) \
934 seq_puts(s, "|"); \
935 seq_puts(s, #flag); \
936 num_conf++; \
937 } \
938} while (0)
939
Marek Roszko4334ac22014-08-23 23:12:04 -0400940#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
941 if ((config & mask) == flag) { \
942 if (num_conf) \
943 seq_puts(s, "|"); \
944 seq_puts(s, #flag); \
945 num_conf++; \
946 } \
947} while (0)
948
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800949static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
950 struct seq_file *s, unsigned pin_id)
951{
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100952 unsigned long config;
Rickard Strandqvist445d2022014-06-26 15:41:31 +0200953 int val, num_conf = 0;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800954
Rickard Strandqvist445d2022014-06-26 15:41:31 +0200955 at91_pinconf_get(pctldev, pin_id, &config);
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100956
957 DBG_SHOW_FLAG(MULTI_DRIVE);
958 DBG_SHOW_FLAG(PULL_UP);
959 DBG_SHOW_FLAG(PULL_DOWN);
960 DBG_SHOW_FLAG(DIS_SCHMIT);
961 DBG_SHOW_FLAG(DEGLITCH);
Marek Roszko4334ac22014-08-23 23:12:04 -0400962 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
963 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
964 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100965 DBG_SHOW_FLAG(DEBOUNCE);
966 if (config & DEBOUNCE) {
967 val = config >> DEBOUNCE_VAL_SHIFT;
968 seq_printf(s, "(%d)", val);
969 }
970
971 return;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800972}
973
974static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
975 struct seq_file *s, unsigned group)
976{
977}
978
Laurent Pinchart022ab142013-02-16 10:25:07 +0100979static const struct pinconf_ops at91_pinconf_ops = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800980 .pin_config_get = at91_pinconf_get,
981 .pin_config_set = at91_pinconf_set,
982 .pin_config_dbg_show = at91_pinconf_dbg_show,
983 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
984};
985
986static struct pinctrl_desc at91_pinctrl_desc = {
987 .pctlops = &at91_pctrl_ops,
988 .pmxops = &at91_pmx_ops,
989 .confops = &at91_pinconf_ops,
990 .owner = THIS_MODULE,
991};
992
993static const char *gpio_compat = "atmel,at91rm9200-gpio";
994
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800995static void at91_pinctrl_child_count(struct at91_pinctrl *info,
996 struct device_node *np)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800997{
998 struct device_node *child;
999
1000 for_each_child_of_node(np, child) {
1001 if (of_device_is_compatible(child, gpio_compat)) {
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001002 if (of_device_is_available(child))
1003 info->nactive_banks++;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001004 } else {
1005 info->nfunctions++;
1006 info->ngroups += of_get_child_count(child);
1007 }
1008 }
1009}
1010
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001011static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1012 struct device_node *np)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001013{
1014 int ret = 0;
1015 int size;
Sachin Kamat1164d732013-03-15 10:07:02 +05301016 const __be32 *list;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001017
1018 list = of_get_property(np, "atmel,mux-mask", &size);
1019 if (!list) {
1020 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1021 return -EINVAL;
1022 }
1023
1024 size /= sizeof(*list);
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001025 if (!size || size % gpio_banks) {
1026 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001027 return -EINVAL;
1028 }
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001029 info->nmux = size / gpio_banks;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001030
1031 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1032 if (!info->mux_mask) {
1033 dev_err(info->dev, "could not alloc mux_mask\n");
1034 return -ENOMEM;
1035 }
1036
1037 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1038 info->mux_mask, size);
1039 if (ret)
1040 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1041 return ret;
1042}
1043
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001044static int at91_pinctrl_parse_groups(struct device_node *np,
1045 struct at91_pin_group *grp,
1046 struct at91_pinctrl *info, u32 index)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001047{
1048 struct at91_pmx_pin *pin;
1049 int size;
Sachin Kamat1164d732013-03-15 10:07:02 +05301050 const __be32 *list;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001051 int i, j;
1052
1053 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1054
1055 /* Initialise group */
1056 grp->name = np->name;
1057
1058 /*
1059 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1060 * do sanity check and calculate pins number
1061 */
1062 list = of_get_property(np, "atmel,pins", &size);
1063 /* we do not check return since it's safe node passed down */
1064 size /= sizeof(*list);
1065 if (!size || size % 4) {
1066 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1067 return -EINVAL;
1068 }
1069
1070 grp->npins = size / 4;
1071 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
1072 GFP_KERNEL);
1073 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1074 GFP_KERNEL);
1075 if (!grp->pins_conf || !grp->pins)
1076 return -ENOMEM;
1077
1078 for (i = 0, j = 0; i < size; i += 4, j++) {
1079 pin->bank = be32_to_cpu(*list++);
1080 pin->pin = be32_to_cpu(*list++);
1081 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1082 pin->mux = be32_to_cpu(*list++);
1083 pin->conf = be32_to_cpu(*list++);
1084
1085 at91_pin_dbg(info->dev, pin);
1086 pin++;
1087 }
1088
1089 return 0;
1090}
1091
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001092static int at91_pinctrl_parse_functions(struct device_node *np,
1093 struct at91_pinctrl *info, u32 index)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001094{
1095 struct device_node *child;
1096 struct at91_pmx_func *func;
1097 struct at91_pin_group *grp;
1098 int ret;
1099 static u32 grp_index;
1100 u32 i = 0;
1101
1102 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1103
1104 func = &info->functions[index];
1105
1106 /* Initialise function */
1107 func->name = np->name;
1108 func->ngroups = of_get_child_count(np);
Rickard Strandqvistca7162a2014-06-26 13:26:45 +02001109 if (func->ngroups == 0) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001110 dev_err(info->dev, "no groups defined\n");
1111 return -EINVAL;
1112 }
1113 func->groups = devm_kzalloc(info->dev,
1114 func->ngroups * sizeof(char *), GFP_KERNEL);
1115 if (!func->groups)
1116 return -ENOMEM;
1117
1118 for_each_child_of_node(np, child) {
1119 func->groups[i] = child->name;
1120 grp = &info->groups[grp_index++];
1121 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
Julia Lawalld94b9862015-10-24 16:42:35 +02001122 if (ret) {
1123 of_node_put(child);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001124 return ret;
Julia Lawalld94b9862015-10-24 16:42:35 +02001125 }
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001126 }
1127
1128 return 0;
1129}
1130
Fabian Frederickbaa9946e2015-03-16 20:59:09 +01001131static const struct of_device_id at91_pinctrl_of_match[] = {
Marek Roszko4334ac22014-08-23 23:12:04 -04001132 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001133 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1134 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1135 { /* sentinel */ }
1136};
1137
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001138static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1139 struct at91_pinctrl *info)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001140{
1141 int ret = 0;
1142 int i, j;
1143 uint32_t *tmp;
1144 struct device_node *np = pdev->dev.of_node;
1145 struct device_node *child;
1146
1147 if (!np)
1148 return -ENODEV;
1149
1150 info->dev = &pdev->dev;
Sachin Kamat3c936002013-03-15 10:07:03 +05301151 info->ops = (struct at91_pinctrl_mux_ops *)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001152 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1153 at91_pinctrl_child_count(info, np);
1154
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001155 if (gpio_banks < 1) {
Alexandre Belloni61e310a2013-10-16 16:12:33 +02001156 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001157 return -EINVAL;
1158 }
1159
1160 ret = at91_pinctrl_mux_mask(info, np);
1161 if (ret)
1162 return ret;
1163
1164 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1165
1166 dev_dbg(&pdev->dev, "mux-mask\n");
1167 tmp = info->mux_mask;
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001168 for (i = 0; i < gpio_banks; i++) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001169 for (j = 0; j < info->nmux; j++, tmp++) {
1170 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1171 }
1172 }
1173
1174 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1175 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1176 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1177 GFP_KERNEL);
1178 if (!info->functions)
1179 return -ENOMEM;
1180
1181 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1182 GFP_KERNEL);
1183 if (!info->groups)
1184 return -ENOMEM;
1185
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001186 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001187 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1188 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1189
1190 i = 0;
1191
1192 for_each_child_of_node(np, child) {
1193 if (of_device_is_compatible(child, gpio_compat))
1194 continue;
1195 ret = at91_pinctrl_parse_functions(child, info, i++);
1196 if (ret) {
1197 dev_err(&pdev->dev, "failed to parse function\n");
Julia Lawalld94b9862015-10-24 16:42:35 +02001198 of_node_put(child);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001199 return ret;
1200 }
1201 }
1202
1203 return 0;
1204}
1205
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001206static int at91_pinctrl_probe(struct platform_device *pdev)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001207{
1208 struct at91_pinctrl *info;
1209 struct pinctrl_pin_desc *pdesc;
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001210 int ret, i, j, k, ngpio_chips_enabled = 0;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001211
1212 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1213 if (!info)
1214 return -ENOMEM;
1215
1216 ret = at91_pinctrl_probe_dt(pdev, info);
1217 if (ret)
1218 return ret;
1219
1220 /*
1221 * We need all the GPIO drivers to probe FIRST, or we will not be able
1222 * to obtain references to the struct gpio_chip * for them, and we
1223 * need this to proceed.
1224 */
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001225 for (i = 0; i < gpio_banks; i++)
1226 if (gpio_chips[i])
1227 ngpio_chips_enabled++;
1228
1229 if (ngpio_chips_enabled < info->nactive_banks) {
1230 dev_warn(&pdev->dev,
1231 "All GPIO chips are not registered yet (%d/%d)\n",
1232 ngpio_chips_enabled, info->nactive_banks);
1233 devm_kfree(&pdev->dev, info);
1234 return -EPROBE_DEFER;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001235 }
1236
1237 at91_pinctrl_desc.name = dev_name(&pdev->dev);
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001238 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001239 at91_pinctrl_desc.pins = pdesc =
1240 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1241
1242 if (!at91_pinctrl_desc.pins)
1243 return -ENOMEM;
1244
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001245 for (i = 0, k = 0; i < gpio_banks; i++) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001246 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1247 pdesc->number = k;
1248 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1249 pdesc++;
1250 }
1251 }
1252
1253 platform_set_drvdata(pdev, info);
Laxman Dewangan5c674252016-02-28 14:32:19 +05301254 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1255 info);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001256
Masahiro Yamada323de9e2015-06-09 13:01:16 +09001257 if (IS_ERR(info->pctl)) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001258 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
Masahiro Yamada323de9e2015-06-09 13:01:16 +09001259 return PTR_ERR(info->pctl);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001260 }
1261
1262 /* We will handle a range of GPIO pins */
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001263 for (i = 0; i < gpio_banks; i++)
1264 if (gpio_chips[i])
1265 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001266
1267 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1268
1269 return 0;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001270}
1271
Richard Genoud8af584b2014-02-17 17:57:26 +01001272static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1273{
Linus Walleij370ea612015-12-08 09:27:45 +01001274 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Richard Genoud8af584b2014-02-17 17:57:26 +01001275 void __iomem *pio = at91_gpio->regbase;
1276 unsigned mask = 1 << offset;
1277 u32 osr;
1278
1279 osr = readl_relaxed(pio + PIO_OSR);
1280 return !(osr & mask);
1281}
1282
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001283static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1284{
Linus Walleij370ea612015-12-08 09:27:45 +01001285 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001286 void __iomem *pio = at91_gpio->regbase;
1287 unsigned mask = 1 << offset;
1288
1289 writel_relaxed(mask, pio + PIO_ODR);
1290 return 0;
1291}
1292
1293static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1294{
Linus Walleij370ea612015-12-08 09:27:45 +01001295 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001296 void __iomem *pio = at91_gpio->regbase;
1297 unsigned mask = 1 << offset;
1298 u32 pdsr;
1299
1300 pdsr = readl_relaxed(pio + PIO_PDSR);
1301 return (pdsr & mask) != 0;
1302}
1303
1304static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1305 int val)
1306{
Linus Walleij370ea612015-12-08 09:27:45 +01001307 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001308 void __iomem *pio = at91_gpio->regbase;
1309 unsigned mask = 1 << offset;
1310
1311 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1312}
1313
Alexander Stein1893b2c2015-04-02 11:55:49 +02001314static void at91_gpio_set_multiple(struct gpio_chip *chip,
1315 unsigned long *mask, unsigned long *bits)
1316{
Linus Walleij370ea612015-12-08 09:27:45 +01001317 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Alexander Stein1893b2c2015-04-02 11:55:49 +02001318 void __iomem *pio = at91_gpio->regbase;
1319
1320#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1321 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1322 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1323 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1324
1325 writel_relaxed(set_mask, pio + PIO_SODR);
1326 writel_relaxed(clear_mask, pio + PIO_CODR);
1327}
1328
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001329static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1330 int val)
1331{
Linus Walleij370ea612015-12-08 09:27:45 +01001332 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001333 void __iomem *pio = at91_gpio->regbase;
1334 unsigned mask = 1 << offset;
1335
1336 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1337 writel_relaxed(mask, pio + PIO_OER);
1338
1339 return 0;
1340}
1341
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001342#ifdef CONFIG_DEBUG_FS
1343static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1344{
1345 enum at91_mux mode;
1346 int i;
Linus Walleij370ea612015-12-08 09:27:45 +01001347 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001348 void __iomem *pio = at91_gpio->regbase;
1349
1350 for (i = 0; i < chip->ngpio; i++) {
Alexander Stein47f22712014-04-14 20:53:08 +02001351 unsigned mask = pin_to_mask(i);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001352 const char *gpio_label;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001353
1354 gpio_label = gpiochip_is_requested(chip, i);
1355 if (!gpio_label)
1356 continue;
1357 mode = at91_gpio->ops->get_periph(pio, mask);
1358 seq_printf(s, "[%s] GPIO%s%d: ",
1359 gpio_label, chip->label, i);
1360 if (mode == AT91_MUX_GPIO) {
Matthieu Crapet853b6bf2014-11-18 15:43:45 +01001361 seq_printf(s, "[gpio] ");
1362 seq_printf(s, "%s ",
1363 readl_relaxed(pio + PIO_OSR) & mask ?
1364 "output" : "input");
1365 seq_printf(s, "%s\n",
1366 readl_relaxed(pio + PIO_PDSR) & mask ?
1367 "set" : "clear");
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001368 } else {
1369 seq_printf(s, "[periph %c]\n",
1370 mode + 'A' - 1);
1371 }
1372 }
1373}
1374#else
1375#define at91_gpio_dbg_show NULL
1376#endif
1377
1378/* Several AIC controller irqs are dispatched through this GPIO handler.
1379 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1380 * at91_set_gpio_input() then maybe enable its glitch filter.
1381 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1382 * handler.
1383 * First implementation always triggers on rising and falling edges
1384 * whereas the newer PIO3 can be additionally configured to trigger on
1385 * level, edge with any polarity.
1386 *
1387 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1388 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1389 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1390 */
1391
1392static void gpio_irq_mask(struct irq_data *d)
1393{
1394 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1395 void __iomem *pio = at91_gpio->regbase;
1396 unsigned mask = 1 << d->hwirq;
1397
1398 if (pio)
1399 writel_relaxed(mask, pio + PIO_IDR);
1400}
1401
1402static void gpio_irq_unmask(struct irq_data *d)
1403{
1404 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1405 void __iomem *pio = at91_gpio->regbase;
1406 unsigned mask = 1 << d->hwirq;
1407
1408 if (pio)
1409 writel_relaxed(mask, pio + PIO_IER);
1410}
1411
1412static int gpio_irq_type(struct irq_data *d, unsigned type)
1413{
1414 switch (type) {
1415 case IRQ_TYPE_NONE:
1416 case IRQ_TYPE_EDGE_BOTH:
1417 return 0;
1418 default:
1419 return -EINVAL;
1420 }
1421}
1422
1423/* Alternate irq type for PIO3 support */
1424static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1425{
1426 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1427 void __iomem *pio = at91_gpio->regbase;
1428 unsigned mask = 1 << d->hwirq;
1429
1430 switch (type) {
1431 case IRQ_TYPE_EDGE_RISING:
Thomas Gleixnerc639845b2015-06-23 15:52:49 +02001432 irq_set_handler_locked(d, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001433 writel_relaxed(mask, pio + PIO_ESR);
1434 writel_relaxed(mask, pio + PIO_REHLSR);
1435 break;
1436 case IRQ_TYPE_EDGE_FALLING:
Thomas Gleixnerc639845b2015-06-23 15:52:49 +02001437 irq_set_handler_locked(d, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001438 writel_relaxed(mask, pio + PIO_ESR);
1439 writel_relaxed(mask, pio + PIO_FELLSR);
1440 break;
1441 case IRQ_TYPE_LEVEL_LOW:
Thomas Gleixnerc639845b2015-06-23 15:52:49 +02001442 irq_set_handler_locked(d, handle_level_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001443 writel_relaxed(mask, pio + PIO_LSR);
1444 writel_relaxed(mask, pio + PIO_FELLSR);
1445 break;
1446 case IRQ_TYPE_LEVEL_HIGH:
Thomas Gleixnerc639845b2015-06-23 15:52:49 +02001447 irq_set_handler_locked(d, handle_level_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001448 writel_relaxed(mask, pio + PIO_LSR);
1449 writel_relaxed(mask, pio + PIO_REHLSR);
1450 break;
1451 case IRQ_TYPE_EDGE_BOTH:
1452 /*
1453 * disable additional interrupt modes:
1454 * fall back to default behavior
1455 */
Thomas Gleixnerc639845b2015-06-23 15:52:49 +02001456 irq_set_handler_locked(d, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001457 writel_relaxed(mask, pio + PIO_AIMDR);
1458 return 0;
1459 case IRQ_TYPE_NONE:
1460 default:
1461 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1462 return -EINVAL;
1463 }
1464
1465 /* enable additional interrupt modes */
1466 writel_relaxed(mask, pio + PIO_AIMER);
1467
1468 return 0;
1469}
1470
Alexander Stein80cc3732014-04-15 22:09:41 +02001471static void gpio_irq_ack(struct irq_data *d)
1472{
1473 /* the interrupt is already cleared before by reading ISR */
1474}
1475
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001476#ifdef CONFIG_PM
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001477
1478static u32 wakeups[MAX_GPIO_BANKS];
1479static u32 backups[MAX_GPIO_BANKS];
1480
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001481static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1482{
1483 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1484 unsigned bank = at91_gpio->pioc_idx;
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001485 unsigned mask = 1 << d->hwirq;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001486
1487 if (unlikely(bank >= MAX_GPIO_BANKS))
1488 return -EINVAL;
1489
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001490 if (state)
1491 wakeups[bank] |= mask;
1492 else
1493 wakeups[bank] &= ~mask;
1494
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001495 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1496
1497 return 0;
1498}
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001499
1500void at91_pinctrl_gpio_suspend(void)
1501{
1502 int i;
1503
1504 for (i = 0; i < gpio_banks; i++) {
1505 void __iomem *pio;
1506
1507 if (!gpio_chips[i])
1508 continue;
1509
1510 pio = gpio_chips[i]->regbase;
1511
Ben Dooksd4802392015-03-26 12:18:49 +00001512 backups[i] = readl_relaxed(pio + PIO_IMR);
1513 writel_relaxed(backups[i], pio + PIO_IDR);
1514 writel_relaxed(wakeups[i], pio + PIO_IER);
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001515
Boris BREZILLON795f9952013-12-15 19:30:51 +01001516 if (!wakeups[i])
1517 clk_disable_unprepare(gpio_chips[i]->clock);
1518 else
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001519 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1520 'A'+i, wakeups[i]);
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001521 }
1522}
1523
1524void at91_pinctrl_gpio_resume(void)
1525{
1526 int i;
1527
1528 for (i = 0; i < gpio_banks; i++) {
1529 void __iomem *pio;
1530
1531 if (!gpio_chips[i])
1532 continue;
1533
1534 pio = gpio_chips[i]->regbase;
1535
Boris BREZILLON37ef1d92013-12-15 19:30:52 +01001536 if (!wakeups[i])
1537 clk_prepare_enable(gpio_chips[i]->clock);
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001538
Ben Dooksd4802392015-03-26 12:18:49 +00001539 writel_relaxed(wakeups[i], pio + PIO_IDR);
1540 writel_relaxed(backups[i], pio + PIO_IER);
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001541 }
1542}
1543
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001544#else
1545#define gpio_irq_set_wake NULL
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001546#endif /* CONFIG_PM */
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001547
1548static struct irq_chip gpio_irqchip = {
1549 .name = "GPIO",
Alexander Stein80cc3732014-04-15 22:09:41 +02001550 .irq_ack = gpio_irq_ack,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001551 .irq_disable = gpio_irq_mask,
1552 .irq_mask = gpio_irq_mask,
1553 .irq_unmask = gpio_irq_unmask,
1554 /* .irq_set_type is set dynamically */
1555 .irq_set_wake = gpio_irq_set_wake,
1556};
1557
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +02001558static void gpio_irq_handler(struct irq_desc *desc)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001559{
Jiang Liu5663bb22015-06-04 12:13:16 +08001560 struct irq_chip *chip = irq_desc_get_chip(desc);
Alexander Stein80cc3732014-04-15 22:09:41 +02001561 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
Linus Walleij370ea612015-12-08 09:27:45 +01001562 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001563 void __iomem *pio = at91_gpio->regbase;
1564 unsigned long isr;
1565 int n;
1566
1567 chained_irq_enter(chip, desc);
1568 for (;;) {
1569 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
Alexandre Bellonic2eb9e72013-12-07 14:08:52 +01001570 * When there are none pending, we're finished unless we need
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001571 * to process multiple banks (like ID_PIOCDE on sam9263).
1572 */
1573 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1574 if (!isr) {
1575 if (!at91_gpio->next)
1576 break;
1577 at91_gpio = at91_gpio->next;
1578 pio = at91_gpio->regbase;
Alexander Steincccb0c32014-04-24 19:55:39 +02001579 gpio_chip = &at91_gpio->chip;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001580 continue;
1581 }
1582
Wei Yongjun05daa162012-10-26 22:50:54 +08001583 for_each_set_bit(n, &isr, BITS_PER_LONG) {
Alexander Stein80cc3732014-04-15 22:09:41 +02001584 generic_handle_irq(irq_find_mapping(
1585 gpio_chip->irqdomain, n));
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001586 }
1587 }
1588 chained_irq_exit(chip, desc);
1589 /* now it may re-trigger */
1590}
1591
Pramod Gurav834e1672014-09-09 15:50:37 +05301592static int at91_gpio_of_irq_setup(struct platform_device *pdev,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001593 struct at91_gpio_chip *at91_gpio)
1594{
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001595 struct gpio_chip *gpiochip_prev = NULL;
Alexander Steincccb0c32014-04-24 19:55:39 +02001596 struct at91_gpio_chip *prev = NULL;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001597 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001598 int ret, i;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001599
1600 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1601
1602 /* Setup proper .irq_set_type function */
1603 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1604
1605 /* Disable irqs of this PIO controller */
1606 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1607
Alexander Stein80cc3732014-04-15 22:09:41 +02001608 /*
1609 * Let the generic code handle this edge IRQ, the the chained
1610 * handler will perform the actual work of handling the parent
1611 * interrupt.
1612 */
1613 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1614 &gpio_irqchip,
1615 0,
1616 handle_edge_irq,
Marc Zyngier58033482016-09-06 14:58:15 +01001617 IRQ_TYPE_NONE);
Pramod Gurav834e1672014-09-09 15:50:37 +05301618 if (ret) {
1619 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001620 at91_gpio->pioc_idx);
Pramod Gurav834e1672014-09-09 15:50:37 +05301621 return ret;
1622 }
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001623
Alexander Steincccb0c32014-04-24 19:55:39 +02001624 /* The top level handler handles one bank of GPIOs, except
1625 * on some SoC it can handle up to three...
1626 * We only set up the handler for the first of the list.
1627 */
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001628 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1629 if (!gpiochip_prev) {
1630 /* Then register the chain on the parent IRQ */
1631 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1632 &gpio_irqchip,
1633 at91_gpio->pioc_virq,
1634 gpio_irq_handler);
Alexander Steincccb0c32014-04-24 19:55:39 +02001635 return 0;
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001636 }
Alexander Steincccb0c32014-04-24 19:55:39 +02001637
Linus Walleij370ea612015-12-08 09:27:45 +01001638 prev = gpiochip_get_data(gpiochip_prev);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001639
Jean-Christophe PLAGNIOL-VILLARDa0b957f2015-01-16 16:31:05 +01001640 /* we can only have 2 banks before */
1641 for (i = 0; i < 2; i++) {
1642 if (prev->next) {
1643 prev = prev->next;
1644 } else {
1645 prev->next = at91_gpio;
1646 return 0;
1647 }
1648 }
1649
1650 return -EINVAL;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001651}
1652
1653/* This structure is replicated for each GPIO block allocated at probe time */
Alexander Stein234b6512016-04-29 14:50:02 +02001654static const struct gpio_chip at91_gpio_template = {
Jonas Gorski98c85d52015-10-11 17:34:19 +02001655 .request = gpiochip_generic_request,
1656 .free = gpiochip_generic_free,
Richard Genoud8af584b2014-02-17 17:57:26 +01001657 .get_direction = at91_gpio_get_direction,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001658 .direction_input = at91_gpio_direction_input,
1659 .get = at91_gpio_get,
1660 .direction_output = at91_gpio_direction_output,
1661 .set = at91_gpio_set,
Alexander Stein1893b2c2015-04-02 11:55:49 +02001662 .set_multiple = at91_gpio_set_multiple,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001663 .dbg_show = at91_gpio_dbg_show,
Linus Walleij9fb1f392013-12-04 14:42:46 +01001664 .can_sleep = false,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001665 .ngpio = MAX_NB_GPIO_PER_BANK,
1666};
1667
Fabian Frederickbaa9946e2015-03-16 20:59:09 +01001668static const struct of_device_id at91_gpio_of_match[] = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001669 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1670 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1671 { /* sentinel */ }
1672};
1673
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001674static int at91_gpio_probe(struct platform_device *pdev)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001675{
1676 struct device_node *np = pdev->dev.of_node;
1677 struct resource *res;
1678 struct at91_gpio_chip *at91_chip = NULL;
1679 struct gpio_chip *chip;
1680 struct pinctrl_gpio_range *range;
1681 int ret = 0;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001682 int irq, i;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001683 int alias_idx = of_alias_get_id(np, "gpio");
1684 uint32_t ngpio;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001685 char **names;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001686
1687 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1688 if (gpio_chips[alias_idx]) {
1689 ret = -EBUSY;
1690 goto err;
1691 }
1692
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001693 irq = platform_get_irq(pdev, 0);
1694 if (irq < 0) {
1695 ret = irq;
1696 goto err;
1697 }
1698
1699 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1700 if (!at91_chip) {
1701 ret = -ENOMEM;
1702 goto err;
1703 }
1704
Wolfram Sangf50b9e12013-05-10 10:17:03 +02001705 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding9e0c1fb2013-01-21 11:09:14 +01001706 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1707 if (IS_ERR(at91_chip->regbase)) {
1708 ret = PTR_ERR(at91_chip->regbase);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001709 goto err;
1710 }
1711
Sachin Kamat3c936002013-03-15 10:07:03 +05301712 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001713 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1714 at91_chip->pioc_virq = irq;
1715 at91_chip->pioc_idx = alias_idx;
1716
Pramod Gurav02b837f2014-08-31 16:51:52 +05301717 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001718 if (IS_ERR(at91_chip->clock)) {
1719 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
Pramod Gurav70e41972014-09-09 15:50:36 +05301720 ret = PTR_ERR(at91_chip->clock);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001721 goto err;
1722 }
1723
Alexander Stein7d3a3fe2016-04-29 14:50:03 +02001724 ret = clk_prepare_enable(at91_chip->clock);
Pramod Gurav70e41972014-09-09 15:50:36 +05301725 if (ret) {
Alexander Stein7d3a3fe2016-04-29 14:50:03 +02001726 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
Pramod Gurav70e41972014-09-09 15:50:36 +05301727 goto clk_enable_err;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001728 }
1729
1730 at91_chip->chip = at91_gpio_template;
1731
1732 chip = &at91_chip->chip;
1733 chip->of_node = np;
1734 chip->label = dev_name(&pdev->dev);
Linus Walleij58383c72015-11-04 09:56:26 +01001735 chip->parent = &pdev->dev;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001736 chip->owner = THIS_MODULE;
1737 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1738
1739 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1740 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1741 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1742 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1743 else
1744 chip->ngpio = ngpio;
1745 }
1746
Sachin Kamat3c936002013-03-15 10:07:03 +05301747 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1748 GFP_KERNEL);
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001749
1750 if (!names) {
1751 ret = -ENOMEM;
Pramod Gurav70e41972014-09-09 15:50:36 +05301752 goto clk_enable_err;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001753 }
1754
1755 for (i = 0; i < chip->ngpio; i++)
1756 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1757
Sachin Kamat3c936002013-03-15 10:07:03 +05301758 chip->names = (const char *const *)names;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001759
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001760 range = &at91_chip->range;
1761 range->name = chip->label;
1762 range->id = alias_idx;
1763 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1764
1765 range->npins = chip->ngpio;
1766 range->gc = chip;
1767
Linus Walleij370ea612015-12-08 09:27:45 +01001768 ret = gpiochip_add_data(chip, at91_chip);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001769 if (ret)
Pramod Gurav70e41972014-09-09 15:50:36 +05301770 goto gpiochip_add_err;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001771
1772 gpio_chips[alias_idx] = at91_chip;
1773 gpio_banks = max(gpio_banks, alias_idx + 1);
1774
Pramod Gurav834e1672014-09-09 15:50:37 +05301775 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1776 if (ret)
1777 goto irq_setup_err;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001778
1779 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1780
1781 return 0;
1782
Pramod Gurav834e1672014-09-09 15:50:37 +05301783irq_setup_err:
1784 gpiochip_remove(chip);
Pramod Gurav70e41972014-09-09 15:50:36 +05301785gpiochip_add_err:
Pramod Gurav70e41972014-09-09 15:50:36 +05301786clk_enable_err:
Alexander Stein7d3a3fe2016-04-29 14:50:03 +02001787 clk_disable_unprepare(at91_chip->clock);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001788err:
1789 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1790
1791 return ret;
1792}
1793
1794static struct platform_driver at91_gpio_driver = {
1795 .driver = {
1796 .name = "gpio-at91",
Sachin Kamat606fca92013-09-28 17:38:48 +05301797 .of_match_table = at91_gpio_of_match,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001798 },
1799 .probe = at91_gpio_probe,
1800};
1801
1802static struct platform_driver at91_pinctrl_driver = {
1803 .driver = {
1804 .name = "pinctrl-at91",
Sachin Kamat606fca92013-09-28 17:38:48 +05301805 .of_match_table = at91_pinctrl_of_match,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001806 },
1807 .probe = at91_pinctrl_probe,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001808};
1809
Thierry Redingbab7f5a2015-12-02 17:31:55 +01001810static struct platform_driver * const drivers[] = {
1811 &at91_gpio_driver,
1812 &at91_pinctrl_driver,
1813};
1814
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001815static int __init at91_pinctrl_init(void)
1816{
Thierry Redingbab7f5a2015-12-02 17:31:55 +01001817 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001818}
1819arch_initcall(at91_pinctrl_init);