blob: c5623694d10f56a25ddc1c6f6073deaa3f250232 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
4 * Copyright 2004 Red Hat, Inc.
5 *
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
9 * by reference.
10 *
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
21 *
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
24 *
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/sched.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020035#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "scsi.h"
37#include <scsi/scsi_host.h>
38#include <linux/libata.h>
39#include <asm/io.h>
40
41#define DRV_NAME "ahci"
Jeff Garzikead5de92005-05-31 11:53:57 -040042#define DRV_VERSION "1.01"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
44
45enum {
46 AHCI_PCI_BAR = 5,
47 AHCI_MAX_SG = 168, /* hardware max is 64K */
48 AHCI_DMA_BOUNDARY = 0xffffffff,
49 AHCI_USE_CLUSTERING = 0,
50 AHCI_CMD_SLOT_SZ = 32 * 32,
51 AHCI_RX_FIS_SZ = 256,
52 AHCI_CMD_TBL_HDR = 0x80,
Jeff Garzika0ea7322005-06-04 01:13:15 -040053 AHCI_CMD_TBL_CDB = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
55 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
56 AHCI_RX_FIS_SZ,
57 AHCI_IRQ_ON_SG = (1 << 31),
58 AHCI_CMD_ATAPI = (1 << 5),
59 AHCI_CMD_WRITE = (1 << 6),
60
61 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
62
63 board_ahci = 0,
64
65 /* global controller registers */
66 HOST_CAP = 0x00, /* host capabilities */
67 HOST_CTL = 0x04, /* global host control */
68 HOST_IRQ_STAT = 0x08, /* interrupt status */
69 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
70 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
71
72 /* HOST_CTL bits */
73 HOST_RESET = (1 << 0), /* reset controller; self-clear */
74 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
75 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
76
77 /* HOST_CAP bits */
78 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
79
80 /* registers for each SATA port */
81 PORT_LST_ADDR = 0x00, /* command list DMA addr */
82 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
83 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
84 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
85 PORT_IRQ_STAT = 0x10, /* interrupt status */
86 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
87 PORT_CMD = 0x18, /* port command */
88 PORT_TFDATA = 0x20, /* taskfile data */
89 PORT_SIG = 0x24, /* device TF signature */
90 PORT_CMD_ISSUE = 0x38, /* command issue */
91 PORT_SCR = 0x28, /* SATA phy register block */
92 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
93 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
94 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
95 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
96
97 /* PORT_IRQ_{STAT,MASK} bits */
98 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
99 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
100 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
101 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
102 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
103 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
104 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
105 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
106
107 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
108 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
109 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
110 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
111 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
112 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
113 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
114 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
115 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
116
117 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
118 PORT_IRQ_HBUS_ERR |
119 PORT_IRQ_HBUS_DATA_ERR |
120 PORT_IRQ_IF_ERR,
121 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
122 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
123 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
124 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
125 PORT_IRQ_D2H_REG_FIS,
126
127 /* PORT_CMD bits */
128 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
129 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
130 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
131 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
132 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
133 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
134
135 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
136 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
137 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400138
139 /* hpriv->flags bits */
140 AHCI_FLAG_MSI = (1 << 0),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141};
142
143struct ahci_cmd_hdr {
144 u32 opts;
145 u32 status;
146 u32 tbl_addr;
147 u32 tbl_addr_hi;
148 u32 reserved[4];
149};
150
151struct ahci_sg {
152 u32 addr;
153 u32 addr_hi;
154 u32 reserved;
155 u32 flags_size;
156};
157
158struct ahci_host_priv {
159 unsigned long flags;
160 u32 cap; /* cache of HOST_CAP register */
161 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
162};
163
164struct ahci_port_priv {
165 struct ahci_cmd_hdr *cmd_slot;
166 dma_addr_t cmd_slot_dma;
167 void *cmd_tbl;
168 dma_addr_t cmd_tbl_dma;
169 struct ahci_sg *cmd_tbl_sg;
170 void *rx_fis;
171 dma_addr_t rx_fis_dma;
172};
173
174static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
175static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
176static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
177static int ahci_qc_issue(struct ata_queued_cmd *qc);
178static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
179static void ahci_phy_reset(struct ata_port *ap);
180static void ahci_irq_clear(struct ata_port *ap);
181static void ahci_eng_timeout(struct ata_port *ap);
182static int ahci_port_start(struct ata_port *ap);
183static void ahci_port_stop(struct ata_port *ap);
184static void ahci_host_stop(struct ata_host_set *host_set);
185static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
186static void ahci_qc_prep(struct ata_queued_cmd *qc);
187static u8 ahci_check_status(struct ata_port *ap);
188static u8 ahci_check_err(struct ata_port *ap);
189static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
Jeff Garzik907f4672005-05-12 15:03:42 -0400190static void ahci_remove_one (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192static Scsi_Host_Template ahci_sht = {
193 .module = THIS_MODULE,
194 .name = DRV_NAME,
195 .ioctl = ata_scsi_ioctl,
196 .queuecommand = ata_scsi_queuecmd,
197 .eh_strategy_handler = ata_scsi_error,
198 .can_queue = ATA_DEF_QUEUE,
199 .this_id = ATA_SHT_THIS_ID,
200 .sg_tablesize = AHCI_MAX_SG,
201 .max_sectors = ATA_MAX_SECTORS,
202 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
203 .emulated = ATA_SHT_EMULATED,
204 .use_clustering = AHCI_USE_CLUSTERING,
205 .proc_name = DRV_NAME,
206 .dma_boundary = AHCI_DMA_BOUNDARY,
207 .slave_configure = ata_scsi_slave_config,
208 .bios_param = ata_std_bios_param,
209 .ordered_flush = 1,
210};
211
212static struct ata_port_operations ahci_ops = {
213 .port_disable = ata_port_disable,
214
215 .check_status = ahci_check_status,
216 .check_altstatus = ahci_check_status,
217 .check_err = ahci_check_err,
218 .dev_select = ata_noop_dev_select,
219
220 .tf_read = ahci_tf_read,
221
222 .phy_reset = ahci_phy_reset,
223
224 .qc_prep = ahci_qc_prep,
225 .qc_issue = ahci_qc_issue,
226
227 .eng_timeout = ahci_eng_timeout,
228
229 .irq_handler = ahci_interrupt,
230 .irq_clear = ahci_irq_clear,
231
232 .scr_read = ahci_scr_read,
233 .scr_write = ahci_scr_write,
234
235 .port_start = ahci_port_start,
236 .port_stop = ahci_port_stop,
237 .host_stop = ahci_host_stop,
238};
239
240static struct ata_port_info ahci_port_info[] = {
241 /* board_ahci */
242 {
243 .sht = &ahci_sht,
244 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
245 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
246 ATA_FLAG_PIO_DMA,
247 .pio_mask = 0x03, /* pio3-4 */
248 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
249 .port_ops = &ahci_ops,
250 },
251};
252
253static struct pci_device_id ahci_pci_tbl[] = {
254 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 board_ahci }, /* ICH6 */
256 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 board_ahci }, /* ICH6M */
258 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_ahci }, /* ICH7 */
260 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH7M */
262 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH7R */
264 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ULi M5288 */
Jason Gaston680d3232005-04-16 15:24:45 -0700266 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ESB2 */
268 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ESB2 */
270 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ESB2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 { } /* terminate list */
273};
274
275
276static struct pci_driver ahci_pci_driver = {
277 .name = DRV_NAME,
278 .id_table = ahci_pci_tbl,
279 .probe = ahci_init_one,
Jeff Garzik907f4672005-05-12 15:03:42 -0400280 .remove = ahci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281};
282
283
284static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
285{
286 return base + 0x100 + (port * 0x80);
287}
288
289static inline void *ahci_port_base (void *base, unsigned int port)
290{
291 return (void *) ahci_port_base_ul((unsigned long)base, port);
292}
293
294static void ahci_host_stop(struct ata_host_set *host_set)
295{
296 struct ahci_host_priv *hpriv = host_set->private_data;
297 kfree(hpriv);
Jeff Garzikaa8f0dc2005-05-26 21:54:27 -0400298
299 ata_host_stop(host_set);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300}
301
302static int ahci_port_start(struct ata_port *ap)
303{
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 void *mem, *mmio = ap->host_set->mmio_base;
308 void *port_mmio = ahci_port_base(mmio, ap->port_no);
309 dma_addr_t mem_dma;
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
Tejun Heo0a139e72005-06-26 23:52:50 +0900312 if (!pp)
313 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 memset(pp, 0, sizeof(*pp));
315
316 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
317 if (!mem) {
Tejun Heo0a139e72005-06-26 23:52:50 +0900318 kfree(pp);
319 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 }
321 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
322
323 /*
324 * First item in chunk of DMA memory: 32-slot command table,
325 * 32 bytes each in size
326 */
327 pp->cmd_slot = mem;
328 pp->cmd_slot_dma = mem_dma;
329
330 mem += AHCI_CMD_SLOT_SZ;
331 mem_dma += AHCI_CMD_SLOT_SZ;
332
333 /*
334 * Second item: Received-FIS area
335 */
336 pp->rx_fis = mem;
337 pp->rx_fis_dma = mem_dma;
338
339 mem += AHCI_RX_FIS_SZ;
340 mem_dma += AHCI_RX_FIS_SZ;
341
342 /*
343 * Third item: data area for storing a single command
344 * and its scatter-gather table
345 */
346 pp->cmd_tbl = mem;
347 pp->cmd_tbl_dma = mem_dma;
348
349 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
350
351 ap->private_data = pp;
352
353 if (hpriv->cap & HOST_CAP_64)
354 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
355 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
356 readl(port_mmio + PORT_LST_ADDR); /* flush */
357
358 if (hpriv->cap & HOST_CAP_64)
359 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
360 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
361 readl(port_mmio + PORT_FIS_ADDR); /* flush */
362
363 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
364 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
365 PORT_CMD_START, port_mmio + PORT_CMD);
366 readl(port_mmio + PORT_CMD); /* flush */
367
368 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369}
370
371
372static void ahci_port_stop(struct ata_port *ap)
373{
374 struct device *dev = ap->host_set->dev;
375 struct ahci_port_priv *pp = ap->private_data;
376 void *mmio = ap->host_set->mmio_base;
377 void *port_mmio = ahci_port_base(mmio, ap->port_no);
378 u32 tmp;
379
380 tmp = readl(port_mmio + PORT_CMD);
381 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
382 writel(tmp, port_mmio + PORT_CMD);
383 readl(port_mmio + PORT_CMD); /* flush */
384
385 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
386 * this is slightly incorrect.
387 */
388 msleep(500);
389
390 ap->private_data = NULL;
391 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
392 pp->cmd_slot, pp->cmd_slot_dma);
393 kfree(pp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394}
395
396static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
397{
398 unsigned int sc_reg;
399
400 switch (sc_reg_in) {
401 case SCR_STATUS: sc_reg = 0; break;
402 case SCR_CONTROL: sc_reg = 1; break;
403 case SCR_ERROR: sc_reg = 2; break;
404 case SCR_ACTIVE: sc_reg = 3; break;
405 default:
406 return 0xffffffffU;
407 }
408
409 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
410}
411
412
413static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
414 u32 val)
415{
416 unsigned int sc_reg;
417
418 switch (sc_reg_in) {
419 case SCR_STATUS: sc_reg = 0; break;
420 case SCR_CONTROL: sc_reg = 1; break;
421 case SCR_ERROR: sc_reg = 2; break;
422 case SCR_ACTIVE: sc_reg = 3; break;
423 default:
424 return;
425 }
426
427 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
428}
429
430static void ahci_phy_reset(struct ata_port *ap)
431{
432 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
433 struct ata_taskfile tf;
434 struct ata_device *dev = &ap->device[0];
435 u32 tmp;
436
437 __sata_phy_reset(ap);
438
439 if (ap->flags & ATA_FLAG_PORT_DISABLED)
440 return;
441
442 tmp = readl(port_mmio + PORT_SIG);
443 tf.lbah = (tmp >> 24) & 0xff;
444 tf.lbam = (tmp >> 16) & 0xff;
445 tf.lbal = (tmp >> 8) & 0xff;
446 tf.nsect = (tmp) & 0xff;
447
448 dev->class = ata_dev_classify(&tf);
449 if (!ata_dev_present(dev))
450 ata_port_disable(ap);
451}
452
453static u8 ahci_check_status(struct ata_port *ap)
454{
455 void *mmio = (void *) ap->ioaddr.cmd_addr;
456
457 return readl(mmio + PORT_TFDATA) & 0xFF;
458}
459
460static u8 ahci_check_err(struct ata_port *ap)
461{
462 void *mmio = (void *) ap->ioaddr.cmd_addr;
463
464 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
465}
466
467static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
468{
469 struct ahci_port_priv *pp = ap->private_data;
470 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
471
472 ata_tf_from_fis(d2h_fis, tf);
473}
474
475static void ahci_fill_sg(struct ata_queued_cmd *qc)
476{
477 struct ahci_port_priv *pp = qc->ap->private_data;
478 unsigned int i;
479
480 VPRINTK("ENTER\n");
481
482 /*
483 * Next, the S/G list.
484 */
485 for (i = 0; i < qc->n_elem; i++) {
486 u32 sg_len;
487 dma_addr_t addr;
488
489 addr = sg_dma_address(&qc->sg[i]);
490 sg_len = sg_dma_len(&qc->sg[i]);
491
492 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
493 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
494 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
495 }
496}
497
498static void ahci_qc_prep(struct ata_queued_cmd *qc)
499{
Jeff Garzika0ea7322005-06-04 01:13:15 -0400500 struct ata_port *ap = qc->ap;
501 struct ahci_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 u32 opts;
503 const u32 cmd_fis_len = 5; /* five dwords */
504
505 /*
506 * Fill in command slot information (currently only one slot,
507 * slot 0, is currently since we don't do queueing)
508 */
509
510 opts = (qc->n_elem << 16) | cmd_fis_len;
511 if (qc->tf.flags & ATA_TFLAG_WRITE)
512 opts |= AHCI_CMD_WRITE;
Jeff Garzika0ea7322005-06-04 01:13:15 -0400513 if (is_atapi_taskfile(&qc->tf))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 opts |= AHCI_CMD_ATAPI;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515
516 pp->cmd_slot[0].opts = cpu_to_le32(opts);
517 pp->cmd_slot[0].status = 0;
518 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
519 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
520
521 /*
522 * Fill in command table information. First, the header,
523 * a SATA Register - Host to Device command FIS.
524 */
525 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
Jeff Garzika0ea7322005-06-04 01:13:15 -0400526 if (opts & AHCI_CMD_ATAPI) {
527 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
528 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
529 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530
531 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
532 return;
533
534 ahci_fill_sg(qc);
535}
536
537static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
538{
539 void *mmio = ap->host_set->mmio_base;
540 void *port_mmio = ahci_port_base(mmio, ap->port_no);
541 u32 tmp;
542 int work;
543
544 /* stop DMA */
545 tmp = readl(port_mmio + PORT_CMD);
546 tmp &= ~PORT_CMD_START;
547 writel(tmp, port_mmio + PORT_CMD);
548
549 /* wait for engine to stop. TODO: this could be
550 * as long as 500 msec
551 */
552 work = 1000;
553 while (work-- > 0) {
554 tmp = readl(port_mmio + PORT_CMD);
555 if ((tmp & PORT_CMD_LIST_ON) == 0)
556 break;
557 udelay(10);
558 }
559
560 /* clear SATA phy error, if any */
561 tmp = readl(port_mmio + PORT_SCR_ERR);
562 writel(tmp, port_mmio + PORT_SCR_ERR);
563
564 /* if DRQ/BSY is set, device needs to be reset.
565 * if so, issue COMRESET
566 */
567 tmp = readl(port_mmio + PORT_TFDATA);
568 if (tmp & (ATA_BUSY | ATA_DRQ)) {
569 writel(0x301, port_mmio + PORT_SCR_CTL);
570 readl(port_mmio + PORT_SCR_CTL); /* flush */
571 udelay(10);
572 writel(0x300, port_mmio + PORT_SCR_CTL);
573 readl(port_mmio + PORT_SCR_CTL); /* flush */
574 }
575
576 /* re-start DMA */
577 tmp = readl(port_mmio + PORT_CMD);
578 tmp |= PORT_CMD_START;
579 writel(tmp, port_mmio + PORT_CMD);
580 readl(port_mmio + PORT_CMD); /* flush */
581
582 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
583}
584
585static void ahci_eng_timeout(struct ata_port *ap)
586{
587 void *mmio = ap->host_set->mmio_base;
588 void *port_mmio = ahci_port_base(mmio, ap->port_no);
589 struct ata_queued_cmd *qc;
590
591 DPRINTK("ENTER\n");
592
593 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
594
595 qc = ata_qc_from_tag(ap, ap->active_tag);
596 if (!qc) {
597 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
598 ap->id);
599 } else {
600 /* hack alert! We cannot use the supplied completion
601 * function from inside the ->eh_strategy_handler() thread.
602 * libata is the only user of ->eh_strategy_handler() in
603 * any kernel, so the default scsi_done() assumes it is
604 * not being called from the SCSI EH.
605 */
606 qc->scsidone = scsi_finish_command;
607 ata_qc_complete(qc, ATA_ERR);
608 }
609
610}
611
612static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
613{
614 void *mmio = ap->host_set->mmio_base;
615 void *port_mmio = ahci_port_base(mmio, ap->port_no);
616 u32 status, serr, ci;
617
618 serr = readl(port_mmio + PORT_SCR_ERR);
619 writel(serr, port_mmio + PORT_SCR_ERR);
620
621 status = readl(port_mmio + PORT_IRQ_STAT);
622 writel(status, port_mmio + PORT_IRQ_STAT);
623
624 ci = readl(port_mmio + PORT_CMD_ISSUE);
625 if (likely((ci & 0x1) == 0)) {
626 if (qc) {
627 ata_qc_complete(qc, 0);
628 qc = NULL;
629 }
630 }
631
632 if (status & PORT_IRQ_FATAL) {
633 ahci_intr_error(ap, status);
634 if (qc)
635 ata_qc_complete(qc, ATA_ERR);
636 }
637
638 return 1;
639}
640
641static void ahci_irq_clear(struct ata_port *ap)
642{
643 /* TODO */
644}
645
646static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
647{
648 struct ata_host_set *host_set = dev_instance;
649 struct ahci_host_priv *hpriv;
650 unsigned int i, handled = 0;
651 void *mmio;
652 u32 irq_stat, irq_ack = 0;
653
654 VPRINTK("ENTER\n");
655
656 hpriv = host_set->private_data;
657 mmio = host_set->mmio_base;
658
659 /* sigh. 0xffffffff is a valid return from h/w */
660 irq_stat = readl(mmio + HOST_IRQ_STAT);
661 irq_stat &= hpriv->port_map;
662 if (!irq_stat)
663 return IRQ_NONE;
664
665 spin_lock(&host_set->lock);
666
667 for (i = 0; i < host_set->n_ports; i++) {
668 struct ata_port *ap;
669 u32 tmp;
670
671 VPRINTK("port %u\n", i);
672 ap = host_set->ports[i];
673 tmp = irq_stat & (1 << i);
674 if (tmp && ap) {
675 struct ata_queued_cmd *qc;
676 qc = ata_qc_from_tag(ap, ap->active_tag);
677 if (ahci_host_intr(ap, qc))
678 irq_ack |= (1 << i);
679 }
680 }
681
682 if (irq_ack) {
683 writel(irq_ack, mmio + HOST_IRQ_STAT);
684 handled = 1;
685 }
686
687 spin_unlock(&host_set->lock);
688
689 VPRINTK("EXIT\n");
690
691 return IRQ_RETVAL(handled);
692}
693
694static int ahci_qc_issue(struct ata_queued_cmd *qc)
695{
696 struct ata_port *ap = qc->ap;
697 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
698
699 writel(1, port_mmio + PORT_SCR_ACT);
700 readl(port_mmio + PORT_SCR_ACT); /* flush */
701
702 writel(1, port_mmio + PORT_CMD_ISSUE);
703 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
704
705 return 0;
706}
707
708static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
709 unsigned int port_idx)
710{
711 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
712 base = ahci_port_base_ul(base, port_idx);
713 VPRINTK("base now==0x%lx\n", base);
714
715 port->cmd_addr = base;
716 port->scr_addr = base + PORT_SCR;
717
718 VPRINTK("EXIT\n");
719}
720
721static int ahci_host_init(struct ata_probe_ent *probe_ent)
722{
723 struct ahci_host_priv *hpriv = probe_ent->private_data;
724 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
725 void __iomem *mmio = probe_ent->mmio_base;
726 u32 tmp, cap_save;
727 u16 tmp16;
728 unsigned int i, j, using_dac;
729 int rc;
730 void __iomem *port_mmio;
731
732 cap_save = readl(mmio + HOST_CAP);
733 cap_save &= ( (1<<28) | (1<<17) );
734 cap_save |= (1 << 27);
735
736 /* global controller reset */
737 tmp = readl(mmio + HOST_CTL);
738 if ((tmp & HOST_RESET) == 0) {
739 writel(tmp | HOST_RESET, mmio + HOST_CTL);
740 readl(mmio + HOST_CTL); /* flush */
741 }
742
743 /* reset must complete within 1 second, or
744 * the hardware should be considered fried.
745 */
746 ssleep(1);
747
748 tmp = readl(mmio + HOST_CTL);
749 if (tmp & HOST_RESET) {
750 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
751 pci_name(pdev), tmp);
752 return -EIO;
753 }
754
755 writel(HOST_AHCI_EN, mmio + HOST_CTL);
756 (void) readl(mmio + HOST_CTL); /* flush */
757 writel(cap_save, mmio + HOST_CAP);
758 writel(0xf, mmio + HOST_PORTS_IMPL);
759 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
760
761 pci_read_config_word(pdev, 0x92, &tmp16);
762 tmp16 |= 0xf;
763 pci_write_config_word(pdev, 0x92, tmp16);
764
765 hpriv->cap = readl(mmio + HOST_CAP);
766 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
767 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
768
769 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
770 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
771
772 using_dac = hpriv->cap & HOST_CAP_64;
773 if (using_dac &&
774 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
775 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
776 if (rc) {
777 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
778 if (rc) {
779 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
780 pci_name(pdev));
781 return rc;
782 }
783 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784 } else {
785 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
786 if (rc) {
787 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
788 pci_name(pdev));
789 return rc;
790 }
791 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
792 if (rc) {
793 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
794 pci_name(pdev));
795 return rc;
796 }
797 }
798
799 for (i = 0; i < probe_ent->n_ports; i++) {
800#if 0 /* BIOSen initialize this incorrectly */
801 if (!(hpriv->port_map & (1 << i)))
802 continue;
803#endif
804
805 port_mmio = ahci_port_base(mmio, i);
806 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
807
808 ahci_setup_port(&probe_ent->port[i],
809 (unsigned long) mmio, i);
810
811 /* make sure port is not active */
812 tmp = readl(port_mmio + PORT_CMD);
813 VPRINTK("PORT_CMD 0x%x\n", tmp);
814 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
815 PORT_CMD_FIS_RX | PORT_CMD_START)) {
816 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
817 PORT_CMD_FIS_RX | PORT_CMD_START);
818 writel(tmp, port_mmio + PORT_CMD);
819 readl(port_mmio + PORT_CMD); /* flush */
820
821 /* spec says 500 msecs for each bit, so
822 * this is slightly incorrect.
823 */
824 msleep(500);
825 }
826
827 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
828
829 j = 0;
830 while (j < 100) {
831 msleep(10);
832 tmp = readl(port_mmio + PORT_SCR_STAT);
833 if ((tmp & 0xf) == 0x3)
834 break;
835 j++;
836 }
837
838 tmp = readl(port_mmio + PORT_SCR_ERR);
839 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
840 writel(tmp, port_mmio + PORT_SCR_ERR);
841
842 /* ack any pending irq events for this port */
843 tmp = readl(port_mmio + PORT_IRQ_STAT);
844 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
845 if (tmp)
846 writel(tmp, port_mmio + PORT_IRQ_STAT);
847
848 writel(1 << i, mmio + HOST_IRQ_STAT);
849
850 /* set irq mask (enables interrupts) */
851 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
852 }
853
854 tmp = readl(mmio + HOST_CTL);
855 VPRINTK("HOST_CTL 0x%x\n", tmp);
856 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
857 tmp = readl(mmio + HOST_CTL);
858 VPRINTK("HOST_CTL 0x%x\n", tmp);
859
860 pci_set_master(pdev);
861
862 return 0;
863}
864
865/* move to PCI layer, integrate w/ MSI stuff */
Jeff Garzik907f4672005-05-12 15:03:42 -0400866static void pci_intx(struct pci_dev *pdev, int enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867{
Jeff Garzik907f4672005-05-12 15:03:42 -0400868 u16 pci_command, new;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869
870 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
Jeff Garzik907f4672005-05-12 15:03:42 -0400871
872 if (enable)
873 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
874 else
875 new = pci_command | PCI_COMMAND_INTX_DISABLE;
876
877 if (new != pci_command)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879}
880
881static void ahci_print_info(struct ata_probe_ent *probe_ent)
882{
883 struct ahci_host_priv *hpriv = probe_ent->private_data;
884 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
885 void *mmio = probe_ent->mmio_base;
886 u32 vers, cap, impl, speed;
887 const char *speed_s;
888 u16 cc;
889 const char *scc_s;
890
891 vers = readl(mmio + HOST_VERSION);
892 cap = hpriv->cap;
893 impl = hpriv->port_map;
894
895 speed = (cap >> 20) & 0xf;
896 if (speed == 1)
897 speed_s = "1.5";
898 else if (speed == 2)
899 speed_s = "3";
900 else
901 speed_s = "?";
902
903 pci_read_config_word(pdev, 0x0a, &cc);
904 if (cc == 0x0101)
905 scc_s = "IDE";
906 else if (cc == 0x0106)
907 scc_s = "SATA";
908 else if (cc == 0x0104)
909 scc_s = "RAID";
910 else
911 scc_s = "unknown";
912
913 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
914 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
915 ,
916 pci_name(pdev),
917
918 (vers >> 24) & 0xff,
919 (vers >> 16) & 0xff,
920 (vers >> 8) & 0xff,
921 vers & 0xff,
922
923 ((cap >> 8) & 0x1f) + 1,
924 (cap & 0x1f) + 1,
925 speed_s,
926 impl,
927 scc_s);
928
929 printk(KERN_INFO DRV_NAME "(%s) flags: "
930 "%s%s%s%s%s%s"
931 "%s%s%s%s%s%s%s\n"
932 ,
933 pci_name(pdev),
934
935 cap & (1 << 31) ? "64bit " : "",
936 cap & (1 << 30) ? "ncq " : "",
937 cap & (1 << 28) ? "ilck " : "",
938 cap & (1 << 27) ? "stag " : "",
939 cap & (1 << 26) ? "pm " : "",
940 cap & (1 << 25) ? "led " : "",
941
942 cap & (1 << 24) ? "clo " : "",
943 cap & (1 << 19) ? "nz " : "",
944 cap & (1 << 18) ? "only " : "",
945 cap & (1 << 17) ? "pmp " : "",
946 cap & (1 << 15) ? "pio " : "",
947 cap & (1 << 14) ? "slum " : "",
948 cap & (1 << 13) ? "part " : ""
949 );
950}
951
952static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
953{
954 static int printed_version;
955 struct ata_probe_ent *probe_ent = NULL;
956 struct ahci_host_priv *hpriv;
957 unsigned long base;
958 void *mmio_base;
959 unsigned int board_idx = (unsigned int) ent->driver_data;
Jeff Garzik907f4672005-05-12 15:03:42 -0400960 int have_msi, pci_dev_busy = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 int rc;
962
963 VPRINTK("ENTER\n");
964
965 if (!printed_version++)
966 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
967
968 rc = pci_enable_device(pdev);
969 if (rc)
970 return rc;
971
972 rc = pci_request_regions(pdev, DRV_NAME);
973 if (rc) {
974 pci_dev_busy = 1;
975 goto err_out;
976 }
977
Jeff Garzik907f4672005-05-12 15:03:42 -0400978 if (pci_enable_msi(pdev) == 0)
979 have_msi = 1;
980 else {
981 pci_intx(pdev, 1);
982 have_msi = 0;
983 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984
985 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
986 if (probe_ent == NULL) {
987 rc = -ENOMEM;
Jeff Garzik907f4672005-05-12 15:03:42 -0400988 goto err_out_msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989 }
990
991 memset(probe_ent, 0, sizeof(*probe_ent));
992 probe_ent->dev = pci_dev_to_dev(pdev);
993 INIT_LIST_HEAD(&probe_ent->node);
994
995 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
996 pci_resource_len(pdev, AHCI_PCI_BAR));
997 if (mmio_base == NULL) {
998 rc = -ENOMEM;
999 goto err_out_free_ent;
1000 }
1001 base = (unsigned long) mmio_base;
1002
1003 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1004 if (!hpriv) {
1005 rc = -ENOMEM;
1006 goto err_out_iounmap;
1007 }
1008 memset(hpriv, 0, sizeof(*hpriv));
1009
1010 probe_ent->sht = ahci_port_info[board_idx].sht;
1011 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1012 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1013 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1014 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1015
1016 probe_ent->irq = pdev->irq;
1017 probe_ent->irq_flags = SA_SHIRQ;
1018 probe_ent->mmio_base = mmio_base;
1019 probe_ent->private_data = hpriv;
1020
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001021 if (have_msi)
1022 hpriv->flags |= AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 /* initialize adapter */
1025 rc = ahci_host_init(probe_ent);
1026 if (rc)
1027 goto err_out_hpriv;
1028
1029 ahci_print_info(probe_ent);
1030
1031 /* FIXME: check ata_device_add return value */
1032 ata_device_add(probe_ent);
1033 kfree(probe_ent);
1034
1035 return 0;
1036
1037err_out_hpriv:
1038 kfree(hpriv);
1039err_out_iounmap:
1040 iounmap(mmio_base);
1041err_out_free_ent:
1042 kfree(probe_ent);
Jeff Garzik907f4672005-05-12 15:03:42 -04001043err_out_msi:
1044 if (have_msi)
1045 pci_disable_msi(pdev);
1046 else
1047 pci_intx(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 pci_release_regions(pdev);
1049err_out:
1050 if (!pci_dev_busy)
1051 pci_disable_device(pdev);
1052 return rc;
1053}
1054
Jeff Garzik907f4672005-05-12 15:03:42 -04001055static void ahci_remove_one (struct pci_dev *pdev)
1056{
1057 struct device *dev = pci_dev_to_dev(pdev);
1058 struct ata_host_set *host_set = dev_get_drvdata(dev);
1059 struct ahci_host_priv *hpriv = host_set->private_data;
1060 struct ata_port *ap;
1061 unsigned int i;
1062 int have_msi;
1063
1064 for (i = 0; i < host_set->n_ports; i++) {
1065 ap = host_set->ports[i];
1066
1067 scsi_remove_host(ap->host);
1068 }
1069
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001070 have_msi = hpriv->flags & AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001071 free_irq(host_set->irq, host_set);
Jeff Garzik907f4672005-05-12 15:03:42 -04001072
1073 for (i = 0; i < host_set->n_ports; i++) {
1074 ap = host_set->ports[i];
1075
1076 ata_scsi_release(ap->host);
1077 scsi_host_put(ap->host);
1078 }
1079
Jeff Garzikead5de92005-05-31 11:53:57 -04001080 host_set->ops->host_stop(host_set);
1081 kfree(host_set);
1082
Jeff Garzik907f4672005-05-12 15:03:42 -04001083 if (have_msi)
1084 pci_disable_msi(pdev);
1085 else
1086 pci_intx(pdev, 0);
1087 pci_release_regions(pdev);
Jeff Garzik907f4672005-05-12 15:03:42 -04001088 pci_disable_device(pdev);
1089 dev_set_drvdata(dev, NULL);
1090}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091
1092static int __init ahci_init(void)
1093{
1094 return pci_module_init(&ahci_pci_driver);
1095}
1096
1097
1098static void __exit ahci_exit(void)
1099{
1100 pci_unregister_driver(&ahci_pci_driver);
1101}
1102
1103
1104MODULE_AUTHOR("Jeff Garzik");
1105MODULE_DESCRIPTION("AHCI SATA low-level driver");
1106MODULE_LICENSE("GPL");
1107MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1108
1109module_init(ahci_init);
1110module_exit(ahci_exit);