| Andreas Noever | 1660315 | 2014-06-03 22:03:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Thunderbolt Cactus Ridge driver - NHI registers |
| 3 | * |
| 4 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef DSL3510_REGS_H_ |
| 8 | #define DSL3510_REGS_H_ |
| 9 | |
| 10 | #include <linux/types.h> |
| 11 | |
| 12 | enum ring_flags { |
| 13 | RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */ |
| 14 | RING_FLAG_E2E_FLOW_CONTROL = 1 << 28, |
| 15 | RING_FLAG_PCI_NO_SNOOP = 1 << 29, |
| 16 | RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */ |
| 17 | RING_FLAG_ENABLE = 1 << 31, |
| 18 | }; |
| 19 | |
| 20 | enum ring_desc_flags { |
| 21 | RING_DESC_ISOCH = 0x1, /* TX only? */ |
| 22 | RING_DESC_COMPLETED = 0x2, /* set by NHI */ |
| 23 | RING_DESC_POSTED = 0x4, /* always set this */ |
| 24 | RING_DESC_INTERRUPT = 0x8, /* request an interrupt on completion */ |
| 25 | }; |
| 26 | |
| 27 | /** |
| 28 | * struct ring_desc - TX/RX ring entry |
| 29 | * |
| 30 | * For TX set length/eof/sof. |
| 31 | * For RX length/eof/sof are set by the NHI. |
| 32 | */ |
| 33 | struct ring_desc { |
| 34 | u64 phys; |
| 35 | u32 length:12; |
| 36 | u32 eof:4; |
| 37 | u32 sof:4; |
| 38 | enum ring_desc_flags flags:12; |
| 39 | u32 time; /* write zero */ |
| 40 | } __packed; |
| 41 | |
| 42 | /* NHI registers in bar 0 */ |
| 43 | |
| 44 | /* |
| 45 | * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT) |
| 46 | * 00: physical pointer to an array of struct ring_desc |
| 47 | * 08: ring tail (set by NHI) |
| 48 | * 10: ring head (index of first non posted descriptor) |
| 49 | * 12: descriptor count |
| 50 | */ |
| 51 | #define REG_TX_RING_BASE 0x00000 |
| 52 | |
| 53 | /* |
| 54 | * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT) |
| 55 | * 00: physical pointer to an array of struct ring_desc |
| 56 | * 08: ring head (index of first not posted descriptor) |
| 57 | * 10: ring tail (set by NHI) |
| 58 | * 12: descriptor count |
| 59 | * 14: max frame sizes (anything larger than 0x100 has no effect) |
| 60 | */ |
| 61 | #define REG_RX_RING_BASE 0x08000 |
| 62 | |
| 63 | /* |
| 64 | * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT) |
| 65 | * 00: enum_ring_flags |
| 66 | * 04: isoch time stamp ?? (write 0) |
| 67 | * ..: unknown |
| 68 | */ |
| 69 | #define REG_TX_OPTIONS_BASE 0x19800 |
| 70 | |
| 71 | /* |
| 72 | * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT) |
| 73 | * 00: enum ring_flags |
| 74 | * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to |
| 75 | * the corresponding TX hop id. |
| 76 | * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings) |
| 77 | * ..: unknown |
| 78 | */ |
| 79 | #define REG_RX_OPTIONS_BASE 0x29800 |
| 80 | |
| 81 | /* |
| 82 | * three bitfields: tx, rx, rx overflow |
| 83 | * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are |
| 84 | * cleared on read. New interrupts are fired only after ALL registers have been |
| 85 | * read (even those containing only disabled rings). |
| 86 | */ |
| 87 | #define REG_RING_NOTIFY_BASE 0x37800 |
| 88 | #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32) |
| 89 | |
| 90 | /* |
| 91 | * two bitfields: rx, tx |
| 92 | * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To |
| 93 | * enable/disable interrupts set/clear the corresponding bits. |
| 94 | */ |
| 95 | #define REG_RING_INTERRUPT_BASE 0x38200 |
| 96 | #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32) |
| 97 | |
| 98 | /* The last 11 bits contain the number of hops supported by the NHI port. */ |
| 99 | #define REG_HOP_COUNT 0x39640 |
| 100 | |
| 101 | #endif |