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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 *
3 * Alchemy Au1x00 ethernet driver include file
4 *
5 * Author: Pete Popov <ppopov@mvista.com>
6 *
7 * Copyright 2001 MontaVista Software Inc.
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 *
24 * ########################################################################
25 *
Jeff Garzik6aa20a22006-09-13 13:24:59 -040026 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 */
28
29
30#define MAC_IOSIZE 0x10000
31#define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
32#define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
33
34#define NUM_RX_BUFFS 4
35#define NUM_TX_BUFFS 4
36#define MAX_BUF_SIZE 2048
37
Florian Fainelli2cc3c6b2010-04-06 22:09:06 +000038#define ETH_TX_TIMEOUT (HZ/4)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#define MAC_MIN_PKT_SIZE 64
40
41#define MULTICAST_FILTER_LIMIT 64
42
Jeff Garzik6aa20a22006-09-13 13:24:59 -040043/*
44 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
Linus Torvalds1da177e2005-04-16 15:20:36 -070045 * boundary for both, receive and transmit.
46 */
Florian Fainelli34415922010-09-08 11:11:25 +000047struct db_dest {
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 struct db_dest *pnext;
Florian Fainellid0e7cb52010-09-08 11:15:13 +000049 u32 *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070050 dma_addr_t dma_addr;
Florian Fainelli34415922010-09-08 11:11:25 +000051};
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -040054 * The transmit and receive descriptors are memory
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 * mapped registers.
56 */
Florian Fainelli34415922010-09-08 11:11:25 +000057struct tx_dma {
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 u32 status;
59 u32 buff_stat;
60 u32 len;
61 u32 pad;
Florian Fainelli34415922010-09-08 11:11:25 +000062};
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Florian Fainelli34415922010-09-08 11:11:25 +000064struct rx_dma {
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 u32 status;
66 u32 buff_stat;
67 u32 pad[2];
Florian Fainelli34415922010-09-08 11:11:25 +000068};
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
70
71/*
72 * MAC control registers, memory mapped.
73 */
Florian Fainelli34415922010-09-08 11:11:25 +000074struct mac_reg {
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 u32 control;
76 u32 mac_addr_high;
77 u32 mac_addr_low;
78 u32 multi_hash_high;
79 u32 multi_hash_low;
80 u32 mii_control;
81 u32 mii_data;
82 u32 flow_control;
83 u32 vlan1_tag;
84 u32 vlan2_tag;
Florian Fainelli34415922010-09-08 11:11:25 +000085};
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
87
88struct au1000_private {
Florian Fainelli34415922010-09-08 11:11:25 +000089 struct db_dest *pDBfree;
90 struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
Florian Fainellid0e7cb52010-09-08 11:15:13 +000091 struct rx_dma *rx_dma_ring[NUM_RX_DMA];
92 struct tx_dma *tx_dma_ring[NUM_TX_DMA];
Florian Fainelli34415922010-09-08 11:11:25 +000093 struct db_dest *rx_db_inuse[NUM_RX_DMA];
94 struct db_dest *tx_db_inuse[NUM_TX_DMA];
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 u32 rx_head;
96 u32 tx_head;
97 u32 tx_tail;
98 u32 tx_full;
99
100 int mac_id;
Herbert Valerio Riedel0638dec2006-06-01 09:41:04 +0200101
Florian Fainelli18b8e152010-09-08 11:11:40 +0000102 int mac_enabled; /* whether MAC is currently enabled and running
Florian Fainellidc998392010-09-08 11:11:59 +0000103 * (req. for mdio)
104 */
Herbert Valerio Riedel0638dec2006-06-01 09:41:04 +0200105
106 int old_link; /* used by au1000_adjust_link */
107 int old_speed;
108 int old_duplex;
109
110 struct phy_device *phy_dev;
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -0700111 struct mii_bus *mii_bus;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400112
Florian Fainellibd2302c2009-11-10 01:13:38 +0100113 /* PHY configuration */
114 int phy_static_config;
115 int phy_search_highest_addr;
116 int phy1_search_mac0;
117
118 int phy_addr;
119 int phy_busid;
120 int phy_irq;
121
Florian Fainelli18b8e152010-09-08 11:11:40 +0000122 /* These variables are just for quick access
Florian Fainellidc998392010-09-08 11:11:59 +0000123 * to certain regs addresses.
124 */
Florian Fainellid0e7cb52010-09-08 11:15:13 +0000125 struct mac_reg *mac; /* mac registers */
126 u32 *enable; /* address of MAC Enable Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127
128 u32 vaddr; /* virtual address of rx/tx buffers */
129 dma_addr_t dma_addr; /* dma address of rx/tx buffers */
130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 spinlock_t lock; /* Serialise access to device */
Florian Fainelli7cd2e6e2010-04-06 22:09:09 +0000132
133 u32 msg_enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134};